Configuration of Variable Gain Amplifier, Front-End Module, and Wireless Device

Abstract

Described herein is a variable gain amplifier that selectively provides a variable or configurable impedance to a degeneration block and / or a feedback block, at least partially depending on the gain mode of the variable gain amplifier. Advantageously, a performance penalty is reduced or eliminated in one or more gain modes. The variable impedance is configured to improve the linearity of the amplification process in the target gain mode. The variable gain amplifier is configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. and / or a feedback block, at least partially depending on the gain mode of the variable gain amplifier. Described herein is a variable gain amplifier that selectively provides a variable or configurable impedance to a degeneration block and / or a feedback block, at least partially depending on the gain mode of the variable gain amplifier. Advantageously, a performance penalty is reduced or eliminated in one or more gain modes. The variable impedance is configured to improve the linearity of the amplification process in the target gain mode. The variable gain amplifier is configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. Described herein is a variable gain amplifier that selectively provides a variable or configurable impedance to a degeneration block and / or a feedback block, at least partially depending on the gain mode of the variable gain amplifier.

Description

Technical Field

[0001] The present disclosure relates to an amplifier for wireless communication applications.

[0002] Cross - Reference to Related Applications This application claims priority to U.S. Provisional Application No. 62 / 381,851, entitled "Multi - Input Amplifier with Degeneration Switching Block and Low - Loss Bypass Function", filed on Aug. 31, 2016. The entire disclosure of the above - referenced application is incorporated herein by reference in its entirety for all purposes.

Background Art

[0003] Wireless communication devices typically include components in a front - end module configured to amplify received radio - frequency (RF) signals. The front - end module may include multiple gain modes that provide different levels of amplification.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

[0005] According to certain implementations, the present disclosure relates to a variable - gain signal amplifier including a variable - gain stage configured to receive an input signal and generate an amplified output signal, and a degeneration switching block coupled to the variable - gain stage and configured to provide a plurality of gain levels for the variable - gain stage.

[0006] In some embodiments, the signal includes a radio frequency signal. In some embodiments, the amplifier is configured to selectively provide a bypass path that bypasses the variable gain stage and an amplification path that passes through the variable gain stage.

[0007] In some embodiments, the degeneration switching block is further configured to provide a set impedance to the variable gain stage. In a further embodiment, the set impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage that is not coupled to the degeneration switching block having the set impedance. In a further embodiment, the degeneration switching block is configured to provide a first set impedance for a first gain level of a plurality of gain levels and a second set impedance for a second gain level of the plurality of gain levels. Still further, in an embodiment, the first set impedance is greater than the second set impedance, and the first gain level is lower than the second gain level.

[0008] In some embodiments, the amplifier also includes a control circuit configured to generate an amplification control signal that controls the variable gain stage and the degeneration switching circuit. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to a plurality of gain levels.

[0009] In some embodiments, the amplifier further includes an intermediate coupled to an input of the variable gain stage. It includes a gain mode feedback block. The intermediate gain mode is configured to provide feedback for a subset of multiple gain levels to the variable gain stage. In a further embodiment, the intermediate gain mode feedback block and the degeneration switching block are configured to provide improved linearity to the amplified output signal compared to an amplifier in which the intermediate gain feedback block and the degeneration switching block do not exist. In some embodiments, the amplifier further includes a bypass block coupled to the input of the variable gain stage. The bypass block is configured to be activated at the low gain levels of the multiple gain levels to provide a bypass path that does not include the variable gain stage.

[0010] In some embodiments, the amplifier further includes a bypass block coupled to the input of the variable gain stage. The bypass block is configured to provide a bypass path that does not include the variable gain stage and is activated at the low gain levels of the multiple gain levels. In a further embodiment, the bypass path does not include the degeneration switching block.

[0011] In some embodiments, the amplifier further includes a cascode buffer coupled to the output of the variable gain stage. In some embodiments, the amplifier further includes a plurality of input nodes coupled to the variable gain stage. In a further embodiment, the amplifier is configured to receive a plurality of input signals at the plurality of input nodes, and the received individual signals have frequencies within different signal frequency bands. In yet a further embodiment, the amplifier is configured to amplify the signals received at the individual input ports independently of the amplification of the other received signals. In some embodiments, the amplifier further includes a plurality of input nodes coupled to the variable gain stage. In a further embodiment, the amplifier is configured to receive a plurality of input signals at the plurality of input nodes, and the received individual signals have frequencies within different signal frequency bands. In yet a further embodiment, the amplifier is configured to amplify the signals received at the individual input ports independently of the amplification of the other received signals.

[0012] According to certain implementations, the present disclosure is coupled to a signal amplifier configured to provide various impedance values associated with various gain levels having various gain levels. ​ a variable impedance stage and a switch implemented to selectively isolate the variable impedance stage from a reference potential node and operably associated with the variable impedance stage and a degeneration switching circuit including the same. Regarding a degeneration switching circuit including the same.

[0013] In some embodiments, the signal amplifier is configured to amplify a radio frequency signal. In some embodiments, a bypass path provided to the circuit bypasses the variable impedance stage. In some embodiments, the various impedance values are configured to provide improved linearity of the signal amplifier compared to a signal amplifier not coupled to a degeneration switching circuit having various impedance values associated with the various gain levels.

[0014] In some embodiments, the variable impedance stage is configured to provide a first set impedance value for a first gain level of the various gain levels and a second set impedance value for a second gain level of the various gain levels. In some embodiments, the circuit further includes a control circuit configured to generate an amplification control signal for controlling the variable impedance stage and the switch. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels. In some embodiments, the circuit further includes a control circuit configured to generate an amplification control signal for controlling the variable impedance stage and the switch. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels. In some embodiments, the circuit further includes a control circuit configured to generate an amplification control signal for controlling the variable impedance stage and the switch. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels.

[0015] In some embodiments, the circuit further includes a control circuit configured to generate an amplification control signal for controlling the variable impedance stage and the switch. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels. In some embodiments, the circuit further includes a control circuit configured to generate an amplification control signal for controlling the variable impedance stage and the switch. In a further embodiment, the control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels.

[0016] According to certain implementations, the present disclosure relates to a front-end architecture including a variable gain signal amplifier. The variable gain signal amplifier receives an input signal and generates an amplified output signal. A variable gain stage configured to, and a plurality of a degeneration switching block coupled to the variable gain stage and configured to provide gain levels of the variable gain stage . The front-end architecture also includes a filter assembly coupled to the variable gain signal amplifier and directing a frequency band at a selection input of the variable gain signal amplifier. The front-end architecture also includes a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes . In the low gain mode, the variable gain signal amplifier directs the signal along a path bypassing the variable gain stage.

[0017] In some embodiments, the degeneration switching block is further configured to provide a matched impedance to the variable gain stage. In further embodiments , the matched impedance is configured to provide improved linearity in the amplified output signal compared to a variable gain stage not coupled to a degeneration switching block having the matched impedance . In further embodiments , the degeneration switching block is configured to provide a first matched impedance for a first gain level of a plurality of gain levels and a second matched impedance for a second gain level of the plurality of gain levels. According to certain implementations, the present disclosure relates to a wireless device including a diversity antenna and a filter assembly coupled to the diversity antenna to direct a frequency band along a receive and select path. The wireless device also receives an input signal .

[0018] According to certain implementations, the present disclosure relates to a wireless device including a diversity antenna and a filter assembly coupled to the diversity antenna to direct a frequency band along a receive and select path. The wireless device also receives an input signal and couples it to the filter assembly. A variable gain stage configured to generate an amplified output signal, and coupled to the variable gain stage to provide a plurality of gain levels for the variable gain stage. A variable gain signal amplifier including a degeneration switching block configured to provide a plurality of gain levels for the variable gain stage. The wireless device also includes a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes. In the low gain mode, the variable gain signal amplifier directs the signal along a path that bypasses the variable gain stage. In some embodiments, the degeneration switching block is further configured to direct a matched impedance toward the variable gain stage. In a further embodiment, the matched impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage not coupled to the degeneration switching block having the matched impedance. In a further embodiment, the degeneration switching block is configured to provide a first matched impedance for a first gain level of the plurality of gain levels and a second matched impedance for a second gain level of the plurality of gain levels. For the purpose of summarizing the present disclosure, certain aspects, advantages, and novel features have been described herein. It is not necessarily the case that all such advantages are achieved in any particular embodiment. Thus, embodiments of the present disclosure can be implemented or optimized in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein without necessarily achieving other advantages taught or suggested herein. In the low gain mode, the variable gain signal amplifier directs the signal along a path that bypasses the variable gain stage.

[0019] In some embodiments, the degeneration switching block is further configured to direct a matched impedance toward the variable gain stage. In a further embodiment, the matched impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage not coupled to the degeneration switching block having the matched impedance. In a further embodiment, the matched impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage not coupled to the degeneration switching block having the matched impedance. In a further embodiment, the matched impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage not coupled to the degeneration switching block having the matched impedance. In a further embodiment, the matched impedance is configured to provide improved linearity in the amplified output signal compared to the variable gain stage not coupled to the degeneration switching block having the matched impedance. In a further embodiment, the degeneration switching block is configured to provide a first matched impedance for a first gain level of the plurality of gain levels and a second matched impedance for a second gain level of the plurality of gain levels. In a further embodiment, the degeneration switching block is configured to provide a first matched impedance for a first gain level of the plurality of gain levels and a second matched impedance for a second gain level of the plurality of gain levels. In a further embodiment, the degeneration switching block is configured to provide a first matched impedance for a first gain level of the plurality of gain levels and a second matched impedance for a second gain level of the plurality of gain levels.

[0020] For the purpose of summarizing the present disclosure, certain aspects, advantages, and novel features have been described herein. It is not necessarily the case that all such advantages are achieved in any particular embodiment. Thus, embodiments of the present disclosure can be implemented or optimized in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein without necessarily achieving other advantages taught or suggested herein. Thus, embodiments of the present disclosure can be implemented or optimized in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein without necessarily achieving other advantages taught or suggested herein.

Brief Description of the Drawings

[0021]

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Best Mode for Carrying Out the Invention

[0022] The headings given here, if any, are for convenience only and do not necessarily affect the scope or meaning of the invention claimed.

[0023] Overview

[0024] FIG. 1 illustrates a wireless device 100 having a primary antenna 160 and a diversity antenna 170. The wireless device 100 includes an RF module 106 and a transceiver 104 that can be controlled by a controller 102. The transceiver 104 is configured to perform conversions between analog signals (e.g., radio frequency (RF) signals) and digital data signals. For that purpose, the transceiver 104 includes a digital-to-analog converter, an analog-to-digital converter, a local oscillator that modulates or demodulates a baseband analog signal to or from a carrier frequency 100 is illustrated. The wireless device 100 includes an RF module 106 and a transceiver 104 that can be controlled by a controller 102. ule 106 and a transceiver 104. The transceiver 104 is configured to perform conversions between analog signals (e.g., radio frequency (RF) signals) and digital data signals. For that purpose, the transceiver 104 includes a digital-to-analog converter, an analog-to-digital converter, a local oscillator that modulates or demodulates a baseband analog signal to or from a carrier frequency (RF) signals) and digital data signals. For that purpose, the transceiver 104 includes a digital-to-analog converter, an analog-to-digital converter, a local oscillator that modulates or demodulates a baseband analog signal to or from a carrier frequency (RF) signals) and digital data signals. For that purpose, the transceiver 104 includes a digital-to-analog converter, an analog-to-digital converter, a local oscillator that modulates or demodulates a baseband analog signal to or from a carrier frequency An oscillator, between a digital sample and data bits (e.g., audio or other types of data). It may include a baseband processor or other components that perform the conversion.

[0025] RF module 106 is coupled between the primary antenna 160 and the transceiver 104. Since the RF module 106 can be physically close to the primary antenna 160 to reduce attenuation due to cable loss, the RF module 106 can be referred to as a front - end module (FEM). The RF module 106 can process analog signals received from the primary antenna 160 for the transceiver 104 or received from the transceiver 104 to be transmitted via the primary antenna 160. For that purpose, the RF module 106 may include filters, power amplifiers, low - noise amplifiers, band - select switches, attenuators, matching circuits, and other components. 106

[0026] When a signal is transmitted to the wireless device 100, the signal can be received at both the primary antenna 160 and the diversity antenna 170. Since the primary antenna 160 and the diversity antenna 170 are physically separated, the signals at the primary antenna 160 and the diversity antenna 170 are received with different characteristics. For example, in one embodiment, the primary antenna 160 and the diversity antenna 170 can receive signals with different attenuation, noise, frequency response, and / or phase shift. The transceiver 104 can use both signals with different characteristics to determine the data bits corresponding to the signal. embodiment, the signals received at the primary antenna 160 and the diversity antenna 170 have different characteristics. For example, in one embodiment, the primary antenna 160 and the diversity antenna 170 can receive signals with different attenuation, noise, frequency response, and / or phase shift. The transceiver 104 can use both signals with different characteristics to determine the data bits corresponding to the signal. In some implementations, the transceiver 104 is between the primary antenna 160 and the diversity antenna 170 antenna 170. ​​​​​It can be selected based on such characteristics from the diversity antenna 170. For example, the antenna with the highest signal-to-noise ratio can be selected. In some implementations, the transceiver 104 combines the signals from the primary antenna 160 and the diversity antenna 170 and increases the signal-to-noise ratio of the combined signal. In some implementations, the transceiver 104 processes the signals to perform multi-input / multi-output (MiMo) communication.

[0027] In some embodiments, the diversity antenna 170 is configured to receive signals in a number of cellular frequency bands and / or wireless local area network (WLAN) frequency bands. In such embodiments, the wireless device 100 may include a multiplexer, a switching network, and / or a filter assembly coupled to the diversity antenna 170 configured to divide the diversity signal into different frequency ranges. For example, the multiplexer can be configured to include a low-pass filter that passes a frequency range including low-band cellular frequencies, a band-pass filter that passes a frequency range including low-band WLAN signals and intermediate-band and high-band cellular signals, and a high-pass filter that passes a frequency range including high-band WLAN signals. This example is for illustrative purposes only. As another example, the multiplexer can have various different configurations such as a diplexer that provides the functions of a high-pass filter and a low-pass filter. Since the diversity antenna 170 is physically separated from the primary antenna 160, the diversity antenna 170 is connected by a cable or a printed circuit board (PCB) trace.

[0028] can be coupled to the transceiver 104 via a transmission line such as. In some implementations, the transmission line is lossy and attenuates the signal received at the diversity antenna 170 before it reaches the transceiver 10 4. Thus, in some implementations, a gain is applied to the signal received at the diversity antenna 170. The gain (and other analog processing such as filtering) can be applied by the diversity receiver module 108. Such a diversity receiver module 108 is located physically close to the diversity antenna 1 70 and can thus be referred to as a diversity receiver front-end module . An example thereof is described in detail herein .

[0029] The RF module 106 and the diversity receiver module 108 include variable gain amplifiers 110a, 110b configured to provide a plurality of gain modes for amplifying the signals from the primary antenna 1 60 and the diversity antenna 170, respectively. The variable gain amplifiers 1 10a, 110b each may include a gain stage 120 and a degeneration switching block 130 that varies the inductance based at least in part on one of the gain modes of the variable gain amplifiers 110a, 110b . The signals received at the variable gain amplifiers 110a, 110b can be amplified using the gain stage 120, or the signal may be allowed to bypass the gain stage 120, as detailed herein . The selected inductance, bypass path, and / or of the degeneration switching block 130 and the gain mode of the variable gain amplifiers 110a, 110b are controlled by the controller 102 . ​​​It is possible. The degeneration switching block 130 can be configured to change the inductance, so the performance of the variable gain amplifiers 110a and 110b can be increased compared to amplifiers with fixed inductance. For example, by increasing linearity and / or reducing noise introduced during amplification, the performance can be increased. The variable gain amplifiers 110a and 110b can receive multiple input signals and output a single signal or multiple output signals. In certain implementations, the individual inputs can have corresponding individual degeneration switching blocks to improve the input isolation between the input ports. Since it can be configured to change the inductance, the performance of the variable gain amplifiers 110a and 110b can be increased compared to amplifiers with fixed inductance. For example, by increasing linearity and / or reducing noise introduced during amplification, the performance can be increased. The variable gain amplifiers 110a and 110b can receive multiple input signals and output a single signal or multiple output signals. In certain implementations, the individual inputs can have corresponding individual degeneration switching blocks to improve the input isolation between the input ports. Advantageously, the architecture of the variable gain amplifiers 110a and 110b can provide multi-input processing without using switches. The variable gain amplifiers 110a and 110b can advantageously achieve the targeted or improved linearity by using switchable degeneration blocks with the provided inductance. The variable gain amplifiers 110a and 110b can provide the targeted or improved input-to-output isolation by using shunt switches in the bypass path.

[0030] The variable gain amplifiers 110a and 110b can provide a low-loss direct bypass mode in certain gain modes such as the low gain mode. The controller 102 can be configured to generate control signals and / or transmit them to other components of the wireless device 100. In some embodiments, the controller 102 is the Mobile Industry Processor Interface Alliance (MIPI (registered It is possible. The degeneration switching block 130 can be configured to change the inductance, so the performance of the variable gain amplifiers 110a and 110b can be increased compared to amplifiers with fixed inductance. For example, by increasing linearity and / or reducing noise introduced during amplification, the performance can be increased. The variable gain amplifiers 110a and 110b can receive multiple input signals and output a single signal or multiple output signals. In certain implementations, the individual inputs can have corresponding individual degeneration switching blocks to improve the input isolation between the input ports. Advantageously, the architecture of the variable gain amplifiers 110a and 110b can provide multi-input processing without using switches. The variable gain amplifiers 110a and 110b can advantageously achieve the targeted or improved linearity by using switchable degeneration blocks with the provided inductance.

[0031] The variable gain amplifiers 110a and 110b can provide the targeted or improved input-to-output isolation by using shunt switches in the bypass path. The variable gain amplifiers 110a and 110b can provide a low-loss direct bypass mode in certain gain modes such as the low gain mode. The controller 102 can be configured to generate control signals and / or transmit them to other components of the wireless device 100. In some embodiments, the controller 102 is the Mobile Industry Processor Interface Alliance (MIPI (registered Provide a signal that is at least partially based on the specifications provided by the trademark) alliance). Controller 1 02 can receive signals from other components of the wireless device 100 and be configured to process them to determine the control signals received by other components In some embodiments, the controller 102 can be configured to analyze signals or data and determine the control signals transmitted to other components of the wireless device 100. The control In some embodiments, the controller 102 can be configured to analyze signals or data and determine the control signals transmitted to other components of the wireless device 100. The control In some embodiments, the controller 102 can be configured to analyze signals or data and determine the control signals transmitted to other components of the wireless device 100. The control The controller 102 can be configured to generate control signals based on the gain mode provided by the wireless device 100 For example, the controller 102 can transmit control signals for controlling the gain mode to the variable gain amplifiers 110a, 110b. Similarly, the controller 102 can generate control signals for selecting the inductance of the generation switching block 130 For example, the controller 102 can transmit control signals for controlling the gain mode to the variable gain amplifiers 110a, 110b. Similarly, the controller 102 can generate control signals for selecting the inductance of the generation switching block 130 For example, the controller 102 can transmit control signals for controlling the gain mode to the variable gain amplifiers 110a, 110b. Similarly, the controller 102 can generate control signals for selecting the inductance of the generation switching block 130 The controller can be configured to generate control signals for controlling the variable gain amplifiers 110a, 110b to provide a bypass path In some implementations, the controller 102 generates amplifier control signals based on the service quality metric of the input signal received at the input section. In some implementations, the controller

[0032] In some implementations, the controller 102 generates amplifier control signals based on the service quality metric of the input signal received at the input section. In some implementations, the controller In some implementations, the controller 102 generates amplifier control signals based on the service quality metric of the input signal received at the input section. In some implementations, the controller 102 generates amplifier control signals based on the signal received from the communication controller and thus based on the quality of service (QoS) metric of the received signal The QoS metric of the received signal can be based at least in part on the diversity signal received at the diversity antenna 170 (e.g., the input signal received at the input section). The received The QoS metric of the received signal can be based at least in part on the diversity signal received at the diversity antenna 170 (e.g., the input signal received at the input section). The received The QoS metric of the received signal can be based at least in part on the diversity signal received at the diversity antenna 170 (e.g., the input signal received at the input section). The received The QoS metric of the received signal can be further based on the signal received at the primary antenna 160 can be obtained. In some implementations, the controller 102 receives a signal from the communication controller and generates an amplifier control signal based on the QoS metric of the diversity signal. In some implementations, the QoS metric includes signal strength. As another example, the QoS metric may include bit error rate, data throughput, transmission delay, or any other QoS metric. In some implementations, the controller 102 controls the gain (and / or current) of the amplifiers in variable gain amplifiers 110a, 110b. In some implementations, the controller 102 controls the gain of other components of the wireless device based on the amplifier control signal.

[0033] In some implementations, variable gain amplifiers 110a, 110b include a step variable gain amplifier configured to amplify the received signal by one of a plurality of set values indicated by the amplifier control signal. In some implementations, variable gain amplifiers 110a, 110b include a continuously variable gain amplifier configured to amplify the received signal by a gain proportional to or indicated by the amplifier control signal. In some implementations, variable gain amplifiers 110a, 110b include a step variable current amplifier configured to amplify the received signal by drawing one of a plurality of set values of current indicated by the amplifier control signal. In some implementations, variable gain amplifiers 110a, 110b include a continuously variable current amplifier configured to amplify the received signal by drawing a current proportional to the

[0034] amplifier control signal. Figure 2 shows a diversity receiver including a DRx front end module (FEM) 208.The diversity receiver (DRx) configuration 200 is illustrated. The DRx configuration 200 receives a diversity signal and includes a diversity antenna 170 configured to provide the diversity signal to the DRx FEM 150 via a filter assembly 272. The filter assembly 27 2 may include a multiplexer configured to selectively direct signals within a target frequency range along each path to a multi-input amplifier 220 coupled to a de-generation switching circuit 230. The signals may be, for example, radio frequency (RF) signals including, but not limited to, cellular signals (e.g., cellular frequencies in low, medium, high, and / or ultra-high bands), WLAN signals, BLUETOOTH (registered trademark) signals, GPS signals, etc. .

[0035] The DRx FEM 208 is configured to process the diversity signal received from the filter assembly 272. For example, the DRx FEM 208 can be configured to filter the diversity signal into one or more active frequency bands that may include cellular and / or WLAN frequency bands. The controller 102 can be configured to control the DRx FEM 208 to selectively direct signals to a target filter to achieve filtering. As another example, the DRx FEM 208 can be configured to amplify one or more of the filtered signals using an amplifier 22 0. For that purpose, the DRx FEM 208 may include filters, low noise amplifiers, band selection switches, matching circuits, and other components. The controller 102 can be configured to intelligently select a path for the diversity signal passing through the DRx FEM 208. ​​​​​​​It can be configured to interact with the components in 208.

[0036] The DRx FEM 208 transmits and receives at least a portion of the processed diversity signal. It transmits to the transceiver 104. The transceiver 104 can be controlled by the controller 102. In some implementations, the controller 102 can be implemented within the transceiver 104.

[0037] The DRx FEM 208 can be configured to provide multiple gain modes. For multiple gain modes, different inductances can be provided by the variable impedance stage 232 of the degeneration switching circuit 230. For multiple gain modes, different inductances can be provided by the variable impedance stage 232 of the degeneration switching circuit 230. In one or more gain modes, the switch 234 of the variable impedance stage 232 can be configured to select an impedance (e.g., inductance) coupled to the amplifier 220. In one or more gain modes, the switch 234 of the variable impedance stage 232 can be configured to select an impedance (e.g., inductance) coupled to the amplifier 220. This can be done, for example, to improve the linearity of the amplification process. Such selectable impedances can be embedded in a multi-input amplifier architecture. This can be done, for example, to improve the linearity of the amplification process. Such selectable impedances can be embedded in a multi-input amplifier architecture. This can be done, for example, to improve the linearity of the amplification process. Such selectable impedances can be embedded in a multi-input amplifier architecture.

[0038] In some embodiments, the use of a selectable impedance, such as LNA, coupled to the amplification stage can improve linearity and / or IIP3. In some embodiments, the use of a selectable impedance, such as LNA, coupled to the amplification stage can improve linearity and / or IIP3. The variable impedance stage 232 with the switch 234 advantageously enables coupling the amplifier 220 to a desired or targeted impedance for a particular gain mode and / or signal amplitude. The variable impedance stage 232 with the switch 234 advantageously enables coupling the amplifier 220 to a desired or targeted impedance for a particular gain mode and / or signal amplitude. In some embodiments, the DRx configuration 200 bypasses amplification when operating in the low gain mode and uses the amplifier 220 when operating in other gain modes. In some embodiments, the DRx configuration 200 bypasses amplification when operating in the low gain mode and uses the amplifier 220 when operating in other gain modes. is configured to amplify the signal. Advantageously, thereby, the DRx configuration 200 can improve the linearity in a specific gain mode.

[0039] In some embodiments, the amplifier 220 is configured to receive a plurality of input signals and provide a single output signal. In certain embodiments, the amplifier 220 can be configured to receive a plurality of input signals and provide a corresponding plurality of output signals. The filter assembly 272 can be configured to direct signals corresponding to a specific frequency band along a designated path to the amplifier 220. In certain implementations, the amplifier 220 can provide different gain modes for the received signals. The variable impedance stage 232 can use the switch 234 coupled to the amplifier 220 to select different impedances. The selected impedance is based at least in part on the gain mode of the amplifier 220. In certain implementations, the amplifier 220 can operate such that the signal passes through the bypass path in the bypass configuration and the signal passes through the amplification path in the amplification configuration. The selected impedance is provided by the variable impedance stage 232. Advantageously, thereby, the DRx FEM 208 can provide variable gain and / or multiple gain modes while reducing the negative impact on linearity (e.g., IIP3) and / or noise figure (NF) compared to a configuration that does not selectively provide a bypass path and / or variable impedance. The amplifier 220 includes any suitable amplifier circuit configured to provide the desired or target amplification. The amplifier 220 includes any suitable amplifier circuit configured to provide the desired or target amplification. The amplifier 220 includes any suitable amplifier circuit configured to provide the desired or target amplification. The amplifier 220 includes any suitable amplifier circuit configured to provide the desired or target amplification. It is possible. In some embodiments, amplifier 220 includes a low-noise amplifier (LNA) circuit seen, which is configured to amplify signals from a plurality of frequency bands ( e.g., cellular frequency bands and / or WLAN frequency bands) received at a plurality of input sections or a multi-input LNA. However, it should be understood that the embodiments described herein are not limited to implementations that utilize a low-noise amplifier, and also include implementations that use any of a variety of amplifiers.

[0040] Amplifier 220 can be configured to amplify a signal based at least in part on a plurality of gain modes. For example, amplifier 220 can be configured to provide a first amplification or gain for a first gain mode, a second amplification or gain for a second gain mode, and so on. Amplifier 220 can be controlled by a controller 102 that controls the gain applied to amplifier 220. For example, controller 102 can provide a signal indicating a desired or target gain to amplifier 220, and amplifier 220 can provide the target gain. Controller 102 can receive, for example, an indicator of a target gain from other components in the wireless device and control amplifier 220 based at least in part on the indicator. Similarly, the de-generation switching circuit 230 can be controlled based at least in part on the gain mode of amplifier 220 and / or the target gain.

[0041] Controller 102 can be configured to control the DRx FEM 208 to selectively provide an assigned impedance. For example, controller 102 and the DRx FE ​​​​​​​​​​​​M208 is capable of controlling the variable impedance stage 232 to configure the switch 234 so as to provide a target impedance based at least in part on a gain mode. As another example, the controller 102 and the DRx FEM 208 can control an amplifier to provide a bypass path based at least in part on a gain mode. As another example, the controller 102 and the DRx FEM 208 can use the amplifier 220 to provide multiple gain modes. As another example, the controller 102 and the DRx FEM 208 can control an amplifier to provide a bypass path based at least in part on a gain mode. As another example, the controller 102 and the DRx FEM 208 can use the amplifier 220 to provide multiple gain modes.

[0042] Example architectures of variable gain amplifiers

[0043] A front-end module generally includes an amplifier such as a low-noise amplifier (LNA) to amplify a received signal. In a wireless device that provides various gain modes, it can be advantageous to selectively provide a variable or tunable impedance to a gain stage to improve performance. Similarly, it can be advantageous to bypass a gain stage to improve performance (e.g., improve linearity) for at least one gain mode. In a wireless device that provides various gain modes, it can be advantageous to selectively provide a variable or tunable impedance to a gain stage to improve performance. Similarly, it can be advantageous to bypass a gain stage to improve performance (e.g., improve linearity) for at least one gain mode. In a wireless device that provides various gain modes, it can be advantageous to selectively provide a variable or tunable impedance to a gain stage to improve performance. Similarly, it can be advantageous to bypass a gain stage to improve performance (e.g., improve linearity) for at least one gain mode. Accordingly, provided herein is a variable gain amplifier that selectively provides a variable or tunable impedance to a degeneration block and / or a feedback block depending at least in part on a gain mode of the variable gain amplifier. Thereby, advantageously, a performance penalty is reduced or eliminated in one or more gain modes. Further, the variable impedance can be configured to improve the linearity of the amplification process in a target gain mode. Similarly, the variable gain amplifier can improve signal quality.

[0044] Accordingly, provided herein is a variable gain amplifier that selectively provides a variable or tunable impedance to a degeneration block and / or a feedback block depending at least in part on a gain mode of the variable gain amplifier. Thereby, advantageously, a performance penalty is reduced or eliminated in one or more gain modes. Further, the variable impedance can be configured to improve the linearity of the amplification process in a target gain mode. Similarly, the variable gain amplifier can improve signal quality. the variable impedance can be configured to improve the linearity of the amplification process in a target gain mode. Similarly, the variable gain amplifier can improve signal quality. advantageously, a performance penalty is reduced or eliminated in one or more gain modes. Further, the variable impedance can be configured to improve the linearity of the amplification process in a target gain mode. Similarly, the variable gain amplifier can improve signal quality. the variable impedance can be configured to improve the linearity of the amplification process in a target gain mode. Similarly, the variable gain amplifier can improve signal quality. 、In the low-gain mode, it can be configured to provide a low-loss bypass mode.

[0045] FIG. 3A illustrates a variable gain amplifier configuration example 310a including a multi-input gain stage 312. The multi-input gain stage 312 receives a number of inputs and selectively amplifies the received signals by the gain stage 320 or provides a bypass path through the bypass block 340. configured to. The gain stage 320 is coupled to a degeneration switching block 330. The degeneration switching block 330 is configured to selectively provide an impedance arranged at least partially based on the gain mode of the variable gain amplifier configuration 310a. In a certain implementation, the multi-input gain stage 312 is configured to receive a number of signals at separate input ports. Each of the separate input ports is configured to receive a signal in one or more specific cellular frequency bands. For example, a signal in the first band is received at the first input port, a signal in the second band is received at the second input port, and a signal in the third band is received at the third input port. The variable gain amplifier 310a can be configured to provide multi-input processing without using a switching network. The variable gain amplifier 310a can be configured to achieve relatively high linearity through the use of the degeneration switching block 330. In a certain implementation, the bypass block 340 includes a shunt switch.

[0046] The shunt switch can provide high input-to-output isolation compared to configurations having such a switch. The variable gain amplifier 310a routes a signal from the input section through the bypass block ​​​​Direct it to pass through the lock 340 but not through the gain stage 320 to provide a low-loss direct bypass mode. The low-loss direct bypass mode can be configured, for example, to be implemented in a low-gain mode.

[0047] The variable gain amplifier 310a includes a multi-input gain stage 312 that supplies a voltage to the current gain stage 320. The multi-input gain stage 312 can be configured to provide isolation between the inputs. In some embodiments, the variable gain amplifier 310a can further separate the input sections by including a degeneration switching block 330 for each input section.

[0048] The degeneration switching block 330 is configured to provide an impedance to the input of the gain stage 320. In this way, the performance can be improved by providing power and / or noise that matches the previous stage in the processing chain. The degeneration switching block 330 can be configured to improve the linearity of the gain stage 320 by providing a feedback mechanism. In some embodiments, the degeneration switching block 330 is configured to provide a first impedance for a first gain mode and a second impedance for a second gain mode. The selected impedance provided by the degeneration switching block 330 can also be configured to improve the linearity of the gain stage 320. The variable gain amplifier 310a can be configured to bypass the degeneration switching block 330 in the bypass mode. In this way, the signal passing through the gain stage 320 Linear performance can be improved by reducing or minimizing leakage current.

[0049] The bypass block 340 is configured to receive signals from a number of input sections and provide a path to an output section that does not pass through the gain stage 32 0 or the degeneration switching block 330. The bypass block 340 may include components that serve to separate the input and output sections in one or more of the gain modes provided by the variable gain amplifier 310a.

[0050] The intermediate gain mode feedback block 350a is configured to be activated for a subset of the gain modes provided by the variable gain amplifier 310a. The intermediate gain mode feedback block 350a is configured to provide a target impedance to the input signal. This can help improve the linearity of the amplification process. The intermediate gain mode feedback block 350a can also be configured to control the feedback within the variable gain amplifier 310a. The intermediate gain mode feedback block 350a can be configured to provide functionality similar to including a second degeneration block in the circuit.

[0051] The bypass switch 360 is configured to selectively provide a path from the input section to the output section via the bypass block 340 or a path from the input section to the output section via the gain stage 320. The bypass switch 360 may include one or more switching elements that separate and / or select the desired path based at least in part on the gain mode of the variable gain amplifier 310a.

[0052] In certain embodiments, the variable gain amplifier 310a can be configured to provide a plurality of gain modes, such as gain modes G0, G1, …, GN. G0 is the highest gain, and GN is the bypass mode. When operating in the gain mode GN, the variable gain amplifier 31 0a can be configured to direct the signal from the input section to the bypass block 340. When operating in the gain modes G0 to GN−1, the variable gain amplifier 310a can be configured to activate the degeneration switching block 330 by directing the signal through the gain stage 32 . The degeneration switching block 330 can be configured to provide different impedance levels for individual gain modes or for multiple groups of gain modes. Even in these gain modes, the bypass block 340 can be made at least partially active by activating the shunt switch of the bypass block 340 to provide isolation between the input section and the output section. The variable gain amplifier 310a can be configured to activate the intermediate gain mode feedback block 350a for one or more of the gain modes G0 to GN−1.

[0053] The variable gain signal amplifier 310a can be configured to achieve relatively low noise and high linearity (e.g., higher IIP3) compared to an amplifier without the intermediate gain mode feedback block 35 0a, the bypass block 340, and the degeneration switching block 330 of the present disclosure. The variable gain signal amplifier 310a can be used for wireless frequency (R such as cellular signals, WLAN signals, BLUETOOTH® signals, GPS signals, etc. F) can be configured to amplify the signal. The variable gain signal amplifier 310a can receive signals over a plurality of frequency bands at a number of input sections and process the signals, thereby being configured to provide broadband performance. The variable gain signal amplifier 310a can be configured to process the signals at each input section independently. The variable gain signal amplifier 310a can be configured to be controlled by a control circuit assembly such as a controller (e.g., the controller 102 described herein with reference to FIGS. 1 and 2). The control circuit assembly can intelligently and selectively switch the path between the amplification path and the bypass path, and can selectively provide impedance by the degeneration switching block 330. Although three input sections are illustrated, it should be understood that the variable gain amplifier 310a can include any number of suitable input sections. For example, without limitation, the variable gain amplifier 310a can include at least two input sections, at least four input sections, at least eight input sections, at least

[0054] sixteen input sections, at least thirty-two input sections, at least sixty-four input sections, or at least any number within the range described. As another example and without limitation, the variable gain amplifier 310a can include sixty-four or fewer input sections, thirty-two or fewer input sections, sixteen or fewer inputs, eight or fewer, four or fewer input sections, or any number or fewer within the range described. eight or fewer, four or fewer input sections, or any number or fewer within the range described. eight or fewer, four or fewer input sections, or any number or fewer within the range described.

[0055] FIG. 3B illustrates another example variable gain amplifier 310b that includes the same components as the variable gain amplifier 310a of FIG. 3A with the addition of certain elements. For example, the variable gain amplifier 310 b includes matching networks 313, 318, and 345. The input matching network 313 is configured to provide impedance matching to the signal received at the input section. Similarly, the output matching network 318 is configured to provide impedance matching to the output load 316 and the amplifier including the gain stage 320 and the cascode buffer 314. The bypass matching network 345 is also configured to provide impedance matching to the bypass block 340. For the matching networks 313, 318, 345, any suitable combination of inductors and capacitors can be used to provide the targeted impedance. The variable gain amplifier 310b also includes the output load 316 and the cascode buffer 314 as part of the amplification chain. The cascode buffer 314 can be configured to act as a current buffer. The cascode buffer 314 is configured to provide isolation between the gain stage 320 and the output section. The cascode buffer 314 can also be configured to improve the gain of the variable gain amplifier 310b. The output load 316 is configured to apply a load to the current to generate an output voltage amplitude. The output load 316 can be configured to be tuned or tunable for each band received at the input section. The output load 316 can be configured to improve the reflection loss and / or increase the bandwidth by adjusting the resistance of the output load 316. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state.

[0056] amplifier 310b is in a certain gain state. The cascode buffer 314 can be configured to act as a current buffer. The cascode buffer 314 is configured to provide isolation between the gain stage 320 and the output section. The cascode buffer 314 can also be configured to improve the gain of the variable gain amplifier 310b. The output load 316 is configured to apply a load to the current to generate an output voltage amplitude. The output load 316 can be configured to be tuned or tunable for each band received at the input section. The output load 316 can be configured to improve the reflection loss and / or increase the bandwidth by adjusting the resistance of the output load 316. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state. The output load 316 is configured to apply a load to the current to generate an output voltage amplitude. The output load 316 can be configured to be tuned or tunable for each band received at the input section. The output load 316 can be configured to improve the reflection loss and / or increase the bandwidth by adjusting the resistance of the output load 316. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state. The output load 316 is configured to apply a load to the current to generate an output voltage amplitude. The output load 316 can be configured to be tuned or tunable for each band received at the input section. The output load 316 can be configured to improve the reflection loss and / or increase the bandwidth by adjusting the resistance of the output load 316. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state. The output load 316 can be configured to improve the reflection loss and / or increase the bandwidth by adjusting the resistance of the output load 316. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state. The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain amplifier 310b is in a certain gain state. For example, the voltage VDD can be such that the current flowing through the output load 316 is low when the variable gain ​It can be configured to respond to a decrease in the gain of the amplifier 310b.

[0057] FIG. 3C is similar to the variable gain amplifier 310a of FIG. 3A, but illustrates another variable gain amplifier example 310c excluding the bypass switch 360. Since the bypass switch 360 is absent, the output of the bypass block 340 is coupled to the output of the output section of the gain stage 320. Furthermore, the intermediate gain mode feedback block is replaced by the shutdown switch block 350c, but the shutdown switch block 350c is not coupled to the output section as in the variable gain amplifier 310a of FIG. 3A. Instead, the shutdown switch block 350c is configured to selectively isolate the input node so as to reduce leakage in the amplifier 310c. In some embodiments, this can be activated by activating a switch between the input node and the reference potential node when the input section is not in use. In various implementations, the switch can couple the input node to the reference potential node via a capacitive element.

[0058] FIG. 3D illustrates another variable gain amplifier example 310d that includes the same components as the variable gain amplifier 310c of FIG. 3C, along with the addition of certain elements. For example, the variable gain amplifier 31 0d includes matching networks 313, 318, and 345. The input matching network 31 3 is configured to provide impedance matching for the signal received at the input section. Similarly, the output matching network 318 is configured to provide impedance matching for the output load 316 and the amplifier including the gain stage 320 and the cascode buffer 314. ​ Similarly, bypass matching network 345 also provides impedance matching to bypass block 340. For matching networks 313, 318, and 345, any suitable combination of inductors and capacitors can be used to provide the desired impedance matching.

[0059] Variable gain amplifier 310d also includes output load 316 and cascode buffer 314 as part of the amplification chain. Cascode buffer 314 can be configured to act as a current buffer. Cascode buffer 314 is configured to provide isolation between gain stage 320 and the output. Cascode buffer 314 can also be configured to improve the gain of variable gain amplifier 310d. Output load 316 is configured to provide a load to the current to generate an output voltage amplitude. Output load 316 can be configured to be tuned or tunable for each band received at the input. Output load 316 can be configured to improve reflection loss and / or increase bandwidth by adjusting the resistance of output load 316. Voltage VDD can be configured to set the gain mode of variable gain amplifier 310d. For example, voltage VDD can be configured such that a decrease in the current flowing through output load 316 corresponds to a decrease in the gain of variable gain amplifier 310d.

[0060] FIG. 4 illustrates variable gain signal amplifier 410 including variable gain stage 420 configured to receive an input signal and generate an amplified output signal. Variable gain signal amplifier 410 also Also includes a degeneration switching block 430 coupled to the variable gain stage 420 . The degeneration switching block 430 can be configured to provide a plurality of different gain levels of the variable gain stage 420.

[0061] FIG. 5 illustrates a degeneration switching circuit 530 including a variable impedance stage 532 coupled to a signal amplifier 520 having various gain levels. The variable impedance stage 532 can be configured to provide various impedance values associated with various gain levels. The degeneration switching circuit 530 includes a switch 534 operably associated with the variable impedance stage 532. The switch 534 is implemented to selectively isolate the variable impedance stage 532 from the reference potential node . .

[0062] FIG. 6 illustrates a variable gain amplifier configuration example 610 configured similarly to the variable gain amplifier 310b described herein with reference to FIG. 3B. The variable gain amplifier 610 includes electrical component examples demonstrating implementation examples of the amplifier. However, this is merely an example of an implementation example , and it should be understood that the scope of the present disclosure extends to additional implementations including similar architectures .

[0063] The variable gain amplifier configuration 610 includes a multi-input gain stage 612 configured to receive inputs A, B, and C and selectively amplify the received signals by corresponding transistors Q3, Q 4, and Q5 in conjunction with a cascode buffer 614 having a transistor Q10. The multi-input gain stage 612 also includes switching transistors for each of the inputs A, B, and C . . ​​​To provide a bypass path through bypass block 340 including resistors Q6, Q7 and Q8. It is configured as follows.

[0064] The multi-input gain stage 612 is coupled to a degeneration switching block 630. The degeneration switching block 630 is Selectively providing a tailored impedance based at least in part on the gain mode. In certain implementations, the multi-input gain stage 612 is configured to have separate input ports. Each separate input port is configured to receive a number of signals at a single configured to receive signals in one or more specific cellular frequency bands. Input A receives signals in the first band, input B receives signals in the second band, and input C receives signals in the third band. In some embodiments, transistors Q3, Q4, and Q5 receive a signal in the band. Each has a dedicated degeneration switch to increase isolation between input ports. Each of these inputs can be coupled to a switching block 630. The FETs are coupled to inductors L4, L5 and L6 to provide phase matching.

[0065] The variable gain amplifier configuration 610 provides multi-input signals without the use of a switching network. The variable gain amplifier arrangement 610 can be configured to provide power processing. To achieve relatively high linearity through the use of a phase switching block 630 In certain implementations, the bypass block 640 can be configured to The shunt switch Q can provide higher input-to-output isolation compared to a configuration with a includes 9. The variable gain amplifier configuration 610 is configured to provide a low-loss direct bypass mode by directing a signal from the input section through the bypass block 640. This can be achieved by directing the signal through the bypass block 640 from the input section, providing a low-loss direct bypass mode. The low-loss direct bypass mode can be implemented, for example, in a low-gain mode.

[0066] The variable gain amplifier configuration 610 includes a multi-input gain stage that applies a voltage to a current gain stage including transistors Q3 to Q5. 612 The multi-input gain stage 612 is configured to apply a voltage to the current gain stage. Further, the multi-input gain stage 612 is configured to amplify each input signal in conjunction with a cascode buffer 614 including transistor Q10, and the cascode buffer 614 is configured to act as a current buffer that reduces the input impedance and increases the output impedance.

[0067] The degeneration switching block 630 is configured to apply an impedance to the gain stage of the multi-input gain stage 612. In this way, the performance can be improved by providing power and / or noise that matches the previous stage in the processing chain. The degeneration switching block 630 can be configured to improve the linearity of the gain stage (e.g., transistors Q3 to Q5) by providing a feedback mechanism. The degeneration switching block 630 can be configured to apply the first impedance L1 to the first gain mode by activating transistors Q2 and transistor Q1 respectively, and apply the second impedance obtained by L1 and L2 to the second gain mode. The degeneration switching block 630 can be configured to improve the linearity of the gain stage (e.g., transistors Q3 to Q5) by providing a feedback mechanism. The degeneration switching block 630 can be configured to apply the first impedance L1 to the first gain mode by activating transistors Q2 and transistor Q1 respectively, and apply the second impedance obtained by L1 and L2 to the second gain mode. The degeneration switching block 630 can be configured to apply the first impedance L1 to the first gain mode by activating transistors Q2 and transistor Q1 respectively, and apply the second impedance obtained by L1 and L2 to the second gain mode. ​The selected impedance provided by 0 can also be configured to improve the linearity of the gain stage. This can be done. The variable gain amplifier configuration 610 can be configured to bypass the degeneration switching block 630 in bypass mode. In this way by reducing or minimizing the leakage current passing through the gain stage, the linear performance can be improved. In a certain implementation, the degeneration switching block 630 can be configured to provide a low inductance in high gain mode. The amount of inductance provided by the degeneration switching block 630 can be changed according to the change of the gain mode of the variable gain amplifier configuration 610.

[0068] The bypass block 640 is configured to receive signals from multiple input parts and provide a path to an output part that does not pass through the gain stage (e.g., transistors Q3 - Q5) or the degeneration switching block 630. The bypass block 640 is configured to provide a single path to the output part via transistors Q11 and capacitor C1. The capacitor C1 can be configured to block the DC voltage from the output supply. The bypass block 640 also includes a shunt switch via transistor Q9 that selectively couples the bypass block 640 to the reference potential node to assist in separating the input part from the output part. The bypass block 640 is configured to provide a single path to the output part via transistors Q11 and capacitor C1. The capacitor C1 can be configured to block the DC voltage from the output supply. The bypass block 640 also includes a shunt switch via transistor Q9 that selectively couples the bypass block 640 to the reference potential node to assist in separating the input part from the output part. The bypass block 640 is configured to provide a single path to the output part via transistors Q11 and capacitor C1. The capacitor C1 can be configured to block the DC voltage from the output supply. The bypass block 640 also includes a shunt switch via transistor Q9 that selectively couples the bypass block 640 to the reference potential node to assist in separating the input part from the output part. The bypass matching network 645 can provide additional impedance matching flexibility. The bypass matching network 645 can provide additional impedance matching flexibility.

[0069] The intermediate gain mode feedback block 650 is provided by the variable gain amplifier configuration 610. It is configured to be activated for a subset of the gain modes. Intermediate gain mode f eedback block 650 is configured to provide a target impedance to the input signal. This can help improve the linearity of the amplification process. An RC matching network 651 can be used to control the amount of feedback in the system. Additionally, the RC matching network 651 can be configured to function as a block for DC voltage. The RC matching network 651 can be configured to control the feedback behavior of amplitude and phase. The RC matching network 651 can include a capacitor, a resistor, a series combination of a capacitor and a resistor, or any suitable combination of a capacitor, a resistor, and other components. The intermediate gain mode feedback block 65 0 can also be configured to control the feedback within the variable gain amplifier 610. The intermediate gain mode feedback block 650 can be configured to provide similar functionality as including a second generation block in the circuit.

[0070] When activated, the signals from input parts A, B, and C respectively enter the A intermediate gain feedback block 650 at points B and C and exit the block at point D . This point is coupled to the circuit prior to the output matching network 618 and the bypass D switch 6 60. In other words, the intermediate gain mode feedback block 650 couples each of input parts A, B, and C to transistors Q14~Q16 and Q18. It can be coupled to the output section via. The additional transistor Q17 can be configured to provide a shunt switch to the reference potential node in the same manner as the bypass block 640. The point can be configured to be positioned at the end of the output matching network 618, within the output matching network D 618, or after the output matching network 618. The intermediate gain mode feedback block 650 can be configured to generate a cancellation of the input and output, so the point can be positioned within the variable gain amplifier configuration 610 to improve performance. The bypass switch 660 is configured to selectively provide a path from the input sections A, B, and C to the output section via the bypass block 640, or a path from the input sections A, B, and C to the output section via the gain stage elements and amplifier elements (e.g., the cascode buffer 614 and the output matching network 618). The bypass switch 660 includes a transistor Q12 that controls the connection between the amplification path and the output section, and a transistor Q D 13 that controls the connection between the bypass path and the output section. The bypass switch 660 can be controlled at least partially based on the gain mode of the variable gain amplifier 610.

[0071]

[0072] The matching networks 618 and 645 can include any suitable combination of inductors and capacitors that can be used to provide a target impedance. The output matching network 618 provides impedance matching to the output load 616 and the amplifier including the gain stage (e.g., transistors Q3 - Q5) and the cascode buffer 614. It is configured. Similarly, the bypass matching network 645 provides impedance matching for the bypass block 640. to provide impedance matching.

[0073] The variable gain amplifier 610 includes an output load 616 and a cascode buffer 614 as part of the amplification path. The cascode buffer 614 includes a transistor Q10 configured to act as a current buffer. The cascode buffer 614 is configured to provide isolation between the gain stage and the output section. The cascode buffer 614 can also be configured to improve the gain of the variable gain amplifier 610. The output load 616 is configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. configured to include a transistor Q10 configured to act as a current buffer. The cascode buffer 614 is configured to provide isolation between the gain stage and the output section. The cascode buffer 614 can also be configured to improve the gain of the variable gain amplifier 610. The output load 616 is configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. configured to include a transistor Q10 configured to act as a current buffer. The cascode buffer 614 is configured to provide isolation between the gain stage and the output section. The cascode buffer 614 can also be configured to improve the gain of the variable gain amplifier 610. The output load 616 is configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. configured to include a transistor Q10 configured to act as a current buffer. The cascode buffer 614 is configured to provide isolation between the gain stage and the output section. The cascode buffer 614 can also be configured to improve the gain of the variable gain amplifier 610. The output load 616 is configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. 10 can also be configured to improve the gain of the variable gain amplifier 610. The output load 616 is configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. configured to provide an additional current to generate an output voltage amplitude. The output load 616 can be configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. configured to be tuned or tunable for each band received at the input section. For example, the output load includes a variable capacitor C2 that is tunable for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. For example, the output load can be tuned for a specific cellular frequency band. The output load 616 can also be configured to improve reflection loss and / or increase bandwidth by varying the resistance R1 of the output load 616. By varying the resistance R1 of the output load 616, the output load 616 can be configured to improve reflection loss and / or increase bandwidth. can also be done.

[0074] The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD can be configured such that a decrease in the current flowing through the output load 316 corresponds to a decrease in the gain of the variable gain amplifier 310b. For example, the voltage VDD can be configured such that a decrease in the current flowing through the output load 316 corresponds to a decrease in the gain of the variable gain amplifier 310b. The voltage VDD can be configured such that a decrease in the current flowing through the output load 316 corresponds to a decrease in the gain of the variable gain amplifier 310b.

[0075] Figures 7A - 7C illustrate multiple examples of the operating modes of the variable gain signal amplifier configuration 610 of FIG. 6. FIG. 7A illustrates the operation in one or more high - gain modes. These high - gain modes Figures 7A - 7C illustrate multiple examples of the operating modes of the variable gain signal amplifier configuration 610 of FIG. 6. FIG. 7A illustrates the operation in one or more high - gain modes. These high - gain modes In the DO, the bypass block 640 is deactivated except for the shunt switch Q9. The signals received at the input sections A, B, and C are directed to pass through the gain stage including transistors Q3 to Q5 and through the cascode buffer 614, and reach the output section through the output matching network 618 and the bypass switch 660. The bypass switch activates Q12 and deactivates Q13 in these high-gain modes. Furthermore, in these high-gain modes, since the transistor Q2 is turned on and the transistor Q1 is turned off, the inductance provided to the gain stage through the degeneration switching block 630 is L1. In these high-gain modes, the intermediate gain mode feedback block 650 is also deactivated.

[0076] Figure 7B illustrates the operation in one or more intermediate gain modes. These modes can also be referred to as low-gain high-linearity modes. The operation in these intermediate gain modes is similar to the operation of one or more high-gain modes with significant differences. First, in the degeneration block 630, since the transistor Q2 is turned off and the transistor Q1 is turned on, the inductance provided to the gain stage through the degeneration switching block 630 is provided by both L1 and L2. Therefore, an increased impedance is obtained when the gain mode is low, or a decreased impedance is obtained when the gain mode is high. Second, the intermediate gain mode feedback block 650 is activated. As a result, additional feedback to the circuit is obtained, similar to adding a second degeneration block.

[0077] FIG. 7C illustrates the operation in one or more low-gain modes. In these low-gain modes the bypass block 640 is activated and the gain stage transistors Q3 - Q5 are deactivated. The signals received at the input sections A, B, and C are directed to the output section through the bypass block 640, through the bypass matching network 645 and the bypass switch 660. In these low-gain modes, the bypass switch activates Q13 and deactivates Q12. Further, transistors Q1 and Q2 are turned off to deactivate the degeneration switching block 630 and improve the linear performance by reducing or minimizing the leakage current through the gain stage transistors Q3 - Q5. The intermediate gain mode feedback block 650 is also deactivated in these low-gain modes.

[0078] FIG. 8 illustrates a variable gain signal amplifier configuration 810 similar to the variable gain signal amplifier configuration 610 of FIG. 6, but excluding the bypass switch 660. Excluding the bypass switch causes the output of the bypass matching network 645 to be coupled instead to the input node of the output matching network 618. In this configuration, there is no bypass switch to control the selection of the amplification path or the bypass path. Instead, the selected transistors of the gain stage (e.g., transistors Q3 - Q5), and the selected transistors of the bypass block (e.g., transistors Q6 - Q8) are selectively activated and deactivated to provide the bypass path or the amplification path.

[0079] ​​​​​​​​​​​​​FIG. 9 is similar to the variable gain signal amplifier configuration 610 of FIG. 6, but with an intermediate gain mode feed back module replaced by a shutdown switch block 950, illustrating a variable gain signal amplifier 910. In this configuration, since the shutdown switch block 950 is not coupled to the amplification path at the output node of the output matching network 618, point D is excluded. Instead, the shutdown switch block 950 includes transistors Q14 - Q16 and capacitors C3 - C5 configured to selectively isolate input nodes A, B, and C. In some embodiments, the shutdown switch block 950 does not include capacitors C3 - C5. The shutdown switch block 950 can be configured to turn on the switch (e.g., activate the transistor) when the corresponding input section is not in use. This can be done to shut off the input section with respect to ground to reduce or eliminate leakage in the amplifier configuration.

[0080] FIG. 10 is similar to the variable gain signal amplifier configuration 910 of FIG. 9, but illustrates a variable gain signal amplifier 1010 with bypass switch 6 60 excluded. Similar to the variable gain signal amplifier 8 10 of FIG. 8, the exclusion of the bypass switch results in the output of the bypass matching network 6 45 being coupled to the input node of the output matching network 618. In this configuration, there is no bypass switch to control the selection of the amplification path or the bypass path. Instead, the selected transistors of the gain stage (e.g., transistors Q3 - Q5), and the selected transistors of the bypass block (e.g., transistors Q6 - Q8) are such that the bypass path is... The amplifiers are selectively activated and deactivated to provide either a passive or an amplifying path.

[0081] Example Products and Architectures

[0082] FIG. 11 illustrates, in some embodiments, a combination of features (e.g., FIGS. 1-10). Diversity receiver configurations including some or all of the diversity receiver configurations having Some or all of the above may be implemented in whole or in part in modules. The module may be, for example, a front-end module (FEM). The module may be, for example, a diversity receiver (DRx) FEM. The module may be, for example, a multiple input, multiple output (MiMo) module.

[0083] In the example of FIG. 11, module 1108 includes a package substrate 1101. A certain number of components are mounted on the package board 1101. For example, controller 1102 (which may include an end-end power management integrated circuit [FE-PIMC]), Assembly 1106, a gain stage 1120 having one or more features described herein, and a delay a variable gain amplifier assembly 1110 including a generation switching block 1130; and a filter bank 1108 (which may include one or more bandpass filters) in a package. Mounted and / or mounted on and / or within the package substrate 1101 Other components, such as a certain number of SMT devices 1105, can be packaged. All of the various components can be mounted on a package board 1101. Although depicted as laid out on a printed circuit board 1101, certain components It is understood that a component can also be implemented on top of other components.

[0084] FIG. 12 shows, in some embodiments, some or all of a diversity receiver configuration that includes some or all of the combinations of features (e.g., FIGS. 1-10) can be implemented, in whole or in part, in an architecture. Such an architecture can include one or more modules and can be configured to provide front-end functions such as a diversity receiver (DRx) front-end function. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In some implementations, a device and / or circuit having one or more of the features described herein can be included in an RF electronic device such as a wireless device. Such devices and / or circuits can be implemented directly in a wireless device, in the modular forms described herein, or in certain combinations thereof. In some embodiments, such

[0085] In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208. In the example of FIG. 12, architecture 1208 includes a controller 1202 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 1206, a gain stage 1220 having one or more of the features described herein, and a variable gain amplifier assembly 1210 including a degeneration switching block 1230, and a filter bank 1208 (which may include one or more bandpass filters) can be mounted and / or implemented on and / or within a package substrate 1201. A number of other components, such as a number of SMT devices 1205, can also be implemented in architecture 1208.

[0086] In some implementations, a device and / or circuit having one or more of the features described herein can be included in an RF electronic device such as a wireless device. Such devices and / or circuits can be implemented directly in a wireless device, in the modular forms described herein, or in certain combinations thereof. In some embodiments, such In some implementations, a device and / or circuit having one or more of the features described herein can be included in an RF electronic device such as a wireless device. Such devices and / or circuits can be implemented directly in a wireless device, in the modular forms described herein, or in certain combinations thereof. In some embodiments, such In some implementations, a device and / or circuit having one or more of the features described herein can be included in an RF electronic device such as a wireless device. Such devices and / or circuits can be implemented directly in a wireless device, in the modular forms described herein, or in certain combinations thereof. In some embodiments, such In some implementations, a device and / or circuit having one or more of the features described herein can be included in an RF electronic device such as a wireless device. Such devices and / or circuits can be implemented directly in a wireless device, in the modular forms described herein, or in certain combinations thereof. In some embodiments, such The wireless device may include, for example, a mobile phone, a smartphone, a handheld wireless device with or without a telephone function, a wireless tablet, etc.

[0087] FIG. 13 depicts a wireless device example 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, such modules are generally depicted by the dashed enclosure 1306 (which may be implemented as a front-end module, for example), and the diversity receiver (DRx) module 1308 (which may be implemented as a front-end module, for example).

[0088] Referring to FIG. 13, a plurality of power amplifiers (PAs) 1382 can each receive an RF signal from the transceiver 130 4. The transceiver 1304 can be configured and operate to generate an RF signal to be amplified and transmitted, and to process the received signal. The transceiver 1304 is shown to interact with a baseband subsystem 130 5 configured to provide a conversion between data and / or voice signals suitable for the user and RF signals suitable for the transceiver 1304. The transceiver 1304 can also communicate with a power management component 1307 configured to manage power for the operation of the wireless device 1300. Such power management can also control the operation of the baseband subsystem 1305 as well as the modules 1306 and 1308.

[0089] The baseband subsystem 1305 interfaces with a user interface 1301 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. is shown to be connected. The baseband subsystem 1305 is also configured to facilitate the operation of the wireless device and / or provide information storage for the user, and is also connected to the memory 1 303. The memory 1303 is configured to store data and / or instructions.

[0090] In the wireless device example 1300, the output of the PA 1382 is routed (through each matching circuit 1384) to each duplexer 1386 after being matched. Such amplified and filtered signals can be routed through the switching network 1309 to the next antenna 1360 for transmission purposes. In some embodiments, the duplexer 1386 may allow for simultaneous transmission and reception operations using a common antenna (e.g., the primary antenna 1360). In FIG. 13, the received signal is shown to be routed to a variable gain amplifier assembly 1310a that provides the features and benefits of the variable gain amplifier shown herein. The DRx module 1308 also includes a similar variable gain amplifier assembly 1310b.

[0091] In the wireless device example 1300, the signal received at the primary antenna 1360 can be sent to the variable gain amplifier 1310a of the front-end module 1306. The variable gain amplifier 1310a may include a gain stage 1320 and a regeneration switching block 13 30. The variable gain amplifier 1310a is configured to receive a plurality of signals at an input section 1311 and output a plurality of processed signals at an output section 1319. The variable gain amplifier 1310a is configured to amplify the signal based at least in part on the gain mode. ​​​​​​​​​​​​​​and a degeneration switching block based at least in part on the gain mode configured to provide a target impedance via 330. This is compared to a variable gain amplifier that does not include one or more of the features described herein and can be done to improve the linearity of the signal. In at least one low gain mode, the gain stage 1320 and the degeneration switching block 1330 may be bypassed. In at least one non-low gain mode, additional feedback can be provided to the variable gain amplifier 1310a to improve the linearity of the amplification process, such as via the intermediate gain mode feedback module described herein

[0092] The wireless device also includes a diversity antenna 1370 and a diversity receiver module 1308 that receives signals from the diversity antenna 1370. The diversity receiver module 1308 includes a variable gain amplifier 1310b similar to the variable gain amplifier 1310a in the front-end module 1306. The diversity receiver module 1308 and the variable gain amplifier 1310b process the received signal and transmit the processed signal to the transceiver 1304. In some embodiments, a diplexer, triplexer, or other multiplexer or filter assembly can be included between the diversity antenna 1370 and the diversity receiver module 1370 as described herein

[0093] One or more features of the present disclosure can be implemented with the various cellular frequency bands described herein Examples of such bands are listed in Table 1. It is understood that at least some of the bands​​​​​​​​ At least some can be divided into sub-bands. It is also understood that one or more features of the present disclosure can be implemented with a frequency range that does not have a designation such as that of the example in Table 1. The terms radio frequency (RF) and radio frequency signal are understood to refer to signals including at least the frequencies listed in Table 1. **Table 1**

[0094] Throughout this specification and the claims, unless the context clearly dictates otherwise, words such as "comprising", "including", etc. are to be construed in an inclusive sense opposed to an exclusive or exhaustive sense, that is, in the sense of "including but not limited to". Here, the word "coupled" generally used refers to two or more elements that can be either directly connected or connected through one or more intermediate elements. In addition, the words "here", "above", "below" and words of a similar import, when used in this application, refer to the whole of this application and not to any particular part of this application. Where the context permits, the words in the above description of a given embodiment using the singular or plural may each also include the plural or singular. The words "or" and "alternatively" referring to a list of two or more items cover all of the following interpretations of the word. That is, any item in the list, all items in the list, and any combination of items in the list.

[0095] The above detailed description of embodiments of the invention is not exclusive, that is, the invention is not limited to the above disclosure ​It is not intended to be limited to the exact form. Specific embodiments of the invention and its examples are presented for illustration as described above for the purpose, but as will be recognized by those skilled in the art, various equivalent modifications are possible within the scope of the invention. For example, although a process or block is presented in a given order, alternative embodiments can perform a routine having steps in a different order or use a system having blocks, and some processes or blocks can be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different manners. Also, although a process or block may be shown to be performed serially, these processes or blocks can instead be performed in parallel or at different times. The teachings of the invention provided herein are not necessarily limited to the systems described above and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments.

[0096] Some embodiments of the invention have been described, but these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the forms of the methods and systems described herein can be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure. The various embodiment elements and acts described above can be combined to provide further embodiments.

[0097] Some embodiments of the invention have been described, but these embodiments are presented as examples only and are not intended to limit the scope of the disclosure There is no intention to limit the scope of the disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the forms of the methods and systems described herein can be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure. The novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the forms of the methods and systems described herein can be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure. The various omissions, substitutions, and changes in the forms of the methods and systems described herein can be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure. It is intended that the appended claims and their equivalents cover such forms or modifications that fall within the scope and spirit of the disclosure.

Claims

1. A configuration of a variable gain amplifier, comprising: A multi-input gain stage including a plurality of input nodes and gain stage transistors corresponding to each input node; A cascode buffer including cascode transistors coupled to the plurality of gain stage transistors, wherein a combination of the cascode buffer and a corresponding gain stage transistor provides an amplification path for selectively amplifying an input signal received at a corresponding input node to an output node, the cascode buffer; A bypass block including bypass transistors corresponding to each input node and shunt transistors; Including; The bypass block is configured to provide a bypass path for bypassing the plurality of gain stage transistors and the cascode buffer to the output node.

2. The configuration of claim 1, further comprising a degeneration switching block coupled to the multi-input gain stage, the degeneration switching block being configured to selectively provide an impedance configured at least partially based on a gain mode of the configuration of the variable gain amplifier.

3. The degeneration switching block includes a first inductor, a second inductor, a first transistor, and a second transistor; The configuration of claim 2, wherein the degeneration switching block is configured to operate the first transistor and the second transistor to provide the configured impedance.

4. The configuration of claim 1, wherein the multi-input gain stage further includes an inductor coupled between each input node and the corresponding gain stage transistor.

5. Further including a plurality of degeneration switching blocks; The configuration of claim 1, wherein each input node is coupled to a corresponding degeneration switching block configured to selectively provide an impedance configured at least partially based on a gain mode of the configuration of the variable gain amplifier.

6. The configuration of claim 1, further comprising a bypass matching network coupled between the output node and the bypass block to provide impedance matching.

7. The configuration of claim 1, further comprising a bypass switch configured to selectively provide the bypass path and the amplification path.

8. The bypass switch according to claim 7 includes a first transistor that controls the connection of the bypass path to the output node and a second transistor that controls the connection of the amplification path to the output node.

9. The configuration according to claim 1, wherein separate input nodes are configured to receive signals in separate cellular frequency bands from other input nodes.

10. The configuration according to claim 9, wherein the amplification path is configured to amplify a signal received at a separate input port independently of the amplification of other received signals.

11. The configuration according to claim 1, wherein in bypass mode, each of the plurality of gain stage transistors is configured to be turned off and each of the plurality of bypass transistors is configured to be turned on.

12. The configuration according to claim 1, wherein in amplification mode, each of the plurality of gain stage transistors is configured to be turned on, each of the plurality of bypass transistors is configured to be turned off, and the shunt transistor is configured to be turned on.

13. A front-end module, a package substrate configured to receive a plurality of components, a variable gain amplifier assembly mounted on the package substrate and includes, the variable gain amplifier assembly includes a multi-input gain stage including a plurality of input nodes and gain stage transistors corresponding to each input node, the variable gain amplifier assembly further includes a cascode buffer including cascode transistors coupled to the plurality of gain stage transistors, a combination of the cascode buffer and a corresponding gain stage transistor is configured to provide an amplification path that selectively amplifies an input signal received at a corresponding input node to an output node, the variable gain amplifier assembly further includes a bypass block including bypass transistors corresponding to each input node and a shunt transistor, the bypass block is configured to provide a bypass path that bypasses the plurality of gain stage transistors and the cascode buffer to the output node, a front-end module.

14. further includes a filter assembly mounted on the package substrate, The front-end module of claim 13, wherein the filter assembly is coupled to the variable gain amplifier assembly to direct a frequency band to select inputs of the plurality of input nodes.

15. Further comprising a controller mounted on the package substrate, The controller is configured to control the variable gain amplifier assembly to provide a plurality of gain modes, The front-end module of claim 13, wherein in bypass mode, the bypass path is activated and the amplification path is deactivated.

16. The front-end module of claim 13, wherein the variable gain amplifier assembly further includes a degeneration switching block coupled to the multi-input gain stage, the degeneration switching block being configured to selectively provide an impedance configured at least in part based on the gain mode of the variable gain amplifier assembly.

17. The variable gain amplifier assembly further includes a plurality of degeneration switching blocks, The module of claim 13, wherein each input node is coupled to a corresponding degeneration switching block configured to selectively provide an impedance configured at least in part based on the gain mode of the variable gain amplifier assembly.

18. A wireless device, A diversity antenna, A filter assembly coupled to the diversity antenna to receive a signal and direct a frequency band along a selected path, A variable gain amplifier assembly including a multi-input gain stage including a plurality of input nodes and gain stage transistors corresponding to each input node, A controller Including, The variable gain amplifier assembly further includes a cascode buffer including cascode transistors coupled to a plurality of the gain stage transistors, The combination of the cascode buffer and the corresponding gain stage transistor is configured to provide an amplification path to an output node that selectively amplifies an input signal received at the corresponding input node, The variable gain amplifier assembly further includes a bypass block including a bypass transistor and a shunt transistor corresponding to each input node, the bypass block is configured to provide a bypass path to the output node that bypasses the plurality of gain stage transistors and the cascode buffer; the controller is configured to control the variable gain amplifier assembly to provide a plurality of gain modes; In a bypass mode, the wireless device activates the bypass path and deactivates the amplification path.

19. 20. The wireless device of claim 18, wherein the variable gain amplifier assembly further includes a degeneration switching block coupled to the multi-input gain stage, the degeneration switching block configured to selectively provide a tailored impedance based at least in part on a gain mode of the variable gain amplifier assembly.

20. the variable gain amplifier assembly further includes a plurality of degeneration switching blocks; 20. The wireless device of claim 18, wherein each input node is coupled to a corresponding degeneration switching block configured to selectively provide a tailored impedance based at least in part on a gain mode of the variable gain amplifier assembly.

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