Multilayer Wiring Substrate and Method for Manufacturing Multilayer Wiring Substrate

Abstract

To provide a multilayer wiring board and a method for manufacturing a multilayer wiring board, capable of suppressing cracks and disconnections in the multilayer wiring board even after joining to a FC-BGA substrate, the multilayer wiring board being formed on a support 1.SOLUTION: A wiring board includes a first layer having a first interlayer connecting conductor 36 and a second layer having a second interlayer connecting conductor 36. The first interlayer connecting conductor and the second interlayer connecting conductor are embedded in an insulating resin forming the respective first and second layers through a seed adhesion layer, the first and second interlayer connecting conductors being joined to each other through a seed adhesion layer. The top and bottom of each of the first layer and the second layer are coated with an inorganic insulating film 7 except for portions where the first and second interlayer connecting conductors are connected to each other or to other connecting conductor.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a multilayer wiring board and a method for manufacturing the multilayer wiring board.

Background Art

[0002] In recent years, as semiconductor devices have been advancing in high speed and high integration, for FC-BGA (Flip Chip-Ball Grid Array) substrates on which semiconductor elements are mounted, there is a demand for reducing the pitch of bonding terminals with semiconductor elements and miniaturizing the wiring within the substrate. On the other hand, the bonding between the FC-BGA substrate and the motherboard is required to be performed with bonding terminals having substantially the same pitch as in the prior art. In order to cope with such a reduction in the pitch of bonding terminals with semiconductor elements and the accompanying miniaturization of wiring within the FC-BGA substrate, a technique has been adopted in which a multilayer wiring board including fine wiring, also called an interposer, is provided between the FC-BGA substrate and the semiconductor element. One of them is the silicon interposer technology in which an interposer is formed on a silicon wafer using semiconductor circuit manufacturing technology. In addition, a method has been developed in which instead of forming an interposer on a silicon wafer, it is directly fabricated on the FC-BGA substrate. This is a method in which the surface of the FC-BGA substrate is planarized by CMP (Chemical Mechanical Polishing) or the like, and a multilayer wiring board serving as an interposer is directly formed on the FC-BGA substrate. This is disclosed in Patent Document 1. Furthermore, there is also a method in which an interposer (multilayer wiring board) is formed on a support such as a glass substrate, mounted on the FC-BGA substrate, and then the support substrate is peeled off to form a narrow pitch multilayer wiring board on the FC-BGA substrate. This is disclosed in Patent Document 2.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] Since a silicon interposer is manufactured using a silicon wafer and equipment for pre-processes in semiconductor manufacturing, it is suitable for forming fine wiring layers. However, silicon wafers have limitations in shape and size, the number of interposers that can be manufactured from a single wafer is small, and manufacturing equipment is also expensive. Therefore, interposers are also expensive. In addition, since silicon wafers are semiconductors, there is a problem that transmission characteristics also deteriorate.

[0005] Also, in a method of planarizing the surface of an FC-BGA substrate and forming a multilayer wiring layer serving as an interposer thereon, the deterioration of transmission characteristics seen in silicon interposers is small. However, there are problems such as low overall manufacturing yield because the manufacturing yield of the FC-BGA substrate itself and the difficulty of forming fine wiring formed on the FC-BGA substrate are high. Furthermore, there are also problems in mounting semiconductor elements due to warping and distortion of the FC-BGA substrate.

[0006] Furthermore, in a method of forming a multilayer wiring board on a support such as a glass substrate, placing this on an FC-BGA substrate, and then peeling off the support, a semi-additive method is often used when forming a multilayer wiring layer on the support. However, the photosensitive resin layer used in the semi-additive method does not contain a filler, and compared with an underfill layer and a solder resist layer containing a filler used in later processes, it has a low elastic modulus and a large CTE tendency. Therefore, only the photosensitive resin layer is greatly deformed during heating, and the substrate is likely to warp. In particular, stress concentrates at the connection portion between the via portion and the land portion that serves as the interlayer connection of the multilayer wiring on the side connected to the FC-BGA substrate. Starting from the connection portion between the via portion and the land portion, cracks occur in the resin layer, and further, due to the progression of these cracks, there is a problem that the connection between the via portion and the land portion is disconnected. In addition, due to this warping caused by heat, there is also a problem that the photosensitive resin peels off from the side surface or the upper surface of the land portion.

[0007] Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer wiring substrate capable of suppressing cracks and disconnection in the multilayer wiring substrate even after bonding to an FC-BGA substrate, and a method for manufacturing the multilayer wiring substrate, for a multilayer wiring substrate formed on a support.

Means for Solving the Problems

[0008] In order to solve the above problems, one of the typical multilayer wiring substrates of the present invention has a first layer having a first interlayer connection conductor and a second layer having a second interlayer connection conductor. The first interlayer connection conductor and the second interlayer connection conductor are each embedded in an insulating resin forming the first layer and the second layer via a seed adhesion layer. The first interlayer connection conductor and the second interlayer connection conductor are joined to each other via a seed adhesion layer. The upper and lower surfaces of the first layer and the second layer are covered with an inorganic insulating film except for the portions where the first interlayer connection conductor and the second interlayer connection conductor are connected to each other or to other connection conductors.

[0009] Further, one of the manufacturing methods of the typical multilayer wiring substrate of the present invention includes a step of forming an inorganic insulating film layer, and a step of forming a pattern of a first photosensitive resin having a first opening on the inorganic insulating film layer. A step of forming a pattern of a second photosensitive resin having a second opening with a larger opening diameter than that of the first opening above the first photosensitive resin; a step of removing an inorganic insulating film layer within the first opening; a step of forming a seed adhesion layer and a seed layer at ends of the pattern of the first opening, the first photosensitive resin, and the second photosensitive resin; a step of forming an electrolytic copper plating layer on the seed layer; and a step of polishing the electrolytic copper plating layer, the seed layer, and the seed adhesion layer until the second photosensitive resin pattern is exposed.

Advantages of the Invention

[0010] According to the present invention, it becomes possible to provide a multilayer wiring board capable of suppressing cracks and disconnections in the multilayer wiring board and a method for manufacturing the multilayer wiring board. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0012] Hereinafter, with reference to FIGS. 1 to 8, an example of a multilayer wiring board and its manufacturing process according to an embodiment of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0013] Also, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as the following. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

[0014] In the present disclosure, the "surface" may refer not only to the surface of a plate-like member but also to the interface of a layer included in the plate-like member that is substantially parallel to the surface of the plate-like member. Further, the "upper surface" and "lower surface" mean the surface shown above or below in the drawing when the plate-like member or the layer included in the plate-like member is illustrated. Further, the "side surface" means the surface or the thickness portion of the layer in the plate-like member or the layer included in the plate-like member. Furthermore, the part of the surface and the side surface may be collectively referred to as the "end portion". Further, the "upper direction" means the vertically upward direction when the plate-like member or the layer is placed horizontally. Furthermore, the "upper direction" and the opposite "lower direction" may be referred to as the "Z-axis direction", and the horizontal direction may be referred to as the "X-axis direction" and the "Y-axis direction". Further, the "planar shape" and "plan view" mean the shape when the surface or the layer is viewed from above. Furthermore, the "cross-sectional shape" and "cross-sectional view" mean the shape when the plate-like member or the layer is viewed from the horizontal direction after being cut in a specific direction. Furthermore, the "central portion" means the central portion that is not the peripheral portion of the surface or the layer. And the "central direction" means the direction from the peripheral portion of the surface or the layer toward the center in the planar shape of the surface or the layer.

[0015] The multilayer wiring board 30 of this embodiment can be connected to a semiconductor element on the first surface and can be connected to another wiring board on the second surface. First, as shown in FIG. 1, the entire semiconductor device 18 manufactured using the multilayer wiring board 30 of this embodiment will be described. In FIG. 1, a semiconductor element 17 is bonded to the upper surface of the multilayer wiring board 30, and an FC-BGA substrate 14 is bonded to the lower surface of the multilayer wiring board 30, and these are integrated to form the semiconductor device 18.

[0016] The semiconductor element 17 is bonded to the multilayer wiring board 30 at the solder joint 25 and then is sealed and fixed by the sealing resin 26. Further, the semiconductor element 17 is bonded to the FC-BGA substrate 14 at the solder joint 27 and then is sealed and fixed by the sealing resin 28. As will be described later, the multilayer wiring board 30 is formed above the support 1 with the release layer 2 interposed therebetween, and after being joined to the FC-BGA substrate 14, the support 1 is removed by peeling off with the release layer.

[0017] The semiconductor element 17 may be joined to the multilayer wiring board 30 after the multilayer wiring board 30 is joined to the FC-BGA substrate 14, or may be joined to the multilayer wiring board 30 before the multilayer wiring board 30 is joined to the FC-BGA substrate 14. In the description of the following embodiments, an aspect in which the semiconductor element 17 is joined to the multilayer wiring board 30 after the multilayer wiring board 30 is joined to the FC-BGA substrate 14 will be described.

[0018] Next, with reference to FIGS. 2 to 11, the configuration and manufacturing method of the multilayer wiring board 30 will be described. FIG. 2 is a cross-sectional view showing a state in which a release layer 2, a photosensitive resin 3, a seed adhesion layer 4, a seed layer 5, and a conductor layer 6 are formed above the support. Hereinafter, the steps for obtaining the configuration of FIG. 2 will be sequentially described.

[0019] (1) Formation of the release layer 2 on the upper surface of the support 1 Since the support 1 may be irradiated with light through the support 1 to the release layer 2 in some cases, it is advantageous to have light transmittance. For example, rectangular glass can be used. The rectangular glass is suitable for increasing the size, and the glass has excellent flatness and high rigidity, so it is suitable for forming a fine pattern on the support. In addition, since glass has a small coefficient of thermal expansion (CTE) and is less likely to be distorted, it is excellent in ensuring pattern arrangement accuracy and flatness. When glass is used as the support 1, the thickness of the glass is preferably large from the viewpoint of suppressing the occurrence of warpage in the manufacturing process, for example, a thickness of 0.5 mm or more, preferably 1.2 mm or more.

[0020] Furthermore, the CTE of the glass is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm from the viewpoint of compatibility with the CTE of the FC-BGA substrate 14 and the semiconductor element 17. On the one hand, when the support 1 does not require light transmissibility when peeling off the support 1, for example, by using a resin that foams by heat for the release layer 2, the support 1 can be made of, for example, metal or ceramics with little distortion. Hereinafter, in one embodiment of the present invention, an example will be described in which a resin that absorbs UV light and becomes peelable is used as the release layer 2, and glass is used for the support 1.

[0021] The release layer 2 may be, for example, a resin that absorbs light such as UV light to generate heat or becomes peelable by alteration, or a resin that foams by heat and becomes peelable. Further, the release layer 2 may contain additives such as a photodegradation accelerator, a light absorber, a sensitizer, and a filler.

[0022] Furthermore, the release layer 2 may be composed of a plurality of layers. For example, for the purpose of protecting the multilayer wiring layer formed on the support 1 in a later process, a protective layer may be further provided on the release layer 2, or a layer for improving the adhesion to the support 1 may be provided under the release layer 2. Further, a laser light reflection layer or a metal layer may be provided between the release layer 2 and the multilayer wiring layer, and its configuration is not limited by this embodiment. In addition, when a resin that can be peeled off by light such as UV light, for example, laser light, is used as the release layer 2, if the support 1 is translucent, the direction of irradiating the release layer 2 with light may be to irradiate the support 1 with light from the surface on the side opposite to the side where the release layer 2 is provided.

[0023] <L (2) Formation of the photosensitive resin layer 3 on the upper surface of the release layer 2 After forming the release layer 2 on the upper surface of the support 1, the photosensitive resin layer 3 is formed on the upper surface of the release layer 2. In this embodiment, as the photosensitive resin layer 3, for example, a photosensitive epoxy resin is formed by the spin coating method.

[0024] (3) Patterning of the photosensitive resin 3 Next, an opening is provided in the photosensitive resin layer 3 by photolithography. Plasma treatment may be performed on the opening for the purpose of removing residues during development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the opening, and is, for example, 8 μm in one embodiment of the present invention. Also, the shape of the opening in plan view is set according to the pitch and shape of the bonding electrodes of the semiconductor element. In one embodiment of the present invention, for example, the opening shape is φ25 μm and the pitch is 55 μm.

[0025] (4) Formation of the seed adhesion layer 4 and the seed layer 5 Next, in a vacuum, the seed adhesion layer 4 and the seed layer 5 are formed. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and is a layer that prevents the peeling of the seed layer 5. The seed layer 5 acts as a power supply layer for electrolytic plating in wiring formation. The seed adhesion layer 4 and the seed layer 5 are formed, for example, by sputtering, evaporation, or the like. For example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloys, or combinations of these can be applied. In the present invention, considering electrical characteristics, ease of manufacturing, and cost, a titanium layer is formed on the seed adhesion layer 4 by sputtering, and then a copper layer of the seed layer 5 is sequentially formed. The total film thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are adopted.

[0026] (5) Formation of the conductor layer 6 Next, a conductor layer 6 is formed by electrolytic plating above the seed layer 5. The conductor layer 6 serves as an electrode for bonding with the semiconductor element 17. Options for electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. Among them, electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is desirably 1 μm or more and 30 μm or less from the viewpoint of productivity, taking into account that the conductor layer 6 serves as an electrode for bonding with the semiconductor element 17 and is solder-bonded. In one embodiment of the present invention, Cu: 10 μm is formed in the opening of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0027] The configuration of FIG. 2 can be obtained by such a process. Next, the following process is performed to obtain the configuration of FIG. 3. (6) Polishing of the conductor layer 6 With respect to the configuration obtained in FIG. 2, the copper layer is polished by CMP (Chemical Mechanical Polishing) processing or the like to remove the conductor layer 6 and the seed layer 5. Then, polishing is performed so that the seed adhesion layer 4 and the conductor layer 6 become the surface. In one embodiment of the present invention, Cu: 2 μm of the upper conductor layer 6 of the photosensitive resin 3 and Cu: 300 nm of the seed layer 5 are removed by polishing.

[0028] (7) Polishing of the seed adhesion layer 4 and the photosensitive resin 3 Next, polishing such as CMP processing is performed again to remove the seed adhesion layer 4 and the photosensitive resin 3. Since the seed adhesion layer 4 and the photosensitive resin 3 are polished with different materials, the effect of chemical polishing is small, and physical polishing with an abrasive is dominant. For the purpose of process simplification, the same method as the polishing of the conductor layer 6 and the seed layer 5 described above may be used, or the polishing method may be changed according to the material types of the seed adhesion layer 4 and the photosensitive resin 3 for the purpose of improving the polishing efficiency. And the conductor layer 6 remaining after polishing serves as an electrode for bonding with the semiconductor element 17. Also, by making the conductor contact the photosensitive resin via the seed adhesion layer 4, it is possible to suppress the conductor from peeling off from the photosensitive resin due to warping during heating or the like.

[0029] (8) Formation of the inorganic insulating film 7 Next, an inorganic insulating film 7 is formed on the upper surface of the conductor layer 6 that serves as an electrode for bonding with the polished semiconductor element, and a structure with the insulating film formed in the direction shown in FIG. 3 can be obtained. As the inorganic insulating film 7, a silicon oxide film (SiOx), a silicon nitride film (SiNx), SiC, SiOF, SiOC, etc. can be applied. In one embodiment of the present invention, the inorganic insulating film 7 is 50 nm of SiNx and is formed by plasma CVD method.

[0030] The inorganic insulating film 7 does not necessarily have to be an insulating film formed by plasma CVD method such as the silicon oxide film (SiOx) or the silicon nitride film (SiNx). As long as it is an inorganic insulating film, the type and manufacturing method are not limited.

[0031] (9) Formation of the first opening Next, as shown in FIG. 4, a pattern of the first photosensitive resin 31 that becomes an interlayer insulating resin is formed on the upper surface of the inorganic insulating film 7. The thickness of the first photosensitive resin layer 31, which is an insulating resin, is set according to the thickness of the conductor layer to be formed in the opening. In one embodiment of the present invention, for example, 2 μm is formed. Also, the opening diameter of the first opening provided in the first photosensitive resin is set from the viewpoint of connection with the conductor layer 6. In one embodiment of the present invention, for example, an opening shape of φ11 μm is formed. This opening will be the diameter of the via portion connecting the upper and lower layers of the multilayer wiring.

[0032] Also, as shown in FIG. 4, by interposing the inorganic insulating film 7 at the interface between the photosensitive resin layer and the photosensitive resin layer, the adhesion is improved as compared with the case where the photosensitive resin is directly formed on the photosensitive resin. Furthermore, by interposing the inorganic insulating film 7 between the photosensitive resin layer 3 and the conductor layer 6, the adhesion is improved as compared with the case where the conductor layer 6 is in direct contact with the photosensitive resin layer 3. Due to these effects, cracks in the resin layer starting from the connection portion between the via portion and the land portion during multilayer formation and disconnection between the via portion and the land portion caused by these cracks can be suppressed.

[0033] (10) Formation of the second opening Further, as shown in FIG. 5, on the upper surface thereof, a pattern of a second photosensitive resin 32 that becomes an interlayer insulating resin is formed on the upper surface of the pattern of the first photosensitive resin 31. The thickness of the second photosensitive resin 32 which is an insulating resin is set according to the thickness of the conductor layer formed in the opening, and for example, 2 μm is formed in one embodiment of the present invention. Further, the opening diameter of the second opening provided in the second photosensitive resin is set from the viewpoint of the connectivity of the laminate and has an opening shape with a larger opening diameter than the lower first opening, and is formed in a shape surrounding the outside of the first opening. In one embodiment of the present invention, for example, an opening shape of φ25 μm is formed. This second opening is a wiring portion of the multilayer wiring board. Further, when multilayered, it becomes a receiving pad of the via portion, so-called a land portion. In the present invention, the via portion for connecting layers is integrally formed together with the land portion.

[0034] (11) Removal of the inorganic insulating film 7 Next, as shown in FIG. 6, for example, in a vacuum, the inorganic insulating film 7 in the opening of the first photosensitive resin layer 31 is removed by a dry etching method.

[0035] (12) Formation of the seed adhesion layer 4 and the seed layer 5 Next, as shown in FIG. 7, in a vacuum, the seed adhesion layer 4 and the seed layer 5 are formed. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

[0036] At this time, the seed adhesion layer 4 is formed on the side surface of the inorganic insulating film 7. By forming the seed adhesion layer 4 as a continuous film also on the side surface of the resin and the side surface of the inorganic insulating film 7, the risk of disconnection between the via portion and the land portion due to thermal warping can be reduced.

[0037] (13) Formation of the conductor layer 6 Next, a conductor layer 6 is formed by electrolytic plating, as shown in Fig. 8. The conductor layer 6 formed at this stage will become the via portion and the wiring portion. Options for electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, but electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is preferably 0.5 μm or more from the viewpoint of electrical resistance of the wiring portion, and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 6 μm is formed in the double opening of the photosensitive resin layer 3, Cu: 4 μm is formed in the single opening of the photosensitive resin layer 3, and Cu: 2 μm is formed on the top of the photosensitive resin layer 3.

[0038] (14) Surface polishing Next, as shown in FIG. 9, the conductive layer 6 and the seed layer 5 are removed by polishing using a CMP (chemical mechanical polishing) process or the like.

[0039] (15) Removal of seed adhesion layer 4 and photosensitive resin layer 3 Next, as shown in FIG. 10 , polishing is again performed by CMP (chemical mechanical polishing) or the like to remove the seed adhesion layer 4 and a portion of the surface layer of the second photosensitive resin 32. The conductor layer 6 remaining after CMP or the like becomes the conductor portion of the via portion and the wiring portion. In one embodiment of the present invention, 2 μm of Cu from the upper conductor layer 6 of the photosensitive resin layer 3 and 300 nm of Cu from the seed layer 5 are removed by polishing. In this manner, an interlayer connection conductor in which the via portion and the land portion are integrated can be formed. Here, as shown in FIG. 10 , by contacting the conductor with the photosensitive resin via the seed adhesion layer 4, peeling of the conductor from the photosensitive resin due to warping during heating or the like can be suppressed.

[0040] (16) Formation of multi-layer wiring by repeating the process As shown in FIG. 11, FIGS. 4 to 10 are repeated to form multilayer wiring. In one embodiment of the present invention, two wiring layers are formed. Further, as shown in FIG. 11, the interlayer connection conductors are formed such that the land portion of the previously formed interlayer connection conductor and the via portion of the subsequently fabricated interlayer connection conductor are electrically connected.

[0041] Hereinafter, the steps until the configuration of FIG. 12, which is a step of forming electrodes for bonding to the FC - BGA substrate 14, will be sequentially described. (17) Formation of inorganic insulating film 7 An inorganic insulating film 7 is formed on the upper surface of the polished surface formed in FIG. 11. The inorganic insulating film 7 is formed, for example, with SiNx: 50 nm by plasma CVD method. Next, a photosensitive resin layer 3 is formed on the inorganic insulating film 7. Next, in the same manner as in FIG. 6, the inorganic insulating film 7 within the opening of the photosensitive resin layer 3 is removed by dry etching.

[0042] (18) Formation of seed adhesion layer 4 and seed layer 5 Next, in a vacuum, a seed adhesion layer 4 and a seed layer 5 are formed. Next, a resist pattern 8 is formed.

[0043] (19) Formation of conductor layer (for solder connection) 9 Thereafter, a conductor layer (for solder connection) 9 is formed by electrolytic plating. This conductor layer (for solder connection) 9 will later become an electrode for bonding to the FC - BGA substrate 14. The thickness of the electrolytic copper plating is desirably 1 μm or more from the viewpoint of solder bonding and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 10 μm is formed in the opening of the photosensitive resin layer 3, and Cu: 8 μm is formed on the upper part of the photosensitive resin layer 3. Thus, the configuration shown in FIG. 12 can be obtained.

[0044] Next, the steps until the wiring substrate on the support shown in FIG. 13 is completed will be sequentially described. (20) Removal of resist pattern and formation of solder resist 10 First, after removing the resist pattern 8 shown in FIG. 12, the unnecessary seed adhesion layer 4 and seed layer 5 are etched away. Then, the solder resist 10 is formed. The solder resist 10 is formed by exposing and developing so as to cover the photosensitive resin layer 3 and having an opening so that the conductor layer (for solder connection) 9 is exposed. Note that, as the material of the solder resist 10, an insulating resin such as an epoxy resin or an acrylic resin can be used, for example. In the embodiment of the present invention, the solder resist 10 is formed using a photosensitive epoxy resin containing a filler as the solder resist 10.

[0045] (21) Formation of the surface treatment layer 11 Next, in order to prevent oxidation of the surface of the conductor layer (for solder connection) 9 and improve the wettability of the solder bump, the surface treatment layer 11 is provided. In the embodiment of the present invention, electroless Ni / Pd / Au plating is formed as the surface treatment layer 11. Note that, an OSP (Organic Solderability Preservative surface treatment with a water-soluble preflux) film may be formed on the surface treatment layer 11. Further, electroless tin plating, electroless Ni / Au plating, etc. may be appropriately selected according to the application.

[0046] (22) Formation of the solder joint Next, after mounting a solder material on the surface treatment layer 11, it is melted and cooled once to be fixed, thereby obtaining the solder 12 joint. As a result, as shown in FIG. 13, the multilayer wiring board 13 is completed on the support 1.

[0047] The multilayer wiring board 13 on the support completed in this way is joined to the FC - BGA substrate 14, and then the joint is sealed with an underfill layer. As the underfill layer, for example, a resin in which one of an epoxy resin, a urethane resin, a silicone resin, a polyester resin, an oxetane resin, and a maleimide resin or a resin in which two or more of these resins are mixed is used, and a material in which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like as a filler is added is used. The underfill layer is formed by filling a liquid resin.

[0048] Next, the support 1 can be removed by irradiating the release layer 2 with laser light. Next, the release layer 2, the seed adhesion layer 4, and the seed layer 5 are removed.

[0049] Thereafter, the semiconductor element 17 is mounted and the semiconductor device 18 shown in FIG. 1 is completed. At this time, prior to the mounting of the semiconductor element 17, surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. may be performed on the conductor layer 6 exposed on the surface in order to prevent oxidation and improve the wettability of the solder bumps.

[0050] <Verification of effects> Next, the operation and effects when using the configuration and manufacturing method of the multilayer wiring board as described above will be described with reference to FIG. 14 which is an example of an embodiment of the present invention and FIG. 15 which is a comparative example.

[0051] This embodiment will be described with reference to FIG. 14. FIG. 14 is an enlarged view of a connection portion between the interlayer connection conductors of the multilayer wiring board 13. As shown in FIG. 14, the outer periphery of the interlayer connection conductor is covered with the seed adhesion layer 4 or the inorganic insulating film 7. Thereby, by forming the inorganic insulating film 7 on the land portion except for the surface where the via portion and the land portion are in contact due to warping of the substrate during heating, the adhesion between the photosensitive resins is improved, and the crack in the photosensitive resin layer starting from the portion A' where the most stress is applied due to the warping can be suppressed. Furthermore, this can suppress the disconnection between the via portion and the land portion from easily occurring. Also, it can suppress the peeling of the via portion and the land portion from the photosensitive resin due to warping of the substrate during heating.

[0052] The comparative example will be described with reference to FIG. 15. FIG. 15 shows a multilayer wiring board 19 in which the inner conductor layer and the interlayer connection conductor are formed by a semi-additive process: SAP process, which is a known technique. In the configuration shown in FIG. 15, the side surface of the land portion and a part of the upper end conductors are exposed. In this case, as shown in FIG. 14, compared with the case where the entire outer periphery of the via portion and the land portion in the interlayer connection conductor is covered by the seed adhesion layer 4 or the inorganic insulating film 7, starting from the contact point B' between the via portion 20 and the land portion 21, that is, where the adhesion layer is not formed on the land portion 21, cracks enter the resin in the X direction, and as these cracks spread, stress further concentrates at the connection interface between the via portion and the land portion, making it easier to break the wire. Furthermore, due to warping during heating or the like, the wiring is likely to peel off from the resin in the wiring portion.

[0053] As a confirmation of the effects of the present embodiment, the multilayer wiring board 13 manufactured in the embodiment of the present invention and the multilayer wiring board 19 manufactured in the comparative example were mounted on the FC-BGA substrate 14, and the temperature change from -55°C to 125°C was repeated 500 cycles. As a result, in the wiring board 19 manufactured in the comparative example, wire breaks were confirmed along with resin cracks at the via connection portions. On the other hand, neither resin cracks nor wire breaks were confirmed in the multilayer wiring board 13 manufactured in the embodiment of the present invention.

[0054] The above-described embodiment is an example, and of course, other specific detailed structures and the like can be appropriately changed.

Explanation of Reference Numerals

[0055] 1 Support 2 Release Layer 3 Photosensitive Resin 4 Seed Adhesion Layer 5 Seed Layer 6 Conductor Layer 7 Inorganic Insulating Film 8 Resist Pattern 9 Conductor Layer (for Solder Connection) 10 Solder Resist 11 Surface Treatment Layer 12 Solder 13 Multilayer wiring board on a support 14 FC-BGA substrate 15 Laser light 17 Semiconductor element 18 Semiconductor device 19 Multilayer wiring board (SAP) 20 Via part 21 Land part 30 Multilayer wiring board 31 First photosensitive resin 32 Second photosensitive resin 36 Interlayer connection conductor

Claims

1. A multilayer wiring board having a first layer with a first interlayer connection conductor and a second layer with a second interlayer connection conductor, wherein the first interlayer connection conductor and the second interlayer connection conductor are each embedded in an insulating resin forming the first layer and the second layer via a seed adhesion layer, the first interlayer connection conductor and the second interlayer connection conductor are an integrated body of a via portion and a land portion having a larger diameter than the via portion, the side surface of the via portion of the first interlayer connection conductor, the surface of the land portion surrounding the outside of the via portion, and the side surface of the land portion are in contact with the insulating resin forming the first layer via the seed adhesion layer, the side surface of the via portion of the second interlayer connection conductor, the surface of the land portion surrounding the outside of the via portion, and the side surface of the land portion are in contact with the insulating resin forming the second layer via the seed adhesion layer, the first interlayer connection conductor and the second interlayer connection conductor are joined to each other via the seed adhesion layer, the upper and lower surfaces of the first layer and the second layer are covered with an inorganic insulating film except for portions where the first interlayer connection conductor and the second interlayer connection conductor are connected to each other or to other connection conductors A multilayer wiring board characterized by the above.

2. In the multilayer wiring board according to Claim 1, the seed adhesion layer covers the side surface of the inorganic insulating film A multilayer wiring board characterized by the above.

3. In the multilayer wiring board according to Claim 1 or 2, the seed adhesion layer is a layer containing titanium A multilayer wiring board characterized by the above.

4. In the multilayer wiring board according to any one of Claims 1 to 3, the insulating resin is a photosensitive insulating resin A multilayer wiring board characterized by the above.

5. A method for manufacturing a multilayer wiring board, which forms the multilayer wiring layer according to any one of Claims 1 to 4, which consists of an insulating resin layer and a wiring layer, above a support, comprising: a step of forming an inorganic insulating film layer; a step of forming a pattern of a first photosensitive resin having a first opening on the inorganic insulating film layer; a step of forming a pattern of a second photosensitive resin having a second opening with a larger opening diameter than the first opening above the first photosensitive resin; a step of removing the inorganic insulating film layer within the first opening; a step of forming the seed adhesion layer and the seed layer at the first opening and at the ends of the patterns of the first photosensitive resin and the second photosensitive resin A step of forming an electrolytic copper plating layer on the seed layer; A step of polishing the electrolytic copper plating layer, the seed layer, and the seed adhesion layer until the pattern of the second photosensitive resin is exposed. A method for manufacturing a multilayer wiring board, characterized by the above.

6. In the method for manufacturing a multilayer wiring board according to claim 5, The seed adhesion layer and the seed layer are formed by a sputtering method. A method for manufacturing a multilayer wiring board, characterized by the above.

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