Semiconductor device

Abstract

To provide a semiconductor device with high noise tolerance and capable of suppressing an operation of a parasitic bipolar transistor of a high-withstand-voltage MOSFET, which is a level shifter, in a self-shielding method HVIC.SOLUTION: A semiconductor device comprises: a well region 3 of a second conductivity type provided in a surface layer of a semiconductor layer 1 of a first conductivity type; a breakdown voltage region 4 of the second conductivity type surrounding a periphery of the well region 3 and having lower impurity concentration than the well region 3; a base region 61 of the first conductivity type surrounding a periphery of the breakdown voltage region 4; a carrier supply region 56 of the second conductivity type of a level shifter 41a provided in a surface layer of the base region 61; and a carrier reception region (51, 52) of the level shifter 41a provided in a surface layer of the well region 3 or the breakdown voltage region 4. The carrier reception region (51, 52) is composed of a first universal contact region in which a region 51 of the first conductivity type and a region 52 of the second conductivity type are provided in contact with each other.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a high-voltage integrated circuit device (HVIC) used when transmitting an on / off drive signal to the gate of a switching power device in a pulse-width modulation (PWM) inverter, a switching power supply, or the like.

Background Art

[0002] As a means for driving a switching power device that constitutes the upper arm of a bridge circuit for power inversion (DC-AC conversion) such as a PWM inverter, an element isolation type HVIC using a high-voltage junction is used. The HVIC can be made highly functional by providing means for detecting overcurrent and temperature during an abnormality of the switching power device. Further, since the HVIC does not perform potential insulation by a transformer, a photocoupler, or the like, miniaturization and cost reduction of the power supply system can be achieved.

[0003] A power conversion system configured by combining half-bridge circuits composed of switching power devices is widely used in many fields such as an inverter for motor control, power supply applications for amusement devices, liquid crystal panels, and inverters for home appliances such as air conditioners and lighting. Since these motors, lighting, etc. are inductive loads (L loads), the influence of parasitic inductance components due to wiring on a printed circuit board, cables to the L load, etc. occurs.

[0004] That is, when the switching power device of the upper arm turns off or during switching when the switching power device of the lower arm turns on, the potential of the Vs terminal, which is the reference potential on the high-potential side of the high-side circuit section constituting the HVIC, and the potential of the H-VDD terminal fluctuate to the negative potential side with respect to the ground potential (GND potential). This fluctuation to the negative potential side (negative surge voltage) may cause malfunction or latch-up of the high-side circuit section, and thereby the HVIC may be destroyed.

[0005] A chip layout configuration has been disclosed to prevent malfunction and destruction of the HVIC itself, which drives a half-bridge power device, in the event of such a negative surge voltage (see Patent Document 1). Patent Document 1 discloses that the pickup region, which is an area located on the periphery of the high-side circuit and fixed to the high-potential side of the power supply of the high-side circuit, is made into a universal contact region, thereby reducing the amount of carriers flowing into the low-side circuit and preventing malfunction and destruction due to latch-up in the logic section of the low-side circuit. Patent Document 2 also discloses that n + / p + It is disclosed that a short region is provided to promote extraction of minority carriers.

[0006] In recent years, from the viewpoint of chip miniaturization, it has become mainstream for self-isolated and junction-isolated HVICs to use a self-shielding method that integrates a level shifter consisting of a high-voltage n-channel MOSFET with a high-voltage junction termination region (HVJT). In order to achieve stable level shift circuit operation with the self-shielding method, a p-channel MOSFET is integrated into the high-voltage region surrounding the high-side circuit section in order to increase the parasitic resistance component between the drain of the level shifter and the H-VDD potential region. - A configuration in which an opening is provided in a mold is disclosed (see Patent Documents 3 to 5). - The structure in which a high-voltage n-channel MOSFET is integrated into an HVJT without using an opening also belongs to the self-shielding method mentioned above. - A divided RESURF technology has been disclosed that completely eliminates the parasitic resistance components of the drain of the level shifter and the H-VDD potential region by junction isolation using a layer (see Patent Document 6). The configuration disclosed in Patent Document 6 also belongs to the above-mentioned self-shielding method.

[0007] In addition, Patent Document 7 discloses a configuration in which, in order to improve the soft recovery characteristics so that the diode built in the power MOSFET can be used as the protection diode of the MOSFET, the thickness of at least a part of the low-concentration layer in the outer peripheral region is larger than the thickness of the low-concentration layer in the cell region. Further, Patent Document 8 discloses a configuration in which, in an HVIC, the effective channel width defined by the width of the base region of the portion overlapping the control electrode of the level shifter is wider than the width of the drain region measured along the same direction as the effective channel width in order to improve the trade-off between the heat generation and the propagation delay time of the level shifter.

[0008] In addition, Patent Document 9 discloses a technique for improving the short-circuit withstand by providing a channel layer on the trench sidewall of a trench MOSFET. Patent Document 10 discloses a MOSFET technique of a trench contact structure in which an SBD with a Schottky contact is built in the trench sidewall. Patent Document 11 discloses a technique in which a groove communicating with the silicon substrate is formed in the source region, the source electrode is electrically connected to the source region and the silicon substrate by this groove so that the source region becomes short, and the lower part of the source region is directly connected to the source electrode to reduce the resistance component of the lower part of the source region.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

[0010] In the technology described in Patent Document 1, when a negative surge voltage is applied via the H-VDD terminal, the n-type parasitic pn diode of the HVJT - Electrons are injected as minority carriers from the n-type MOSFET (H-VDD side) to the p-type MOSFET. - Electrons flow into the region. At that time, n - Area (H-VDD side) to n - Some of the electrons that have entered the p region along the path of electrons flowing into the n region (low-side circuit side) have a higher junction barrier than the p region (about 0.6 V higher), i.e., a lower electron energy barrier. + The electrons are trapped in the anode electrode and extracted in the n - This reduces the amount of electrons flowing into the low-side circuit region, preventing malfunction of the logic in the low-side circuit and damage due to latch-up. + The amount of holes emitted from the region (GND side) to the p region is p + Adjacent to the area (GND side) + Therefore, the parasitic pn diode is suppressed by the presence of the p region to the n region. - The amount of holes injected into the region is also reduced, making it possible to prevent malfunction of the logic of the high-side circuitry and destruction due to latch-up.

[0011] However, in a self-shielded HVIC in which a high-voltage n-channel MOSFET is formed inside an HVJT, when a negative surge voltage is applied to the H-VDD terminal, a forward current of the parasitic diode of the HVJT starts to flow, and a forward current also starts to flow in the body diode of the high-voltage n-channel MOSFET. At this time, p - The opening becomes a state with a higher potential than the n region, the junction barrier is broken, and it no longer functions as a junction separation region. As a result, the drain of the high-voltage n-channel MOSFET and p - Excessive electron carriers injected from the H-VDD potential region through the opening flow into the p + region at the GND potential. On the other hand, excessive hole carriers flow from the p + region at the GND potential into the drain region.

[0012] Then, when the VS potential recovers from the negative surge state, the body diode of the high-voltage n-channel MOSFET enters the reverse recovery state, and an excessive reverse recovery current Irr flows. The excessive reverse recovery current Irr (hole current) induces a voltage drop of 0.6 V or more in the base region under the source region of the high-voltage n-channel MOSFET, and the parasitic npn bipolar operates. When the parasitic npn bipolar operates, not only is the potential of the drain pulled down for a certain period and the input signal is not received (signal ignored), but it also causes malfunction of the level shift circuit and thermal runaway breakdown at high temperatures.

[0013] That is, the universal electrode having a configuration in which the p region and the n region are provided in contact with each other described in Patent Documents 1 and 2 is only applicable to the high-voltage diode region, and it is impossible to avoid the parasitic npn bipolar transistor operation of the high-voltage MOSFET triggered by the above-described reverse recovery current Irr.

[0014] In view of the above problems, an object of the present invention is to provide a semiconductor device with high noise resistance capable of suppressing the parasitic bipolar transistor operation of a high-voltage MOSFET that is a level shifter in a self-shielded HVIC.

Means for Solving the Problem

[0015] One aspect of the present invention is a semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, comprising: (a) a semiconductor layer of a first conductivity type; (b) a well region of a second conductivity type located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer; (c) a breakdown voltage region of the second conductivity type surrounding the well region and having a lower impurity concentration than the well region and provided in contact with the well region; (d) a base region of the first conductivity type surrounding the breakdown voltage region and provided in contact with the breakdown voltage region; (e) a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region; and (f) a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the breakdown voltage region, the gist of which is a semiconductor device in which the carrier reception region is composed of a universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other.

[0016] Another aspect of the present invention is a semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, comprising: (a) a semiconductor layer of a first conductivity type; (b) a well region of a second conductivity type located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer; (c) a high-voltage-resistant region of the second conductivity type having a lower impurity concentration than the well region, surrounding the well region and provided in contact with the well region; (d) a base region of the first conductivity type surrounding the high-voltage-resistant region and provided in contact with the high-voltage-resistant region; (e) a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region; (f) a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the high-voltage-resistant region; and (g) a plurality of pickup regions provided on the surface layer of the well region, the pickup regions being composed of a universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other. The gist of the invention is that it is a semiconductor device having the above configuration.

[0017] Still another aspect of the present invention is a semiconductor device in which a high-potential side circuit region, a high-voltage withstand junction termination structure provided around the high-potential side circuit region, and a low-potential side circuit region provided around the high-potential side circuit region via the high-voltage withstand junction termination structure are integrated on the same semiconductor chip, comprising: (a) a semiconductor layer of a first conductivity type; (b) a well region of a second conductivity type located in the high-potential side circuit region and provided on the surface layer of the semiconductor layer; (c) a breakdown voltage region of the second conductivity type surrounding the well region and having a lower impurity concentration than the well region and provided in contact with the well region; (d) a base region of the first conductivity type surrounding the breakdown voltage region and provided in contact with the breakdown voltage region; (e) a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential side circuit region and the high-potential side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region; and (f) a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the breakdown voltage region, wherein, in a planar pattern, the carrier supply region and the carrier reception region are provided in parallel with each other, the width of the carrier supply region is wider than the width of the carrier reception region, and the density of the carrier supply region at a position facing the carrier reception region in the planar pattern is lower than the density of the carrier supply region at a position not facing the carrier reception region.

Advantages of the Invention

[0018] According to the present invention, in a self-shielding type HVIC, it is possible to provide a semiconductor device with high noise resistance capable of suppressing the parasitic bipolar transistor operation of a high-voltage withstand MOSFET serving as a level shifter.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, with reference to the drawings, the first to ninth embodiments of the present invention will be described. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different even between the drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the components as the following.

[0021] In this specification, the "carrier supply region" means a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field effect transistor (FET) or a static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). Also, in a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the anode region becomes the carrier supply region. Further, the "carrier receiving region" means a semiconductor region that receives majority carriers constituting the main current, such as the drain region of an FET or a SIT, or the collector region of an IGBT. In an SI thyristor or a GTO thyristor, the cathode region functions as the carrier receiving region. Also, the "control electrode" means the gate electrode of an FET, SIT, IGBT, SI thyristor, or GTO thyristor, and has a function of controlling the flow of the main current flowing between the carrier supply region and the carrier receiving region.

[0022] In addition, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse, which goes without saying.

[0023] In addition, in the following description, the case where the first conductivity type is p-type and the second conductivity type is n-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Also, the “+” and “-” attached to “n” and “p” mean semiconductor regions with relatively high or low impurity concentrations compared to the semiconductor regions without the attached “+” and “-”. However, even for semiconductor regions with the same “n” attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same. Furthermore, in the following description, members and regions with the limitation of “the first conductivity type” and “the second conductivity type” mean members and regions made of semiconductor materials even without specific explicit limitation.

[0024] (First Embodiment) As a semiconductor device (semiconductor integrated circuit) according to the first embodiment of the present invention, a high-voltage integrated circuit device (HVIC) of a self-shielding type will be described. FIG. 1 shows a connection example between an HVIC 111 which is a semiconductor device according to the first embodiment of the present invention and IGBTs 114 and 115 which are switching power devices (switching elements) of a power conversion device such as an inverter driven by the HVIC 111. Note that the switching elements of the power conversion device are not limited to IGBTs 114 and 115, and switching elements such as MOSFETs may also be used.

[0025] The IGBTs 114 and 115 are connected in series to form a half bridge. Freewheeling diodes (FWD) 116 and 117 are connected in anti-parallel to the IGBTs 114 and 115. The emitter of the IGBT 114 is connected to the ground potential (GND potential). The collector of the IGBT 115 is connected to the Vss potential on the high-potential side of the high-voltage power supply which is the main circuit power supply.

[0026] By alternately turning on the IGBT 115 in the upper arm and the IGBT 114 in the lower arm of the power conversion device shown in FIG. 1, a high potential or a low potential is alternately output from the Vs terminal 110, which is the output terminal, to supply AC power (flow an AC current) to the L load 118. That is, when outputting a high potential, the IGBTs 114 and 115 are operated so that the IGBT 115 in the upper arm is turned on and the IGBT 114 in the lower arm is turned off. Conversely, when outputting a low potential, the IGBTs 114 and 115 are operated so that the IGBT 115 in the upper arm is turned off and the IGBT 114 in the lower arm is turned on.

[0027] At this time, the HVIC 111 that drives the IGBTs 114 and 115 outputs a gate signal with a GND reference to the gate of the IGBT 114 in the lower arm and outputs a gate signal with the Vs potential of the Vs terminal 110 as a reference to the gate of the IGBT 115 in the upper arm. Therefore, the HVIC 111 needs to have a level shift function.

[0028] The symbol "Vs" of the HVIC 111 shown in FIG. 1 is an intermediate potential that varies from the Vss potential to the GND potential. "H-VDD" is the high potential side of the low voltage power supply 113 with the Vs potential as a reference. "L-VDD" is the high potential side of the low voltage power supply 112 with the GND potential as a reference. In the case of the bootstrap circuit method, the low voltage power supply 113 is composed of an external capacitor (not shown) by an external bootstrap diode (not shown) connected between "L-VDD" and "H-VDD".

[0029] "H-IN" is an input signal and an input terminal that are input to the gate of the CMOS circuit on the low side connected to the level-up circuit. "L-IN" is an input signal and an input terminal that are input to the gate of the CMOS circuit on the low side connected to the gate of the lower-arm IGBT114. "H-OUT" is an output signal and an output terminal of the CMOS circuit on the high side that outputs to the gate of the upper-arm IGBT115. "L-OUT" is an output signal and an output terminal that outputs to the gate of the lower-arm IGBT114. "ALM-IN" is an input signal and an input terminal of the detection signal 119 when detecting the temperature and overcurrent of the upper-arm IGBT115. "ALM-OUT" is an output signal and an output terminal of the leveled-down detection signal.

[0030] Figure 2 is a circuit diagram showing the level-shift circuit (level-up circuit) 132 inside the HVIC111 shown in Figure 1 and the peripheral circuits (131, 133) of the level-up circuit 132. As the peripheral circuits (131, 133), the low-side circuit 131 that transmits the input signal to the level-up circuit 132 and the high-side circuit 133 that transmits the output signal from the level-up circuit 132 to the upper-arm IGBT115 are exemplified. The low-side circuit 131 has a p-channel MOSFET 71 and an n-channel MOSFET 72 that constitute a CMOS circuit. The high-side circuit 133 has a p-channel MOSFET 75 and an n-channel MOSFET 76 that constitute a CMOS circuit.

[0031] The level-up circuit 132 includes a level-shifting resistor 73 and an n-channel MOSFET 41 whose drain is connected to the level-shifting resistor 73. The connection part of the level-shifting resistor 73 and the n-channel MOSFET 41 is defined as the output part 101 of the level-up circuit 132. The anode and cathode of a diode 74 are respectively connected to both ends of the level-shifting resistor 73. The diode 74 clamps the overvoltage drop at both ends of the level-shifting resistor 73. The high-potential-side H-VDD terminal 120 of the low-voltage power supply 113 with the Vs potential as a reference is connected to one end of the level-shifting resistor 73 and the source of the p-channel MOSFET 75 in the high-side circuit 133.

[0032] When an input signal H-IN is input to the low-side circuit 131 shown in FIG. 2, a low-side level on / off signal passes through the CMOS circuits (71, 72) of the low-side circuit 131 and is input to the gate of the n-channel MOSFET 41 of the level-up circuit 132. Due to this signal, the n-channel MOSFET 41 turns on and off, and outputs a high-side level on / off signal from the output part 101 of the level-up circuit 132. Due to this signal, the CMOS circuits (75, 76) of the high-side circuit 133 turn on and off to output an output signal H-OUT. The output signal H-OUT is converted into a signal with the Vs potential as a reference. The output signal H-OUT is applied to the gate of the upper-arm IGBT 115 shown in FIG. 1 to turn on and off the upper-arm IGBT 115.

[0033] Next, the structure of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 3 is a plan view showing a main part of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view including the high-voltage-resistant n-channel MOSFET 41a viewed from the A-A' direction in FIG. 3, and FIG. 5 is a cross-sectional view viewed from the B-B' direction in FIG. 3.

[0034] As shown in FIG. 3, the HVIC 111, which is a semiconductor device according to the first embodiment of the present invention, includes a high-potential-side circuit region (high-side circuit region) 301, a high-voltage withstand junction termination structure (HVJT) 303 provided annularly around the high-side circuit region 301, and a low-potential-side circuit region (low-side circuit region) 302 provided around the high-side circuit region 301 via the HVJT 303 on one chip. The high-side circuit region 301 includes the high-side circuit 133 shown in FIG. 2 as an internal circuit. The low-side circuit region 302 includes the low-side circuit 131 shown in FIG. 2 as an internal circuit. The HVJT 303 electrically separates the high-side circuit region 301 and the low-side circuit region 302.

[0035] As shown in FIGS. 3 to 5, the HVIC 111 includes an n-type well region 3, which is a high-side floating potential region, provided on one main surface side (hereinafter referred to as the "surface layer") inside the p-type semiconductor layer 1. As the p-type semiconductor layer 1, for example, a silicon (Si) substrate can be used, but a compound semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or a semi-metal substrate may also be used. Further, the semiconductor layer 1 may be a p-type or n-type epitaxial growth layer provided on a p-type semiconductor substrate. In this case, an n-type buried layer may be provided in part between the p-type semiconductor substrate and the epitaxial growth layer. Furthermore, the n-type well region 3 may be provided at a depth in contact with the n-type buried layer.

[0036] The n-type well region 3 is located in the high-side circuit region 301. The Vs potential region 200 and the H-VDD potential region 201 are provided in the n-type well region 3. The Vs potential region 200 includes the n-type source region, p-type base region, and n-type drain region of the n-channel MOSFET, which is a high-side logic part, and the p-type drain region of the p-channel MOSFET. + The H-VDD potential region 201 includes the p-type source and n-type base regions of the p-channel MOSFET, which is a high-side logic part. Further, an H-VDD pad 102, an H-OUT pad 103, and a Vs pad 104 are provided on the n-type well region 3. +

[0037] As shown in FIG. 3, in the n-type well region 3, a p-type junction isolation region (slit region) 63 is provided in an annular (C-shaped) manner so as to surround the peripheries of the Vs potential region 200 and the H-VDD potential region 201. As shown in FIGS. 4 and 5, the p-type junction isolation region 63 has a depth that penetrates the n-type well region 3 and reaches the p-type semiconductor layer 1, and junction-isolates the n-type well region 3. In the cross section shown in FIG. 5, pickup electrodes 203 are provided on the p-type junction isolation region 63 via insulating films 81 and 82.

[0038] As shown in FIG. 3, in the surface layer of the n-type well region 3 inside the p-type junction isolation region 63, + n-type pickup regions 62a, 62b, and 62c are provided in a strip or annular shape. + Pickup electrodes (pickup contacts) 203a, 203b, and 203c connected to the H-VDD terminal are respectively provided on the n-type pickup regions 62a, 62b, and 62c.

[0039] Also, at the position of the opening (missing portion) of the planar pattern of the p-type junction isolation region 63, in the surface layer of the n-type well region 3 outside the p-type junction isolation region 63, + an n-type pickup region 62d is provided. + The n-type pickup region 62d + is provided at a position facing the n-type pickup region 62c. + A pickup electrode (pickup contact) 203d connected to the H-VDD terminal is provided on the n-type pickup region 62d.

[0040] As shown in FIGS. 3 to 5, an n-type breakdown voltage region 4 having a lower impurity concentration than the n-type well region 3 is provided in an annular shape so as to surround the n-type well region 3 and be in contact with the n-type well region 3. - Furthermore, a p-type base region 61 is provided in an annular shape so as to surround the n-type breakdown voltage region 4 and be in contact with the - n-type breakdown voltage region 4. The n-type well region 3, n - type breakdown voltage region 4, and p-type base region 61 are provided in an annular shape so as to surround the n-type well region 3 and be in contact with the n-type well region 3. -On the n-type pressure-resistant region 4 and the p-type base region 61, insulating films 81, 82, and 83 are provided. As schematically shown in FIG. 4, n - A parasitic diode 42 is formed by the pn junction between the n-type pressure-resistant region 4 and the p-type base region 61, and the HVJT303 is constituted by this parasitic diode 42.

[0041] The impurity concentration of the p-type base region 61 is higher than that of the p-type semiconductor layer 1. The p-type base region 61 fixes the p-type semiconductor layer 1 to the GND potential. On the surface layer of the p-type base region 61, along the surface of the p-type semiconductor layer 1, a p-type contact region 56 having an impurity concentration higher than that of the p-type base region 61 is provided in a ring shape. + As shown in FIGS. 3 and 5, a p-type contact region 56 is provided in a ring shape. + On the p-type contact region 56, a pickup electrode (pickup contact) 202 connected to the GND potential is provided in a ring shape.

[0042] As shown in the lower part of FIG. 3, a low-side circuit region 302 is provided in a p-type well region 2 provided so as to surround the periphery of the p-type base region 61. Further, an H-IN pad 105, an L-VDD pad 106, and a GND pad 107 are provided in the p-type well region 2.

[0043] As shown in FIG. 3, high-voltage n-channel MOSFETs 41a and 41b, which are level shifters for performing signal transmission between the high-side circuit region 301 and the low-side circuit region 302, are provided in a part of the HVJT303. The high-voltage n-channel MOSFETs 41a and 41b correspond to the n-channel MOSFET 41 shown in FIG. 2. Since signal transmission to the high-side logic and the output circuit is performed by a two-input method of the SET signal and the RESET signal, two high-voltage n-channel MOSFETs 41a and 41b for the SET signal and the RESET signal are provided. The structures of the high-voltage n-channel MOSFETs 41a and 41b are the same, and hereinafter, mainly the high-voltage n-channel MOSFET 41a will be described with attention.

[0044] As shown in FIGS. 3 and 4, the high-voltage n-channel MOSFET 41a is an n- The pressure-resistant region 4 of type is used as a drift region. The high-voltage n-channel MOSFET 41a has an n + type source region 53 provided adjacent to the p + type contact region 56 on the surface layer of the p-type base region 61. + type contact region 56 and n + type source region 53, a source electrode 400 is provided in contact with the p + type contact region 56 and n + type source region 53.

[0045] The high-voltage n-channel MOSFET 41a has a universal contact region (51, 52) as a drain region provided in the surface layer of the n-type well region 3. Here, the "universal contact region" means a region in which at least one p + type contact region (p + type region) and at least one n + type contact region (n + type region) are arranged in contact with each other. In FIGS. 3 and 4, the universal contact region (51, 52) is composed of a p + type contact region 51 and an n + type contact region 5 that are arranged in contact with each other alternately along the surface of the p-type semiconductor layer When the depths of the p + type contact region 51 and the n + type contact region 52 may be the same as each other, or either one of the p + type contact region 51 and the n + type contact region 52 may be relatively deeper.

[0046] In FIGS. 3 and 4, the structure in which the universal contact region (51, 52) is provided in the surface layer of the n-type well region 3 is illustrated, but the universal contact region (51, 52) may be provided in the surface layer of the n - type pressure-resistant region 4.

[0047] On the universal contact regions (51, 52), a universal electrode (universal contact) 401 that makes ohmic contact with the universal contact regions (51, 52) is provided. The universal contact regions (51, 52) and the universal electrode 401 constitute a universal contact structure (51, 52, 401).

[0048] As shown in FIG. 4, a gate electrode 402 is provided on a p-type base region 61 between a source electrode 400 and a drain electrode 401 via a gate insulating film. The gate electrode 402 is made of, for example, polysilicon. The pickup electrode 202 and the source electrode 400 are connected to the GND potential and have the same potential.

[0049] FIG. 6 is a partially enlarged view of the peripheral portion of the high-voltage n-channel MOSFET 41a in FIG. 1. In FIG. 6, the contact portion of the source electrode 400 is shown by a broken line. As shown in FIG. 6, the n + type source region 53 and the universal contact regions (51, 52) are provided parallel to each other. The n + type source region 53 and the universal contact regions (51, 52) have a linear planar pattern. In the vertical direction of FIG. 6, the width Ws of the n + type source region 53 of the high-voltage n-channel MOSFET 41a is wider than the width Wd of the universal contact regions (51, 52) that are the drain regions of the high-voltage n-channel MOSFET 41a. Also, the effective channel width defined by the width of the p-type base region 61 that overlaps with the gate electrode 402 is also substantially the same as the width Ws of the n + type source region 53 and is wider than the width Wd of the universal contact regions (51, 52).

[0050] n + The width Ws of the n-type source region 53 is + the width between both ends of the n-type source region 53, and as shown in FIG. 6, a p + type contact region 56 may be provided between the n-type source regions 53. In FIG. 6, a p + type contact region 56 may be provided between the n-type source regions 53. Note that in FIG. 6, between the n-type source regions 53, a p + type contact region 56 may be provided between the n-type source regions 53.+ A type contact region 56 is provided, but n + between the type source regions 53, p + type contact region 56 may not be provided. In that case, n + type source region 53 may have a planar pattern extending linearly.

[0051] FIG. 7 shows a planar pattern of the universal contact regions (51, 52). p + type contact regions 51 each have a rectangular planar shape and are provided in an island shape. n + type contact region 52 is p + provided so as to surround the periphery of the type contact region 51. In FIG. 7, the planar pattern of the contact portion of the universal electrode 401 is shown by a broken line. Here, the case where the planar pattern of the contact portion of the universal electrode 401 is rectangular is illustrated, but it may be in a line shape extending in the longitudinal direction of the universal contact regions (51, 52).

[0052] p + type contact regions 51 and n + type contact regions 52 are each formed using an individual ion implantation mask. For example, after forming the p + type contact region 51, from the surface of the p + type contact region 51, a deeper n + type contact region 52 than the p + type contact region 51 may be selectively formed.

[0053] By using the drain region of the high-voltage n-channel MOSFET 41a as the universal contact regions (51, 52), when a negative surge voltage is applied to the H-VDD terminal via the Vs terminal 110, as shown in FIG. 8, holes, which are minority carriers flowing through the parasitic body diode 42, can be quickly extracted from the universal electrode 401. As a result, the reverse recovery current Irr (hole current) when the Vs potential returns and the body diode 42 enters the reverse recovery state can be reduced, n +The parasitic npn bipolar transistor operation composed of the n-type source region 53, p-type base region 61, and n - By suppressing the parasitic npn bipolar transistor operation composed of the n-type breakdown voltage region 4, malfunction of the level shift circuit and thermal runaway breakdown due to parasitic operation can be prevented.

[0054] During the period when a negative surge voltage is applied to the Vs terminal 110, in order to enhance the hole carrier extraction effect in the n-type breakdown voltage region 4 and n-type well region 3, in the universal contact regions (51, 52), - it is desirable to increase the ratio of the p + -type contact region 51 compared to the n + -type contact region 52.

[0055] However, increasing the ratio of the p + -type contact region 51 not only increases the drain contact resistance of the high-voltage n-channel MOSFET 41a and causes a decrease in the on-current, but also when a positive surge such as electrostatic discharge (ESD) is input from the H-VDD terminal to the n + -type contact region 52, the body diode 42 becomes reverse-biased and undergoes avalanche breakdown. At this time, electrons generated by the avalanche breakdown flow as majority carriers in the n-type well region 3. These electrons are taken into the n + -type contact region 52 of the universal contact regions (51, 52). When the p + -type contact region 51 is arranged in a double or triple wide line shape so as to surround the n + -type contact region 52, the resistance (base resistance) in the n-type well region 3 directly below the p + -type contact region 51 becomes high. Therefore, when a voltage drop of 0.6 V occurs in the n-type well region 3 directly below the p + -type contact region 51, a parasitic pnp bipolar transistor composed of the p-type semiconductor layer 1, n-type well region 3, and p + -type contact region 51 may operate and lead to current breakdown.

[0056] In order to suppress such parasitic pnp bipolar transistor operation, as shown in FIG. 7, an n + -type contact region 52 is arranged on the outer periphery, and an n + -type contact region 52 has a p + -type contact region 51 arranged not in a line shape but in a short, divided island shape that alternately overlaps in a double layer or more (exemplified by a double layer structure in FIG. 7). Then, an n + -type contact region 52 and a p + -type contact region 51 are formed with contacts of the universal electrode 401 so as to straddle them. When arranged in this way, electrons can also be absorbed by the n + -type contact region 52 sandwiched between the p + -type contact regions 51, so that an increase in local base resistance can be suppressed and parasitic pnp bipolar transistor operation can be suppressed.

[0057] Note that, as the planar pattern of the universal contact regions (51, 52), the planar pattern of the p + -type contact region 51 provided in an island shape may be circular or may be a polygon such as a quadrilateral. Also, an n + -type contact region 52 and a p + -type contact region 51 may be formed in a stripe shape (for example, a stripe shape) and in contact with each other. By arranging the n + -type contact region 52 on the outer peripheral side, a significant decrease in the on-current of the high-voltage n-channel MOSFET 41a can also be suppressed, so that parasitic pnp bipolar transistor operation can be prevented without impairing the stability of the level shift operation.

[0058] Although not shown in FIG. 3, as shown in FIG. 4, a resistor (level shift resistor) 173 is provided on the n-type well region 3 via an insulating film 81. The level shift resistor 173 corresponds to the level shift resistor 73 in the equivalent circuit diagram shown in FIG. 2. The level shift resistor 173 can be formed of, for example, polysilicon. The level shift resistor 173 can be formed in the same layer as, or in a different layer from, the gate electrode 402 of the high-voltage n-channel MOSFET 41a.

[0059] On the upper surface side of the level shift resistor 173, a first electrode 501 and a second electrode 502 are provided. The first electrode 501 and the second electrode 502 are electrically connected to both ends of the level shift resistor 173, respectively. For convenience in FIG. 4, the electrical connection between the pickup electrode 203a and the first electrode 501 is shown by a solid line, but it may be formed in a wiring layer of the same layer as the pickup electrode 203a and the first electrode 501 or in a wiring layer of a different layer, and connected to the pickup electrode 203a and the first electrode 501 via a via. Also, for convenience in FIG. 4, the electrical connection between the universal electrode 401 and the second electrode 502 is shown by a solid line, but it may be formed in a wiring layer of the same layer as the universal electrode 401 and the second electrode 502 or in a wiring layer of a different layer, and connected to the universal electrode 401 and the second electrode 502 via a via. The pickup electrode 203a is electrically connected to the universal contact regions (51, 52) which are the drain regions of the high breakdown voltage n-channel MOSFET 41a via the level shift resistor 173.

[0060] Regarding the manufacturing process of the semiconductor device according to the first embodiment of the present invention, the n - type breakdown voltage region 4, n-type well region 3, p-type base region 61, and p-type junction isolation region 63 are formed by ion-implanting an n-type impurity such as phosphorus or a p-type impurity such as boron through a patterning process, and then diffusing to a predetermined diffusion depth in a diffusion process at a high temperature (about 1100 to 1200 °C), for example. Also, the Vs potential region 200 provided in the high-side circuit portion, the well region of the low-side circuit portion, etc. are formed by diffusing to a predetermined diffusion depth in a diffusion process different from the diffusion process for forming the n - type breakdown voltage region 4, n-type well region 3, p-type base region 61, and p-type junction isolation region 63 at a high temperature (about 1100 to 1200 °C), for example.

[0061] n + type pickup region 62 has a surface concentration of an n-type impurity such as arsenic of 1×10 20 / cm 3Ion implantation is performed to a certain degree, and then, for example, by an annealing process at about 750 to 900 °C, it is formed at a predetermined depth. The n of the high breakdown voltage n-channel MOSFET 41a + source region 53 and the n + type contact region 52 are also formed by ion implantation and annealing treatment in the same manner as the n + type pickup region 62. The p + type contact region 56 and the p + type contact region 51 are formed through a patterning process for region formation. For example, BF2 is ion-implanted to a surface concentration of 1×10 + / cm 20 to a certain degree, and then, for example, by an annealing process at about 750 to 900 °C, which is the same as the above, they are formed at predetermined diffusion depths respectively. 3

[0062] <Comparative Example> Next, a conventional self-shielding type HVIC will be described as a comparative example. FIG. 9 is a plan layout of the HVIC according to the comparative example, and FIG. 10 is a cross-sectional view including the high breakdown voltage n-channel MOSFET 41a as viewed from the A-A' direction of FIG. 9. In FIG. 9, the parasitic resistances Rs1, Rr1, and Rsr inherent in the self-shielding type HVIC are schematically shown. Such parasitic resistances Rs1, Rr1, and Rsr also exist in the semiconductor device according to the first embodiment shown in FIG. 3.

[0063] As shown in FIGS. 9 and 10, the HVIC according to the comparative example is different from the semiconductor device according to the first embodiment shown in FIG. 3 in that the n + type drain region 52 of the high breakdown voltage n-channel MOSFET 41a is not a universal contact region. Further, the width Ws of the n + type source region 53 of the high breakdown voltage n-channel MOSFET 41a is the same as the width Wd of the n + type drain region 52, which is different from the semiconductor device according to the first embodiment shown in FIG. 3. The high breakdown voltage n-channel MOSFET 41b also has the same structure as the high breakdown voltage n-channel MOSFET 41a.

[0064] When driving the IGBT 115 of the upper arm shown in FIG. 1 using the HVIC according to the comparative example, when the IGBT 115 of the upper arm turns off, or when the IGBT 114 of the lower arm switches to on, the potential of the Vs terminal, which is the reference potential on the high-potential side of the high-side circuit section constituting the HVIC, and the potential of the H-VDD terminal fluctuate to the negative potential side with respect to the GND potential. This fluctuation to the negative potential side (negative surge voltage) causes malfunction or latch-up of the high-side circuit section, and as a result, there is a possibility that the HVIC may be destroyed.

[0065] When the negative surge voltage VS0 becomes lower than the GND potential (0 V) - (Vspy + Vfd), the parasitic pn diode of the HVIC starts to conduct. Here, Vspy is the battery voltage between both ends of the low-voltage power supply 113 on the high side or a bootstrap capacitor (not shown), and Vfd is the forward voltage drop of the parasitic pn diode. When the negative surge voltage VS0 is strongly pulled in the negative direction, an overcurrent flows through the HVIC. As a result, there is a risk that the HVIC may be destroyed due to the occurrence of malfunction in the high-side circuit section and the parasitic operation of the high-voltage-tolerant n-channel MOSFETs 41a and 41b, which are level shifters.

[0066] The applied negative surge voltage VS0 is proportional to the product {L1 × (dI1 / dt)} of the parasitic inductance component L1 due to wiring on the printed circuit board and the cable to the L load 118, etc., and dI1 / dt during the period when the on-current I1 flowing through the IGBT 115 turns off. This spiky negative surge voltage VS0 is applied to the Vs terminal. The applied voltage varies depending on the inductance, the on-current of the IGBT, the transient VF characteristics of the FWD, etc., but is about -50 V, and the application period is about 100 to 500 ns.

[0067] On the other hand, according to the semiconductor device according to the first embodiment of the present invention, by making the drain regions of the high-voltage-tolerant n-channel MOSFETs 41a and 41b into universal contact regions (51, 52), the body diode current that flows when a negative surge voltage is input to the Vs terminal 110 holes carriers are transferred to the p of the universal contact regions (51, 52). +Efficient extraction can be achieved in the type - contact region 51, reducing the residual carriers. Therefore, the reverse - recovery current Irr (hole current) when the Vs potential recovers can be decreased, and the parasitic npn bipolar transistor operation triggered by the reverse - recovery current Irr can be suppressed. Thus, in the self - shielded HVIC111, the noise tolerance against the negative surge voltage of the Vs terminal is improved, and a robust and highly reliable HVIC111 that does not cause malfunction or breakdown can be realized.

[0068] Furthermore, in the self - shielded HVIC111, for the n - type source regions 53 of the high - voltage - tolerant n - channel MOSFETs 41a, 41b which are level shifters + By making the width Ws of the n - type source region 53 wider than the width Wd of the universal contact regions (51, 52) which are the drain regions of the high - voltage - tolerant n - channel MOSFETs 41a, 41b, the carrier density under the n - type source region 53 when the body diode 42 is in reverse recovery can be reduced. + And the voltage drop in the p - type base region 61 under the n - type source region 53 can be suppressed, preventing the parasitic npn bipolar transistor operation. + Moreover, the area required to form the universal contact regions (51, 52) as the drain regions of the high - voltage - tolerant n - channel MOSFETs 41a, 41b is the same as the area of the n - type drain region 52 in the HVIC of the comparative example shown in FIGS. 9 and 10. Therefore, since there is no increase in the chip size and the manufacturing process steps do not change, the manufacturing cost does not increase.

[0069] In addition, for the high - voltage - tolerant n - channel MOSFETs 41a, 41b, the area required to form the universal contact regions (51, 52) as the drain regions is the same as the area of the n - type drain region 52 in the HVIC of the comparative example shown in FIGS. 9 and 10. + For this reason, since there is no increase in the chip size and the manufacturing process steps do not change, the manufacturing cost does not increase.

[0070] Note that in the semiconductor device according to the first embodiment of the present invention, for the n - type source regions 53 of the high - voltage - tolerant n - channel MOSFETs 41a, 41b which are level shifters + the width Ws of the n - type source region 53 of the high - voltage - tolerant n - channel MOSFETs 41a, 41b Universal contact areas (51, 52) as drain regions is made wider than the width Wd However, similar to the HVIC according to the comparative example shown in FIGS. 9 and 10, for the n - type +The width Ws of the type source region 53 and the width Wd of the universal contact regions (51, 52) may be made substantially the same. In that case, the drain regions of the high-voltage n-channel MOSFETs 41a and 41b may be made the universal contact regions (51, 52).

[0071] (Second Embodiment) FIG. 11 is a plan view showing a main part of a semiconductor device (HVIC) according to a second embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along the A-A' direction of FIG. 11 and including the high-voltage n-channel MOSFET 41a. As shown in FIGS. 11 and 12, in the HVIC according to the second embodiment of the present invention, among the pickup regions (62a, 64), 62b, 62c, 62d of the H-VDD potential, the contacts of the pickup regions (62a, 64) near the drain regions of the high-voltage n-channel MOSFETs 41a and 41b are used as the universal contact regions, which is different from the semiconductor device according to the first embodiment of the present invention shown in FIG. 3.

[0072] As shown in FIGS. 11 and 12, the pickup regions (62a, 64) are arranged such that the n + -type pickup region 62a and the p + -type contact region 64 are in contact with each other and alternately arranged to form the universal contact region. The pickup regions (62a, 64) and the pickup electrode 203a form the universal contact structure (62a, 64, 203a).

[0073] The planar pattern of the pickup regions (62a, 64) is the same as the planar pattern of the universal contact regions (51, 52) shown in FIG. 7. For example, the p + -type contact regions 64 each have a rectangular planar shape and are provided in an island shape. The n + -type pickup region 62a is provided so as to surround the p + -type contact regions 64 The other configurations of the semiconductor device according to the second embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and redundant descriptions are omitted.

[0074] According to the semiconductor device according to the second embodiment of the present invention, by using the pickup regions (62a, 64) of the H-VDD potential near the drain regions of the high-voltage n-channel MOSFETs 41a and 41b as universal contact regions, the amount of hole carriers flowing through the p-type junction isolation region 63 into the body diode 42 can be reduced. Therefore, the parasitic npn bipolar transistor operation due to the reverse recovery phenomenon of the body diode 42 during the return from the negative surge of the Vs potential can be prevented.

[0075] (Third Embodiment) FIG. 13 is a plan view showing a main part of a semiconductor device (HVIC) according to the third embodiment of the present invention, and FIG. 14 is a cross-sectional view including the high-voltage n-channel MOSFET 41a as viewed from the A-A' direction of FIG. 13. The HVIC according to the 3 third embodiment of the present invention is different from the semiconductor device according to the second embodiment of the present invention shown in FIG. 11 in that the drain regions 52 of the high-voltage n-channel MOSFETs 41a and 41b are not universal contact regions as shown in FIGS. 13 and 14.

[0076] According to the semiconductor device according to the third embodiment of the present invention, by using the pickup regions (62a, 64) of the H-VDD potential near the drain regions 52 of the high-voltage n-channel MOSFETs 41a and 41b as universal contact regions, the amount of hole carriers flowing through the p-type junction isolation region 63 into the body diode 42 can be reduced. Therefore, the parasitic npn bipolar transistor operation due to the reverse recovery phenomenon of the body diode 42 during the return from the negative surge of the Vs potential can be prevented. Thus, the on-current of the high-voltage n-channel MOSFETs 41a and 41b can be increased compared to the second embodiment.

[0077] In the second and third embodiments, the pickup regions (62a, 64) serving as the universal contact regions are desirably arranged inside the drain regions of the high-voltage n-channel MOSFETs 41a and 41b on the planar pattern and outside the high-side circuit portions (the Vs potential region 200, the H-VDD potential region 201, and the regions connected to the Vs potential region 200 and the H-VDD potential region 201) in the high-side circuit region 301. Further, this pickup region (62a, 64) is desirably arranged between the drain regions of the high-voltage n-channel MOSFETs 41a and 41b and the high-side circuit portion on the planar pattern. Furthermore, it is desirable that the distance between this pickup region (62a, 64) and the drain regions of the high-voltage n-channel MOSFETs 41a and 41b is within 100 μm on the planar pattern. With such a configuration, the amount of hole carriers flowing into the body diode 42 through the p-type junction isolation region 63 can be reduced. Therefore, the parasitic npn bipolar transistor operation due to the reverse recovery phenomenon of the body diode 42 during the return from the negative surge of the Vs potential can be prevented.

[0078] (Fourth Embodiment) FIG. 15 is a plan view of the periphery of the high-voltage n-channel MOSFET 41a of the semiconductor device (HVIC) according to the fourth embodiment of the present invention. As shown in FIG. 15, in the semiconductor device according to the fourth embodiment of the present invention, the density of the n + type source region 53 is higher at a position not facing the universal contact regions (51, 52) than at a position facing the universal contact regions (51, 52), which is different from the semiconductor device according to the first embodiment of the present invention shown in FIG. 6.

[0079] As shown in FIG. 15, the n +The p-type source region 53 includes a plurality of opposing regions 53a provided at positions facing the universal contact regions (51, 52), and end regions (overhanging regions) 53b and 53c that sandwich the plurality of opposing regions 53a and are provided at positions not facing the universal contact regions (51, 52). The plurality of opposing regions 53a have a rectangular planar pattern and are provided parallel to each other and spaced apart from the universal contact regions (51, 52). The end regions 53b and 53c have a linear planar pattern.

[0080] Although illustration is omitted, the high-voltage n-channel MOSFET 41b shown in FIG. 3 also has the same structure as the high-voltage n-channel MOSFET 41a shown in FIG. 15. Other configurations of the semiconductor device according to the fourth embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and redundant descriptions are omitted.

[0081] According to the semiconductor device according to the fourth embodiment of the present invention, as shown in FIG. 15, the drain current Id of the high-voltage n-channel MOSFET 41a is also supplied from the end regions 53b and 53c at positions not facing the universal contact regions (51, 52), and it is possible to secure the drain current Id necessary for the level shift circuit operation. On the other hand, the plurality of opposing regions 53a at positions facing the universal contact regions (51, 52) are arranged alternately with the p + type contact region 56, so that the reverse recovery current Irr during reverse recovery concentrates in the plurality of opposing regions 53a with low impedance, and it is possible to suppress the parasitic npn bipolar transistor operation due to the voltage drop under the plurality of opposing regions 53a. That is, it is possible to suppress the parasitic npn bipolar transistor operation during reverse recovery while maintaining the level shift circuit operation margin.

[0082] In the semiconductor device according to the fourth embodiment, the drain region of the high-voltage n-channel MOSFET 41a is the universal contact region (51, 52), but it may be the same n + type drain region 52 as in the HVIC according to the comparative example shown in FIGS. 9 and 10.

[0083] (Fifth Embodiment) FIG. 16 is a plan view of the periphery of the high-voltage n-channel MOSFET 41a and the pickup regions (62a, 64) of the semiconductor device (HVIC) according to the fifth embodiment of the present invention. FIG. 17 is a cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention, corresponding to the position viewed from the A-A' direction in FIG. 3.

[0084] As shown in FIGS. 16 and 17, the semiconductor device according to the fifth embodiment of the present invention is different from the semiconductor device according to the first embodiment of the present invention shown in FIG. 6 in the configuration of the pickup regions (62a, 64). Also, the drain region of the high-voltage n-channel MOSFET 41a is an n + type drain region 52, which is different from the semiconductor device according to the first embodiment of the present invention shown in FIG. 6.

[0085] As shown in FIG. 16, the pickup regions (62a, 64) extend linearly (in a line shape) on the planar pattern and are in contact with each other, with an n + type pickup region 62a and a p + type contact region 64. The n + type pickup region 62a and the p + type contact region 64 constitute a universal contact region.

[0086] As shown in FIG. 17, a pickup electrode 203a that makes an ohmic contact with the pickup regions (62a, 64) is provided on the pickup regions (62a, 64). The pickup regions (62a, 64) and the pickup electrode 203a constitute a universal contact structure (62a, 64, 203a).

[0087] Although not shown, the high-voltage n-channel MOSFET 41b shown in FIG. 3 has the same structure as the high-voltage n-channel MOSFET 41a shown in FIGS. 16 and 17. Other configurations of the semiconductor device according to the fifth embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and redundant descriptions are omitted.

[0088] According to the semiconductor device according to the fifth embodiment of the present invention, a pickup region (62a, 64) of the H-VDD potential near the drain regions of the high-voltage n-channel MOSFETs 41a and 41b is formed into a linear n + -type pickup region 62a and a p + -type contact region 64 to form a universal contact region, thereby enhancing the hole carrier extraction effect and reducing the amount of hole carriers flowing into the body diode 42 through the p-type junction isolation region 63.

[0089] (Sixth Embodiment) FIG. 18 is a plan view of the periphery of the high-voltage n-channel MOSFET 41a and the pickup regions (62a, 64) of the semiconductor device (HVIC) according to the sixth embodiment of the present invention. FIG. 19 is a cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention, corresponding to the position viewed from the A-A' direction in FIG. 3.

[0090] As shown in FIGS. 18 and 19, the semiconductor device according to the sixth embodiment of the present invention is different from the semiconductor device according to the fifth embodiment of the present invention shown in FIGS. 16 and 17 in that the drain region of the high-voltage n-channel MOSFET 41a is composed of universal contact regions (51, 52). As shown in FIG. 18, the universal contact regions (51, 52) extend linearly (in a line shape) on the planar pattern and are in contact with each other, with a p + -type contact region 51 and an n + -type contact region 52.

[0091] As shown in FIG. 19, a universal electrode (universal contact) 401 that makes an ohmic contact with the universal contact regions (51, 52) is provided on the universal contact regions (51, 52). The universal contact regions (51, 52) and the universal electrode 401 constitute a universal contact structure (51, 52, 401).

[0092] Although illustration is omitted, the high-voltage n-channel MOSFET 41b shown in FIG. 3 has the same structure as the high-voltage n-channel MOSFET 41a shown in FIGS. 18 and 19. Other configurations of the semiconductor device according to the sixth embodiment of the present invention are the same as those of the semiconductor device according to the fifth embodiment of the present invention, and duplicate explanations are omitted.

[0093] According to the semiconductor device according to the sixth embodiment of the present invention, the drain region of the high-voltage n-channel MOSFET 41a is formed into a universal contact region (51, 52) composed of a linear p + type contact region 51 and an n + type contact region 52. By doing so, when a negative surge voltage is applied, the extraction effect of holes, which are minority carriers flowing through the parasitic body diode, is enhanced, and the holes can be quickly extracted from the universal electrode 401.

[0094] (Seventh Embodiment) FIG. 20 is a plan view showing a main part of a semiconductor device according to the seventh embodiment of the present invention. FIG. 21 is a cross-sectional view including the high-voltage n-channel MOSFET 41a viewed from the A-A' direction in FIG. 20, and FIG. 22 is a cross-sectional view viewed from the B-B' direction in FIG. 20.

[0095] As shown in FIGS. 20 to 22, a trench (groove portion) 65 formed on the surface of the p-type semiconductor layer 1 is annularly provided on the surface side of the p-type base region 61. Further, a p + type trench contact region (p + type high-concentration base region) 57 having a higher impurity concentration than the p-type base region 61 formed on the side wall of the trench 65 is annularly provided. As shown in FIGS. 20 and 22, the p + type trench contact region 57 is connected to a pickup electrode (pickup contact) 202 connected to the GND potential.

[0096] As shown in FIG. 21, in the high-voltage n-channel MOSFET 41a viewed from the A-A' direction in FIG. 20, p +The p-type trench contact region 57 is in contact with the sidewall and the bottom surface of the trench 65 so as to surround the periphery of the trench 65. p + The p-type trench contact region 57 is provided in contact with the side surface and the bottom surface of the n + type source region 53.

[0097] p + On the p-type trench contact region 57 and the n + type source region 53, a source electrode (trench contact electrode) 400 is provided. The source electrode 400 is embedded in the trench 65 and is in ohmic contact with the p + type trench contact region 57 on the sidewall and the bottom surface of the trench 65. That is, the source electrode 400 is shorted to the pickup electrode (pickup contact) 202 connected to the GND potential at the same potential. Further, the source electrode 400 is in ohmic contact with the n + type source region 53 through a contact.

[0098] p + The p-type trench contact region 57 is formed in a normal flat active region and is used as, for example, the pickup region 202 at the GND potential or the source / drain region of the p-channel MOSFET constituting the logic circuit. The p + type trench contact region 57 is formed using an ion implantation mask separate from the p + type contact region 56. For example, after forming a polysilicon pattern, a trench 65 is dug in the region where the p 11 type trench contact region 5 is to be formed, a buffer oxide film is deposited, and boron ( + B) impurities are formed by high-concentration four-divided oblique ion implantation using a mask for ion implantation into the trench 65. Then, the p + type contact region 56 which is the source / drain region of the p-channel MOSFET constituting the logic circuit and the n + type contact regions 52 and 53 which are the source / drain regions of the high-voltage n-channel MOSFET 41a are selectively formed. By using boron ( 11 B) as the impurity for ion implantation for forming the p-type trench contact region 57, generally arsenic (75 using n of As) + diffuses deeper than the n-type contact region 52 and is formed by laterally diffusing not only along the sidewalls of the trench 65 but also down to below the n-type source region 53 of the high breakdown voltage n-channel MOSFET 41a. + It is formed by lateral diffusion down to below the n-type source region 53.

[0099] Although not shown, the high breakdown voltage n-channel MOSFET 41b shown in FIG. 20 also has the same structure as the high breakdown voltage n-channel MOSFET 41a shown in FIG. 21. Other configurations of the semiconductor device according to the seventh embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and redundant descriptions are omitted.

[0100] According to the semiconductor device according to the seventh embodiment of the present invention, when a negative surge voltage is applied to the H-VDD terminal (such as the pickup electrode 203a connected to the H-VDD terminal) via the Vs terminal 110, the forward current of the parasitic body diode 42 flows excessively from the GND terminal toward the H-VDD terminal because the p-type trench contact region (high-concentration base region) 57 is formed so as to contact the lower surface of the n-type source region 53 of the high breakdown voltage n-channel MOSFET 41a. Then, when the Vs potential returns and the H-VDD potential also returns to its voltage, the parasitic diode 42 enters the reverse recovery state. + type trench contact region (high-concentration base region) 57 is formed so as to contact the lower surface of the n-type source region 53 of the high breakdown voltage n-channel MOSFET 41a. Then, when a negative surge voltage is applied to the H-VDD terminal (such as the pickup electrode 203a connected to the H-VDD terminal) via the Vs terminal 110, the forward current of the parasitic body diode 42 flows excessively from the GND terminal toward the H-VDD terminal. Then, when the Vs potential returns and the H-VDD potential also returns to its voltage, the parasitic diode 42 enters the reverse recovery state. + At that time, as shown in FIG. 23, holes, which are minority carriers, flow excessively through the p-type semiconductor layer 1 and the n-type breakdown voltage region 4 and reach below the n-type source region 53. However, since there is a drawing structure of the p-type trench contact region 57 in the front stage, holes can be quickly drawn out. As a result, even when the reverse recovery current Irr (hole current) of the excessive body diode 42 flows in when the Vs potential returns, no voltage drop of 0.6 V or more occurs in the p-type base region 61 below the n-type source region 53, and the n-type source region 53, the p-type base region 61, and the n

[0101] At that time, as shown in FIG. 23, holes, which are minority carriers, flow excessively through the p-type semiconductor layer 1 and the n-type breakdown voltage region 4 and reach below the n-type source region 53. However, since there is a drawing structure of the p-type trench contact region 57 in the front stage, holes can be quickly drawn out. As a result, even when the reverse recovery current Irr (hole current) of the excessive body diode 42 flows in when the Vs potential returns, no voltage drop of 0.6 V or more occurs in the p-type base region 61 below the n-type source region 53, and the n-type source region 53, the p-type base region 61, and the n - type breakdown voltage region 4 to reach below the n-type source region 53. However, since there is a drawing structure of the p-type trench contact region 57 in the front stage, holes can be quickly drawn out. As a result, even when the reverse recovery current Irr (hole current) of the excessive body diode 42 flows in when the Vs potential returns, no voltage drop of 0.6 V or more occurs in the p-type base region 61 below the n-type source region 53, and the n-type source region 53, the p-type base region 61, and the n + type source region 53. However, since there is a drawing structure of the p-type trench contact region 57 in the front stage, holes can be quickly drawn out. As a result, even when the reverse recovery current Irr (hole current) of the excessive body diode 42 flows in when the Vs potential returns, no voltage drop of 0.6 V or more occurs in the p-type base region 61 below the n-type source region 53, and the n-type source region 53, the p-type base region 61, and the n + type trench contact region 57 exists, holes can be quickly drawn out. As a result, even when the reverse recovery current Irr (hole current) of the excessive body diode 42 flows in when the Vs potential returns, no voltage drop of 0.6 V or more occurs in the p-type base region 61 below the n-type source region 53, and the n-type source region 53, the p-type base region 61, and the n + type source region 53, the p-type base region 61, and the n + type source region 53, the p-type base region 61, and the n -It is possible to suppress the parasitic npn bipolar transistor operation constituted by the pressure-resistant region 4, and prevent malfunction of the level shift circuit, thermal runaway destruction due to parasitic operation, etc.

[0102] Note that, regarding the p-type trench contact region (p-type high-concentration base region) 57 in contact with the trench 65 of the semiconductor device according to the seventh embodiment of the present invention and the structure of the source electrode (trench contact electrode) 400 embedded in the trench 65, the structure in which the density of the n-type source region 53 of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. 15 is higher at a position not facing the universal contact regions (51, 52) than at a position facing the universal contact regions (51, 52) can also be applied. + type trench contact region (p + type high-concentration base region) 57 and the source electrode (trench contact electrode) 400 embedded in the trench 65, the structure of the n-type source region 53 of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. 15 is higher at a position not facing the universal contact regions (51, 52) than at a position facing the universal contact regions (51, 52). + type source region 53 of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. 15 is higher at a position not facing the universal contact regions (51, 52) than at a position facing the universal contact regions (51, 52).

[0103] (Eighth Embodiment) FIG. 24 is a plan view showing a high-voltage n-channel MOSFET 41a of a semiconductor device (HVIC) according to the eighth embodiment of the present invention. In the semiconductor device according to the seventh embodiment of the present invention described above, in order to enhance the hole carrier extraction effect in the n-type pressure-resistant region 4 and the n-type well region 3 during the period when a negative surge voltage is applied to the Vs terminal 110, it is desirable to widen the high-concentration p-type region under the n-type source region 53. - However, attempting to surround the entire area under the n-type contact region 53 with the p-type trench contact region 57 may cause an excessive dose amount of ion implantation or a high-acceleration voltage ion implantation, resulting in an overly wide p-type trench contact region 57. Conversely, narrowing the width of the n-type contact region (n-type source region) 53 of the source too much may increase the source contact resistance of the high-voltage n-channel MOSFET 41a, leading to a significant decrease in on-current and an increase in threshold voltage. + source region 53, it is desirable to widen the high-concentration p-type region under the n-type source region 53. + type region under the n-type source region 53.

[0104] However, + attempting to surround the entire area under the n-type contact region 53 with the p-type trench contact region 57 may cause an excessive dose amount of ion implantation or a high-acceleration voltage ion implantation, resulting in an overly wide p-type trench contact region 57. + type trench contact region 57. + type trench contact region 57 or, conversely, narrowing the width of the n-type contact region (n-type source region) 53 of the source too much may increase the source contact resistance of the high-voltage n-channel MOSFET 41a, leading to a significant decrease in on-current and an increase in threshold voltage. + type contact region (n + type source region) 53 of the source too much may increase the source contact resistance of the high-voltage n-channel MOSFET 41a, leading to a significant decrease in on-current and an increase in threshold voltage.

[0105] Therefore, in the semiconductor device according to the eighth embodiment of the present invention, as shown in FIG. + The source region 53 is not linearly shaped but is divided into a plurality of small pieces, and a plurality of n + Between the source regions 53 + The contact region 56 is arranged between the electrodes. + The number of divisions, size, intervals, etc. of the source region 53 are not particularly limited. + The source region 53 and p + A contact for the source electrode 400 is formed across the mold contact region 56 .

[0106] Although not shown in the figure, the high-voltage n-channel MOSFET 41b has the same structure as the high-voltage n-channel MOSFET 41a shown in Fig. 24. Other configurations of the semiconductor device according to the eighth embodiment of the present invention are the same as those of the semiconductor device according to the seventh embodiment of the present invention, and therefore redundant explanations will be omitted.

[0107] According to the semiconductor device of the eighth embodiment of the present invention, holes, which are minority carriers, are transported to n + The p + Since the light can be absorbed by the n-type contact region 56, + The entire area under the source region 53 is p + Even if the base is not surrounded by the trench contact region 57, an increase in base resistance can be suppressed, and the operation of a parasitic npn bipolar transistor can be suppressed.

[0108] Regarding the manufacturing process of the semiconductor device according to the seventh and eighth embodiments of the present invention, - The high-voltage breakdown voltage region 4, the n-type well region 3, the p-type base region 61, and the p-type junction isolation region 63 are formed by ion-implanting n-type impurities such as phosphorus or p-type impurities such as boron through a patterning process, and then diffusing them to a predetermined diffusion depth in a diffusion process at a high temperature (about 1100 to 1200°C). The Vs potential region 200 provided in the high-side circuit section and the well region of the low-side circuit section are formed by ion-implanting n-type impurities such as phosphorus or p-type impurities such as boron through a patterning process, and then diffusing them to a predetermined diffusion depth in a diffusion process at a high temperature (about 1100 to 1200°C). -It is formed by diffusion to a predetermined diffusion depth in a diffusion process different from the diffusion process for forming the p-type pressure-resistant region 4, n-type well region 3, p-type base region 61, and p-type junction isolation region 63.

[0109] n + The n-type pickup region 62 is ion-implanted with an n-type impurity such as arsenic to a surface concentration of about 1×10 20 / cm 3 and then formed at a predetermined depth by an annealing process at about 750 to 900 °C, for example. The n + source region 53 and n + type contact region 52 of the high-voltage n-channel MOSFET 41a are also formed by ion implantation and annealing treatment in the same manner as the n + type pickup region 62.

[0110] p + The p-type contact region 56 is ion-implanted with BF2 to a surface concentration of about 1×10 + through a patterning process for region formation, and then formed at a predetermined diffusion depth by an annealing process at about 750 to 900 °C, which is the same as the annealing process of the n 20 / cm 3 type pickup region 62, for example. + After the annealing process, each is formed at a predetermined diffusion depth.

[0111] p + The p-type trench contact region 57 is formed by dry etching a trench 65 with a depth of about 0.5 to 5.0 μm and a width of about 0.5 to 5.0 μm in a region adjacent to the n + source region 53 after forming a polysilicon pattern, depositing a buffer oxide film, and using a mask for ion implantation into the trench groove region to perform four-part oblique ion implantation of boron (B11) impurities so that the concentration on the trench sidewall is 1×10 19 ~1×10 20 / cm 3 and then formed in the same manner as the n + type pickup region 62 and p +They are formed at predetermined diffusion depths by an annealing process at about 750 to 900 °C, which is the same as the annealing process for the type - contact region 56. Note that when performing four - divided diagonal ion implantation, 0° ion implantation may be used in combination so that boron impurities also enter the trench bottom surface.

[0112] (Embodiment 9) FIG. 25 is a cross - sectional view of a semiconductor device (HVIC) according to the ninth embodiment of the present invention, corresponding to the cross - section of the semiconductor device according to the seventh embodiment of the present invention shown in FIG. 21. As shown in FIG. 25, the semiconductor device according to the ninth embodiment of the present invention has a p + - type trench contact region (p + - type high - concentration base region) 57 and a source electrode (trench contact electrode) 400 embedded in the trench 65, which is the same as the semiconductor device according to the seventh embodiment of the present invention shown in FIG. 21.

[0113] However, the semiconductor device according to the ninth embodiment of the present invention is different from the semiconductor device according to the seventh embodiment of the present invention shown in FIG. 21 in that the high - voltage - resistant n - channel MOSFET 41a has a universal contact region (51, 52) as a drain region provided in the surface layer of the n - type well region 3. The universal contact region (51, 52) is composed of a p + - type contact region 51 and an n + - type contact region 52 that are in contact with each other and arranged alternately.

[0114] Furthermore, the semiconductor device according to the ninth embodiment of the present invention is different from the semiconductor device according to the seventh embodiment of the present invention shown in FIG. 21 in that the contacts of the pickup regions (62a, 64) near the drain region of the high - voltage - resistant n - channel MOSFET 41a are used as the universal contact region. As shown in FIGS. 11 and 12, the pickup regions (62a, 64) are composed of an n + - type pickup region 62a and a p + - type contact region 64 that are in contact with each other and arranged alternately to form the universal contact region.

[0115] Although illustration is omitted, the high breakdown voltage n-channel MOSFET 41b also has the same structure as the high breakdown voltage n-channel MOSFET 41a shown in FIG. 25. Other configurations of the semiconductor device according to the ninth embodiment of the present invention are the same as those of the semiconductor device according to the seventh embodiment of the present invention, and redundant descriptions are omitted.

[0116] According to the semiconductor device according to the ninth embodiment of the present invention, the same effects as those of the semiconductor device according to the seventh embodiment of the present invention are achieved. Furthermore, by making the drain regions of the high breakdown voltage n-channel MOSFETs 41a and 41b into universal contact regions (51, 52), the body diode current that flows when a negative surge voltage is input to the Vs terminal 110 efficiently extracts hole carriers in the p-type contact region 51 of the universal contact regions (51, 52) and can reduce residual carriers. Therefore, the reverse recovery current Irr (hole current) when the Vs potential recovers can be reduced, and the parasitic npn bipolar transistor operation triggered by the reverse recovery current Irr can be suppressed. + Moreover, by making the pickup regions (62a, 64) of the H-VDD potential near the drain region 52 of the high breakdown voltage n-channel MOSFETs 41a and 41b into universal contact regions, the amount of hole carriers flowing into the body diode 42 through the p-type junction isolation region 63 can be reduced. Therefore, the parasitic npn bipolar transistor operation due to the reverse recovery phenomenon of the body diode 42 when recovering from the negative surge of the Vs potential can be prevented.

[0117] Furthermore, by making the pickup regions (62a, 64) of the H-VDD potential near the drain region 52 of the high breakdown voltage n-channel MOSFETs 41a and 41b into universal contact regions, the amount of hole carriers flowing into the body diode 42 through the p-type junction isolation region 63 can be reduced. Therefore, the parasitic npn bipolar transistor operation due to the reverse recovery phenomenon of the body diode 42 when recovering from the negative surge of the Vs potential can be prevented.

[0118] (Other Embodiments) As described above, the present invention has been described by the first to ninth embodiments, but it should not be understood that the discussions and drawings forming a part of this disclosure limit the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0119] For example, as the semiconductor device according to the first to ninth embodiments, a structure in which an n-type diffusion layer such as an n-type well region 3 is formed on the surface layer of the p-type semiconductor layer 1 is exemplified, but the present invention is not limited thereto. For example, a structure in which an n-type epitaxial growth layer is grown on the p-type semiconductor layer 1 also has the same effect. Further, even when a p-type epitaxial growth layer is grown on the p-type semiconductor layer 1 and an n-type buried layer is provided at the junction between the p-type epitaxial growth layer and the p-type semiconductor layer 1, the same effect is obtained.

[0120] Further, as the semiconductor device according to the first to ninth embodiments, a structure in which high-voltage n-channel MOSFETs 41a and 41b are provided on the same side of the annular planar pattern of the HVJT303 is exemplified, but the present invention is not limited thereto. For example, the high-voltage n-channel MOSFETs 41a and 41b may be individually provided on opposite sides of the annular planar pattern of the HVJT303. When this structure is adopted in the second embodiment, the contacts of the pickup regions closest to the respective drain regions of the high-voltage n-channel MOSFETs 41a and 41b may be made into universal contact regions.

[0121] Further, although the HVIC is exemplified as the semiconductor device according to the first to ninth embodiments, the present invention is also applicable to semiconductor devices other than the HVIC. For example, it is particularly effective for semiconductor devices to which a high voltage of several tens of volts or more is applied.

Description of Reference Numerals

[0122] 1... p-type semiconductor layer 2... p-type well region 3... n-type well region 4... n - -type high-voltage region 41, 41a, 41b... level shifter 42... body diode 51... p + -type contact region 52... n + -type contact region (n + -type drain region) 53... n + -type source region 53a... opposing region 53b, 53c… End regions 56… p + Type contact region 57… p + Type trench contact region (high-concentration base region) 61… p-type base region 62a, 62b, 62c, 62d… n + Type pickup region 63… p-type junction isolation region 64… p + Type contact region 65… Trench (groove part) 71, 72, 75, 76… MOSFET 73… Level shift resistor 74… Diode 101… Output part 102… H-VDD pad 103… H-OUT pad 104… Vs pad 105… H-IN pad 106… L-VDD pad 107… GND pad 110… Vs terminal 111… High-voltage integrated circuit device (HVIC) 112, 113… Low-voltage power supply 114, 115… IGBT 116, 117… Freewheeling diode 118… L load 119… Detection signal 120… H-VDD terminal 131… Low-side circuit 132… Level shift circuit (level-up circuit) 133… High-side circuit 173… Level shift resistor 200… Vs potential region 201… H-VDD potential region 202, 203, 203a, 203b, 203c, 203d… Pickup electrodes 301… High-side circuit region 302… Low-side circuit region 303… High-voltage junction termination region (HVJT) 400…Source electrode 401…Universal electrode 402…Gate electrode 501…First electrode 502…Second electrode

Claims

1. A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type that is located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region and has a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region, a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the breakdown voltage region, a plurality of pickup regions provided on the surface layer of the well region, comprising, the carrier reception region is composed of a first universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other, a semiconductor device, characterized in that one of the plurality of pickup regions is electrically connected to the carrier reception region via a resistor.

2. A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type that is located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region and has a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region, a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the breakdown voltage region, comprising, wherein the carrier receiving region is composed of a first universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, further comprising a plurality of pickup regions provided on a surface layer of the well region, wherein the pickup region is composed of a second universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, The semiconductor device is characterized in that the second universal contact region is a pickup region disposed inside the carrier receiving region and outside a circuit portion in the high potential side circuit region on a planar pattern. **Claim 3**: A semiconductor device in which a high potential side circuit region, a high voltage resistant junction termination structure provided around the high potential side circuit region, and a low potential side circuit region provided around the high potential side circuit region via the high voltage resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type, which is located in the high potential side circuit region and provided on a surface layer of the semiconductor layer, a second conductivity type high voltage resistant region surrounding the well region and provided in contact with the well region, having a lower impurity concentration than the well region, a base region of a first conductivity type surrounding the high voltage resistant region and provided in contact with the high voltage resistant region, a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region, the carrier supply region of a second conductivity type provided on a surface layer of the base region, a carrier receiving region of the level shifter, the carrier receiving region being provided on a surface layer of the well region or the high voltage resistant region, comprising, wherein the carrier receiving region is composed of a first universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, further comprising a plurality of pickup regions provided on a surface layer of the well region, wherein the pickup region is composed of a second universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, The semiconductor device is characterized in that the second universal contact region is the pickup region closest to the carrier receiving region. **Claim 4**: A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type; a well region of a second conductivity type, which is located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer; a breakdown voltage region of a second conductivity type, which surrounds the well region, has a lower impurity concentration than the well region, and is provided in contact with the well region; a base region of a first conductivity type, which surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region; a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of a second conductivity type being provided on the surface layer of the base region; a carrier receiving region of the level shifter, the carrier receiving region being provided on the surface layer of the well region or the breakdown voltage region; comprising: the carrier receiving region is composed of a first universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other; further comprising a plurality of pickup regions provided on the surface layer of the well region; the pickup region is composed of a second universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other; the semiconductor device is characterized in that the second universal contact region is the pickup region closest to the carrier receiving region, and the distance from the carrier receiving region is within 100 μm. **Claim 5** The semiconductor device according to claim 3, characterized in that the second universal contact region is the pickup region disposed between a circuit portion in the high-potential-side circuit region and the carrier receiving region on a planar pattern. **Claim 6**: A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type; a well region of a second conductivity type, which is located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer; a breakdown voltage region of a second conductivity type, which surrounds the well region, has a lower impurity concentration than the well region, and is provided in contact with the well region; Surrounding the pressure-resistant region, a base region of the first conductivity type provided in contact with the pressure-resistant region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type provided on the surface layer of the base region, A carrier reception region of the level shifter, the carrier reception region provided on the surface layer of the well region or the pressure-resistant region, Comprising: The carrier reception region is composed of a first universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other, On a planar pattern, the carrier supply region and the carrier reception region are provided parallel to each other, The width of the carrier supply region is wider than the width of the carrier reception region A semiconductor device characterized by the above.

7. On a planar pattern, the density of the carrier supply region at a position facing the carrier reception region is lower than the density of the carrier supply region at a position not facing the carrier reception region, the semiconductor device according to claim 6.

8. A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, A semiconductor layer of the first conductivity type, A well region of the second conductivity type located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer, Surrounding the well region, a pressure-resistant region of the second conductivity type having a lower impurity concentration than the well region, provided in contact with the well region, Surrounding the pressure-resistant region, a base region of the first conductivity type provided in contact with the pressure-resistant region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type provided on the surface layer of the base region, A carrier reception region of the level shifter, the carrier reception region provided on the surface layer of the well region or the pressure-resistant region, A plurality of pickup regions provided on the surface layer of the well region, Comprising: The pickup region is composed of a universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other, The semiconductor device is characterized in that the universal contact region is a pickup region disposed on a planar pattern, outside a circuit portion in the high-potential side circuit region and inside the carrier receiving region. **Claim 9**: A semiconductor device in which a high-potential side circuit region, a high-voltage breakdown termination structure provided around the high-potential side circuit region, and a low-potential side circuit region provided around the high-potential side circuit region via the high-voltage breakdown termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type located in the high-potential side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region, having a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential side circuit region and the high-potential side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region, a carrier receiving region of the level shifter, the carrier receiving region being provided on the surface layer of the well region or the breakdown voltage region, a plurality of pickup regions provided on the surface layer of the well region, comprising: the pickup region is composed of a universal contact region in which a region of the first conductivity type and a region of the second conductivity type are provided in contact with each other, the semiconductor device is characterized in that the universal contact region is the pickup region closest to the carrier receiving region. **Claim 10**: A semiconductor device in which a high-potential side circuit region, a high-voltage breakdown termination structure provided around the high-potential side circuit region, and a low-potential side circuit region provided around the high-potential side circuit region via the high-voltage breakdown termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type located in the high-potential side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region, having a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region, the carrier supply region being a carrier supply region of a second conductivity type provided in a surface layer of the base region, and A carrier receiving region of the level shifter, the carrier receiving region being a carrier receiving region provided in a surface layer of the well region or the breakdown voltage region, and A plurality of pickup regions provided in a surface layer of the well region, and Comprising The pickup region is composed of a universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, The universal contact region is the pickup region closest to the carrier receiving region, and the semiconductor device is characterized in that the distance from the carrier receiving region is within 100 μm.

11. The semiconductor device according to claim 8, wherein the universal contact region is a pickup region disposed between a circuit portion in the high potential side circuit region and the carrier receiving region on a planar pattern.

12. A semiconductor device in which a high potential side circuit region, a high breakdown voltage junction termination structure provided around the high potential side circuit region, and a low potential side circuit region provided around the high potential side circuit region via the high breakdown voltage junction termination structure are integrated on the same semiconductor chip, A semiconductor layer of a first conductivity type, and A well region of a second conductivity type that is located in the high potential side circuit region and is provided in a surface layer of the semiconductor layer, A breakdown voltage region of a second conductivity type having a lower impurity concentration than the well region, surrounding the well region and provided in contact with the well region, A base region of a first conductivity type surrounding the breakdown voltage region and provided in contact with the breakdown voltage region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region, the carrier supply region being a carrier supply region of a second conductivity type provided in a surface layer of the base region, and A carrier receiving region of the level shifter, the carrier receiving region being a carrier receiving region provided in a surface layer of the well region or the breakdown voltage region, and A plurality of pickup regions provided in a surface layer of the well region, and Comprising The pickup region is composed of a universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, The semiconductor device is characterized in that the pickup region is electrically connected to the carrier receiving region via a resistor.

13. A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region and has a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, a carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential-side circuit region and the high-potential-side circuit region, the carrier supply region of the second conductivity type being provided on the surface layer of the base region, a carrier reception region of the level shifter, the carrier reception region being provided on the surface layer of the well region or the breakdown voltage region, comprising: On a planar pattern, the carrier supply region and the carrier reception region are provided parallel to each other, the width of the carrier supply region is wider than the width of the carrier reception region, On a planar pattern, the density of the carrier supply region at a position facing the carrier reception region is lower than the density of the carrier supply region at a position not facing the carrier reception region, a semiconductor device characterized by this.

14. The semiconductor device according to any one of claims 1 to 13, further comprising a junction isolation region of the first conductivity type provided so as to penetrate the well region and reach the semiconductor layer.

15. A semiconductor device in which a high-potential-side circuit region, a high-voltage-resistant junction termination structure provided around the high-potential-side circuit region, and a low-potential-side circuit region provided around the high-potential-side circuit region via the high-voltage-resistant junction termination structure are integrated on the same semiconductor chip, a semiconductor layer of a first conductivity type, a well region of a second conductivity type located in the high-potential-side circuit region and provided on the surface layer of the semiconductor layer, a breakdown voltage region of the second conductivity type that surrounds the well region and is provided in contact with the well region and has a lower impurity concentration than the well region, a base region of the first conductivity type that surrounds the breakdown voltage region and is provided in contact with the breakdown voltage region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential side circuit region and the high-potential side circuit region, the carrier supply region being a carrier supply region of a second conductivity type provided in a surface layer of the base region, and A carrier receiving region of the level shifter, the carrier receiving region being a carrier receiving region provided in a surface layer of the well region or the high-voltage withstand region, and Comprising: The carrier receiving region is composed of a first universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, A high-concentration base region of a first conductivity type having a higher impurity concentration than the base region, which is in contact with a side wall of a trench provided in a surface layer of the base region and is provided in contact with the carrier supply region, and A trench contact electrode embedded in the trench and making ohmic contact with the high-concentration base region, and A semiconductor device, further comprising:

16. The semiconductor device according to claim 15, wherein the high-concentration base region is in contact with a lower surface of the carrier supply region.

17. The semiconductor device according to claim 15 or 16, wherein the high-concentration base region is in contact with a bottom surface of the trench.

18. A semiconductor device in which a high-potential side circuit region, a high-voltage withstand junction termination structure provided around the high-potential side circuit region, and a low-potential side circuit region provided around the high-potential side circuit region via the high-voltage withstand junction termination structure are integrated on the same semiconductor chip, A semiconductor layer of a first conductivity type, A well region of a second conductivity type provided in a surface layer of the semiconductor layer and located in the high-potential side circuit region, A high-voltage withstand region of a second conductivity type having a lower impurity concentration than the well region, surrounding the well region and provided in contact with the well region, A base region of a first conductivity type surrounding the high-voltage withstand region and provided in contact with the high-voltage withstand region, A carrier supply region of a level shifter included in a level shift circuit that transmits a signal between the low-potential side circuit region and the high-potential side circuit region, the carrier supply region being a carrier supply region of a second conductivity type provided in a surface layer of the base region, and A carrier receiving region of the level shifter, the carrier receiving region being a carrier receiving region provided in a surface layer of the well region or the high-voltage withstand region, and A plurality of pickup regions provided in a surface layer of the well region, and Comprising: The pickup region is composed of a universal contact region in which a region of a first conductivity type and a region of a second conductivity type are provided in contact with each other, A high-concentration base region of a first conductivity type having an impurity concentration higher than that of the base region, which is in contact with the side wall of a trench provided in the surface layer of the base region and is provided in contact with the carrier supply region, A trench contact electrode embedded in the trench and in ohmic contact with the high-concentration base region, A semiconductor device, further comprising the same.

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