Wiring Substrate, Method for Manufacturing the Same, and Semiconductor Device

Abstract

To improve adhesion between a wiring pattern and an insulation layer constituting a stripline in a wiring board including the stripline.SOLUTION: A wiring board comprises a first wiring layer, a first insulation layer covering a side surface and a lower surface of the first wiring layer, a second insulation layer arranged on the first insulation layer and covering the upper surface of the first wiring layer, a second wiring layer formed on a lower surface of the first insulation layer, and a third wiring layer formed on an upper surface of the second insulation layer. The second wiring layer includes a first ground plane, and the third wiring layer includes a second ground plane. The first ground plane, the first insulation layer, the first wiring layer, the second insulation layer, and the second ground plane constitute a stripline.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board, a method for manufacturing the same, and a semiconductor device.

Background Art

[0002] A wiring board for mounting a semiconductor chip, which is a part of a semiconductor device, on which a semiconductor chip is mounted is known (see, for example, Patent Document 1). When the semiconductor chip supports high-frequency signals, a microstrip line or a strip line may be provided on the wiring board in order to control the characteristic impedance.

[0003] Since the line / space of the wiring pattern constituting the strip line can be made smaller than the line / space of the wiring pattern constituting the microstrip line having the same characteristic impedance, by adopting the strip line, it becomes possible to increase the wiring density on the wiring board.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the line / space of the wiring pattern constituting the strip line becomes small, the adhesion strength between the wiring pattern and the insulating layer decreases, and there is a risk that the wiring pattern peels off from the insulating layer.

[0006] The present invention has been made in view of the above points, and an object thereof is to improve the adhesion between the wiring pattern constituting the strip line and the insulating layer in a wiring board having a strip line.

Means for Solving the Problems

[0007] This wiring board includes a first wiring layer, a first insulating layer that covers the side surface and the lower surface of the first wiring layer, a second insulating layer that is disposed on the first insulating layer and covers the upper surface of the first wiring layer, a second wiring layer formed on the lower surface of the first insulating layer, and a third wiring layer formed on the upper surface of the second insulating layer, A solder resist layer formed on the upper surface of the second insulating layer and covering the third wiring layer; and the second wiring layer includes a first ground plane, the third wiring layer includes a second ground plane, and the first ground plane, the first insulating layer, the first wiring layer, the second insulating layer, and the second ground plane constitute a stripline And , The second wiring layer includes a first signal pad disposed in an opening provided in the first ground plane. The third wiring layer includes a second signal pad disposed in an opening provided in the second ground plane. The first wiring layer includes a pad electrically connected to the second signal pad via a via wiring penetrating the second insulating layer. The second signal pad is exposed in an opening provided in the solder resist layer, and the side of the solder resist layer is the side on which the semiconductor chip is mounted. .

Advantages of the Invention

[0008] According to the disclosed technology, in a wiring board having a stripline, the adhesion between the wiring pattern and the insulating layer constituting the stripline can be improved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

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Figure 7

Figure 8

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Figure 10

Figure 11

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Figure 16

MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and redundant explanations may be omitted.

[0011] 〈FIRST EMBODIMENT〉 [Structure of Wiring Board] FIG. 1 is a cross-sectional view illustrating a wiring board according to the First Embodiment. FIG. 2 is a partial plan view illustrating the wiring board according to the First Embodiment. Specifically, FIG. 2(a) is a partial plan view of portion A in FIG. 1 viewed from the upper surface side of the first wiring layer 11, FIG. 2(b) is a partial plan view of portion B in FIG. 1 viewed from the lower surface side of the second wiring layer 14, and FIG. 2(c) is a partial plan view of portion C in FIG. 1 viewed from the upper surface side of the third wiring layer 15.

[0012] Referring to FIG. 1, the wiring board 1 includes a first wiring layer 11, a first insulating layer 12, a second insulating layer 13, a second wiring layer 14, a third wiring layer 15, a third insulating layer 16, a fourth wiring layer 17, a solder resist layer 21, and a solder resist layer 22.

[0013] In this embodiment, for convenience, the side of the wiring board 1 where the solder resist layer 21 is located in FIG. 1 is defined as the upper side or one side, and the side where the solder resist layer 22 is located is defined as the lower side or the other side. Also, the surface on the solder resist layer 21 side of each part is defined as one surface or the upper surface, and the surface on the solder resist layer 22 side is defined as the other surface or the lower surface. However, the wiring board 1 can be used in an upside-down state or arranged at an arbitrary angle. Further, a plan view means viewing an object from the normal direction of one surface of the solder resist layer 21, and a planar shape means the shape of an object viewed from the normal direction of one surface of the solder resist layer 21. When the wiring board 1 is illustrated with an upside-down orientation compared to FIG. 1, the definitions of the upper surface and the lower surface are opposite to the above in accordance with the drawing display.

[0014] The first wiring layer 11 includes a plurality of wiring patterns 11W and a plurality of pads 11P. The planar shape of the pad 11P is, for example, a circle with a diameter of about 60 μm to 120 μm. Note that the diameter of the pad 11P is smaller than the diameter of the first signal pad 14A and the diameter of the second signal pad 15A, which will be described later, within any of the above ranges. As the material of the wiring pattern 11W and the pad 11P, for example, copper (Cu) or the like can be used. The wiring pattern 11W and the pad 11P may have a laminated structure of a plurality of metal layers. The thickness of the wiring pattern 11W and the pad 11P can be, for example, about 10 to 30 μm.

[0015] The first wiring layer 11 is the wiring layer with the highest density among the wiring patterns of the wiring substrate 1. That is, the minimum interval between adjacent wiring patterns 11W in the first wiring layer 11 is narrower than the minimum interval between adjacent wiring patterns in other wiring layers. The line / space of the wiring pattern 11W can be, for example, about line 8 - 10 μm / space 8 - 10 μm. Here, the line in the line / space represents the wiring width, and the space represents the interval (wiring interval) between adjacent wirings. For example, when it is described as line 8 μm / space 10 μm, it means that the wiring width is 8 μm and the interval between adjacent wirings is 10 μm.

[0016] The first insulating layer 12 is formed so as to cover the side surface and the lower surface of the first wiring layer 11. The upper surface of the first insulating layer 12 can be flush with the upper surface of the first wiring layer 11, for example. As the material of the first insulating layer 12, for example, an insulating resin mainly composed of an epoxy-based resin or a polyimide-based resin can be used. The thickness of the first insulating layer 12 can be about 20 - 30 μm, for example. Here, the thickness of the first insulating layer 12 refers to the distance from the lower surface of the first wiring layer 11 to the lower surface of the first insulating layer 12. The same applies to the thickness of the subsequent insulating layers and the like. The first insulating layer 12 can contain a filler such as silica (SiO2). The content of the filler in the first insulating layer 12 can be appropriately set according to the required coefficient of thermal expansion (CTE).

[0017] On the upper surface of the first insulating layer 12, a second insulating layer 13 that covers the upper surface of the first wiring layer 11 is laminated. The material and thickness of the second insulating layer 13 can be the same as those of the first insulating layer 12, for example. The second insulating layer 13 can contain a filler such as silica (SiO2). The content of the filler in the second insulating layer 13 can be the same as that of the first insulating layer 12, for example.

[0018] On the lower surface of the first insulating layer 12, a second wiring layer 14 is formed. The second wiring layer 14 includes a first ground plane 14G, a first signal pad 14A, a first ground pad 14B, and via wiring 14V. The first ground plane 14G is formed in a substantially solid state so as to cover most of the lower surface of the first insulating layer 12. The first signal pad 14A is disposed within an opening 14x provided in the first ground plane 14G. The planar shape of the first signal pad 14A is, for example, a circle with a diameter of about 80 μm to 200 μm. The first ground pad 14B forms a part of the first ground plane 14G.

[0019] The first signal pad 14A and the first ground pad 14B are integrally formed with via wiring 14V filled in via holes 12x that penetrate the first insulating layer 12 and expose the lower surface of the first wiring layer 11. The via holes 12x can be frustum-shaped recesses in which the diameter of the opening on the side of the third insulating layer 16 is larger than the diameter of the bottom surface of the opening formed by the lower surface of the pad 11P. In this case, the area of the portion of the via wiring 14V connected to the lower surface of the pad 11P is smaller than the area of the portion connected to the upper surface of the first signal pad 14A or the first ground pad 14B.

[0020] The plurality of pads 11P include pads 11P electrically connected to the first signal pad 14A via via wiring 14V penetrating the first insulating layer 12, and pads 11P electrically connected to the first ground pad 14B via via wiring 14V penetrating the first insulating layer 12. The material of the second wiring layer 14 and the thickness of the ground plane and the pads can be, for example, the same as those of the first wiring layer 11.

[0021] On the upper surface of the second insulating layer 13, a third wiring layer 15 is formed. The third wiring layer 15 includes a second ground plane 15G, second signal pads 15A, second ground pads 15B, and via wirings 15V. The second ground plane 15G is formed in a substantially solid shape so as to cover most of the upper surface of the second insulating layer 13. The second signal pads 15A are disposed within openings 15x provided in the second ground plane 15G. The planar shape of the second signal pads 15A is, for example, circular with a diameter of about 80 μm to 200 μm. The second ground pads 15B form part of the second ground plane 15G.

[0022] The second signal pads 15A and the second ground pads 15B are integrally formed with via wirings 15V filled in via holes 13x that penetrate the second insulating layer 13 and expose the upper surface of the first wiring layer 11, respectively. The via holes 13x can be formed as inverted frustoconical recesses in which the diameter of the opening on the solder resist layer 21 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the pads 11P. In this case, the area of the portion of the via wiring 15V connected to the upper surface of the pads 11P is smaller than the area of the portion connected to the lower surface of the second signal pads 15A or the second ground pads 15B.

[0023] The plurality of pads 11P include pads 11P electrically connected to the second signal pads 15A via via wirings 15V penetrating the second insulating layer 13, and pads 11P electrically connected to the second ground pads 15B via via wirings 15V penetrating the second insulating layer 13. The material of the third wiring layer 15, the thickness of the ground plane and the pads can be, for example, the same as those of the first wiring layer 11.

[0024] The third insulating layer 16 is formed on the lower surface of the first insulating layer 12 so as to cover the second wiring layer 14. The material and thickness of the third insulating layer 16 can be, for example, the same as those of the first insulating layer 12. The third insulating layer 16 can contain fillers such as silica (SiO2). The content of the filler in the third insulating layer 16 can be, for example, the same as that in the first insulating layer 12.

[0025] The fourth wiring layer 17 is formed on the other side of the third insulating layer 16. The fourth wiring layer 17 includes via wirings filled in via holes 16x that penetrate the third insulating layer 16 and expose the bottom surface of the second wiring layer 14, pads formed on the bottom surface of the third insulating layer 16, and wiring patterns. The pads constituting the fourth wiring layer 17 are electrically connected to the first signal pads 14A or the first ground pads 14B via the via wirings. The via holes 16x can be frustum-shaped recesses in which the diameter of the opening on the solder resist layer 22 side is larger than the diameter of the bottom surface of the opening formed by the bottom surface of the first signal pads 14A or the first ground pads 14B. The material of the fourth wiring layer 17, and the thicknesses of the pads and the wiring patterns can be the same as those of the first wiring layer 11, for example.

[0026] The solder resist layer 21 is the outermost layer on one side of the wiring substrate 1, and is formed on the upper surface of the second insulating layer 13 so as to cover the third wiring layer 15. The solder resist layer 21 can be formed from a photosensitive resin such as an epoxy resin or an acrylic resin, for example. The thickness of the solder resist layer 21 can be about 15 to 35 μm, for example.

[0027] The solder resist layer 21 has openings 21x, and a part of the upper surface of the second signal pads 15A or the second ground pads 15B constituting the third wiring layer 15 is exposed at the bottom of the openings 21x. The planar shape of the openings 21x can be circular, for example. The second signal pads 15A and the second ground pads 15B of the third wiring layer 15 exposed in the openings 21x can be used to be electrically connected to the semiconductor chip. That is, the side of the solder resist layer 21 is the side on which the semiconductor chip is mounted.

[0028] If necessary, a metal layer may be formed on the upper surface of the second signal pad 15A or the second ground pad 15B exposed within the opening 21x, or an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order), and the like.

[0029] The solder resist layer 22 is the outermost layer on the other side of the wiring board 1 and is formed on the lower surface of the third insulating layer 16 so as to cover the fourth wiring layer 17. The material and thickness of the solder resist layer 22 can be the same as those of the solder resist layer 21, for example. The solder resist layer 22 has an opening 22x, and a part of the lower surface of the pad of the fourth wiring layer 17 is exposed within the opening 22x. The planar shape of the opening 22x can be circular, for example. The pad of the fourth wiring layer 17 exposed within the opening 22x can be used for electrical connection with a mounting board (not shown) such as a motherboard. If necessary, a metal layer as described above may be formed on the lower surface of the pad of the fourth wiring layer 17 exposed within the opening 22x, or an anti-oxidation treatment such as OSP treatment may be performed.

[0030] In this way, in the wiring board 1, the first wiring layer 11 is sandwiched vertically between the first ground plane 14G and the second ground plane 15G via insulating layers (the first insulating layer 12 and the second insulating layer 13). That is, in the wiring board 1, the first ground plane 14G, the first insulating layer 12, the first wiring layer 11, the second insulating layer 13, and the second ground plane 15G constitute a stripline SL. Thereby, the characteristic impedance of the first wiring layer 11 can be controlled, and the electromagnetic waves leaking from the first wiring layer 11 can be reduced.

[0031] The stripline SL is preferably disposed immediately below the solder resist layer 21 on the side where the semiconductor chip is mounted. Thereby, since the wiring path connecting the semiconductor chip and the first wiring layer 11 can be shortened, when manufacturing a semiconductor device in which a semiconductor chip is disposed on the wiring substrate 1, the electrical characteristics of the semiconductor device can be improved.

[0032] Also, in the wiring substrate 1, the first wiring layer 11 constituting the stripline SL is an embedded wiring whose side surface and bottom surface are covered with the first insulating layer 12. Thereby, compared with non-embedded wiring in which only the bottom surface contacts the insulating layer and the side surface is exposed from the insulating layer as in the prior art, the adhesion between the wiring pattern 11W and the pad 11P constituting the first wiring layer 11 and the first insulating layer 12 can be improved.

[0033] Also, in the wiring substrate 1, the area of the portion where the via wiring 14V is connected to the bottom surface of the pad 11P is smaller than the area of the portion where the via wiring 14V is connected to the upper surface of the first signal pad 14A or the first ground pad 14B. And the area of the portion where the via wiring 15V is connected to the upper surface of the pad 11P is smaller than the area of the portion where the via wiring 15V is connected to the lower surface of the second signal pad 15A or the second ground pad 15B. Thereby, since the area of the bottom surface of the pad 11P can be made smaller than the area of the upper surface of the first signal pad 14A, and the area of the upper surface of the pad 11P can be made smaller than the area of the lower surface of the second signal pad 15A, it becomes possible to increase the density of the first wiring layer 11.

[0034] [Manufacturing Method of Wiring Substrate] Next, a manufacturing method of the wiring substrate according to the first embodiment will be described. FIGS. 3 to 6 are diagrams illustrating the manufacturing process of the wiring substrate according to the first embodiment. Here, an example of a process of forming a layer structure only on one side of the support is shown, but it may also be a process of forming a layer structure on one side and the other side of the support. The broken line C in each figure indicates the position to be cut when the wiring substrate is singulated. The region located between adjacent broken lines C in a cross-sectional view is finally singulated to become one wiring substrate.

[0035] First, in the process shown in FIG. 3(a), a support 300 is prepared. The support 300 has, for example, a structure in which a copper foil with a carrier 304 is laminated on one side of a core substrate 301. The core substrate 301 is, for example, a resin substrate with a thickness of about 0.7 mm and may have a reinforcing member such as glass fiber. The copper foil with a carrier 304 has a structure in which a thin foil 304a with a thickness of about 1.5 to 5 μm made of, for example, copper is adhered in a peelable state via a release layer (not shown) on a thick foil (carrier foil) 304b with a thickness of about 10 to 50 μm made of, for example, copper. The thick foil 304b is provided as a support material for facilitating the handling of the thin foil 304a.

[0036] Note that the structure of the above support 300 is an example and is not limited thereto. For example, in the support 300, instead of the core substrate 301, a laminate in which a plurality of prepregs are laminated may be used. Also, the support 300 may have a structure in which a copper foil with a carrier 304 is disposed via a release layer on one side of a glass substrate, a metal substrate, or the like.

[0037] Next, in the process shown in FIG. 3(b), a first wiring layer 11 including a wiring pattern 11W and pads 11P is formed on the support 300. Specifically, a resist layer having openings in a portion where the first wiring layer 11 is to be formed is formed on the upper surface of the copper foil with a carrier 304 (the upper surface of the thin foil 304a) using a dry film resist or the like. Then, by an electrolytic plating method using the copper foil with a carrier 304, which is a metal layer, as a power supply layer, a first wiring layer 11, which is an electrolytic plating layer, is formed on the upper surface of the copper foil with a carrier 304 exposed in the openings. The material and thickness of the first wiring layer 11 are as described above. Thereafter, the resist layer is peeled off and removed.

[0038] Next, in the process shown in FIG. 3(c), a first insulating layer 12 that covers the surface of the first wiring layer 11 that is not in contact with the support 300 is formed on the support 300. Specifically, the first insulating layer 12 that covers the first wiring layer 11 is formed on the upper surface of the copper foil 304 with a carrier. First, for example, a semi-cured film-like insulating resin mainly composed of a thermosetting resin is prepared. Then, this insulating resin is laminated on the upper surface of the copper foil 304 with a carrier, and cured while heating and applying pressure to form the first insulating layer 12. Alternatively, instead of laminating the film-like insulating resin, a liquid or paste-like insulating resin may be applied and then cured to form the first insulating layer 12. The material and thickness of the first insulating layer 12 are as described above.

[0039] Next, in the process shown in FIG. 4(a), via holes 12x that penetrate the first insulating layer 12 and expose the upper surface of the first wiring layer 11 are formed in the first insulating layer 12. The via holes 12x can be formed, for example, by a laser processing method using a CO2 laser, a YAG laser, an excimer laser, or the like. After forming the via holes 12x, it is preferable to perform a desmear treatment to remove the resin residues adhering to the surfaces of the first wiring layer 11 exposed at the bottoms of the via holes 12x.

[0040] Next, in the process shown in FIG. 4(b), a second wiring layer 14 is formed on the first insulating layer 12. As described above, the second wiring layer 14 includes a first ground plane 14G, a first signal pad 14A, a first ground pad 14B, and via wirings 14V. The material and thickness of the second wiring layer 14 are as described above. The detailed formation method of the second wiring layer 14 will be described later.

[0041] Next, in the processes shown in FIGS. 4(c) and 5(a), the support 300 shown in FIG. 4(b) is removed. To remove the support 300, first, as shown in FIG. 4(c), the core substrate 301 and the thick foil 304b are mechanically peeled from the thin foil 304a. Then, as shown in FIG. 5(a), the thin foil 304a is removed by wet etching using, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, or an aqueous solution of ammonium persulfate.

[0042] Next, in the process shown in FIG. 5(b), a second insulating layer 13 is formed on one side of the first insulating layer 12 so as to cover the surface of the support 300 of the first wiring layer 11 that was in contact therewith. Also, a third insulating layer 16 is formed on the other side of the first insulating layer 12 so as to cover the second wiring layer 14. Specifically, for example, two semi-cured film-like insulating resins mainly composed of a thermosetting resin are prepared. Then, this insulating resin is laminated on one surface and the other surface of the first insulating layer 12, and cured while heating and pressurizing to form the second insulating layer 13 and the third insulating layer 16. Alternatively, instead of laminating the film-like insulating resin, a liquid or paste-like insulating resin may be applied and then cured to form the second insulating layer 13 and the third insulating layer 16. The materials and thicknesses of the second insulating layer 13 and the third insulating layer 16 can be the same as those of the first insulating layer 12, for example. Note that FIG. 5(b) is drawn in a state where it is inverted vertically with respect to FIG. 5(a). The same applies to FIGS. 5(c) to 6(b) described later.

[0043] Next, in the process shown in FIG. 5(c), via holes 13x that penetrate the second insulating layer 13 and expose the upper surface of the first wiring layer 11 are formed in the second insulating layer 13. Also, via holes 16x that penetrate the third insulating layer 16 and expose the lower surface of the second wiring layer 14 are formed in the third insulating layer 16. The via holes 13x and 16x can be formed, for example, by a laser processing method using a CO2 laser or the like. After forming the via holes 13x and 16x, if necessary, desmear treatment is performed to remove the resin residues adhering to the surface of the first wiring layer 11 exposed at the bottom of the via hole 13x and the surface of the second wiring layer 14 exposed at the bottom of the via hole 16x.

[0044] Next, in the process shown in Fig. 6(a), a third wiring layer 15 is formed on the second insulating layer 13. The third wiring layer 15 includes a via wiring 15V filled in a via hole 13x, a second ground plane 15G formed on the upper surface of the second insulating layer 13, a second signal pad 15A, and a second ground pad 15B. The second ground plane 15G is formed in a substantially solid state so as to cover most of the upper surface of the second insulating layer 13. The second signal pad 15A is disposed in an opening 15x provided in the second ground plane 15G. The second ground pad 15B forms part of the second ground plane 15G. The second signal pad 15A and the second ground pad 15B are each electrically connected to the pad 11P via the via wiring 15V. The material of the third wiring layer 15 and the thicknesses of the second ground plane 15G, the second signal pad 15A, and the second ground pad 15B can be, for example, the same as those of the first wiring layer 11.

[0045] Also, a fourth wiring layer 17 is formed on the other side of the third insulating layer 16. The fourth wiring layer 17 includes a via wiring filled in a via hole 16x, a wiring pattern and pads formed on the lower surface of the third insulating layer 16. The material of the fourth wiring layer 17 and the thicknesses of the wiring pattern and pads can be, for example, the same as those of the first wiring layer 11. The fourth wiring layer 17 is electrically connected to the second wiring layer 14 exposed at the bottom of the via hole 16x.

[0046] Next, in the process shown in FIG. 6(b), a solder resist layer 21 is formed on the upper surface of the second insulating layer 13 so as to cover the third wiring layer 15. Also, a solder resist layer 22 is formed on the lower surface of the third insulating layer 16 so as to cover the fourth wiring layer 17. The solder resist layer 21 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy-based insulating resin or acrylic-based insulating resin onto the upper surface of the second insulating layer 13 so as to cover the third wiring layer 15 by screen printing, roll coating, spin coating, or the like. Alternatively, for example, a film-like photosensitive epoxy-based insulating resin or acrylic-based insulating resin may be laminated onto the upper surface of the second insulating layer 13 so as to cover the third wiring layer 15. The method for forming the solder resist layer 22 is the same as that of the solder resist layer 21.

[0047] Next, by exposing and developing the solder resist layers 21 and 22, an opening 21x that exposes a part of the upper surface of the third wiring layer 15 is formed in the solder resist layer 21 (photolithography method). Also, an opening 22x that exposes a part of the lower surface of the fourth wiring layer 17 is formed in the solder resist layer 22 (photolithography method). Note that the openings 21x and 22x may be formed by a laser processing method or a blasting process. In that case, a photosensitive material does not have to be used for the solder resist layers 21 and 22. The planar shape of each of the openings 21x and 22x can be, for example, circular. The diameter of each of the openings 21x and 22x can be arbitrarily designed according to the connection target (such as a semiconductor chip or a mother board).

[0048] Note that, in this process, the above-described metal layer may be formed, for example, by electroless plating or the like on the upper surface of the third wiring layer 15 exposed at the bottom of the opening 21x and on the lower surface of the fourth wiring layer 17 exposed at the bottom of the opening 22x. Alternatively, instead of forming the metal layer, an antioxidant treatment such as OSP treatment may be performed. After the process of FIG. 6(b), cutting is performed at the portion of the broken line C to obtain individual wiring boards 1.

[0049] Thus, in the method for manufacturing the wiring board 1, the first wiring layer 11 that constitutes the strip line SL becomes an embedded wiring whose side surface and bottom surface are covered with the first insulating layer 12. In the conventional method for manufacturing a wiring board, since the embedded wiring is disposed on the outermost layer of the wiring board, a microstrip line could be formed, but a strip line could not be formed. On the other hand, in the method for manufacturing the wiring board 1, after removing the support and exposing the upper surface of the embedded wiring, an insulating layer and a wiring layer are further formed, so that a strip line can be formed by the embedded wiring. As a result, the adhesion between the wiring pattern 11W and the pad 11P that constitute the first wiring layer 11 and the first insulating layer 12 can be improved, and a highly reliable strip line SL can be realized.

[0050] Also, as will be described in the <Details of the Method for Forming a Wiring Layer> described later, when forming a wiring layer by a semi-additive method or a modified semi-additive method, a step of etching a seed layer using an electrolytic plating layer as a mask is required. In this step, since the side surface of the electrolytic plating layer is also etched when the seed layer is etched, the interval between the wiring layers becomes wider, and it is difficult to reduce the line / space. On the other hand, since the side surface of the first wiring layer 11, which is an embedded wiring, is covered with the first insulating layer 12 in the step of removing the thin foil 304a that constitutes the support 300 by etching, the interval between the wirings does not become wider when the thin foil 304a is removed by etching, so that the line / space can be reduced. For example, the line / space that can be formed by the semi-additive method or the modified semi-additive method is about line 11 to 13 μm / space 11 to 13 μm. On the other hand, in the first wiring layer 11, which is an embedded wiring, it is possible to set the line to about 8 to 10 μm / space 8 to 10 μm. That is, in the wiring board 1, a strip line SL can be formed by fine wirings with a pitch of the wiring pattern 11W of 20 μm or less. Also, due to the miniaturization of the wiring, the wiring board 1 can be miniaturized.

[0051] <Modification Example 1 of the First Embodiment> In Modification Example 1 of the first embodiment, an example of a wiring board having five wiring layers is shown. In Modification Example 1 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0052] FIG. 7 is a cross-sectional view illustrating a wiring board according to Modification Example 1 of the first embodiment. Referring to FIG. 7, the wiring board 1A has a fourth insulating layer 18 and a fifth wiring layer 19 between the fourth wiring layer 17 and the solder resist layer 22 of the wiring board 1.

[0053] The fourth insulating layer 18 is formed so as to cover the fourth wiring layer 17 on the other surface of the third insulating layer 16. The material and thickness of the fourth insulating layer 18 can be the same as those of the first insulating layer 12, for example. The fourth insulating layer 18 can contain a filler such as silica (SiO2). The content of the filler in the fourth insulating layer 18 can be the same as that in the first insulating layer 12, for example.

[0054] The fifth wiring layer 19 is formed on the other side of the fourth insulating layer 18. The fifth wiring layer 19 includes via wirings filled in via holes 18x that penetrate the fourth insulating layer 18 and expose the lower surface of the fourth wiring layer 17, pads formed on the lower surface of the fourth insulating layer 18, and wiring patterns. The pads constituting the fifth wiring layer 19 are electrically connected to the pads constituting the fourth wiring layer 17 via the via wirings. The via hole 18x can be a frustum-shaped recess in which the diameter of the opening on the solder resist layer 22 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the pad constituting the fourth wiring layer 17. The material of the fifth wiring layer 19 and the thickness of the wiring pattern can be the same as those of the first wiring layer 11, for example.

[0055] The solder resist layer 22 is the outermost layer on the other side of the wiring board 1A, and is formed on the lower surface of the fourth insulating layer 18 so as to cover the fifth wiring layer 19. The solder resist layer 22 has an opening 22x, and a part of the lower surface of the pad of the fifth wiring layer 19 is exposed in the opening 22x. The planar shape of the opening 22x can be, for example, circular. The pad of the fifth wiring layer 19 exposed in the opening 22x can be used for electrical connection with a mounting board (not shown) such as a motherboard. If necessary, the metal layer described above may be formed on the lower surface of the pad of the fifth wiring layer 19 exposed in the opening 22x, or an antioxidant treatment such as OSP treatment may be performed.

[0056] To fabricate the wiring board 1A, after the process of FIG. 4(b) of the first embodiment, as shown in FIG. 8(a), a third insulating layer 16 is formed on one side of the first insulating layer 12 in the same manner as the process of FIG. 5(b). Next, in the process of FIG. 8(b), in the same manner as the process shown in FIG. 5(c), a via hole 16x that penetrates the third insulating layer 16 and exposes the upper surface of the second wiring layer 14 is formed in the third insulating layer 16. After forming the via hole 16x, it is preferable to perform a desmear treatment to remove the resin residue attached to the surface of the second wiring layer 14 exposed at the bottom of the via hole 16x if necessary. Next, in the process of FIG. 8(c), a fourth wiring layer 17 is formed on one side of the third insulating layer 16 in the same manner as the process shown in FIG. 6(a).

[0057] Next, in the process shown in FIG. 9(a), the support 300 shown in FIG. 8(c) is removed in the same manner as the processes shown in FIGS. 4(c) and 5(a). Then, in the process shown in FIG. 9(b), in the same manner as the process shown in FIG. 5(b), a second insulating layer 13 is formed on one side of the first insulating layer 12 so as to cover the surface of the first wiring layer 11 that was in contact with the support 300, and further a third wiring layer 15 is formed. Also, a fourth insulating layer 18 is formed on the other side of the third insulating layer 16 so as to cover the fourth wiring layer 17, and further a fifth wiring layer 19 is formed. Thereafter, by performing the same process as FIG. 6(b), the wiring board 1A is completed. Note that FIG. 9(b) is drawn in a state where it is inverted vertically with respect to FIG. 9(a).

[0058] Thus, the wiring board having the stripline SL is not limited to a structure having four wiring layers like the wiring board 1. For example, it may have a structure having five wiring layers like the wiring board 1A, and as long as it has at least three or more wiring layers, it may have a structure having wiring layers other than four and five layers.

[0059] <Details of the method for forming the wiring layer> FIGS. 10 and 11 are diagrams for explaining an example of a detailed method for forming a wiring layer. Here, an example of forming the second wiring layer 14 by a semi-additive method is shown.

[0060] First, after the process of FIG. 4(a) of the first embodiment, in the process shown in FIG. 10(a), a seed layer 14s is formed on the surface of the first insulating layer 12 including the inner wall of the via hole 12x and on the surface of the first wiring layer 11 exposed in the via hole 12x. The seed layer 14s can be formed, for example, by electroless plating or sputtering using copper or the like.

[0061] Next, in the process shown in FIG. 10(b), a resist layer 400 is formed on the seed layer 14s using a photosensitive dry film resist or the like. Then, the resist layer 400 is exposed and developed to form an opening 400x conforming to the shape of the second wiring layer 14. The seed layer 14s is exposed in the opening 400x.

[0062] Next, in the process shown in FIG. 10(c), an electrolytic plating layer 14p is deposited on the seed layer 14s exposed in the opening 400x of the resist layer 400 by electrolytic plating powered from the seed layer 14s. As the material of the electrolytic plating layer 14p, for example, copper or the like can be used. Then, in the process shown in FIG. 11(a), the resist layer 400 is removed.

[0063] Next, in the process shown in FIG. 11(b), etching is performed using the electrolytic plating layer 14p as a mask to remove the seed layer 14s exposed from the electrolytic plating layer 14p, whereby the second wiring layer 14 including the seed layer 14s and the electrolytic plating layer 14p can be obtained. As shown in FIG. 1, the second wiring layer 14 has a structure including a first ground plane 14G, a first signal pad 14A, a first ground pad 14B, and via wiring 14V. When the seed layer 14s is formed of copper, the seed layer 14s can be removed, for example, by wet etching using an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. At this time, the upper surface and side surfaces of the electrolytic plating layer 14p are also slightly removed.

[0064] FIGS. 12 to 14 are diagrams for explaining another example of a detailed method for forming a wiring layer. Here, an example of forming the second wiring layer 14 by a modified semi-additive method is shown.

[0065] First, in the process of FIG. 12(a), in the same manner as FIGS. 3(a) and 3(b) of the first embodiment, the first wiring layer 11 is formed on the support 300. Then, in the process shown in FIG. 12(b), in the same manner as the process shown in FIG. 3(c), a semi-cured first insulating layer 12 that covers the first wiring layer 11 is formed on the upper surface of the copper foil 304 with a carrier, and further, a metal foil 14m is disposed on the upper surface of the first insulating layer 12, and the first insulating layer 12 is cured. It is preferable to cure the first insulating layer 12 by heating while pressing the metal foil 14m toward the first insulating layer 12 side. Thereby, the adhesion strength between the metal foil 14m and the first insulating layer 12 is ensured, and the effect of preventing the metal foil 14m from peeling off from the first insulating layer 12 is obtained. As the material of the metal foil 14m, for example, Cu, a Cu alloy, or the like can be used. The thickness of the metal foil 14m can be, for example, about 5 to 10 μm.

[0066] Next, in the process shown in FIG. 12(c), a laser beam is irradiated onto the first insulating layer 12 through the metal foil 14m to form a via hole 12x that penetrates through the metal foil 14m and the first insulating layer 12 and exposes the upper surface of the first wiring layer 11. The via hole 12x can be formed, for example, by a laser processing method using a CO2 laser, a YAG laser, an excimer laser, or the like. After forming the via hole 12x, it is preferable to perform a desmear treatment to remove the resin residue adhering to the surface of the first wiring layer 11 exposed at the bottom of the via hole 12x.

[0067] Next, in the process shown in FIG. 13(a), a seed layer 14s is formed on the surface of the metal foil 14m, the surface of the first insulating layer 12 that constitutes the inner wall of the via hole 12x, and the surface of the first wiring layer 11 exposed in the via hole 12x. The seed layer 14s can be formed, for example, by electroless plating or sputtering using copper or the like.

[0068] Next, in the process shown in FIG. 13(b), a resist layer 410 is formed on the seed layer 14s using a photosensitive dry film resist or the like. Then, the resist layer 410 is exposed and developed to form an opening 410x that conforms to the shape of the second wiring layer 14. The seed layer 14s is exposed within the opening 410x.

[0069] Next, in the process shown in FIG. 14(a), an electrolytic plating layer 14p is deposited on the seed layer 14s exposed within the opening 410x of the resist layer 410 by electrolytic plating powered by the metal foil 14m and the seed layer 14s. As the material of the electrolytic plating layer 14p, for example, copper or the like can be used.

[0070] Next, in the process shown in FIG. 14(b), after removing the resist layer 410 shown in FIG. 14(a), etching is performed using the electrolytic plating layer 14p as a mask, and by removing the metal foil 14m and the seed layer 14s exposed from the electrolytic plating layer 14p, the second wiring layer 14 including the metal foil 14m, the seed layer 14s, and the electrolytic plating layer 14p can be obtained. As shown in FIG. 1, the second wiring layer 14 has a structure including a first ground plane 14G, a first signal pad 14A, a first ground pad 14B, and via wiring 14V. When the metal foil 14m and the seed layer 14s are formed of copper, the metal foil 14m and the seed layer 14s can be removed by wet etching using, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, or an aqueous solution of ammonium persulfate. At this time, the upper surface and side surfaces of the electrolytic plating layer 14p are also slightly removed.

[0071] In this way, the wiring layer can be formed by the semi-additive method or the modified semi-additive method.

[0072] In the modified semi-additive method, a metal foil is laminated on an insulating layer, and a seed layer is formed on the surface of the metal foil. Metal foils with various surface roughnesses are prepared, and a metal foil with a small surface roughness can be selected. When a metal foil with a small surface roughness is selected, a wiring layer with small unevenness suitable for high-frequency transmission can be formed. Here, the wiring layer includes a wiring pattern, pads, and a ground plane.

[0073] On the other hand, in the semi-additive method, a seed layer is directly formed on the surface of the insulating layer. That is, in the semi-additive method, the step of laminating a metal foil on the insulating layer becomes unnecessary, so the manufacturing method of the wiring substrate can be simplified. However, since the surface of the insulating layer is often rougher than the surface of the metal foil, when an insulating layer with a large surface roughness is selected, a wiring layer with relatively large unevenness is formed. Also in the semi-additive method, if an insulating layer with a small surface roughness is selected, a wiring layer with small unevenness suitable for high-frequency transmission can be formed.

[0074] <Application Example of the First Embodiment> In the application example of the first embodiment, an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board is shown. In the application example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0075] FIG. 15 is a cross-sectional view (part 1) illustrating a semiconductor device according to an application example of the first embodiment. Referring to FIG. 15, the semiconductor device 100 includes a wiring board 1 shown in FIG. 1, a semiconductor chip 110, an electrode post 120, a bump 130, and an underfill resin 140.

[0076] The semiconductor chip 110 is, for example, formed by forming a semiconductor integrated circuit (not shown) or the like on a thinned semiconductor substrate (not shown) made of silicon or the like. An electrode post 120 electrically connected to the semiconductor integrated circuit (not shown) is formed on the semiconductor substrate (not shown).

[0077] The bump 130 is formed between the electrode post 120 of the semiconductor chip 110 and the pad of the third wiring layer 15 of the wiring board 1. The bump 130 covers at least a part of the lower surface and the side surface of the electrode post 120 and the upper surface of the pad of the third wiring layer 15 of the wiring board 1, and electrically connects the two. The electrode post 120 is, for example, a copper post. The bump 130 is, for example, a solder bump. As the material of the solder bump, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, or the like can be used. The underfill resin 140 is filled between the semiconductor chip 110 and the upper surface of the wiring board 1.

[0078] In this way, a semiconductor device can be realized by mounting a semiconductor chip on the wiring board according to the first embodiment. Note that, as in the semiconductor device 100A shown in FIG. 16, a wiring board 1A may be used instead of the wiring board 1. In any case of the semiconductor device, since the strip line SL is provided on the wiring board, the characteristic impedance of the first wiring layer 11 can be controlled, the electromagnetic wave leaking from the first wiring layer 11 can be reduced, and high-speed signal transmission is possible.

[0079] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

Description of Reference Numerals

[0080] 1, 1A Wiring Substrate 11 First Wiring Layer 11P Pad 11W Wiring Pattern 12 First Insulating Layer 12x, 13x, 16x via hole 13 Second Insulating Layer 14 Second Wiring Layer 14A First Signal Pad 14B First Ground Pad 14G First Ground Plane 14V via wiring 14x, 15x, 21x, 22x, 400x, 410x Opening 14s Seed Layer 14p Electrolytic Plating Layer 14m Metal Foil 15 Third Wiring Layer 15A Second Signal Pad 15B Second Ground Pad 15G Second Ground Plane 15V via wiring 16 Third Insulating Layer 17 Fourth Wiring Layer 18 Fourth Insulating Layer 19 Fifth Wiring Layer 21, 22 Solder Resist Layer 100, 100A Semiconductor Device 110 Semiconductor Chip 120 Electrode Post 130 Bump 140 Underfill Resin 300 Support 301 Core Substrate 304 Copper Foil with Carrier 304a Thin Foil 304b thick foil 400, 410 resist layers

Claims

1. a first wiring layer; a first insulating layer covering side and bottom surfaces of the first wiring layer; a second insulating layer disposed on the first insulating layer and covering an upper surface of the first wiring layer; a second wiring layer formed on a bottom surface of the first insulating layer; a third wiring layer formed on an upper surface of the second insulating layer; a solder resist layer formed on the upper surface of the second insulating layer and covering the third wiring layer, and having: the second wiring layer includes a first ground plane; the third wiring layer includes a second ground plane; the first ground plane, the first insulating layer, the first wiring layer, the second insulating layer, and the second ground plane constitute a stripline; the second wiring layer includes a first signal pad disposed in an opening provided in the first ground plane; the third wiring layer includes a second signal pad disposed in an opening provided in the second ground plane; the first wiring layer includes a pad electrically connected to the second signal pad via a via wiring penetrating the second insulating layer; the second signal pad is exposed in an opening provided in the solder resist layer; a wiring substrate, wherein a side where the solder resist layer is located is a side where a semiconductor chip is mounted.

2. the second wiring layer includes a first ground pad forming a part of the first ground plane; The wiring substrate according to claim 1, wherein the first wiring layer includes a pad electrically connected to the first signal pad via a via wiring penetrating the first insulating layer, and a pad electrically connected to the first ground pad via a via wiring penetrating the first insulating layer.

3. the third wiring layer includes a second ground pad forming a part of the second ground plane; The wiring substrate according to claim 2, wherein the first wiring layer includes a pad electrically connected to the second ground pad via a via wiring penetrating the second insulating layer.

4. For the via wiring penetrating the first insulating layer, an area of a portion connected to a bottom surface of the pad is smaller than an area of a portion connected to an upper surface of the first signal pad or the first ground pad; For the via wiring penetrating the second insulating layer, an area of a portion connected to an upper surface of the pad is smaller than an area of a portion connected to a bottom surface of the second signal pad or the second ground pad. The wiring substrate according to claim 3.

5. The area of the lower surface of the pad is smaller than the area of the upper surface of the pad for the first signal, and the area of the upper surface of the pad is smaller than the area of the lower surface of the pad for the second signal. The wiring board according to claim 4.

6. The minimum distance between adjacent wiring patterns in the first wiring layer is narrower than the minimum distance between adjacent wiring patterns in other wiring layers. The wiring board according to any one of claims 1 to 5.

7. A wiring board according to any one of claims 1 to 6, A semiconductor device comprising: a semiconductor chip disposed on the solder resist layer of the wiring board and connected to the pad for the second signal.

8. A step of forming a first wiring layer on a support; A step of forming a first insulating layer on the support to cover a surface of the first wiring layer that is not in contact with the support; A step of forming a second wiring layer on the first insulating layer; A step of removing the support; A step of forming a second insulating layer to cover a surface of the first wiring layer that was in contact with the support; A step of forming a third wiring layer on the second insulating layer; A step of forming a solder resist layer on the upper surface of the second insulating layer to cover the third wiring layer; A step of forming an opening in the solder resist layer to expose a part of the third wiring layer, and The second wiring layer includes a first ground plane, The third wiring layer includes a second ground plane, The first ground plane, the first insulating layer, the first wiring layer, the second insulating layer, and the second ground plane constitute a stripline, The step of forming the third wiring layer includes a step of forming a signal pad disposed in an opening provided in the second ground plane and electrically connected to the first wiring layer through a via wiring penetrating the second insulating layer, In the step of forming the opening, the signal pad is exposed in the opening, A method of manufacturing a wiring board, wherein the side of the solder resist layer is the side on which a semiconductor chip is mounted.

9. The step of forming a first wiring layer on a support includes: A step of forming a resist layer having an opening on the outermost metal layer of the support; A step of forming the first wiring layer in the opening by an electrolytic plating method using the metal layer as a power supply layer; A step of removing the resist layer. The method of manufacturing a wiring board according to claim 8.

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