Semiconductor device, amplification device, and method of manufacturing semiconductor device

Abstract

This semiconductor device comprises: a substrate; a gate electrode, a source electrode and a drain electrode which are positioned on the substrate; a plurality of non-conductive nanowires which are arranged two-dimensionally on the top surface of the substrate so as to extend in a direction which is perpendicular to the top surface of the substrate; an electrode pad which is supported by the plurality of nanowires and is positioned at the top end of the plurality of nanowires in a manner such that a gap exists between the pad and the substrate; and an extraction electrode which connects the electrode pad and the gate electrode to one another.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an amplifier device, and a method for manufacturing a semiconductor device.

Background Art

[0002] In a quantum computer, a microwave output signal from a qubit is extremely weak, and a low-noise amplifier that amplifies the microwave output signal with low noise is used. Since the noise characteristics of the transistor used in the amplifier greatly depend on the gate capacitance, it is preferable to reduce the gate capacitance by shortening the gate length. However, even if the gate length is shortened to reduce the true capacitance, there is a semiconductor layer with a high dielectric constant under the electrode pad connected to the gate electrode for signal supply from the external wiring. As a result, a relatively large parasitic capacitance of the electrode pad remains as the capacitance of the gate electrode. The area of the electrode pad is several μm square, which is much larger than the several tens of nm of the gate length. Therefore, the parasitic capacitance due to the electrode pad becomes a major factor hindering the noise reduction of the amplifier. Since the electrode pad provided for electrical connection requires a minimum area to some extent, there is a limit to reducing the parasitic capacitance by reducing the size of the electrode pad.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of the above, a semiconductor device with reduced parasitic capacitance of the electrode pad connected to the gate electrode is desired.

Means for Solving the Problem

[0005] The semiconductor device includes a substrate, a gate electrode, a source electrode, and a drain electrode disposed on the substrate, a transistor having and a plurality of non-conductive nanowires two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate, made of material an electrode pad disposed so as to have a gap between the upper ends of the plurality of nanowires and the substrate and supported by the plurality of nanowires, and a lead-out electrode connecting the electrode pad and the gate electrode.

Advantages of the Invention

[0006] According to at least one embodiment disclosed in the present application, a semiconductor device with reduced parasitic capacitance of the electrode pad connected to the gate electrode can be obtained.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0009] FIG. 1 is a diagram showing an example of the configuration of a quantum computer. The quantum computer shown in FIG. 1 includes a cryogenic dilution refrigerator 10, a microwave pulse generator 11, a quantum bit chip 12, a low-noise amplifier 13, and a demodulator 14.

[0010] The cryogenic dilution refrigerator 10 cools the inside of, for example, a cylindrical housing to an extremely low temperature of several mK by using helium 4 and helium 3, which are helium isotopes. The microwave pulse generator 11 placed in the external room temperature environment generates microwave pulses and inputs the generated microwave pulses to the quantum bit chip 12 maintained at an extremely low temperature of about 10 mK. The quantum bit chip 12 executes a quantum operation based on the quantum bit in response to the input microwave pulse and outputs a microwave corresponding to the state of the quantum bit after the operation. The low-noise amplifier 13 maintained at an extremely low temperature of about 4 K amplifies the output microwave with low noise and supplies the amplified microwave to the demodulator 14 placed in the external room temperature environment. The demodulator 14 demodulates the amplified microwave.

[0011] FIG. 2 is a diagram showing an example of the configuration of the low-noise amplifier 13. The low-noise amplifier 13 includes a plurality of amplification devices 13-1 to 13-n connected in cascade. The output signal from the quantum bit chip 12 shown in FIG. 1 is input to the first-stage amplification device 13-1, and the output signal of the i-th stage (i = 1 to n-1) amplification device 13-1 is input to the (i + 1)-th stage amplification device 13-1. The output signal of the n-th stage amplification device 13-1 is supplied to the demodulator 14 shown in FIG. 1 as the output of the low-noise amplifier 13.

[0012] FIG. 3 is a diagram showing an example of the configuration of one amplification device. The amplification device shown in FIG. 3 may be used as each of the amplification devices 13-1 to 13-n.

[0013] The amplifying device shown in FIG. 3 includes a first matching circuit 20, a transistor 21, a second matching circuit 22, capacitor elements 23 to 26, and resistor elements 27 and 28. An input signal to the amplifying device is applied to the gate electrode of the transistor 21 via the capacitor element 23 and the first matching circuit 20. The first matching circuit 20 achieves impedance matching between the input side and the transistor 21 side. The transistor 21 amplifies the input signal applied to the gate electrode. The amplified signal is output to the outside via the second matching circuit 22 and the capacitor element 24. The second matching circuit 22 achieves impedance matching between the transistor 21 side and the output side.

[0014] To apply an input signal to the gate electrode of the transistor 21, a signal line for supplying the input signal is connected to an electrode pad connected to the gate electrode. In order to realize a low-noise amplification operation by the transistor 21, it is required to reduce the parasitic capacitance existing between the electrode pad and the source electrode or the drain electrode via the substrate.

[0015] FIG. 4 is a top view showing an example of the configuration of a semiconductor device with reduced parasitic capacitance of the electrode pad. FIG. 5 is a cross-sectional view taken along line A-A' of the semiconductor device shown in FIG. 4.

[0016] The semiconductor device shown in FIGS. 4 and 5 includes a substrate 30 that is a dielectric, an active region 31, a source electrode 32, a drain electrode 33, a gate electrode 34, a lead-out electrode 35, an electrode pad 36, and a plurality of non-conductive nanowires 37. The semiconductor device shown in FIGS. 4 and 5 is a compound semiconductor, and the active region 31 is formed on the substrate 30. The substrate 30 functions as an element isolation region.

[0017] The gate electrode 34, source electrode 32, and drain electrode 33 are disposed on the substrate 30 (more specifically, on the upper surface of the active region 31). A plurality of non-conductive nanowires 37 are two-dimensionally arranged on the upper surface of the substrate 30 so as to extend perpendicular to the upper surface of the substrate 30. The electrode pad 36 is disposed with a gap between the upper ends of the plurality of nanowires 37 and the substrate 30 and is supported by the plurality of nanowires 37. The lead-out electrode 35 electrically connects the electrode pad 36 and the gate electrode 34.

[0018] Examples of preferred materials for the plurality of nanowires 37 include AlGaAs, InAlAs, AlAs, InP, InAlP, GaP, AlGaP, InAsP, GaAsSP, GaSb, AlSb, AlGaSb, GaAsSb, and AlAsSb. Further examples of this material include GaN, AlN, AlGaN, InAlN, Si, Ge, SiGe, and C (diamond).

[0019] With the configuration in which the electrode pad 36 is supported in a hollow manner by the plurality of nanowires 37 as described above, a space with nothing is provided between the electrode pad 36 and the dielectric substrate 30. Therefore, the parasitic capacitance generated by the substrate 30, which is a semiconductor with a high dielectric constant, under the electrode pad 36 can be greatly reduced. Accordingly, the noise in the signal input to the transistor can be reduced.

[0020] Also, in the semiconductor device shown in FIG. 5, the gate electrode 34, source electrode 32, and drain electrode 33 are formed on the upper surface of the active region 31, and the active region 31 includes a channel layer and an electron supply layer as will be described later. Since the transistor thus has a HEMT (High Electron Mobility Transistor) structure, the noise in the transistor can be further reduced.

[0021] FIG. 6 is a cross-sectional view showing the configuration of a gate electrode in a normal compound semiconductor. Different from the configuration shown in FIG. 5, in a normal compound semiconductor, an electrode pad 38 integrated with the gate electrode is formed so as to directly touch the upper surface of the substrate 30. Therefore, a relatively large capacitance is generated between the electrode pad 38 and a source electrode (not shown) or a drain electrode (not shown) through the dielectric substrate 30.

[0022] On the other hand, in the configuration shown in FIG. 5, since a gap is provided between the electrode pad 36 and the substrate 30, the capacitance between the electrode pad 36 and the source electrode 32 or the drain electrode 33 is reduced. Further, since the electrode pad 36 is supported by a plurality of nanowires 37, sufficient mechanical strength can be maintained. Thereby, bonding wires or bumps can be easily formed on the electrode pad 36. Further, in the configuration shown in FIG. 5, since the lead-out electrode 35 is arranged so as to overlap the upper surface of the gate electrode 34, considering both of them together is equivalent to an increase in the cross-sectional area of the gate electrode. Thereby, since the gate resistance can be reduced, a further noise reduction effect can be obtained.

[0023] FIG. 7 is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing a cross-section along line B-B' of the semiconductor device shown in FIG. 7.

[0024] The semiconductor device shown in FIGS. 7 and 8 includes a semi-insulating InP substrate 40, an i-InAlAs buffer layer 41, an i-GaAs layer 42, an SiO2 layer 43, an i-InGaAs channel layer 44, and an n-InAlAs supply layer 45. The semiconductor device further includes a source electrode 46, a drain electrode 47, a gate electrode 48, a lead-out electrode 49, an electrode pad 50, and a plurality of non-conductive nanowires 51. The source electrode 46, the drain electrode 47, and the gate electrode 48 may all be Ti / Pt / Au. Although not shown, n-InGaAs for performing a non-alloy ohmic connection may be provided directly under the source electrode 46 and the drain electrode 47.

[0025] The semiconductor device according to the first embodiment shown in FIGS. 7 and 8 has basically the same configuration as the semiconductor device shown in FIG. 4. That is, the gate electrode 48, the source electrode 46, and the drain electrode 47 are disposed on (above) a substrate (InP substrate 40, i-InAlAs buffer layer 41, i-GaAs layer 42, and SiO2 layer 43). A plurality of non-conductive nanowires 51 are two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate. The electrode pad 50 is disposed with a gap between the upper ends of the plurality of nanowires 51 and the substrate and is supported by the plurality of nanowires 51. The lead-out electrode 49 electrically connects the electrode pad 50 and the gate electrode 48.

[0026] In the semiconductor device according to the first embodiment shown in FIGS. 7 and 8, the i-InGaAs channel layer 44 and the n-InAlAs supply layer 45 correspond to the active region. The gate electrode 48, the source electrode 46, and the drain electrode 47 are formed on the upper surface of the active region. The n-InAlAs supply layer 45 functions as an electron supply layer that supplies electrons, and the i-InGaAs channel layer 44 functions as an electron traveling layer in which electrons move from the source electrode side toward the drain electrode side. Thus, the semiconductor device according to the first embodiment has a HEMT structure.

[0027] The plurality of nanowires 51 are formed by crystal-growing non-doped GaAs (i-GaAs). The nanowires 51 have a substantially circular cross-section (specifically, a prismatic shape according to the crystal structure) in the horizontal direction, and the diameter is on the order of nanometers. The diameter of the nanowires 51 is preferably, for example, 50 nm or more and 200 nm or less, and more preferably 90 nm or more and 110 nm or less. If it becomes thinner than 50 nm, there may be a problem with strength, and if it exceeds 200 nm, the effect of capacitance reduction may be impaired. Also, when the diameter is smaller than 50 nm or larger than 200 nm, it becomes difficult to crystal-grow the plurality of nanowires 51 into a desired shape.

[0028] The interval between the plurality of nanowires 51 is preferably, for example, 250 nm or more and 1000 nm or less, and more preferably about 500 nm. When the interval becomes narrower than 250 nm and the number increases, the effect of reducing the capacitance becomes smaller. When the interval becomes wider than 1000 nm and the number decreases, a problem occurs in the strength. Also, when the interval is narrower than 250 nm or wider than 1000 nm, it becomes difficult to grow the plurality of nanowires 51 into a desired shape.

[0029] In the semiconductor device according to the first embodiment, the substrate includes a first layer (i-GaAs layer 42) formed of the same material as the material (i-GaAs) in which the plurality of nanowires 51 are formed, and the lower ends of the plurality of nanowires 51 are in contact with the first layer (i-GaAs layer 42). By providing the i-GaAs layer 42, the i-GaAs layer 42 functions as a basis for crystal growth, and it becomes possible to grow the plurality of nanowires 51. As the i-GaAs layer 42, by using an i-GaAs layer having a (111)B plane on the upper surface of the layer, that is, having a (111)B plane orientation, the plurality of nanowires 51 can be grown in the vertical direction. The (111)B plane orientation of the i-GaAs layer 42 is realized by using an InP substrate 40 having a (111)B plane orientation as the InP substrate 40.

[0030] In the semiconductor device shown in FIGS. 7 and 8, the i-InGaAs channel layer 44 and the n-InAlAs supply layer 45 are element-separated by mesa etching. The i-InGaAs channel layer 44 has a shorter length than the n-InAlAs supply layer 45 in the lateral direction of the drawing. This is to prevent the gate electrode 48 formed not only on the upper surface but also on the side surface of the activation region from being electrically short-circuited with the i-InGaAs channel layer 44.

[0031] Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment shown in FIGS. 7 and 8 will be described in detail.

[0032] As shown in Fig. 9, an InP substrate 40 having a (111)B plane orientation, an InP substrate 40, an i-InAlAs buffer layer 41, an i-GaAs layer 42, an i-InGaAs layer 44A, and an n-InAlAs layer 45A are sequentially grown. The thickness of each layer is, for example, 200 nm for the i-InAlAs buffer layer 41, 5 nm for the i-GaAs layer 42, 10 nm for the i-InGaAs layer 44A, and 9 nm for the n-InAlAs layer 45A. The doping concentration of the n-InAlAs layer 45A is, for example, 1e19 cm -3 it may be.

[0033] In Fig. 10, a resist 100 covering the active region is formed by photolithography, and the InGaAs layer 44A and the n-InAlAs layer 45A are wet-etched to form element isolation of a mesa structure. That is, the i-InGaAs layer 44A and the n-InAlAs layer 45A are etched away by wet etching to form an InGaAs layer 44B and an n-InAlAs supply layer 45.

[0034] As shown in Fig. 11, the InGaAs layer 44B is slightly selectively etched to make the horizontal spread narrower than that of the n-InAlAs supply layer 45, thereby forming an i-InGaAs channel layer 44. Then the resist 100 is removed.

[0035] As shown in Fig. 12, the entire structure obtained in Fig. 11 is covered with a SiO2 film 43A by chemical vapor deposition.

[0036] As shown in Fig. 13, a resist (not shown) covering the region other than the nanowire formation region is formed by electron beam lithography, and a plurality of openings are formed in the SiO2 film 43A by dry etching. After the opening formation, the resist is removed. The diameter of the opening is about 50 nm to 200 nm, and the number and arrangement position of the openings coincide with the number and arrangement position of the plurality of nanowires 51. In order to facilitate the growth of the plurality of nanowires 51, an Au catalyst (with a thickness of about 10 nm) may be deposited and lifted off to form an Au catalyst film at the opening position.

[0037] As shown in FIG. 14, i-GaAs nanowires 51 are grown at the opening positions using metalorganic chemical vapor deposition. Specifically, when the substrate temperature is heated from 400 to 500 degrees Celsius and triethylgallium (TEGa) and arsine (AsH3) are supplied as source gases, the source gases decompose and chemically react on the substrate surface, and grow while inheriting the crystal information of the base (i-GaAs layer 42). The height of the plurality of nanowires 51 may be more than that of the mesa, for example, about 0.5 μm.

[0038] As shown in FIG. 15, a resist 101 covering areas other than the gate electrode region is formed by photolithography, and the SiO2 film 43A is etched by dry etching. Thereby, the SiO2 layer 43 is formed.

[0039] As shown in FIG. 16, a gate electrode 48 (Ti / Pt / Au) is deposited and lifted off. At this time, since a gap is formed between the gate electrode 48 and the i-InGaAs channel layer 44, an electrical short circuit between the gate electrode 48 and the i-InGaAs channel layer 44 can be avoided. Note that, at positions other than the position shown in the cross-sectional view of FIG. 16, before forming the gate electrode 48, a source electrode 46 (Ti / Pt / Au) and a drain electrode 47 (Ti / Pt / Au) are formed.

[0040] As shown in FIG. 17, the entire upper side of the structure obtained in FIG. 16 is covered with a filler 102 such as PMGI (Polydimethylglutarimide).

[0041] As shown in FIG. 18, the filler 102 is etched back by dry etching to expose the tips of the gate electrode 48 and the plurality of nanowires 51.

[0042] As shown in FIG. 19, a lead electrode 49 and an electrode pad 50 formed of Ti / Au are provided on the upper surfaces of the gate electrode 48, the filler 102, and the plurality of nanowires 51. Specifically, resist formation by photolithography, electrode material formation by vapor deposition, and lift-off are sequentially performed.

[0043] As shown in FIG. 20, by dissolving the filler 102 with a solvent, all the fillers 102 are removed, including the filler 102 present in the region where the plurality of nanowires 51 are arranged directly below the electrode pad 50. As a result, a gap is formed between the electrode pad 50 and the substrate, and only a plurality of thin nanowires 51 exist between the electrode pad 50 and the substrate.

[0044] Through the above steps, a semiconductor device having a HEMT structure according to the first embodiment is formed.

[0045] FIG. 21 is a diagram showing the device parameters of the HEMT element. As the main parameters, there are source resistance R s , gate resistance R g , gate-source capacitance C gs , gate-drain capacitance C gd , true transconductance g m int (shown simply as g m in FIG. 21). Based on these parameters, the minimum noise figure F min is expressed by the following equation (1).

[0046]

Equation

[0047]

Equation

[0048] Hereinafter, for the configuration in which the electrode pad is directly placed on the substrate (for example, the configuration shown in FIG. 6) and the configuration in which the electrode pad is supported hollow by a plurality of nanowires (the configurations shown in FIGS. 4, 5, 7, 8, etc.), the noise figure represented by the above Equation (1) is evaluated.

[0049] In Table 1 shown below, "normal pad" corresponds to the configuration in which the electrode pad is directly placed on the substrate, and "nanowire pad" corresponds to the configuration in which the electrode pad is supported hollow by a plurality of nanowires.

[0050]

Table 1

[0051] Assuming that 49 nanowires with a diameter of 0.2 μm are arranged in a 0.5 μm pitch, 7 vertically and 7 horizontally, the cross-sectional area of the nanowires is 1.5386 (= 0.1 × 0.1 × 3.14 × 49) μm2 It is. Since the area of a 3 μm × 3 μm pad is 9 μm², the parasitic capacitance of the nanowire pad calculated by the area ratio is about 54 (= 315 × 1.5386 / 9) fF / mm. That is, as shown in Table 1, when focusing on the gate-source capacitance C gs the 54 fF / mm of the nanowire pad is reduced to 17% compared to 315 fF / mm of the normal pad.

[0052] Using these values, based on the actually measured f T = 300 GHz for the transistor with the normal pad, estimating f T for the case of the nanowire pad, as shown in Table 1, f T = 408 GHz. That is, taking 574 fF / mm obtained by adding 54 fF / mm of the nanowire pad and 520 fF / mm of the finger part capacitance as the gate-source capacitance C gs and substituting the gate-drain capacitance Cgd (166 fF / mm) and the true mutual conductance g m int (0.152 S) into Equation (2), f T = 408 GHz for the nanowire pad is calculated.

[0053] Furthermore, by inputting the obtained gate-source capacitance C gs and the value of the cut-off frequency f T and the values of other parameters into the aforementioned Equation (1), the noise figure F min can be obtained for both the case of the normal pad and the case of the nanowire pad. Specifically, at a measurement frequency of 10 GHz, as shown in Table 1, the noise figure F min = 1.53 for the normal pad at room temperature and F min = 1.39 for the nanowire pad are calculated. Moreover, the noise temperature calculated as the value at 4 K by (F min - 1)·K is shown in Table 1. As can be seen from Table 1, the noise temperature in the case of the nanowire pad is reduced to 73% compared to the case of the normal pad.

[0054] Table 2 shows the calculated values of the area coverage rate when forming the nanowire posts on 3 μm × 3 μm pads. The cases of nanowire pitches of 0.5 μm, 1.0 μm, and 1.5 μm are shown respectively.

[0055]

Table 2

[0056] FIG. 22 is a top view showing an example of the configuration of a semiconductor device according to the second embodiment. FIG. 23 is a cross-sectional view showing a cross-section along line C - C' of the semiconductor device shown in FIG. 22.

[0057] The semiconductor device shown in FIGS. 22 and 23 includes a semi-insulating GaAs substrate 60, an i-GaAs buffer layer 61, a SiO2 layer 62, an i-InAlGaAs buffer layer 63, an i-InGaAs channel layer 64, and an n-InAlAs supply layer 65. The semiconductor device further includes a source electrode 66, a drain electrode 67, a gate electrode 68, a lead-out electrode 69, an electrode pad 70, and a plurality of non-conductive nanowires 71. The source electrode 66, the drain electrode 67, and the gate electrode 68 may all be Ti / Pt / Au. Although not shown, n-InGaAs for performing a non-alloy ohmic connection may be provided directly under the source electrode 66 and the drain electrode 67.

[0058] The semiconductor device according to the second embodiment shown in FIGS. 22 and 23 has basically the same configuration as the semiconductor device shown in FIG. 4. That is, the gate electrode 68, the source electrode 66, and the drain electrode 67 are disposed above (on the upper side of) the substrate (GaAs substrate 60, i-GaAs buffer layer 61, and SiO2 layer 62). A plurality of non-conductive nanowires 71 are two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicular to the upper surface of the substrate. The electrode pad 70 is disposed with a gap between the upper ends of the plurality of nanowires 71 and the substrate and is supported by the plurality of nanowires 71. The lead-out electrode 69 electrically connects the electrode pad 70 and the gate electrode 68.

[0059] In the semiconductor device according to the second embodiment shown in FIGS. 22 and 23, the i-InGaAs channel layer 64 and the n-InAlAs supply layer 65 correspond to the active region. The gate electrode 68, the source electrode 66, and the drain electrode 67 are formed on the upper surface of the active region. The n-InAlAs supply layer 65 functions as an electron supply layer that supplies electrons, and the i-InGaAs channel layer 64 functions as an electron traveling layer in which electrons move from the source electrode side toward the drain electrode side. Thus, the semiconductor device according to the second embodiment has a HEMT structure.

[0060] The plurality of nanowires 71 are formed by crystal growth of non-doped GaAs (i-GaAs). The nanowires 71 have a substantially circular cross-section (specifically, a prismatic shape according to the crystal structure) in the horizontal direction, and the diameter is on the order of nanometers. The preferred diameter and pitch of the nanowires 71 are the same as those in the case of the first embodiment.

[0061] In the semiconductor device according to the second embodiment, the substrate includes a first layer (i-GaAs buffer layer 61) formed of the same material as the material (i-GaAs) on which the plurality of nanowires 71 are formed, and the lower ends of the plurality of nanowires 71 are in contact with the first layer (i-GaAs buffer layer 61). By providing the i-GaAs buffer layer 61, the i-GaAs buffer layer 61 functions as a basis for crystal growth, and it becomes possible to grow a plurality of nanowires 71. As the i-GaAs buffer layer 61, by using an i-GaAs layer whose upper surface of the layer is the (111)B plane, that is, an i-GaAs layer having the (111)B plane orientation, a plurality of nanowires 71 can be grown in the vertical direction. The (111)B plane orientation of the i-GaAs buffer layer 61 is realized by using a GaAs substrate 60 having the (111)B plane orientation as a semi-insulating GaAs substrate 60.

[0062] In the semiconductor device shown in FIGS. 22 and 23, the i-InAlGaAs buffer layer 63, the i-InGaAs channel layer 64, and the n-InAlAs supply layer 65 are element-separated by mesa etching. The i-InGaAs channel layer 64 has a shorter length than the n-InAlAs supply layer 65 in the lateral direction of the drawing. This is to prevent the gate electrode 68 formed not only on the upper surface but also on the side surface of the activation region from being electrically short-circuited with the i-InGaAs channel layer 64.

[0063] Note that the lattice constants of the crystal of the i-GaAs buffer layer 61 and the crystal of the i-InGaAs channel layer 64 are mismatched. Therefore, if the i-InGaAs channel layer 64 is provided directly on the upper surface of the i-GaAs buffer layer 61, it is difficult to stably grow the i-InGaAs channel layer 64 with little strain. An i-InAlGaAs buffer layer 63 is provided to relieve this lattice constant mismatch.

[0064] FIG. 24 is a diagram showing an example of the structure of the i-InAlGaAs buffer layer 63. As shown in FIG. 24, the i-InAlGaAs buffer layer 63 has a composition that gradually changes along its thickness direction. That is, when the composition of the i-InAlGaAs buffer layer 63 is i-In x Al y Ga 1-x-y As, the values of x and y are gradually changed along the thickness direction of the layer. Specifically, the values of x and y are close to 0 on the i-GaAs buffer layer 61 side, and the values of x are close to 0.52 and y are close to 0.48 on the i-InGaAs channel layer 64 side, and the values of x and y are gradually changed along the thickness direction of the layer. By providing such an i-InAlGaAs buffer layer 63, crystal defects are less likely to enter the i-InGaAs channel layer 64, and the i-InGaAs channel layer 64 can be stably crystal-grown.

[0065] The manufacturing method of the semiconductor device according to the second embodiment shown in FIGS. 22 and 23 will be described in detail below.

[0066] As shown in FIG. 25, an i-GaAs buffer layer 61, an i-InAlGaAs layer 63A, an i-InGaAs layer 64A, and an n-InAlAs layer 65A are sequentially grown on a semi-insulating GaAs substrate 60 having a (111)B plane orientation. The thickness of each layer is, for example, 200 nm for the i-GaAs buffer layer 61, 500 nm for the i-InAlGaAs layer 63A, 10 nm for the i-InGaAs layer 64A, and 8 nm for the n-InAlAs 65A. The doping concentration of the n-InAlAs layer 65A may be, for example, 1e19 cm -3 or the like.

[0067] In FIG. 26, a resist 200 covering the active region is formed by photolithography, and mesa-structured device isolation is formed by wet-etching the i-InAlGaAs layer 63A, the i-InGaAs layer 64A, and the n-InAlAs layer 65A. That is, the i-InAlGaAs layer 63A, the i-InGaAs layer 64A, and the n-InAlAs layer 65A are etched away by wet-etching, and the i-InAlGaAs buffer layer 63, the i-InGaAs layer 64B, and the n-InAlAs supply layer 65 are formed.

[0068] As shown in FIG. 27, the i-InGaAs channel layer 64 is formed by slightly selectively etching the i-InGaAs layer 64B to make the horizontal spread narrower than that of the n-InAlAs supply layer 65. Thereafter, the resist 200 is removed.

[0069] As shown in FIG. 28, the entire structure obtained in FIG. 27 is covered with a SiO2 film 62A by chemical vapor deposition.

[0070] As shown in FIG. 29, a resist (not shown) covering areas other than the nanowire formation region is formed by electron beam lithography, and a plurality of openings are formed in the SiO2 film 62A by dry etching. After the opening formation, the resist is removed. The diameter of the openings is about 50 nm to 200 nm, and the number and arrangement positions of the openings correspond to the number and arrangement positions of the plurality of nanowires 71. In order to facilitate the growth of the plurality of nanowires 71, an Au catalyst (with a thickness of about 10 nm) may be deposited and lifted off to form an Au catalyst film at the opening positions.

[0071] As shown in FIG. 30, i-GaAs nanowires 71 are grown at the opening positions using metalorganic chemical vapor deposition. Specifically, when the substrate temperature is heated from 400 to 500 degrees Celsius and triethylgallium (TEGa) and arsine (AsH3) are supplied as source gases, the source gases decompose and chemically react on the substrate surface, and grow while inheriting the crystal information of the base (i-GaAs buffer layer 61). The height of the plurality of nanowires 71 may be more than that of the mesa, for example, about 0.8 μm.

[0072] As shown in FIG. 31, a resist 201 that covers areas other than the gate electrode region is formed by photolithography, and the SiO2 film 62A is etched by dry etching. Thereby, the SiO2 layer 62 is formed.

[0073] As shown in FIG. 32, a gate electrode 68 (Ti / Pt / Au) is deposited and lifted off. At this time, since a gap is formed between the gate electrode 68 and the i-InGaAs channel layer 64, an electrical short circuit between the gate electrode 68 and the i-InGaAs channel layer 64 can be avoided. Note that, at positions other than the position shown in the cross-sectional view of FIG. 32, before forming the gate electrode 68, a source electrode 66 (Ti / Pt / Au) and a drain electrode (Ti / Pt / Au) are formed.

[0074] As shown in FIG. 33, the entire upper side of the structure obtained in FIG. 32 is covered with a filler 202 such as PMGI.

[0075] As shown in FIG. 34, the filler 202 is etched back by dry etching to expose the tips of the gate electrode 68 and the plurality of nanowires 71.

[0076] As shown in FIG. 35, a lead-out electrode 69 and an electrode pad 70 formed of Ti / Au are provided on the upper surfaces of the gate electrode 68, the filler 202, and the plurality of nanowires 71. Specifically, resist formation by photolithography, electrode material formation by deposition, and lift-off are sequentially performed.

[0077] As shown in FIG. 36, by dissolving the filler 202 with a solvent, all the fillers 202 are removed, including the filler 202 present in the region where a plurality of nanowires 71 are arranged directly under the electrode pad 70. As a result, a gap is formed between the electrode pad 70 and the substrate, and only a plurality of thin nanowires 71 exist between the electrode pad 70 and the substrate.

[0078] Through the above process, a semiconductor device having a HEMT structure according to the second embodiment is formed.

[0079] FIG. 37 is a top view showing an example of the configuration of a semiconductor device according to the third embodiment. FIG. 38 is a cross-sectional view showing a cross-section along line D-D' of the semiconductor device shown in FIG. 37.

[0080] The semiconductor device according to the second embodiment shown in FIGS. 37 and 38 is different from the semiconductor device according to the first embodiment shown in FIGS. 7 and 8 only in that a plurality of nanowires 51 are replaced by a plurality of nanowires 51A. Other configurations are the same between the first embodiment and the second embodiment.

[0081] The material of the plurality of nanowires 51 in the first embodiment was i-GaAs containing no impurities, but the material of the plurality of nanowires 51A in the second embodiment is GaAs regardless of the conductivity type (i.e., impurities may be included). However, in order to remove the conductivity of the plurality of nanowires 51A caused by impurities, defects are introduced into the nanowires by performing an ion implantation process on the plurality of nanowires 51A as schematically shown by a plurality of arrows in FIG. 38. Carriers caused by impurities contained in GaAs are trapped by these defects, whereby the plurality of nanowires 51A can be made non-conductive.

[0082] As described above, in the third embodiment, the plurality of nanowires 51A are formed of a semiconductor deactivated by introducing defects. Therefore, when it is found by inspection that the plurality of nanowires 51A are conductive in the manufactured semiconductor device, by incorporating the ion implantation process into the manufacturing process, it is possible to ensure that the nanowires are non-conductive in the semiconductor device manufactured thereafter.

[0083] Hereinafter, a method for manufacturing a semiconductor device according to a third embodiment shown in FIGS. 37 and 38 will be described in detail.

[0084] In the manufacturing process of the third embodiment, first, the same manufacturing process as that in the manufacturing process of the first embodiment shown in FIGS. 7 to 13 is executed.

[0085] Thereafter, as shown in FIG. 39, using metalorganic chemical vapor deposition, nanowires 51A of, for example, n-GaAs (5e17 cm -3 ) are grown at the opening positions. The height of the plurality of nanowires 51A may be more than that of the mesa, but may be, for example, about 0.5 μm.

[0086] As shown in FIG. 40, a resist 103 that covers areas other than the gate electrode region is formed by photolithography.

[0087] As shown in FIG. 41, oxygen ions are implanted into the plurality of nanowires 51A at an angle with respect to the vertical direction to introduce defects into the plurality of nanowires 51A and compensate for carriers. After the ion implantation process, the resist 103 is removed.

[0088] Thereafter, by executing the same manufacturing process as that in the manufacturing process of the first embodiment shown in FIGS. 15 to 20, the semiconductor device according to the third embodiment is completed.

[0089] FIG. 42 is a top view showing an example of the configuration of a semiconductor device according to a fourth embodiment. FIG. 43 is a cross-sectional view showing a cross-section along line E-E' of the semiconductor device shown in FIG. 42.

[0090] The semiconductor device according to the fourth embodiment shown in FIGS. 42 and 43 is different from the semiconductor device according to the first embodiment shown in FIGS. 7 and 8 only in that an interlayer insulating film 55 is provided. Other configurations are the same between the first embodiment and the fourth embodiment.

[0091] The semiconductor device according to the fourth embodiment includes an insulating film provided on a substrate (more specifically, on the substrate, transistors, electrode pads, etc.). By using this insulating film as an interlayer insulating film, a circuit can be further formed on the upper surface of the interlayer insulating film. Further, since the insulating film 55 has voids at the positions of the plurality of nanowires 51, at least some of the plurality of nanowires 51 are not in contact with the insulating film 55. As a result, even when an interlayer insulating film is provided, it is possible to provide a space with nothing between the electrode pad 50 and the dielectric substrate, and the parasitic capacitance generated by the high-permittivity semiconductor substrate under the electrode pad 50 can be greatly reduced. Therefore, noise in the signal input to the transistor can be reduced.

[0092] Hereinafter, the manufacturing method of the semiconductor device according to the fourth embodiment shown in FIGS. 42 and 43 will be described in detail.

[0093] In the manufacturing process of the fourth embodiment, first, the same manufacturing process as that in the first embodiment shown in FIGS. 7 to 19 is executed.

[0094] Thereafter, as shown in FIG. 44, the filler 102 (see FIG. 19) is etched and removed by dry etching. At this time, the filler 102 remains only directly under the electrode pad 50. Note that a resist covering the position of the electrode pad 50 may be formed by photolithography so that the filler 102 surely remains directly under the electrode pad 50, and then the resist may be removed.

[0095] As shown in FIG. 45, an insulating film 55 made of, for example, BCB (Benzocyclobutene) is formed so as to cover the entire upper side of the structure obtained in FIG. 44. As a result, each member such as the gate electrode 48, the lead-out electrode 49, and the electrode pad 50 is covered with the insulating film 55, including the filler 102 remaining so as to surround the plurality of nanowires 51.

[0096] As shown in FIG. 46, by dissolving the filler 102 with a solvent, the filler 102 present in the region where the plurality of nanowires 51 are arranged directly under the electrode pad 50 is removed. Specifically, a hole reaching from the upper surface of the insulating film 55 to the filler 102 is formed, and the solvent is poured into the hole to melt and remove the filler 102. As a result, a gap is formed between the electrode pad 50 and the substrate, and only a plurality of thin nanowires 51 exist between the electrode pad 50 and the substrate.

[0097] FIG. 47 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fifth embodiment.

[0098] The semiconductor device according to the fifth embodiment shown in FIG. 47 is different from the semiconductor device according to the first embodiment only in that the plurality of nanowires 51 are replaced by a plurality of nanowires 81, the i-GaAs layer 42 is deleted, and an AlO2 layer 80 is provided instead of the SiO2 layer 43. Other configurations are the same in the first embodiment and the fifth embodiment.

[0099] In the semiconductor device according to the fifth embodiment, the plurality of nanowires 81 are formed of an insulator. That is, the plurality of nanowires 81 are formed of an insulating material instead of a semiconductor such as i-GaAs. The material of the plurality of nanowires 81 may be, for example, BCB and may be formed by dry etching. In this case, an AlO2 layer 80 is provided as a protective film instead of the SiO2 layer 43 in order to enable selective etching. In this configuration, since it is not necessary to grow i-GaAs nanowires, the i-GaAs layer 42 provided in the semiconductor device according to the first embodiment becomes unnecessary.

[0100] Also in the fifth embodiment, a plurality of non-conductive nanowires 81 made of an insulator are two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicular to the upper surface of the substrate. The electrode pad 50 is arranged so as to have a gap between the upper ends of the plurality of nanowires 81 and the substrate and is supported by the plurality of nanowires 81. Therefore, the parasitic capacitance generated by the substrate, which is a semiconductor with a high dielectric constant, under the electrode pad 50 can be greatly reduced. Accordingly, noise in the signal input to the transistor can be reduced.

[0101] As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications are possible within the scope described in the claims.

Explanation of Reference Numerals

[0102] 10 Cryogenic dilution refrigerator 11 Microwave pulse generator 12 Quantum bit chip 13 Low-noise amplifier 13-1 to 13-n Amplifying device 14 Demodulator 20 First matching circuit 21 Transistor 22 Second matching circuit 23 to 26 Capacitive elements 27, 28 Resistive elements 30 Substrate 31 Active region 32 Source electrode 33 Drain electrode 34 Gate electrode 35 Lead-out electrode 36 Electrode pad 37 Nanowire 40 InP substrate 41 i-InAlAs buffer layer 42 i-GaAs layer 43 SiO2 layer 44 i-InGaAs channel layer 45 n-InAlAs supply layer 46 Source electrode 47 Drain electrode 48 Gate electrode 49 Lead-out electrode 50 Electrode pad 51 Nanowire

Claims

1. A substrate, a transistor having a gate electrode, a source electrode, and a drain electrode disposed on the substrate, a plurality of nanowires made of a non-conductive material two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicular to the upper surface of the substrate, an electrode pad disposed with a gap between the upper ends of the plurality of nanowires and the substrate and supported by the plurality of nanowires, and a lead electrode connecting the electrode pad and the gate electrode A semiconductor device comprising.

2. The semiconductor device according to claim 1, further comprising an active region formed on the upper surface of the substrate, wherein the gate electrode, the source electrode, and the drain electrode are formed on the upper surface of the active region, and the active region includes a channel layer and an electron supply layer.

3. The semiconductor device according to claim 1 or 2, wherein the plurality of nanowires are formed of undoped GaAs.

4. The semiconductor device according to any one of claims 1 to 3, wherein the substrate includes a first layer formed of the same material as the material on which the plurality of nanowires are formed, and the lower ends of the plurality of nanowires are in contact with the first layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the plurality of nanowires are formed of a semiconductor inactivated by introducing defects.

6. The semiconductor device according to any one of claims 1 to 5, further comprising an insulating film provided on the substrate, wherein the insulating film has a gap at the position of the plurality of nanowires, so that at least some of the plurality of nanowires are not in contact with the insulating film.

7. The semiconductor device according to claim 1 or 2, wherein the nanowires are formed of an insulator.

8. A substrate, a transistor having a gate electrode, a source electrode, and a drain electrode disposed on the substrate, a plurality of nanowires made of a non-conductive material two-dimensionally arranged on the upper surface of the substrate so as to extend perpendicular to the upper surface of the substrate, an electrode pad disposed with a gap between the upper ends of the plurality of nanowires and the substrate and supported by the plurality of nanowires, a lead electrode connecting the electrode pad and the gate electrode, a first matching circuit for applying an input signal from the outside to the electrode pad, a second matching circuit for outputting a signal from the source electrode or the drain electrode to the outside, An amplification device comprising.

9. Form a substrate including a first layer formed of a first material, Form a transistor on the substrate, Crystal-grow a plurality of nanowires formed of the first material on the upper surface of the first layer, Form an electrode pad disposed so as to have a gap with the substrate at the upper ends of the plurality of nanowires and supported by the plurality of nanowires, A method of manufacturing a semiconductor device including each step.

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