Substrate for semiconductor package and method for manufacturing substrate for semiconductor package

Abstract

To provide an organic interposer and a method for manufacturing the organic interposer capable of improving insulation reliability.SOLUTION: An organic interposer 10 includes: an organic insulating laminate 12 comprising a plurality of organic insulating layers; and a plurality of wires 13 arranged in the organic insulating laminate 12, where the wires 13 and the organic insulating layers are separated by a barrier metal film 14. The organic insulating laminate 12 may include: a first organic insulating layer 21 having a plurality of grooves 21a having the wires 13 disposed therein; and a second organic insulating layer 22 laminated on the first organic insulating layer 21 in such a way as to embed the wires 13.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to an organic interposer and a method for manufacturing an organic interposer.

Background Art

[0002] For the purpose of increasing the density and performance of semiconductor packages, a mounting form in which chips with different performances are mixed and mounted in one package has been proposed. In this case, a high-density interconnect technology between chips, which is excellent in terms of cost, has become important (see, for example, Patent Document 1).

[0003] Non-Patent Document 1 and Non-Patent Document 2 describe a package-on-package (PoP) aspect in which different packages are stacked and connected on a package by flip-chip mounting. This PoP is an aspect widely adopted in smartphones, tablet terminals, and the like.

[0004] Furthermore, as other forms for mounting a plurality of chips at high density, package technology using an organic substrate having high-density wiring (organic interposer), fan-out type package technology having through mold vias (TMV) (FO-WLP: F a n Out-Wafer Level Package), package technology using a silicon or glass interposer, package technology using through silicon vias (TSV), package technology using chips embedded in a substrate for inter-chip transmission, and the like have been proposed.

[0005] Particularly, when mounting semiconductor chips on each other in an organic interposer and FO-WLP, a fine wiring layer for electrically connecting the semiconductor chips at high density is required (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2012-529770 [Patent Document 2] U.S. Patent Application Publication No. 2011 / 0221071 [Non-Patent Document]

[0007] [Non-Patent Document 1] Jinseong Kim et al., 「Application of Through Mold Via (TMV) as PoP Base Package」, Electronic Components and Technology Conference (ECTC), p.1089-1092 (2008) [Non-Patent Document 2] S.W. Yoon et al., 「Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology」, ECTC, p.1250-1254 (2012) [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] For a build-up substrate, a wafer-level package (WLP), a bottom package of a fan-out type PoP, etc., an organic interposer having a laminate (organic insulation laminate) formed by laminating a plurality of organic insulation layers may be used. For example, when a plurality of fine wirings having a line width and a space width of 10 μm or less are arranged in this organic insulation laminate, the wirings are formed using a trench method. The trench method is a method of forming a metal layer serving as a wiring in a trench (groove) formed on the surface of an organic insulation layer by a plating method or the like. Therefore, the shape of the wiring formed on the organic insulation layer follows the shape of the groove.

[0009] When forming fine wiring in an organic insulating laminate by the trench method, in order to reduce costs and suppress an increase in wiring resistance, for example, a metal material having high conductivity such as copper may be used. When wiring is formed using such a metal material, the metal material may diffuse into the organic insulating laminate. In this case, there is a risk of short - circuiting between wirings through the diffused metal material, and there are problems with the insulation reliability of the organic interposer.

[0010] An object of the present invention is to provide an organic interposer capable of improving insulation reliability and a method for manufacturing the same.

Means for Solving the Problems

[0011] The organic interposer according to the first aspect of the present invention includes an organic insulating laminate including a plurality of organic insulating layers, and a plurality of wirings arranged in the organic insulating laminate, and the wiring and the organic insulating layer are partitioned by a barrier metal film.

[0012] In this organic interposer, the wiring and the organic insulating layer are partitioned by a barrier metal film. Therefore, the diffusion of the metal material in the wiring into the organic insulating laminate is suppressed by the barrier metal film. Accordingly, short - circuiting between a plurality of wirings through the diffused metal material can be suppressed, and the insulation reliability of the organic interposer can be improved.

[0013] The organic insulating laminate may include a first organic insulating layer having a plurality of groove portions in which the wirings are arranged, and a second organic insulating layer laminated on the first organic insulating layer so as to embed the wirings. In this case, each of the plurality of wirings has a shape along the groove portions of the first organic insulating layer. Therefore, by forming a plurality of groove portions having a fine width and interval, fine wiring can be easily formed.

[0014] The barrier metal film may include a first barrier metal film provided between the wiring and the inner surface of the groove portion, and a second barrier metal film provided between the wiring and the second organic insulating layer. In this case, the diffusion of the metal material in the wiring into the first organic insulating layer is preferably suppressed by the first barrier metal film. Further, the diffusion of the metal material into the second organic insulating layer is preferably suppressed by the second barrier metal film.

[0015] The first barrier metal film may include at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. Titanium, nickel, palladium, chromium, tantalum, tungsten, and gold are all less likely to diffuse into the first and second organic insulating layers, so the insulation reliability of the organic interposer can be further improved.

[0016] The second barrier metal film may be a plating film. In this case, since the second barrier metal film can be selectively formed on the wiring in the groove portion, the manufacturing process of the organic interposer can be simplified.

[0017] The second barrier metal film may be a nickel plating film. In this case, a second barrier metal film having good flatness can be easily formed. In addition, since nickel is less likely to diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be suitably improved.

[0018] The second barrier metal film may be a palladium plating film. In this case, the second barrier metal film can be easily thinned. In addition, since palladium is less likely to diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be suitably improved.

[0019] The thickness of the second barrier metal film may be 0.001 μm or more and 1 μm or less. In this case, the diffusion of the metal material in the wiring into the second organic insulating layer is preferably suppressed by the second barrier metal film.

[0020] The surface roughness of the second barrier metal film may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film can adhere well to the second organic insulating layer. Further, disconnection or the like in the organic interposer due to the surface roughness of the second barrier metal film can be suppressed.

[0021] The thickness of the first organic insulating layer may be 1 μm or more and 10 μm or less. In this case, a plurality of groove portions having a width and an interval of 10 μm or less can be formed using the first organic insulating layer.

[0022] The first organic insulating layer may be a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. In this case, groove portions having a fine width and interval can be easily formed in the first organic insulating layer. In addition, since the moisture contained in the first organic insulating layer can be reduced, it becomes difficult for the metal material to diffuse into the first organic insulating layer. Therefore, the insulation reliability of the organic interposer can be improved.

[0023] The method for manufacturing an organic interposer according to the second aspect of the present invention includes: a first step of forming a plurality of groove portions in a first organic insulating layer; a second step of forming a first barrier metal film on the first organic insulating layer so as to cover the inner surfaces of the groove portions; a third step of forming a wiring layer on the first barrier metal film so as to fill the groove portions; a fourth step of thinning the wiring layer so that the first organic insulating layer is exposed; a fifth step of forming a second barrier metal film so as to cover the wiring layer in the groove portions; and a sixth step of forming a second organic insulating layer on the first organic insulating layer and on the second barrier metal film.

[0024] In the method for manufacturing this organic interposer, by going through the first to third steps, a first barrier metal film can be formed between the inner surface of each groove portion and the wiring layer. Further, by going through the fourth to sixth steps, a second barrier metal film can be formed between the wiring layer and the second organic insulating layer in the stacking direction of the organic insulating layer. For this reason, the diffusion of the metal material in the wiring layer into the first and second organic insulating layers is suppressed by the first and second barrier metal films. Therefore, since a short circuit between a plurality of wirings through the diffused metal material can be suppressed, the insulation reliability of the organic interposer can be improved.

[0025] In the third step, the wiring layer may be formed by a plating method using the first barrier metal film as a seed layer. In this case, the wiring layer can be formed so that the first barrier metal film is sandwiched between the first organic insulating layer and the wiring layer. Thereby, the diffusion of the metal material in the wiring layer into the first organic insulating layer is satisfactorily suppressed.

[0026] In the fifth step, the second barrier metal film may be formed by a plating method using the wiring layer as a seed layer. In this case, since the second barrier metal film can be selectively formed on the wiring layer, the manufacturing process of the organic interposer can be simplified.

[0027] In the fourth step, a part of the wiring layer in the groove portion may be removed, and in the fifth step, the second barrier metal film may be formed so as to fill the groove portion. In this case, since the second barrier metal film is formed by being filled in the groove portion, the formation of steps caused by the second barrier metal film in the organic interposer can be suppressed. Thereby, a semiconductor element or the like can be satisfactorily mounted on the organic interposer.

Advantages of the Invention

[0028] According to the present invention, an organic interposer having good insulation reliability and a method for manufacturing the same can be provided.

Brief Description of the Drawings

[0029]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the positional relationships such as up, down, left, right, etc. are based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[0031] In the description and claims of this embodiment, when terms such as "left", "right", "front", "back", "up", "down", "above", "below", "first", "second", etc. are used, these are for the purpose of explanation and do not necessarily mean that this is the permanent relative position. Also, "layer" and "film" include not only the structure formed over the entire surface when observed as a plan view, but also the structure formed in part. Also, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes as long as the intended purpose of the process is achieved. Also, in the numerical ranges described step by step in this specification, the upper limit value or lower limit value of a numerical range at a certain step may be replaced with the upper limit value or lower limit value of a numerical range at another step.

[0032] FIG. 1 is a schematic cross-sectional view of a semiconductor package having an organic interposer according to this embodiment. The organic interposer of the present disclosure is preferably used in a package form that requires an interposer for mounting different types of chips.

[0033] As shown in FIG. 1, the semiconductor package 100 is a device in which semiconductor chips 2A and 2B are mounted on an organic interposer 10 provided on a substrate 1. The semiconductor chips 2A and 2B are respectively fixed on the organic interposer 10 by corresponding underfills 3A and 3B, and are electrically connected to each other through surface wirings 16 (details will be described later) provided in the organic interposer 10. The substrate 1 is a sealed body formed by sealing semiconductor chips 2C and 2D and electrodes 5A and 5B with an insulating material 4. The semiconductor chips 2C and 2D in the substrate 1 can be connected to an external device through electrodes exposed from the insulating material 4. The electrodes 5A and 5B function as conductive paths for electrically connecting the organic interposer 10 and the external device to each other, for example.

[0034] Each of the semiconductor chips 2A to 2D is, for example, a graphics processing unit (GPU), a volatile memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), a non-volatile memory such as a flash memory, an RF chip, a silicon photonics chip, a MEMS (Micro Electro Mechanical Systems), a sensor chip, or the like. The semiconductor chips 2A to 2D may have TSVs. Each of the semiconductor chips 2A to 2D can use, for example, a stacked semiconductor element. In this case, a stacked semiconductor element using TSVs can be used. The thickness of the semiconductor chips 2A and 2B is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 100, the thickness of the semiconductor chips 2A and 2B is preferably 100 μm or less. Also, from the viewpoint of handleability, the thickness of the semiconductor chips 2A and 2B is more preferably 30 μm or more.

[0035] The underfills 3A and 3B are, for example, capillary underfill (CUF), mold underfill (MUF), paste underfill (NCP), film underfill (NCF), or photosensitive underfill. The underfills 3A and 3B are each composed mainly of a liquid curable resin (e.g., an epoxy resin). Further, the insulating material 4 is, for example, a curable resin having insulation properties.

[0036] Next, the organic interposer 10 according to this embodiment will be described in detail with reference to FIG. 2. The organic interposer 10 in this embodiment is an organic substrate that supports a semiconductor element or the like. For example, it is a build-up substrate formed by laminating a material (prepreg) impregnated with resin on glass cloth or carbon fiber, a substrate for wafer-level packaging, a coreless substrate, a substrate produced by thermally curing a sealing material, or a substrate in which chips are sealed or embedded. The shape of the organic interposer 10 depends on the shape of the substrate 11 described later, and may be wafer-shaped (substantially circular in plan view) or panel-shaped (substantially rectangular in plan view). Note that, from the viewpoint of suppressing warping, the coefficient of thermal expansion of the organic interposer 10 is preferably, for example, 40 ppm / °C or less. From the viewpoint of insulation reliability of the organic interposer 10, the coefficient of thermal expansion is preferably 20 ppm / °C or less.

[0037] The organic interposer 10 provided on the substrate 11 shown in FIG. 2 includes an organic insulation laminate 12 including a plurality of organic insulation layers, a plurality of wirings 13 arranged in the organic insulation laminate 12, a barrier metal film 14 covering the wirings 13, a through-wiring 15 penetrating the organic insulation laminate 12, and a surface wiring 16 formed on the surface of the organic insulation laminate 12 and in the vicinity thereof.

[0038] The substrate 11 is a support that supports the organic interposer 10. The shape of the substrate 11 in plan view is, for example, circular or rectangular. When it is circular, the substrate 11 has a diameter of, for example, 200 mm to 450 mm. When it is rectangular, one side of the substrate 11 is, for example, 300 mm to 700 mm.

[0039] The substrate 11 is, for example, a silicon substrate, a glass substrate, or a peelable copper foil. The substrate 11 may be, for example, a build-up substrate, a substrate for wafer-level packaging, a coreless substrate, a substrate manufactured by thermally curing a sealing material, or a substrate in which chips are sealed or embedded. When a silicon substrate, a glass substrate, or the like is used as the substrate 11, a temporary fixing layer (not shown) for temporarily fixing the organic interposer 10 and the substrate 11 may be provided. In this case, the substrate 11 can be easily peeled from the organic interposer 10 by removing the temporary fixing layer. Note that the peelable copper foil is a laminate in which a support, a release layer, and a copper foil are laminated in this order. In the peelable copper foil, the support corresponds to the substrate 11, and the copper foil corresponds to the material of a part of the copper wiring included in the through wiring 15.

[0040] The organic insulating laminate 12 includes a first organic insulating layer 21 having a plurality of groove portions 21a in which the corresponding wirings 13 are disposed, and a second organic insulating layer 22 laminated on the first organic insulating layer 21 so as to embed the wirings 13. Further, the organic insulating laminate 12 is provided with a plurality of openings 12a through which the through wirings 15 are provided.

[0041] The plurality of groove portions 21a are provided on the surface of the first organic insulating layer 21 on the side opposite to the substrate 11. In a cross section along the direction orthogonal to the extending direction of the groove portions 21a, each of the groove portions 21a has a substantially rectangular shape. For this reason, the inner surface of the groove portion 21a has side surfaces and a bottom surface. Further, the plurality of groove portions 21a have a predetermined line width L and a space width S. Each of the line width L and the space width S is, for example, from 0.5 μm to 10 μm, preferably from 0.5 μm to 5 μm, and more preferably from 2 μm to 5 μm. From the viewpoint of realizing high-density transmission of the organic interposer 10, the line width L is preferably from 1 μm to 5 μm. The line width L and the space width S may be set to be the same as each other or may be set to be different from each other. The line width L corresponds to the width of the groove portion 21a in the direction orthogonal to the extending direction of the groove portion 21a in a plan view. The space width S corresponds to the distance between adjacent groove portions 21a. The depth of the groove portion 21a corresponds to, for example, the thickness of a fourth organic insulating layer 24 described later.

[0042] The surface roughness of the inner surface in the groove portion 21a is preferably from 0.01 μm to 0.1 μm. When this surface roughness is 0.01 μm or more, the adhesion of an object that adheres to the first organic insulating layer 21 in the groove portion 21a and the temperature cycle resistance are improved. When the surface roughness is 0.1 μm or less, a short circuit of the wiring 13 is suppressed, and the high-frequency characteristics of the wiring 13 tend to be improved. The surface roughness of the inner surface in the groove portion 21a is calculated, for example, by observing the cross section of the groove portion 21a with an electron microscope. Note that the surface roughness is an arithmetic mean roughness (Ra) defined in JIS B 0601 2001, and the following "surface roughness" is all "surface roughness Ra". The temperature cycle resistance is the resistance to volume change, performance deterioration, breakage, etc. accompanying temperature change.

[0043] The first organic insulating layer 21 is provided between the substrate 11 and the second organic insulating layer 22. The storage elastic modulus of the first organic insulating layer 21 at room temperature is, for example, 500 MPa to 10GIt is Pa. By having the storage elastic modulus of 500 MPa or more, stretching during grinding of the first organic insulating layer 21 can be suppressed. Thereby, for example, it is possible to prevent the stretched resin material from covering the wiring 13 in the groove portion 21a. Further, by having the storage elastic modulus of 10 GPa or less, for example, breakage of the grinding blade can be prevented, and as a result, an increase in the surface roughness of the first organic insulating layer 21 and the like can be suppressed. Note that "room temperature" indicates about 25°C.

[0044] The first organic insulating layer 21 includes a third organic insulating layer 23 located on the substrate 11 side and a fourth organic insulating layer 24 located on the second organic insulating layer 22 side. A plurality of openings corresponding to the groove portion 21a are provided in a part of the fourth organic insulating layer 24. The surface of the third organic insulating layer 23 exposed by these openings constitutes the bottom surface of the inner surface of the groove portion 21a. Further, each side surface of the inner surface of the groove portion 21a is constituted by the fourth organic insulating layer 24.

[0045] The thicknesses of the third organic insulating layer 23 and the fourth organic insulating layer 24 are, for example, 0.5 μm to 10 μm each. Therefore, the thickness of the first organic insulating layer 21 is, for example, 1 μm to 20 μm. By having the thickness of the first organic insulating layer 21 of 1 μm or more, the first organic insulating layer 21 can contribute to stress relaxation of the organic insulating laminate 12, and the temperature cycle resistance of the organic insulating laminate 12 can be improved. By having the thickness of the first organic insulating layer 21 of 20 μm or less, warpage of the organic insulating laminate 12 can be suppressed, and for example, when the organic insulating laminate 12 is ground, the wiring and the like can be easily exposed. From the viewpoint of forming the wiring 13 having a width of 3 μm or less by performing exposure and development, the thickness of the first organic insulating layer 21 is preferably 15 μm or less, and more preferably 10 μm or less.

[0046] Each of the first organic insulating layer 21 and the second organic insulating layer 22 in the organic insulating laminate 12 is, for example, liquid or film-shaped and contains an insulating material having curability. From the viewpoints of the flatness of the organic insulating layer and the manufacturing cost, a film-shaped material (organic insulating material) is preferable. In this case, for example, even if the surface roughness of the substrate 11 is 300 μm or more, the surface roughness of the organic insulating laminate 12 can be reduced. Further, the film-shaped organic insulating material is preferably laminatable at 40°C to 120°C. By setting the laminatable temperature to 40°C or higher, it is possible to suppress the increase in the tack (adhesiveness) of the organic insulating material at room temperature and maintain good handleability. By setting the laminatable temperature to 120°C or lower, it is possible to suppress the occurrence of warpage in the organic insulating laminate 12.

[0047] From the viewpoint of suppressing warpage of the organic insulating layer (and the organic insulating laminate 12), the coefficient of thermal expansion of the cured organic insulating material is, for example, 80 ppm / °C or less. From the viewpoint of the insulation reliability of the organic interposer 10, the coefficient of thermal expansion is preferably 70 ppm / °C or less. Further, from the viewpoints of the stress relaxation property and the processing accuracy of the organic insulating material, the coefficient of thermal expansion is more preferably 20 ppm / °C or more.

[0048] The organic insulating material is preferably a photosensitive organic insulating material (photosensitive insulating resin) from the viewpoints of ease of processing and processing accuracy. This photosensitive insulating resin is more preferably a negative photosensitive insulating resin from the viewpoints of heat resistance and ease of handling. The insulating resin that is photocured may contain a photo radical initiator or a photoacid generator, but from the viewpoint of ease of microfabrication, it is preferably contained a photoacid generator. From the above viewpoints, the organic insulating layer is most preferably a negative photosensitive insulating resin film containing a photoacid generator.

[0049] The photoacid generator is not particularly limited as long as it is a compound that generates an acid upon light irradiation. From the viewpoint of efficiently generating an acid, the photoacid generator is preferably, for example, an onium salt compound or a sulfonimide compound. Examples of the onium salt compound include iodonium salts and sulfonium salts. Specific examples include diaryliodonium salts such as diphenyliodonium trifluoromethanesulfonate, diphenyliodonium p-toluenesulfonate, diphenyliodonium hexafluoroantimonate, diphenyliodonium hexafluorophosphate, diphenyliodonium tetrafluoroborate, etc.; triarylsulfonium salts such as triphenylsulfonium trifluoromethanesulfonate, triphenylsulfonium p-toluenesulfonate, triphenylsulfonium hexafluoroantimonate, etc.; 4-tert-butylphenyl-diphenylsulfonium p-toluenesulfonate; 4,7-di-n-butoxynaphthyltetrahydrothiophenium trifluoromethanesulfonate, etc. Specific examples of the sulfonimide compound include N-(trifluoromethylsulfonyloxy)succinimide, N-(trifluoromethylsulfonyloxy)phthalimide, N-(trifluoromethylsulfonyloxy)diphenylmaleimide, N-(trifluoromethylsulfonyloxy)bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide, N-(trifluoromethylsulfonyloxy)naphthalimide, N-(p-toluenesulfonyloxy)-1,8-naphthalimide, N-(10-camphorsulfonyloxy)-1,8-naphthalimide, etc.

[0050] From the viewpoint of resolution, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group may be used as the photoacid generator.

[0051] The photosensitive insulating resin is preferably soluble in a 2.38 mass% aqueous solution of tetramethylammonium. From the viewpoints of the resolution, storage stability, and insulation reliability of the photosensitive insulating resin, the photosensitive insulating resin preferably contains a compound having a phenolic hydroxyl group. Examples of the compound having a phenolic hydroxyl group include phenol / formaldehyde condensation novolak resin, cresol / formaldehyde condensation novolak resin, phenol-naphthol / formaldehyde condensation novolak resin, polyhydroxystyrene and its polymers, phenol-xylylene glycol condensation resin, cresol-xylylene glycol condensation resin, phenol-dicyclopentadiene condensation resin, and the like.

[0052] The photosensitive insulating resin preferably contains a thermosetting resin. Examples of the thermosetting resin include acrylate resin, epoxy resin, cyanate ester resin, maleimide resin, allyl nadimide resin, phenol resin, urea resin, melamine resin, alkyd resin, unsaturated polyester resin, diallyl phthalate resin, silicone resin, resorcinol formaldehyde resin, triallyl cyanurate resin, polyisocyanate resin, resin containing tris(2-hydroxyethyl) isocyanurate, resin containing triallyl trimellitate, and thermosetting resin synthesized from cyclopentadiene. From the viewpoints of the resolution, insulation reliability, and adhesion to metal of the photosensitive insulating resin, the thermosetting resin is more preferably a compound having any one of a methylol group, an alkoxyalkyl group, and a glycidyl group.

[0053] From the above viewpoints, it is most preferable that each of the first organic insulating layer 21 and the second organic insulating layer 22 is a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. Incidentally, each of the first organic insulating layer 21 and the second organic insulating layer 22 may contain a filler. From the viewpoints of ease of processing and processing accuracy, the average particle diameter of the filler is, for example, 500 nm or less. It is preferable that the content of the filler in the first organic insulating layer 21 (or the second organic insulating layer 22) is less than 1% by mass. Further, it is more preferable that the first organic insulating layer 21 and the second organic insulating layer 22 do not contain a filler.

[0054] As described above, the plurality of wirings 13 are provided in the corresponding groove portions 21a and function as conductive paths inside the organic interposer 10. Therefore, the width of the wiring 13 substantially coincides with the line width L of the groove portion 21a, and the interval between adjacent wirings 13 substantially coincides with the space width S of the groove portion 21a. From the viewpoint of favorably exhibiting the function as a conductive path, it is preferable that the wiring 13 contains a metal material having high conductivity. The metal material having high conductivity is, for example, copper, aluminum, or silver. These metal materials tend to diffuse into the organic insulating laminate 12 by heating. From the viewpoints of conductivity and cost, the metal material contained in the wiring 13 is preferably copper.

[0055] The barrier metal film 14 is a metal film provided so as to partition the wiring 13 from the first organic insulating layer 21 and the second organic insulating layer 22. The barrier metal film 14 includes a first barrier metal film 31 provided between the wiring 13 and the inner surface of the groove portion 21a, and a second barrier metal film 32 provided between the wiring 13 and the second organic insulating layer 22. Therefore, the first barrier metal film 31 is provided so as to partition the wiring 13 from the inner surface of the groove portion 21a (that is, the first organic insulating layer 21). Further, the second barrier metal film 32 is provided so as to partition the wiring 13 from the second organic insulating layer 22.

[0056] The first barrier metal film 31 is a conductive film for preventing the diffusion of the metal material in the wiring 13 into the first organic insulating layer 21, and is formed along the inner surface of the groove portion 21a. The first barrier metal film 31 contains at least one of, for example, titanium, nickel, palladium, chromium, tantalum, tungsten, and gold as a metal material that is less likely to diffuse into the organic insulating layer. From the viewpoint of adhesion to the inner surface of the groove portion 21a, the first barrier metal film 31 is preferably a titanium film or an alloy film containing titanium. Further, from the viewpoint of forming the first barrier metal film 31 by sputtering, the first barrier metal film 31 is preferably a titanium film, a tantalum film, a tungsten film, a chromium film, or an alloy film containing at least any one of titanium, tantalum, tungsten, and chromium.

[0057] The thickness of the first barrier metal film 31 is less than half of the width of the groove portion 21a and less than the depth of the groove portion 21a, and is, for example, 0.001 μm to 0.5 μm. From the viewpoint of preventing the diffusion of the metal material in the wiring 13, the thickness of the first barrier metal film 31 is preferably 0.01 μm to 0.5 μm. Further, from the viewpoints of the flatness of the first barrier metal film 31 and increasing the amount of current flowing through the wiring 13, the thickness of the first barrier metal film 31 is preferably 0.001 μm to 0.3 μm. From the above, the thickness of the first barrier metal film 31 is most preferably 0.01 μm to 0.3 μm.

[0058] The second barrier metal film 32 is a conductive film for preventing the diffusion of the metal material in the wiring 13 into the second organic insulating layer 22, and is formed so as to cover the wiring 13. The second barrier metal film 32 contains at least one of, for example, titanium, nickel, palladium, chromium, tantalum, tungsten, cobalt, and gold as a metal material that is less likely to diffuse into the organic insulating layer. Note that the second barrier metal film 32 may be a laminate of different metal films.

[0059] The second barrier metal film 32 is preferably an electroplated film (e.g., electroless plating film) using the wiring 13 as a seed layer. Therefore, the second barrier metal film 32 is preferably a nickel plating film, a palladium plating film, a cobalt plating film, a gold plating film, or an alloy plating film containing at least one of nickel, palladium, cobalt, and gold. From the viewpoints of adhesion to the wiring 13 and temperature cycle resistance, a nickel plating film or a palladium plating film is preferable.

[0060] Examples of the nickel plating film include an electroless nickel-phosphorus alloy plating film containing phosphorus, an electroless nickel-boron alloy plating film containing boron, or an electroless nickel-nitrogen alloy plating film containing nitrogen. The nickel content of the nickel plating film is preferably 80% by mass or more. When the nickel content is 80% by mass or more, the effect of improving the insulation reliability of the organic interposer 10 by the second barrier metal film 32 is favorably exerted. From the viewpoint of insulation reliability, an electroless nickel-phosphorus alloy plating film is preferable as the nickel plating film.

[0061] From the viewpoint that good insulation reliability can be obtained with a thickness of 0.1 μm or less, the second barrier metal film 32 is preferably an electroless palladium plating film. Examples of the electroless palladium plating film include a substitution palladium plating film, an electroless palladium plating film using a formic acid compound as a reducing agent, a palladium-phosphorus alloy plating film using hypophosphorous acid or phosphorous acid as a reducing agent, or a palladium-boron alloy plating film using a boron compound.

[0062] The thickness of the second barrier metal film 32 is, for example, from 0.001 μm to 1 μm. From the perspective of the yield of the second barrier metal film 32, the thickness of the second barrier metal film 32 is preferably from 0.01 μm to 1 μm. Further, from the perspectives of improving the production tact, thinning, and temperature cycle resistance of the second barrier metal film 32, it is more preferably from 0.001 μm to 0.5 μm. From the perspectives of thinning the second barrier metal film 32 and the resolution of the photosensitive insulating resin, it is even more preferably from 0.001 μm to 0.3 μm. From the above perspectives, the thickness of the second barrier metal film 32 is most preferably from 0.01 μm to 0.3 μm.

[0063] The surface roughness Ra of the second barrier metal film 32 is affected by the surface roughness of the wiring 13 and is, for example, from 0.01 μm to 1 μm. When the surface roughness Ra of the second barrier metal film 32 is 0.01 μm or more, the adhesion between the second barrier metal film 32 and the second organic insulating layer 22 and the reliability such as temperature cycle resistance can be ensured. When the surface roughness Ra of the second barrier metal film 32 is 1 μm or less, disconnection in the organic interposer 10 caused by the unevenness generated during the formation of the second organic insulating layer 22 can be suppressed, and a decrease in the resolution of the organic insulation laminate 12 can be suppressed. From the perspective of adhesion to the second organic insulating layer 22, the surface roughness Ra of the second barrier metal film 32 is preferably 0.03 μm or more. From the perspective of temperature cycle resistance, the surface roughness Ra of the second barrier metal film 32 is preferably 0.5 μm or less. From the perspective of high-frequency characteristics, the surface roughness Ra of the second barrier metal film 32 is more preferably 0.1 μm or less. From the above perspectives, the surface roughness Ra of the second barrier metal film 32 is most preferably from 0.03 μm to 0.1 μm.

[0064] In the organic interposer 10, the surface roughness Ra of the surface of the combined first organic insulating layer 21 (i.e., the fourth organic insulating layer 24) and the second barrier metal film 32 is, for example, 0.01 μm to 1 μm. When the surface roughness Ra of the above surface is 0.01 μm or more, the adhesion between the first organic insulating layer 21 (and the second barrier metal film 32) and the second organic insulating layer 22 becomes good. Further, when the surface roughness of the above surface is 1 μm or less, warping of the organic insulating laminate 12 is suppressed, and for example, when the organic insulating laminate 12 is ground, wiring and the like can be easily exposed. The surface roughness Ra of the above surface is calculated, for example, by scanning a range of 100×100 μm including both the first organic insulating layer 21 and the second barrier metal film 32 using a laser microscope (manufactured by Olympus Corporation, "LEXT OLS3000").

[0065] The surface roughness Ra of the above surface of the combined first organic insulating layer 21 and the second barrier metal film 32 can be controlled by planarizing the wiring 13 and the first organic insulating layer 21. Examples of the planarization treatment for the above surface include chemical mechanical polishing (CMP: Chemical Mechanical Polishing) or flycut method. From the viewpoint of suppressing the occurrence of dishing in the wiring 13, it is preferable to use the flycut method. The flycut method is a method of physically grinding an object using a grinding device such as a surface planer.

[0066] The through-wiring 15 is a wiring embedded in the opening 12a of the organic insulating laminate 12 and functions as a connection terminal to an external device. The through-wiring 15 is composed of a plurality of wiring layers 15a to 15c laminated on each other. The wiring layer 15b includes a wiring layer formed simultaneously with the wiring 13 and a metal film formed simultaneously with the barrier metal film 14.

[0067] The surface wiring 16 is wiring for electrically connecting semiconductor chips mounted on the organic interposer 10. For this reason, both ends of the surface wiring 16 are exposed from the organic interposer 10, and the surface wiring 16 other than the both ends is embedded in the organic interposer 10 (more specifically, the second organic insulating layer 22). For this reason, the second organic insulating layer 22 includes at least two organic insulating layers.

[0068] Next, a method for manufacturing the organic interposer 10 according to the present embodiment will be described with reference to FIGS. 3 to 10. The organic interposer 10 formed by the following manufacturing method is particularly suitable, for example, in a form that requires miniaturization and multi-pinning. Note that FIG. 4(b) is an enlarged view of a part of FIG. 4(a). Similarly, each of FIGS. 5(b), 6(b), 7(b), 8(b), and 9(b) is an enlarged view of a part of the corresponding drawing.

[0069] First, as shown in FIG. 3(a) as the first step, a wiring layer 15a is formed on a substrate 11. The wiring layer 15a is formed by patterning a metal film formed on the substrate 11. In the first step, for example, the metal film is formed by a coating method, a physical vapor deposition method (PVD method) such as vacuum evaporation or sputtering, a printing method or a spraying method using a metal paste, or various plating methods. In the present embodiment, a copper foil is used as the metal film.

[0070] In addition, when a temporary fixing layer (not shown) is provided between the substrate 11 and the wiring layer 15a, the temporary fixing layer contains, for example, a resin containing a non-polar component such as polyimide, polybenzoxazole, silicon, or fluorine, a resin containing a component that expands in volume or foams by heating or UV (ultraviolet rays), a resin containing a component that undergoes a crosslinking reaction by heating or UV, or a resin that generates heat upon light irradiation. Examples of the method for forming the temporary fixing layer include spin coating, spray coating, or lamination. From the viewpoint of highly achieving both handleability and carrier peelability, it is preferable that the temporary fixing layer can be easily peeled by an external stimulus such as light or heat. From the viewpoint of being peelable so that the temporary fixing layer does not remain in the later-produced organic interposer 10, it is most preferable that the temporary fixing layer contains a resin that expands in volume by heat treatment.

[0071] When a temporary fixing layer is provided between the substrate 11 and the wiring layer 15a, the wiring layer 15a may be formed from the copper foil of a peelable copper foil. In this case, the substrate 11 corresponds to the support of the peelable copper foil, and the temporary fixing layer corresponds to the release layer of the peelable copper foil.

[0072] Next, as shown in FIG. 3(b) as the second step, a third organic insulating layer 23 is formed on the substrate 11 so as to cover the wiring layer 15a. In the second step, a film-shaped third organic insulating layer 23 containing a negative photosensitive insulating resin is attached to the substrate 11 to cover the wiring layer 15a. Then, exposure treatment, development treatment, or curing treatment, etc. is performed on the third organic insulating layer 23 as necessary.

[0073] Next, as shown in FIG. 3(c) as the third step, a first organic insulating layer 21 is formed by forming a fourth organic insulating layer 24 on the third organic insulating layer 23. In the third step, similar to the second step, a film-shaped fourth organic insulating layer 24 containing a negative photosensitive insulating resin is attached to the third organic insulating layer 23. Then, exposure treatment, development treatment, or curing treatment, etc. is performed on the fourth organic insulating layer 24 as necessary.

[0074] Next, as a fourth step, as shown in FIGS. 4(a) and 4(b), a plurality of groove portions 21a and opening portions 21b are formed in the first organic insulating layer 21 (also referred to as the first step). In the fourth step, for example, a plurality of groove portions 21a and opening portions 21b are formed by laser ablation, photolithography, or imprinting. From the viewpoints of miniaturization of the groove portions 21a and formation cost, it is preferable to apply photolithography. For this reason, a plurality of groove portions 21a are formed by subjecting the first organic insulating layer 21 to an exposure process and a development process. Further, the opening portions 21b are formed so as to expose the wiring layer 15a. When a photosensitive insulating resin is used for the first organic insulating layer 21, the pattern of the groove portions 21a can be formed in a short time and smoothly. For this reason, the wiring described later can have excellent high-frequency characteristics.

[0075] As a method of exposing the photosensitive insulating resin in the above photolithography, a known projection exposure method, contact exposure method, direct drawing exposure method, or the like can be used. Further, in order to develop the photosensitive insulating resin, for example, an alkaline aqueous solution such as sodium carbonate or TMAH may be used.

[0076] In the above fourth step, after forming a plurality of groove portions 21a and opening portions 21b, the first organic insulating layer 21 may be further heat-cured. In this case, for example, the heating temperature is set to 100 to 200°C, the heating time is set to 30 minutes to 3 hours, and the first organic insulating layer 21 is heat-cured.

[0077] Next, as a fifth step, as shown in FIGS. 5(a) and 5(b), a first barrier metal film 31 is formed on the first organic insulating layer 21 so as to cover the inner surface of the groove portion 21a (also referred to as the second step). In the fifth step, for example, the first barrier metal film 31 is formed by a coating method, a PVD method, a printing method or a spraying method using a metal paste, or various plating methods. In the case of the coating method, the first barrier metal film 31 is formed by coating a complex of palladium or nickel on the first organic insulating layer 21 and then heating it. When using a metal paste, the first barrier metal film 31 is formed by coating a paste containing metal particles such as nickel or palladium on the first organic insulating layer 21 and then sintering it. In the present embodiment, the first barrier metal film 31 is formed by sputtering, which is one of the PVD methods. Note that the first barrier metal film 31 is formed so as to cover the inner surface of the opening 21b as well.

[0078] Next, as a sixth step, as shown in FIGS. 6(a) and 6(b), a wiring layer 13A is formed on the first barrier metal film 31 so as to fill the groove portion 21a (also referred to as the third step). In the sixth step, for example, the wiring layer 13A is formed by a method using a metal paste or a plating method using the first barrier metal film 31 as a seed layer. The thickness of the wiring layer 13A is preferably 0.5 times to 3 times the thickness of the first organic insulating layer 21. When the thickness of the wiring layer 13A is 0.5 times or more, the increase in the surface roughness Ra of the wiring 13 formed in a subsequent process tends to be suppressed. Also, when the thickness of the wiring layer 13A is 3 times or less, the warpage of the wiring layer 13A is suppressed and it tends to adhere well to the first organic insulating layer 21. Note that the wiring layer 13A is formed so as to fill the opening 21b as well.

[0079] Next, as the seventh step, as shown in FIGS. 7(a) and 7(b), the wiring layer 13A is thinned so that the first organic insulating layer 21 is exposed (also referred to as the fourth step). In the seventh step, in the wiring layer 13A, the portion outside the groove portion 21a and the opening portion 21b, and in the first barrier metal film 31, the portion that does not cover the groove portion 21a or the opening portion 21b are removed, thereby exposing the first organic insulating layer 21 and thinning the wiring layer 13A. Thereby, the wiring 13 embedded in the groove portion 21a is formed. This thinning process may be a planarization process of the surface of the combined first organic insulating layer 21 and the wiring 13. In this case, the target portions of the wiring layer 13A and the first barrier metal film 31 are removed by CMP or the fly cut method, and the surface of the first organic insulating layer 21 is polished or ground to be planarized.

[0080] When CMP is used in the seventh step, as the slurry, for example, a slurry containing alumina generally used for resin polishing, a slurry containing hydrogen peroxide and silica used for polishing the first barrier metal film 31, and a slurry containing hydrogen peroxide and ammonium persulfate used for polishing the wiring layer 13A are used. From the viewpoints of reducing cost and controlling the surface roughness Ra to 0.01 μm to 1 μm, it is preferable to grind the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) using the slurry containing alumina. When CMP is used, there is a tendency to incur high costs. Also, when the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) are simultaneously planarized, dishing occurs in the wiring 13 due to the difference in polishing rate, and as a result, the flatness of the surface of the combined first organic insulating layer 21 and the wiring 13 tends to be greatly impaired. Therefore, from the viewpoint of setting the surface roughness Ra of the above surface to 0.03 μm to 0.1 μm, it is more preferable to grind the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) by the fly cut method using a surface planer.

[0081] Next, as the eighth step, as shown in FIGS. 8(a) and 8(b), a second barrier metal film 32 is formed so as to cover the wiring 13 which is the wiring layer 13A in the groove portion 21a (also referred to as the fifth step). In the eighth step, for example, the second barrier metal film 32 is formed by a PVD method, a method using a metal paste, or an electroplating method using the wiring 13 as a seed layer. From the viewpoint of selectively forming the second barrier metal film 32 on the wiring 13, it is preferable to form the second barrier metal film 32 by an electroplating method using the wiring 13 as a seed layer. Note that before the plating process, cleaning of the exposed first organic insulating layer 21 with an acid or a protective treatment with benzotriazole or the like may be performed. Note that through the eighth step, the wiring layer 15b provided on the wiring layer 15a is completed.

[0082] In the eighth step, preferably, in addition to being formed on the wiring 13, the second barrier metal film 32 is formed on a portion of the first barrier metal film 31 that contacts the side surface of the groove portion 21a. In this case, the wiring 13 can be covered without a gap by the first barrier metal film 31 and the second barrier metal film 32.

[0083] Next, as the ninth step, as shown in FIGS. 9(a) and 9(b), a second organic insulating layer 22 is formed on the first organic insulating layer 21 and the second barrier metal film 32 (also referred to as the sixth step). In the ninth step, a film-shaped second organic insulating layer 22 containing a negative photosensitive insulating resin is attached to the first organic insulating layer 21 and the second barrier metal film 32. The second organic insulating layer 22 may be the same film as the first organic insulating layer 21 or may be formed using a different photosensitive insulating resin. From the viewpoint of preventing diffusion of the metal constituting the wiring 13, it is preferable not to perform a development process on the second organic insulating layer 22.

[0084] Next, as the tenth step, as shown in FIG. 10(a), an opening 22a is formed in the second organic insulating layer 22. In the tenth step, the opening 22a is formed so as to expose the wiring layer 15b. The opening 22a is formed by, for example, photolithography or the like.

[0085] Next, as a 11th step, as shown in FIG. 10(b), a through-wiring 15 is formed by filling the opening 22a with a metal material to form a wiring layer 15c. In the 11th step, for example, the wiring layer 15c is formed by a PVD method or various plating methods. Examples of the metal material include copper, nickel, tin, and the like. After the 11th step, the organic interposer 10 shown in FIG. 2 is manufactured by forming a surface wiring 16 or the like. If a temporary fixing layer is provided, the organic interposer 10 may be peeled off from the substrate 11.

[0086] According to the organic interposer 10 having the configuration described above, the wiring 13, the first organic insulating layer 21, and the second organic insulating layer 22 are partitioned by the barrier metal film 14. Therefore, the diffusion of the metal material in the wiring 13 into the organic insulating laminate is suppressed by the barrier metal film 14. Therefore, since the short circuit between the plurality of wirings 13 through the diffused metal material can be suppressed, the insulation reliability of the organic interposer 10 can be improved.

[0087] The organic insulating laminate 12 includes a first organic insulating layer 21 having a plurality of groove portions 21a in which the wirings 13 are disposed, and a second organic insulating layer 22 laminated on the first organic insulating layer 21 so as to embed the wirings 13. Therefore, each of the plurality of wirings 13 has a shape along the groove portion 21a of the first organic insulating layer 21. Therefore, by forming a plurality of groove portions 21a having a fine width and interval, the fine wiring 13 can be easily formed.

[0088] The barrier metal film 14 includes a first barrier metal film 31 provided between the wiring 13 and the inner surface of the groove portion 21a, and a second barrier metal film 32 provided between the wiring 13 and the second organic insulating layer 22. Therefore, the diffusion of the metal material in the wiring 13 into the first organic insulating layer 21 is preferably suppressed by the first barrier metal film 31. Further, the diffusion of the metal material into the second organic insulating layer 22 is preferably suppressed by the second barrier metal film 32.

[0089] The first barrier metal film 31 contains at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. Since titanium, nickel, palladium, chromium, tantalum, tungsten, and gold are all difficult to diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, the insulation reliability of the organic interposer 10 can be further improved.

[0090] The second barrier metal film 32 may be an electroplated film. In this case, since the second barrier metal film 32 can be selectively formed on the wiring 13 in the groove portion 21a, the manufacturing process of the organic interposer 10 can be simplified. For example, a resist coating process, a sputtering process, a resist removal process, etc. for forming the second barrier metal film 32 can be omitted.

[0091] The second barrier metal film 32 may be a nickel electroplated film. In this case, the second barrier metal film 32 having good flatness can be easily formed. In addition, since nickel is difficult to diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, the insulation reliability of the organic interposer 10 can be suitably improved.

[0092] The second barrier metal film 32 may be a palladium electroplated film. In this case, the second barrier metal film 32 can be formed thinly. In addition, since palladium is difficult to diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, the insulation reliability of the organic interposer 10 can be suitably improved.

[0093] The thickness of the second barrier metal film 32 may be 0.001 μm or more and 1 μm or less. In this case, the diffusion of the metal material in the wiring 13 into the second organic insulating layer 22 is well suppressed by the second barrier metal film 32.

[0094] The surface roughness Ra of the second barrier metal film 32 may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film 32 can adhere well to the second organic insulating layer 22. Also, disconnection etc. in the organic interposer 10 due to the surface roughness of the second barrier metal film 32 can be suppressed.

[0095] The thickness of the first organic insulating layer 21 may be 1 μm or more and 10 μm or less. In this case, a plurality of groove portions 21a having a width and interval of 10 μm or less can be formed using the first organic insulating layer 21.

[0096] The first organic insulating layer 21 may be a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. In this case, groove portions 21a having a fine width and interval can be easily formed in the first organic insulating layer 21. In addition, since the moisture contained in the first organic insulating layer 21 can be reduced, it becomes difficult for the metal material to diffuse into the first organic insulating layer 21. Therefore, the insulation reliability of the organic interposer 10 can be improved.

[0097] According to the manufacturing method of the organic interposer 10 according to the present embodiment, by going through the fourth step to the sixth step, a first barrier metal film 31 can be formed between the inner surface of each groove portion 21a and the wiring layer 13A. Further, by going through the seventh step to the ninth step, a second barrier metal film 32 can be formed between the wiring 13 and the second organic insulating layer 22 in the stacking direction of the organic insulating layers. For this reason, the diffusion of the metal material in the wiring 13 into the first organic insulating layer 21 and the second organic insulating layer 22 is suppressed by the first barrier metal film 31 and the second barrier metal film 32. Therefore, since a short circuit between the plurality of wirings 13 via the diffused metal material can be suppressed, the insulation reliability of the organic interposer 10 can be improved.

[0098] In the sixth step, the wiring layer 13A may be formed by an electroplating method using the first barrier metal film 31 as a seed layer. In this case, the wiring layer 13A can be formed so that the first barrier metal film 31 is sandwiched between the first organic insulating layer 21 and the wiring layer 13A. Thereby, the diffusion of the metal material in the wiring layer 13A into the first organic insulating layer 21 is favorably suppressed.

[0099] In the eighth step, the second barrier metal film 32 may be formed by a plating method using the wiring 13 as a seed layer. In this case, for example, the second barrier metal film 32 can be selectively formed on the wiring 13 without using a resist or the like. Thereby, steps such as a resist formation step and a resist removal step can be omitted when forming the second barrier metal film 32, so that the manufacturing process of the organic interposer 10 can be simplified.

[0100] Note that the wiring 13 in the organic interposer 10 may be formed, for example, by a semi-additive method. The semi-additive method is a method in which a seed layer is formed, a resist having a desired pattern is formed on the seed layer, the exposed portion of the seed layer is thickened by an electrolytic plating method or the like, the resist is removed, and then the thin seed layer is etched to obtain a desired wiring. However, when the semi-additive method is applied, the damage applied to the wiring when etching the thin seed layer is large. In addition, it is difficult to ensure the adhesion strength of the wiring to the organic insulating layer. For this reason, when forming a fine wiring having a line width and a space width of 5 μm or less using the semi-additive method, for example, the yield of the organic interposer tends to be significantly reduced. Therefore, in the present embodiment, in order to suppress this reduction in yield, a trench method is adopted in which the groove portion 21a is provided in the first organic insulating layer 21 in the fourth step, and the wiring 13 is formed in the groove portion 21a.

[0101] As described above, the organic interposer and its manufacturing method according to an embodiment of the present disclosure have been described. However, the present disclosure is not limited to the above-described embodiment, and may be appropriately changed without departing from the gist thereof. For example, the cross-sectional shape of the groove portion 21a formed in the first organic insulating layer 21 is not limited to a substantially rectangular shape, and may be other shapes such as a substantially trapezoidal shape and a substantially semicircular shape.

[0102] In the above embodiment, the wiring 13, the wiring layers 15a to 15c, the first barrier metal film 31, the second barrier metal film 32, the surface wiring 16, etc. may each have a single-layer structure or may have a multilayer structure composed of a plurality of conductive layers.

[0103] In the above embodiment, the first organic insulating layer 21 includes both the third organic insulating layer 23 and the fourth organic insulating layer 24, but it is not limited thereto. For example, the first organic insulating layer 21 may have a single-layer structure. In this case, the second step and the third step in the above manufacturing method can be combined into one step, and the manufacturing process of the organic interposer 10 can be simplified.

[0104] In the seventh step of the manufacturing method in the above embodiment, a part of the wiring layer 13A (wiring 13) in the groove 21a may be removed, and in the subsequent eighth step, the second barrier metal film 32 may be formed so as to fill the groove 21a. In this case, since the second barrier metal film 32 is formed by being filled in the groove 21a, the formation of a step caused by the second barrier metal film 32 in the organic interposer 10 can be suppressed. That is, the surface roughness Ra of the surface of the combined second organic insulating layer 22 and the second barrier metal film 32 can be reduced. Thereby, a semiconductor element or the like can be satisfactorily mounted on the organic interposer 10. Note that the removal of a part of the wiring 13 in the groove 21a utilizes, for example, dishing that occurs when performing CMP. Further, a part of the wiring 13 in the groove 21a is, for example, at least a part of the wiring 13 located in the upper half of the groove 21a.

[0105] In the above embodiment, the organic insulating layer included in the organic insulating laminate 12 may contain an adhesion promoter. Examples of the adhesion promoter include a silane coupling agent, a triazole or tetrazole-based compound.

[0106] As a silane coupling agent, a compound having a nitrogen atom is preferably used in order to improve the adhesion to a metal. Specifically, N-2-(aminoethyl)-3-aminopropylmethyldimethoxysilane, N-2-(aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-triethoxysilyl-N-(1,3-dimethyl-butylidene)propylamine, N-phenyl-3-aminopropyltrimethoxysilane, tris-(trimethoxysilylpropyl)isocyanurate, 3-ureidopropyltrialkoxysilane, 3-isocyanatopropyltriethoxysilane, etc. may be mentioned. The amount of the above silane coupling agent used is preferably 0.1 part by mass to 20 parts by mass with respect to 100 parts by mass of the compound having a phenolic hydroxyl group, from the viewpoints of the effect by addition, heat resistance, production cost, etc.

[0107] Examples of the triazole compound include 2-(2'-hydroxy-5'-methylphenyl)benzotriazole, 2-(2'-hydroxy-3'-tert-butyl-5'-methylphenyl)-5-chlorobenzotriazole, 2-(2'-hydroxy-3',5'-di-tert-amylphenyl)benzotriazole, 2-(2'-hydroxy-5'-tert-octylphenyl)benzotriazole, 2,2'-methylenebis[6-(2H-benzotriazol-2-yl)-4-tert-octylphenol], 6-(2-benzotriazolyl)-4-tert-octyl-6'-tert-butyl-4'-methyl-2,2'-methylenebisphenol, 1,2,3-benzotriazole, 1-[N,N-bis(2-ethylhexyl)aminomethyl]benzotriazole, carboxybenzotriazole, 1-[N,N-bis(2-ethylhexyl)aminomethyl]methylbenzotriazole, 2,2'-[[(methyl-1H-benzotriazol-1-yl)methyl]imino]bisethanol, etc.

[0108] Examples of tetrazole compounds include 1H-tetrazole, 5-amino-1H-tetrazole, 5-methyl-1H-tetrazole, 5-phenyl-1H-tetrazole, 1-methyl-5-ethyl-1H-tetrazole, 1-methyl-5-mercapto-1H-tetrazole, 1-phenyl-5-mercapto-1H-tetrazole, 1-(2-dimethylaminoethyl)-5-mercapto-1H-tetrazole, 2-methoxy-5-(5-trifluoromethyl-1H-tetrazol-1-yl)-benzaldehyde, 4,5-di(5-tetrazolyl)-[1,2,3]triazole, 1-methyl-5-benzoyl-1H-tetrazole, and the like. From the viewpoints of the effects of addition, heat resistance, and production cost, the amount of the above triazole or tetrazole-based compound used is preferably 0.1 part by mass to 20 parts by mass with respect to 100 parts by mass of the compound having a phenolic hydroxyl group.

[0109] The above silane coupling agent, triazole-based compound, and tetrazole-based compound may each be used alone or in combination.

[0110] Furthermore, an ion scavenger may be added to the organic insulating layer. By adsorbing ionic impurities in the organic insulating layer with the above ion scavenger, the insulation reliability during moisture absorption can be improved. Examples of such ion scavengers include compounds known as copper corrosion inhibitors for preventing the ionization and dissolution of copper, such as triazine thiol compounds and phenolic reducing agents, and inorganic compounds such as powdery bismuth-based, antimony-based, magnesium-based, aluminum-based, zirconium-based, calcium-based, titanium-based, and tin-based, as well as mixed systems thereof.

[0111] Examples of the above ion scavenger include inorganic ion scavengers manufactured by Toagosei Co., Ltd. (trade names: IXE-300 (antimony-based), IXE-500 (bismuth-based), IXE-600 (antimony and bismuth mixed system), IXE-700 (magnesium and aluminum mixed system), IXE-800 (zirconium-based), and IXE-1100 (calcium-based)). These may be used alone or in combination of two or more. The amount of the ion scavenger used is preferably 0.01 to 10 parts by mass with respect to 100 parts by mass of the compound having a phenolic hydroxyl group, from the viewpoints of the effect by addition, heat resistance, and production cost, etc.

Examples

[0112] The present invention will be described in more detail by the following examples, but the present invention is not limited to these examples.

[0113] (Example 1) The measurement and evaluation samples shown in FIGS. 11(a) and (b) were prepared as follows. First, a photosensitive insulating resin film 52 with a thickness of 5 μm was attached to a silicon wafer 51 with a thickness of 150 mm. This photosensitive insulating resin film 52 was formed as follows. First, a cresol novolak resin (manufactured by Asahi Organic Chemical Industry Co., Ltd., trade name: TR-4020G, 100 parts by mass), 1,3,4,6-tetrakis(methoxymethyl) glycoluril (30 parts by mass), trimethylolpropane triglycidyl ether (40 parts by mass), a triarylsulfonium salt (manufactured by San-Apro Ltd., trade name: CPI-310B, 8 parts by mass), and methyl ethyl ketone (100 parts by mass) were blended to obtain a photosensitive insulating composition. Next, the obtained photosensitive insulating composition was applied to a polyethylene terephthalate film (manufactured by Teijin DuPont Films Ltd., trade name: A-53) and dried in an oven at 90°C for 10 minutes to obtain a photosensitive insulating resin film 52 with a thickness of 5 μm.

[0114] Next, the photosensitive insulating resin film 52 attached to the silicon wafer 51 was sequentially subjected to exposure treatment, heat treatment, development treatment, and heat curing treatment. Next, a photosensitive insulating resin film 53 with a thickness of 5 μm formed in the same manner as the film 52 was attached to the photosensitive insulating resin film 52. Next, the attached photosensitive insulating resin film 53 was exposed through a photomask, and then subjected to heat treatment, development treatment, and heat curing treatment in sequence. As a result, the photosensitive insulating resin film 53 was patterned to form a first groove portion 53a and a second groove portion 53b that are comb-shaped and engage with each other, a first connection portion 53c that connects the first groove portions 53a, and a second connection portion 53d that connects the second groove portions 53b. The width of the first groove portion 53a and the width of the second groove portion 53b were each set to 10 μm. These widths correspond to the line width L of the wiring described later. Also, the distance (space width S) between the adjacent first groove portion 53a and the second groove portion 53b was set to 10 μm, and the length of each groove was set to 1 mm.

[0115] Next, a barrier metal film 54 containing titanium with a thickness of 0.05 μm was formed on the photosensitive insulating resin film 53 by sputtering. Next, a copper layer was formed by electrolytic plating using the barrier metal film 54 as a seed layer so as to fill the first groove portion 53a, the second groove portion 53b, the first connection portion 53c, and the second connection portion 53d. Next, a part of the copper layer and a portion of the barrier metal film 54 that does not cover the inner surfaces of the first groove portion 53a, the second groove portion 53b, the first connection portion 53c, and the second connection portion 53d were ground by a fly cut method using a surface planer. As a result, a first wiring 55a filled in the first groove portion 53a, a second wiring 55b filled in the second groove portion 53b, a first connection wiring 55c filled in the first connection portion 53c, and a second connection wiring 55d filled in the second connection portion 53d were formed. As the surface planer, an automatic surface planer (manufactured by DISCO Corporation, trade name "DAS8930") was used. Also, in the grinding by the fly cut method, the feed rate was set to 1 mm / s, and the spindle rotation speed was set to 2000 min -1 to set.

[0116] Next, a barrier metal film 56 containing a nickel-phosphorus alloy with a thickness of 0.2 μm was formed by electroless plating using the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d as seed layers, respectively. Next, a photosensitive insulating resin film 57 with a thickness of 5 μm formed in the same manner as the photosensitive insulating resin film 52 was attached so as to expose at least a part of the first connection wiring 55c and a part of the second connection wiring 55d. Next, the attached photosensitive insulating resin film 57 was subjected to exposure treatment, heat treatment, development treatment, and thermosetting treatment in order. Thereby, the measurement and evaluation sample 50 shown in FIGS. 11(a) and (b) was formed. In this measurement and evaluation sample 50, the first wiring 55a and the first connection wiring 55c are connected to each other and covered with the barrier metal films 54 and 56. Similarly, the second wiring 55b and the second connection wiring 55d are connected to each other and covered with the barrier metal films 54 and 56. Further, the first wiring 55a and the first connection wiring 55c, and the second wiring 55b and the second connection wiring 55d are insulated from each other by the photosensitive insulating resin films 52, 53, and 57.

[0117] In order to confirm the insulation reliability of the above-described measurement and evaluation sample 50, a highly accelerated stress test (HAST) described below was performed. In this test, a voltage of 3.3 V was applied to the first connection wiring 55c and the second connection wiring 55d under the conditions of 85% humidity and 130° C., and the sample was left standing for a predetermined time. Thereby, the change in the insulation between the first wiring 55a and the second wiring 55b over time was measured. In this test, if the resistance value between the first wiring 55a and the second wiring 55b is 1×10 6 Ω or more after 200 hours from the start of the test, it was evaluated as A, and if it was less than 1×10 6 Ω before 200 hours from the start of the test, it was evaluated as B. The results of the highly accelerated stress test of Example 1 are shown in Table 1 below.

[0118] (Example 2) A measurement and evaluation sample 50 was formed in the same manner as in Example 1 except that the line width L and the space width S were set to 5 μm, and the above-described high-acceleration life test was performed. The results of the high-acceleration life test of Example 2 are shown in Table 1 below.

[0119] (Example 3) A measurement and evaluation sample 50 was formed in the same manner as in Example 1 except that the line width L and the space width S were set to 2 μm, and the above-described high-acceleration life test was performed. The results of the high-acceleration life test of Example 3 are shown in Table 1 below.

[0120] (Example 4) A measurement and evaluation sample 50 was formed in the same manner as in Example 2 except that the photosensitive insulating resin film 57 was a solder resist film (manufactured by Hitachi Chemical Co., Ltd., trade name: FZ-2700GA, thickness 30 μm). The above-described high-acceleration life test was performed on this measurement and evaluation sample 50. The results of the high-acceleration life test of Example 4 are shown in Table 1 below.

[0121] (Example 5) A measurement and evaluation sample 50 was formed in the same manner as in Example 3 except that the photosensitive insulating resin film 57 was a solder resist film (manufactured by Hitachi Chemical Co., Ltd., trade name: FZ-2700GA, thickness 30 μm). The above-described high-acceleration life test was performed on this measurement and evaluation sample 50. The results of the high-acceleration life test of Example 5 are shown in Table 1 below.

[0122] (Comparative Example 1) As shown in FIGS. 12(a) and (b), a measurement and evaluation sample 50A was formed in the same manner as in Example 1 except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d. That is, the measurement and evaluation sample 50A was formed such that the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d were in contact with the photosensitive insulating resin film 57. The above-described high-acceleration life test was performed on this measurement and evaluation sample 50A. The results of the high-acceleration life test of Comparative Example 1 are shown in Table 1 below.

[0123] (Comparative Example 2) A measurement and evaluation sample 50A was formed in the same manner as in Example 2, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d. The above-described high-acceleration life test was performed on this measurement and evaluation sample 50A. The results of the high-acceleration life test for Comparative Example 2 are shown in Table 1 below.

[0124] (Comparative Example 3) A measurement and evaluation sample 50A was formed in the same manner as in Example 3, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d. The above-described high-acceleration life test was performed on this measurement and evaluation sample 50A. The results of the high-acceleration life test for Comparative Example 3 are shown in Table 1 below.

[0125] (Comparative Example 4) A measurement and evaluation sample 50A was formed in the same manner as in Example 4, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d. The above-described high-acceleration life test was performed on this measurement and evaluation sample 50A. The results of the high-acceleration life test for Comparative Example 4 are shown in Table 1 below.

[0126] (Comparative Example 5) A measurement and evaluation sample 50A was formed in the same manner as in Example 5, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connection wiring 55c, and the second connection wiring 55d. The above-described high-acceleration life test was performed on this measurement and evaluation sample 50A. The results of the high-acceleration life test for Comparative Example 5 are shown in Table 1 below.

[0127] [Table 1]

[0128] In Table 1 above, when the barrier metal film 56 is provided, it is indicated as "Y", and when the barrier metal film 56 is not provided, it is indicated as "N". Also in Table 1 above, when the photosensitive insulating resin film 57 is formed in the same manner as the photosensitive insulating resin film 52, it is indicated as "α", and when the photosensitive insulating resin film 57 is formed using a solder resist film, it is indicated as "β". From Table 1, the results of the high-acceleration life tests for Examples 1 to 5 were all evaluated as A, while the results of the high-acceleration life tests for Comparative Examples 1 to 5 were all evaluated as B. From these results, it was found that the insulation reliability of the measurement and evaluation samples differed significantly depending on the presence or absence of the barrier metal film 56.

[0129] FIG. 13(a) is a graph showing the results of the high-acceleration life tests for Example 2 and Comparative Example 2, and FIG. 13(b) is a graph showing the results of the high-acceleration life tests for Example 3 and Comparative Example 3. In FIGS. 13(a) and 13(b), the horizontal axis represents time, and the vertical axis represents the resistance value between the first wiring 55a and the second wiring 55b. In FIG. 13(a), data 61 is the test result of Example 2, and data 62 is the test result of Comparative Example 2. In FIG. 13(b), data 63 is the test result of Example 3, and data 64 is the test result of Comparative Example 3.

[0130] As shown in FIG. 13(a), in Example 2, even when 300 hours had elapsed since the start of the test, the resistance value between the first wiring 55a and the second wiring 55b was 1×10 6 Ω or more. On the other hand, in Comparative Example 2, the resistance value decreased rapidly at around 20 hours from the start of the test and became less than 1×10 6 Ω. Similarly, as shown in FIG. 13(b), in Example 3, even when 200 hours had elapsed since the start of the test, the resistance value between the first wiring 55a and the second wiring 55b was 1×10 6 Ω or more, while in Comparative Example 3 , the resistance value decreased rapidly at around several hours from the start of the test and became less than 1×10 6 Ω.

[0131] Figures 14(a) to (c) show the results of analyzing the components of copper, titanium, and nickel in the cross-sectional sample of the measurement and evaluation sample 50 after 250 hours of the curing speed life test of Example 3 using TEM (transmission electron microscope) / EDX (energy dispersive X-ray analyzer). Figure 14(a) shows the analysis result of Cu (copper) in the cross-sectional sample of the measurement and evaluation sample 50, Figure 14(b) shows the analysis result of Ti (titanium) in the cross-sectional sample, and Figure 14(c) shows the analysis result of Ni (nickel) in the cross-sectional sample. JEM-2100F manufactured by JEOL Ltd. was used as the TEM, and JED-2300 manufactured by JEOL Ltd. was used as the EDX. The acceleration voltage was set to 200 kV, and the above analysis was performed. In Example 3, no elution of the wiring and the barrier metal into the photosensitive insulating resin film was observed after the EDX analysis test. Specifically, no diffusion of copper constituting the copper layer surrounded by the barrier metal films 54 and 56 into the photosensitive insulating resin film, no diffusion of titanium constituting the barrier metal film 54 into the photosensitive insulating resin film, and no diffusion of nickel constituting the barrier metal film 56 into the photosensitive insulating resin film were confirmed.

[0132] When the measurement and evaluation samples 50A of Comparative Examples 2 and 3 after the high-acceleration life test were visually inspected, it was confirmed that in Comparative Examples 2 and 3, at least the photosensitive insulating resin film 57 was contaminated due to some factor. On the other hand, when the measurement and evaluation samples 50 of Examples 2 and 3 after the high-acceleration life test were visually inspected, no contamination of the photosensitive insulating resin films 52, 53, and 57 was confirmed.

[0133] From the above, it is presumed that the rapid decrease in the resistance value in Comparative Examples 2 and 3 is because the metal material in the first wiring 55a and the second wiring 55b diffused into the photosensitive insulating resin film 57, and the first wiring 55a and the second wiring 55b were short-circuited through the diffused metal material. On the other hand, in Examples 2 and 3, it is presumed that the diffusion of the metal material in the first wiring 55a or the second wiring 55b into the photosensitive insulating resin films 52, 53, and 57 was prevented by the barrier metal films 54 and 56, and the first wiring 55a and the second wiring 55b were not short-circuited.

Explanation of Reference Numerals

[0134] 1… Substrate, 2A~2D… Semiconductor chips, 3A, 3B… Underfill, 4… Insulating material, 10… Organic interposer, 11… Substrate, 12… Organic insulating laminate, 13… Wiring, 13A… Wiring layer, 14… Barrier metal film, 15… Through-wiring, 21… First organic insulating layer, 21a… Groove portion, 21b… Opening portion, 22… Second organic insulating layer, 31… First barrier metal film, 32… Second barrier metal film, 100… Semiconductor package, L… Line width, S… Space width.

Claims

1. An organic insulating layer, Wiring disposed within the organic insulating layer, A first barrier conductive film that partitions the wiring and the organic insulating layer, A second barrier conductive film positioned on the wiring, and comprising: At least a part of the second barrier conductive film is located above the organic insulating layer, A substrate for a semiconductor package, wherein at least a part of the top surface of the first barrier conductive film is exposed from the organic insulating layer, the wiring, and the second barrier conductive film.

2. The organic insulating layer is provided with an opening for accommodating the wiring, The substrate for a semiconductor package according to claim 1, wherein the first barrier conductive film is provided between an inner surface of the opening and the wiring.

3. Further comprising a through-wiring that penetrates the organic insulating layer and includes the wiring, the first barrier conductive film, and the second barrier conductive film, The substrate for a semiconductor package according to claim 1 or 2.

4. The substrate for a semiconductor package according to any one of claims 1 to 3, which is a build-up substrate, a substrate for a wafer-level package, a coreless substrate, or a substrate in which a semiconductor chip is encapsulated or embedded.

5. The substrate for a semiconductor package according to any one of claims 1 to 4, including an organic interposer having the organic insulating layer, the wiring, the first barrier conductive film, and the second barrier conductive film.

6. A first step of preparing an organic insulating layer having a plurality of groove portions and openings, A second step of forming a first barrier conductive film that covers a surface of the organic insulating layer, an inner surface of the groove portion, and an inner surface of the opening, A third step of forming a wiring layer on the first barrier conductive film so as to fill the groove portion and the opening, A fourth step of thinning the wiring layer so that the organic insulating layer is exposed, A fifth step of forming a second barrier conductive film that covers an exposed portion of the wiring layer remaining in the groove portion, and comprising: At least a part of the second barrier conductive film is located above the organic insulating layer, At least a part of the top surface of the first barrier conductive film is exposed from the organic insulating layer, the wiring layer, and the second barrier conductive film, A method for manufacturing a substrate for a semiconductor package.

7. In the third step, the wiring layer is formed by an electroplating method using the first barrier conductive film as a seed layer, the method for manufacturing a substrate for a semiconductor package according to claim 6.

8. The manufacturing method of a substrate for a semiconductor package according to claim 6 or 7, wherein in the fifth step, the second barrier conductive film is formed by a plating method using the wiring layer as a seed layer.

9. The manufacturing method of a substrate for a semiconductor package according to any one of claims 6 to 8, wherein in the fourth step, the surface of the organic insulating layer is polished or ground.

Images