Semiconductor device

Abstract

To provide a semiconductor device in which the arrangement area of a transistor can be smaller.SOLUTION: The semiconductor device has a first transistor with a first oxide semiconductor film and a second transistor with a second oxide semiconductor film on a substrate. When the oxide semiconductor films are subjected to an electron-beam diffraction, the first oxide semiconductor film is larger than the second oxide semiconductor film in the ratio of the integrated intensity of the luminance in a diffraction spot due to a C-axial orientation and the integrated intensity of the luminance in a diffraction spot due to orientations in all directions. The semiconductor device also has a part of the first transistor between the second transistor and the substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having an oxide semiconductor film and a display device having the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification or the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, etc.), and an electronic device may have a semiconductor device.

Background Art

[0004] Techniques for forming a transistor (also referred to as a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). As a semiconductor thin film applicable to a transistor, semiconductor materials represented by silicon are widely known, but oxide semiconductors are attracting attention as other materials. ​​​​​​​​​​​It has been done.

[0005] For example, in Patent Document 1, a first transistor using an oxide semiconductor film and an oxide semiconductor By laminating a second transistor using a film, a plurality of memory cells are provided in a stacked manner Thereby, a technique for reducing the cell area is disclosed.

[0006] Further, in Patent Document 2, a pixel portion having a plurality of two-dimensionally arranged pixels and a plurality of pixels are represented It includes a driving circuit portion for driving, a first layer including the driving circuit portion, and a second layer including the pixel portion. By laminating the layers, a technique for reducing the arrangement space of the driving circuit portion in the peripheral region of the pixel portion is disclosed. It has been disclosed.

Prior Art Documents

Patent Documents

[0007] [[ID=z8]]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] As shown in Patent Documents 1 and 2, by stacking a plurality of transistors, the arrangement Area can be reduced. On the other hand, when stacking a plurality of transistors, there is a problem that the number of masks Or the number of processes increases.

[0009] In view of the above problems, in a semiconductor device in which a plurality of transistors are stacked, one aspect of the present invention Is to provide a semiconductor device with a small increase in the number of masks or the number of processes as one of the problems Or, one aspect of the present invention is a semiconductor that can reduce the layout area of transistors. Or, one aspect of the present invention aims to provide a semiconductor device. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with reduced manufacturing costs. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0010] Note that the description of the above problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Other problems than the above are obvious from the description in the specification and the like, and it is possible to extract other problems than the above from the description in the specification and the like.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device including a first transistor and a second transistor on a substrate. The first transistor has a first oxide semiconductor film, the second transistor has a second oxide semiconductor film, and the first transistor has an interlayer film. The first oxide semiconductor film has a first metal oxide film including a first crystal part and a second crystal part. The first crystal part has a c-axis orientation, and the second crystal part has a lower c-axis orientation than the first crystal part. When electron beam diffraction measurement is performed on a cross-section of the first metal oxide film and an electron beam diffraction pattern is observed, the electron beam diffraction pattern has a first region having diffraction spots caused by the first crystal part and a second region having diffraction spots caused by the second crystal part. The second oxide semiconductor film has a second metal oxide film including a third crystal part and a fourth crystal part.

[0012] The first oxide semiconductor film has a first metal oxide film having a first crystal part and a second crystal part. The first crystal part has a c-axis orientation, and the second crystal part has a lower c-axis orientation than the first crystal part. When electron beam diffraction measurement is performed on the cross-section of the first metal oxide film and the electron beam diffraction pattern is observed, the electron beam diffraction pattern has a first region having diffraction spots caused by the first crystal part and a second region having diffraction spots caused by the second crystal part. The first crystal part has a c-axis orientation, and the second crystal part has a lower c-axis orientation than the first crystal part. When electron beam diffraction measurement is performed on the cross-section of the first metal oxide film and the electron beam diffraction pattern is observed, the electron beam diffraction pattern has a first region having diffraction spots caused by the first crystal part and a second region having diffraction spots caused by the second crystal part. When the electron beam diffraction pattern is observed, the electron beam diffraction pattern has a first region having diffraction spots caused by the first crystal part and a second region having diffraction spots caused by the second crystal part. The second oxide semiconductor film has a second metal oxide film having a third crystal part and a fourth crystal part. ​ has an oxide film, the third crystal part has c-axis orientation, and the fourth crystal part has a lower c-axis orientation than the third crystal part. When the second metal oxide film is subjected to electron beam diffraction measurement on the cross section and the electron beam diffraction pattern is observed, the electron beam diffraction pattern has a third region having diffraction spots resulting from the third crystal part and a fourth region having diffraction spots resulting from the fourth crystal part. The ratio of the integrated intensity of the luminance in the first region to the integrated intensity of the luminance in the second region of the first oxide semiconductor film is larger than the ratio of the integrated intensity of the luminance in the third region to the integrated intensity of the luminance in the fourth region of the second oxide semiconductor film. In the above configuration, it is preferable that the source electrode or the drain electrode of the first transistor has a region sandwiched between the substrate and the second oxide semiconductor film. In the above configuration, it is preferable that the first oxide semiconductor film has a region sandwiched between the substrate and the second oxide semiconductor film. In the above configuration, it is preferable that the interlayer film has a region sandwiched between the substrate and the second oxide semiconductor film.

[0013] In the above configuration, the ratio of the number of atoms of In, M, and Zn in the oxide semiconductor film is in the vicinity of In:M:Zn = 4:2:3. When In is 4, M is preferably 1.5 or more and 2.5 or less, and Zn is preferably 2 or more and 4 or less. The ratio of the number of atoms of In, M, and Zn may be different between the first oxide semiconductor film and the second oxide semiconductor film.

[0014]

[0015]

[0016]

[0017] ​​​​​​​​​​​​

[0018] In the above configuration, the field-effect mobility in the saturation region is preferably such that the field-effect mobility of the second transistor is greater than that of the first transistor. In the above configuration, the Id-Vg characteristics of the transistor are preferably measured with the voltage applied to the gate electrode in the range of 3V or more and 10V or less, and the voltage applied to the drain region in the range of 10V or more and 20V or less.

[0019] Another aspect of the present invention is a display device including the semiconductor device according to any one of the above configurations and a light-emitting element.

[0020] Another aspect of the present invention is a display module including the display device and a touch sensor. Another aspect of the present invention is an electronic device including the semiconductor device, the display device, or the display module according to any one of the above aspects, and an operation key or a battery.

Advantages of the Invention

[0021] According to one aspect of the present invention, in a semiconductor device in which a plurality of transistors are stacked, a semiconductor device with a small increase in the number of masks or the number of processes can be provided. Or, according to one aspect of the present invention, in a semiconductor device in which a plurality of transistors having an oxide semiconductor film are stacked, a highly reliable semiconductor device can be provided. Or, according to one aspect of the present invention, in a semiconductor device in which a plurality of transistors having an oxide semiconductor film are stacked, a semiconductor device with reduced manufacturing cost can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0022] ​​​​​​​ Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to have all of these effects. Other effects can be readily apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0023]

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Embodiments for Carrying Out the Invention

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description content of the following embodiments.

[0025] Also, in the drawings, there are cases where the size, layer thickness, or area is exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings show ideal examples in a schematic manner and are not limited to the shapes or values shown in the drawings.

[0026] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are added to avoid confusion of components, and it should be noted that they do not numerically limit.

[0027] Also, in this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0028] Also, in this specification and the like, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals. And between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), it has a channel region, and current can flow between the source and the drain through the channel region. In this specification etc., the channel region refers to the region through which current mainly flows.

[0029] Also, the functions of the source and the drain may be interchanged when different polarity transistors are adopted, or when the direction of current changes in circuit operation. Therefore, in this specification etc., the terms of the source and the drain can be used interchangeably.

[0030] Also, in this specification etc., "electrically connected" includes the case of being connected through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0031] Also, in this specification etc., "parallel" refers to a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0032] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0033] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the on state (also known as the non-conducting state or cut-off state). , Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, Vg When s is lower than the threshold voltage Vth, in a p-channel transistor, the gate and source This refers to the state in which the voltage Vgs between the gates is higher than the threshold voltage Vth. For example, The off-state current of a transistor is the voltage between the gate and source, Vgs, and the threshold voltage, Vth. It may refer to the drain current when the voltage is lower than

[0034] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows in the off state at a given Vgs. Off-state or sufficiently reduced off-current at Vgs within a given range It may refer to the off-state current in the off state at Vgs, etc.

[0035] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vgs The drain current at -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0036] In this specification and the like, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per a given channel width (for example, 1 μm). In the latter case, the unit of the off-state current is the current / length dimension. It may be expressed in units with a constant value (e.g., A / μm).

[0037] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off voltage is measured at room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device including the transistor is used (for example, For example, it may refer to the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less, which means that the There may be a case where there is a value of Vgs such that the off-current of the transistor becomes I or less at a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or at a temperature (for example, any one of 5°C to 35°C) at which the semiconductor device including the transistor is used.

[0038] The off-current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-current may represent the off-current at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Or it may represent the off-current at Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or the off-current at Vds used in the semiconductor device including the transistor. When it is said that the off-current of the transistor is I or less, it may mean that there is a value of Vgs such that the off-current of the transistor at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or Vds used in the semiconductor device including the transistor becomes I or less.

[0039] In the above description of the off-current, the drain and the source may be read as each other. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state.

[0040] Also, in this specification etc., in the same meaning as the off-current, it may be described as the leakage current. Also ​​​​​​​​​​​​​, in this specification and the like, the off-current refers to, for example, the current flowing between the source and the drain when the transistor is in the off state. It may refer to the current flowing between the source and the drain.

[0041] Also, in this specification and the like, the threshold voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor may refer to the gate voltage (Vg) on the horizontal axis and the square root of the drain current (Id) on the vertical axis. In the plotted curve (Vg-√Id characteristic), it refers to the gate voltage (Vg) at the intersection of the straight line obtained by extrapolating the tangent line with the maximum slope and the square root of the drain current (Id) being 0 (Id = 0 A). Alternatively, the threshold voltage of a transistor may refer to the gate voltage (Vg) when the value of Id [A] × L [μm] / W [μm] is 1×10 [A]. In the plotted curve (Vg-√Id characteristic), it refers to the gate voltage (Vg) at the intersection of the straight line obtained by extrapolating the tangent line with the maximum slope and the square root of the drain current (Id) being 0 (Id = 0 A). It may refer to the gate voltage (Vg) at the intersection of the straight line obtained by extrapolating the tangent line with the maximum slope and the square root of the drain current (Id) being 0 (Id = 0 A). Alternatively, the threshold voltage of a transistor may refer to the gate voltage (Vg) when the value of Id [A] × L [μm] / W [μm] is 1×10 [A]. Taking the channel length as L and the channel width as W, it may refer to the gate voltage (Vg) when the value of Id [A] × L [μm] / W [μm] is 1×10 -9 [A]. It may refer to the gate voltage (Vg).

[0042] Also, in this specification and the like, even when it is described as "semiconductor", for example, when the conductivity is extremely low, it may have the characteristics of an "insulator". Also, the boundary between "semiconductor" and "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification and the like may be paraphrased as "insulator". Similarly, the "insulator" described in this specification and the like may be paraphrased as "semiconductor". Or The "insulator" described in this specification and the like may be paraphrased as "semi-insulator". The boundary between "semiconductor" and "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification and the like may be paraphrased as "insulator". Similarly, the "insulator" described in this specification and the like may be paraphrased as "semiconductor". Or The "insulator" described in this specification and the like may be paraphrased as "semi-insulator". The "insulator" described in this specification and the like may be paraphrased as "semi-insulator". Or the "insulator" described in this specification and the like may be paraphrased as "semi-insulator".

[0043] Also, in this specification and the like, even when it is described as "semiconductor", for example, when the conductivity is extremely high, it may have the characteristics of a "conductor". Also, the boundary between "semiconductor" and "conductor" is ambiguous and may not be strictly distinguishable. The boundary with the "electrical conductor" may be ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification, etc. may be paraphrased as an "electrical conductor" in some cases. Similarly, the "electrical conductor" described in this specification, etc. may be paraphrased as a "semiconductor" in some cases.

[0044] In addition, in this specification, etc., impurities in a semiconductor refer to components other than the main component constituting the semiconductor film. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may decrease, and the crystallinity may decrease, etc. may occur. When the semiconductor has an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., and particularly hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen etc. In the case of an oxide semiconductor, for example, oxygen deficiency may be formed by the incorporation of impurities such as hydrogen. Also, when the semiconductor has silicon, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group but excluding oxygen and hydrogen, Group 15 elements, etc.

[0045]

[0045] In addition, in this specification, etc., a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the Metal oxides may be referred to as oxide semiconductors. That is, when described as an OS FET it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor .

[0046] Also, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides (metal oxi de). Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride (met al oxynitride).

[0047] Also, in this specification and the like, there are cases where CAAC (c-axis aligned crystal ) and CAC (Cloud-Aligned Composite) are described . Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or the composition of a material .

[0048] An example of the crystal structure of an oxide semiconductor or a metal oxide will be described. In the following, I n-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be used, and an oxide semiconductor formed by sputtering will be described as an example. Using the above target with the substrate temperature being 100°C or higher and 130°C or lower, an oxide semiconductor formed by sputtering is called sIGZO, and using the above target with the substrate temperature being room temperature (R.T.), an oxide semiconductor formed by sputtering is called tIGZO . For example, sIGZO has a crystal structure of either nc (nano crystal) and / or CAAC . Also, tIGZO has a crystal structure of nc . Note that the room temperature (R.T.) referred to here includes the temperature when the substrate is not intentionally heated

[0049] In addition, in this specification and the like, CAC-OS or CAC-metal oxide refers to having the function of a conductor in part of the material and the function of a dielectric (or insulator) in part of the material and having the function of a semiconductor as a whole. When CAC-OS or CAC-me tal oxide is used for the active layer of a transistor, the conductor has the function of allowing carriers electrons (or holes) to flow, and the dielectric has the function of not allowing carriers electrons to flow By causing the function as a conductor and the function as a dielectric to act complementarily respectively, a switching function (On / Off function) can be imparted to CAC-OS or C AC-metal oxide. In CAC-OS or CAC-m etal oxide, by separating each function, both functions can be enhanced to the maximum limit.

[0050] In addition, in this specification and the like, CAC-OS or CAC-metal oxide has a conductive region and a dielectric region. The conductor region has the function of the above-described conductor, and the dielectric region has the function of the above-described dielectric. Also, in the material, the conductor region and the dielectric region may be separated at the nanoparticle level. Also, the conductor region and the dielectric region may be unevenly distributed in the material, respectively. Also, the conductor region may be observed to be connected in a blurred cloud shape around the periphery.

[0051] That is, CAC-OS or CAC-metal oxide is a matrix composite (matrix composite), or a metal matrix composite (metal It can also be referred to as a "matrix composite".

[0052] Also, in CAC-OS or CAC-metal oxide, the conductor region and the dielectric region may be dispersed in the material at sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0053] (Embodiment 1) In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 1 to 23.

[0054] <1-1. Configuration Example 1 of Semiconductor Device> Cross-sectional views of semiconductor devices 100A, 100B, 100C, and 100D according to an aspect of the present invention are shown ( see FIGS. 1(A)(B) and 2(A)(B)). Semiconductor devices 100A, 100B, 100C and 100D each include a transistor Tr1 and a transistor Tr2.

[0055] The transistor Tr1 of the semiconductor device 100A is a top-gate type transistor, and the transistor Tr2 is a bottom-gate type transistor. The transistors Tr1 and Tr2 of the semiconductor device 100B are top-gate type transistors. The transistors Tr1 and Tr2 of the semiconductor device 100C are bottom-gate type transistors. The transistor Tr1 of the semiconductor device 100D is a bottom-gate type transistor, and the transistor Tr2 is a top-gate type transistor.

[0056] For any of the transistors Tr1 and Tr2 also has an oxide semiconductor film. Each of these oxide semiconductor films has a metal oxide containing In, M (M is Al, Ga, Y, or Sn), and Zn. As will be described in a later part the proportion of the crystalline part having c-axis orientation, the oxide semiconductor film of the transistor Tr1 is larger than the oxide semiconductor film of the transistor Tr2. That is, regardless of the shape of the transistor, the semiconductor device of one aspect of the present invention has an oxide semiconductor film of the transistor Tr1 and an oxide semiconductor film of the transistor Tr2 with different crystallinities. Or, the semiconductor device of one aspect of the present invention has a channel region of the transistor Tr1 formed in an oxide semiconductor film and a channel region of the transistor Tr2 formed in an oxide semiconductor film with different crystallinities.

[0057] The transistors Tr1 of the semiconductor devices 100A and 100B include an insulating film 106 on a substrate 102 an oxide semiconductor film 108 on the insulating film 106, an insulating film 110 on the oxide semiconductor film 108 a conductive film 120 on the insulating film 110, and an insulating film 114 on the insulating film 106, the oxide semiconductor film 108, and the conductive film 12 0. Also, the oxide semiconductor film 108 overlaps with the conductive film 120 and has a channel region 108i in contact with the insulating film 110, a source region 108s in contact with the insulating film 114, and a drain region 108d in contact with the insulating film 114.

[0058] Also, the transistor Tr1 includes an insulating film 116 on the insulating film 114 and, through an opening provided in the insulating film 114 and the insulating film 116, a conductive film 112a electrically connected to the oxide semiconductor film 10 8 in the source region 108s, and provided in the insulating film 114 and the insulating film 116 Electrically connected to the oxide semiconductor film 108 in the drain region 108d through an opening There are a conductive film 112b, an insulating film 116, a conductive film 112a, and an insulating film 118 on the conductive film 112b.

[0059] Also, for the transistor Tr2 of the semiconductor device 100A, there are a conductive film 112b, an insulating film 118 on the conductive film 112b, an oxide semiconductor film 128 on the insulating film 118, and an oxide semiconductor film 128 A conductive film 122a on the surface, a conductive film 122b on the oxide semiconductor film 128, and an oxide semiconductor film 1 There are an insulating film 124 on 28, the conductive film 122a, and the conductive film 122b, and an insulating Film 126 on the film 124, and a conductive film 130 on the insulating film 126. That is, the transistor Tr2 Can use the conductive film 112b and the conductive film 130 as gate electrodes. At this time, the conductive Film 112b can be used as a back gate electrode.

[0060] For the transistor Tr2 of the semiconductor device 100B, there are a conductive film 112b, an insulating film 118 on the conductive film 112b, an oxide semiconductor film 208 on the insulating film 118, and an oxide semiconductor film 208 on the surface An insulating film 210b, a conductive film 212b on the insulating film 210b, an oxide semiconductor film 208, a conductive Film 212b, and an insulating film 214 on the insulating film 118, an insulating film 216, a conductive film 218a, 218b. That is, the transistor Tr2 can use the conductive film 112b and the conductive film 21 2b as gate electrodes. At this time, the conductive film 112b can be used as a back gate electrode And.

[0061] For the transistor Tr1 of the semiconductor devices 100C and 100D, there is a conductive film 107 on the substrate 102 and An insulating film 117 on the conductive film 107, an oxide semiconductor film 108 on the insulating film 117, and an oxide It has conductive films 112a and 112b electrically connected to the semiconductor film 108, and insulating films 118 and 11 9.

[0062] The transistor Tr2 of the semiconductor device 100C includes a conductive film 112b, insulating films 118 and 119 on the conductive film 112b, an oxide semiconductor film 128 on the insulating film 119, a conductive film 122a on the oxide semiconductor film 128, a conductive film 122b on the oxide semiconductor film 128, an insulating film 124, an insulating film 126 on the insulating film 124, and a conductive film 130 on the insulating film 126. That is, the transistor Tr2 can use the conductive film 112b and the conductive film 130 as gate electrodes. At this time, the conductive film 112b can be used as a back gate electrode.

[0063] The transistor Tr2 of the semiconductor device 100D includes a conductive film 112b, insulating films 118 and 119 on the conductive film 112b, an oxide semiconductor film 128 on the insulating film 119, a conductive film 122a on the oxide semiconductor film 128, an insulating film 210b on the oxide semiconductor film 128, a conductive film 212b on the insulating film 210b, and an insulating film 216. That is, the transistor Tr2 can use the conductive film 112b and the conductive film 212b as gate electrodes. At this time, the conductive film 112b can be used as a back gate electrode.

[0064] In addition, in the semiconductor devices 100C and 100D, a conductive film 122c formed simultaneously with the conductive film 122a overlaps with the oxide semiconductor film 108 of the transistor Tr1. That is, the transistor Tr1 can use the conductive film 107 and the conductive film 122c as gate electrodes. At this time, the conductive film 122c can be used as a back gate electrode.

[0065] In the semiconductor devices 100A, 100B, 100C, and 100D, the transistor Tr1 has The oxide semiconductor film and the oxide semiconductor film of the transistor Tr2 overlap each other. The transistor Tr1 and the transistor Tr2 are at least partially overlapped with each other. By providing an area where the transistors are arranged, the layout area of the transistors can be reduced. The channel region formed in the oxide semiconductor film of the transistor Tr1 and the It is preferable that the channel region formed in the oxide semiconductor film does not overlap with the insulating film.

[0066] Similar to the semiconductor device 100A, the semiconductor device 100A has a structure including a transistor Tr1 and a transistor Tr2. The semiconductor device 100E is shown in FIG. 3(A). However, the semiconductor device 100E differs from the semiconductor device 100A in the following points: Unlike the semiconductor device 100A, the semiconductor device 100E has an oxide film of the transistor Tr1. The oxide semiconductor film of the transistor Tr2 and the oxide semiconductor film of the transistor Tr3 have an overlapping region. However, a part of the conductive film 112b is formed on the oxide semiconductor of the transistor Tr2. The conductive film 112b has an area where it overlaps with the conductive film 122a. The semiconductor device 100B has a transistor Tr1 and a transistor Tr2. The transistors Tr1 and Tr2 of the semiconductor device 100F are The same applies to the semiconductor devices 100C and 100D (see FIG. 3B). In the transistor Tr1, an oxide semiconductor film of the transistor Tr2 is The oxide semiconductor film and the oxide semiconductor film may have no overlapping regions. Even with such an arrangement, considering the limit to which the line width can be made fine by exposure, the distance between the wiring on a plane is There is an effect of reducing the layout area of the transistor as compared with the case where a distance is secured.

[0067] Further, in semiconductor devices 100A and 100B, in insulating films 116 and 118, and in semiconductor devices 100C and 100D, it is assumed that insulating films 117, 118, and 119 have films that are difficult for hydrogen to permeate. When the substrate 102 is a material that easily releases hydrogen, the diffusion of this hydrogen can be made smaller in the oxide semiconductor film of the transistor Tr2 than in the amount in the oxide semiconductor film of the transistor Tr1. That is, the transistor Tr2 can be used even as a transistor having a characteristic that the threshold value is likely to vary with respect to the diffusion of hydrogen as compared with the transistor Tr1. r2 r2 Even if it is a transistor, it can be used.

[0068] FIG. 4(A) is a top view of a semiconductor device 100A according to an aspect of the present invention, and FIG. 4(B) corresponds to a cross-sectional view of a cut surface of the semiconductor device 100A between the dashed-dotted line A1 - A2 shown in FIG. 4(A). Note that FIG. 4(B) includes a cross-section in the channel length (L) direction of the transistor Tr1 and a cross-section in the channel length (L) direction of the transistor Tr2.

[0069] Further, in FIG. 4(A), in order to avoid complication, a part of the components of the semiconductor device 100A (such as an insulating film that functions as a gate insulating film) and a part of the reference numerals of the components are omitted and shown. Note that in the top view of the semiconductor device, as in FIG. 4(A) in the following drawings, a part of the components and a part of the reference numerals of the components may be omitted and shown.

[0070] Semiconductor devices 100B, 100C, 100D, and 100E having a structure different from that of the semiconductor device 100A , 100F can be arranged as shown in Fig. 4(A) in the same way as the semiconductor device 100A as well.

[0071] In one aspect of the present invention, the transistor Tr1 and the transistor Tr2 have different field-effect mobilities. In the saturation region measured by Id-Vg measurement, the field-effect mobility of the transistor Tr2 is higher than that of the transistor Tr1. Although details will be described in the later part , the film formation temperature of the oxide semiconductor film of the transistor Tr1 is higher than that of the oxide semiconductor film of the transistor Tr2 . Also, for the transistor Tr2, the difference between the minimum value and the maximum value of the field-effect mobility in the saturation region measured by the Id-Vg measurement of the transistor is preferably within 15 cm / Vs. 2

[0072] In one aspect of the present invention, in any of the structures of the semiconductor devices 100A, 100B, 100C, 100D, 100E, 100F, the field-effect mobility in the saturation region of the transistor Tr2 is higher than that of the transistor Tr1. That is, one aspect of the present invention can have any of the structures of the semiconductor devices 100 A, 100B, 100C, 100D. Also, a structure of the semiconductor device 100E or 100F in which the oxide semiconductor film of the transistor Tr1 and the oxide semiconductor film of the transistor Tr2 do not have an overlapping region with each other is also acceptable.

[0073] When the channel regions of the transistor Tr1 and the transistor Tr2 overlap each other, there is a case where one transistor affects the other when one of the transistors is operating . To avoid this influence, the distance between the transistor Tr1 and the transistor Tr2 ​​​​​ A configuration for increasing the gap, or a configuration in which a conductive film is provided between the transistor Tr1 and the transistor Tr2, etc. can be mentioned. However, in the case of the former configuration, since the semiconductor device becomes thick, for example, when forming the semiconductor device 100A on a flexible substrate or the like, there may be a problem with flexibility and the like. Also, in the case of the latter configuration, an increase in the process of forming the conductive film, and similar to the case of the former configuration, since the semiconductor device becomes thick, there may be a problem.

[0074] Further, since the oxide semiconductor film 108 and the oxide semiconductor film 128 each have a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobilities of both the transistor Tr1 and the transistor Tr2 can be increased.

[0075] For example, by using the above transistor with a high field-effect mobility in a gate driver that generates a gate signal of a display device, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Also, by using the above transistor with a high field-effect mobility in a source driver (particularly, a demultiplexer connected to the output terminal of a shift register included in the source driver) that supplies a signal from a signal line of a display device, a display device with a small number of wirings connected to the display device can be provided. Also, by using the above transistor with a high field-effect mobility in either one or both of the selection transistor and the drive transistor of a pixel circuit of a display device, a display device with high display quality can be provided.

[0076] Also, the semiconductor device 100A shown in FIGS. 4(A) and 4(B) is suitably used for a pixel circuit of a display device. ​​​​​​​​​​​​​​It is possible to arrange as shown in FIGS. 4(A) and 4(B), thereby increasing the pixel density of the display device. For example, when the pixel density of the display device exceeds 1000 ppi (pixels per inch), or when the pixel density of the display device exceeds 2000 ppi even in such cases, by arranging as shown in FIGS. 4(A) and 4(B), the aperture ratio of the pixels can be increased. Note that ppi is a unit representing the number of pixels per inch. Hereinafter, taking the structure of the semiconductor device 100A as an example, the differences between the oxide semiconductor film 108 and the oxide semiconductor film 1

[0077] 28 will be described. In particular, the field-effect mobility in the saturation region in the Id-Vg measurement of the transistor will be described. First, the general characteristics of the transistor will be described with reference to FIGS. 5 and 6.

[0078] <1-2 Field-Effect Mobility in the Saturation Region> First, the general characteristics of the transistor will be described using FIGS. 5 and 6.

[0079] [Id-Vg Characteristics of Transistor] The drain current-gate voltage characteristics (Id-Vg characteristics) of the transistor will be described. FIG. 5(A) is a diagram for explaining an example of the Id-Vg characteristics of the transistor. In FIG. 5(A) for the sake of simplicity of understanding, it is assumed that polycrystalline silicon is used for the active layer of the transistor. Also, in FIG. 5(A), the vertical axis represents Id and the horizontal axis represents Vg.

[0080] As shown in FIG. 5(A), the Id-Vg characteristics are roughly divided into three regions. The first region is the off region, the second region is the subthreshold region, and the third region is the on region. region (subthreshold region), and the third region is the on region (ON The boundary between the subthreshold region and the on-region is called the The gate voltage at this field is called the threshold voltage (Vth).

[0081] The characteristics of a transistor are the drain current in the off region (also called the off current or Ioff). It is desirable that the drain current (also called the on-current or Ion) in the on region is high. In addition, the on-state current of a transistor is often measured using the field-effect mobility as an index. The field-effect mobility will be described in detail later.

[0082] In addition, to operate the transistor at a low voltage, the Id It is desirable that the slope of the -Vg characteristics is steep. Id-Vg characteristics in the subthreshold region As an index showing the magnitude of change in The S value is expressed by the following formula (1):

[0083]

number

[0084] The S value is the gate capacitance required to change the drain current by one order of magnitude in the subthreshold region. The smaller the S value, the faster the on / off switching operation. It can be done steeply.

[0085] [Transistor Id-Vd characteristics] Next, we will explain the drain current-drain voltage characteristics (Id-Vd characteristics) of a transistor. FIG. 5B is a graph illustrating an example of the Id-Vd characteristics of a transistor. In FIG. 5(B), the vertical axis represents Id and the horizontal axis represents Vd.

[0086] As shown in FIG. 5(B), the on-region is further divided into two regions. The first region is referred to as the linear region and the second region as the saturation region, respectively. In the linear region, the drain current increases parabolically as the drain voltage increases. On the other hand, in the saturation region, the drain current does not change significantly even when the drain voltage changes. Note that, analogous to a vacuum tube,

[0087] the linear region may sometimes be referred to as the triode region and the saturation region as the pentode region, respectively. However, in practice, it is necessary to consider the threshold voltage of the transistor. Therefore, the state where the value obtained by subtracting the threshold voltage of the transistor from Vg is greater than Vd (Vd < Vg - Vth) may be regarded as the linear region.

[0088] In the Id-Vd characteristics of a transistor, the characteristic where the current in the saturation region is constant may sometimes be expressed as "good saturation". The goodness of saturation of a transistor is particularly important in applications to organic EL

[0089] [Analysis Model of Drain Current] Next, the analytical model for the drain current will be described. As the analytical model for the drain current, the analytical formula for the drain current based on the Gradual channel approximation (GCA) is known . Based on the GCA, the drain current of the transistor is represented by the following formula (2) .

[0090]

Equation

[0091] In the mathematical formula (2), the upper one is the formula for the drain current in the linear region, and the lower one is the formula for the drain current in the saturation region.

[0092] [Field-effect mobility] Next, the field-effect mobility will be described. As an index of the current driving force of the transistor, the field effect mobility is used. As described above, the on region of the transistor is divided into the linear region and the saturation region. Based on the characteristics of each region, the field-effect mobility of the transistor can be calculated based on the analytical formula for the drain current based on the GCA. When it is necessary to distinguish, they are respectively called linear mobility and saturation mobility. The linear mobility is represented by the following formula (3), and the saturation mobility is represented by the following formula (4).

[0093]

Equation

[0094]

Equation

[0095] In this specification and the like, the curves calculated from Formula (3) and Formula (4) are referred to as mobility curves. This is shown in FIG. 6, which depicts the mobility curves of the linear mobility and the saturation mobility, respectively, superimposed on the Id-Vg characteristics of the transistor. Note that FIG. 6 shows the mobility curves of the linear mobility and the saturation mobility, respectively, superimposed on the Id-Vg characteristics of the transistor. This is shown in FIG. 6, which depicts the mobility curves of the linear mobility and the saturation mobility, respectively, superimposed on the Id-Vg characteristics of the transistor.

[0096] In FIG. 6, the Id-Vg characteristics are calculated from the analytical formula of the drain current based on GCA. The shape of the mobility curve serves as a clue for understanding the internal state of the transistor.

[0097] For example, focus on the shape of the saturation mobility shown in FIG. 6. The carriers (electrons or holes) in the transistor are accelerated by the electric field and gain energy as the gate voltage increases. Therefore, since the carriers obtain a certain speed by the electric field, the saturation mobility increases. However, the carriers are not infinitely accelerated by the electric field and lose energy by colliding with lattice atoms that thermally vibrate or ionized impurity atoms. Therefore, the saturation mobility gradually decreases. This is shown in FIG. 6, which depicts the mobility curves of the linear mobility and the saturation mobility, respectively, superimposed on the Id-Vg characteristics of the transistor.

[0098] [Fabrication of Transistor] Next, a transistor having an oxide semiconductor film was fabricated, and the electrical characteristics of the transistor were evaluated. This is shown in FIG. 6, which depicts the mobility curves of the linear mobility and the saturation mobility, respectively, superimposed on the Id-Vg characteristics of the transistor.

[0099] The transistor shown in FIG. 7 includes a conductive film 107 on a substrate 102, an insulating film 104 on the conductive film 107, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 on the insulating film 110, and an insulating film 116 on the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. Note that the oxide semiconductor film 108 is on the conductive film 1 04 and an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 on the insulating film 110, and an insulating film 116 on the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. Note that the oxide semiconductor film 108 is on the conductive film 1 A channel region 108i overlapping with 12, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116. It has.

[0100] In the present embodiment, samples A1 to A3 were fabricated with the transistor configuration shown in FIG. 7.

[0101] Note that samples A1 to A3 are samples in which transistors with a channel length L of 2 μm and a channel width W of 3 μm are formed. Also, samples A1 and A2 are samples in which comparative transistors are formed, and sample A3 is a sample in which a transistor according to one aspect of the present invention is formed. Note that samples A1 to A3 were each formed by changing the film formation conditions of the oxide semiconductor film, and the same manufacturing method was used for the other steps.

[0102] [Method for manufacturing samples A1 to A3] First, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering ring device. Subsequently, the conductive film was processed by photolithography.

[0103] Next, four insulating films were laminated and formed on the substrate and the conductive film. The insulating films were continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) apparatus. As the insulating films, a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used from the bottom.

[0104] Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a semiconductor layer. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was used. ​​​​​​​​​​were formed. In Samples A1 to A3, the film formation conditions of the oxide semiconductor films were different respectively. respectively.

[0105] The oxide semiconductor film of Sample A1 was formed by introducing argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm into the chamber of a sputtering apparatus at a substrate temperature of 170°C, setting the pressure to 0.6 Pa, and applying 2.5 kW of AC power to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc. Incidentally, when described from the ratio of oxygen in the entire film-forming gas, it may be referred to as the "oxygen flow ratio". The oxygen flow ratio during film formation of Sample A1 is 30%. respectively. respectively. respectively. respectively. respectively.

[0106] The oxide semiconductor film of Sample A2 was formed by introducing argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm into the chamber of a sputtering apparatus at a substrate temperature of 130°C, setting the pressure to 0.6 Pa, and applying 2.5 kW of AC power to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc. Incidentally, the oxygen flow ratio during film formation of Sample A2 is 10%. respectively. respectively. respectively. respectively.

[0107] The metal oxide film used for the oxide semiconductor film of Sample A3 was under the same conditions as Sample A6. That is, at a substrate temperature of room temperature (R.T.), argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of a sputtering apparatus, the pressure was set to 0.6 Pa, and 2.5 kW of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc to form it. respectively. respectively. Pa, and 2.5 kW of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc to form it. respectively. This was achieved. Note that the oxygen flow ratio during the film formation of Sample A3 was 10%.

[0108] Next, an insulating film was formed on the insulating film and the oxide semiconductor layer. As the insulating film, a silicon oxynitride film with a thickness of 150 nm was formed using a PECVD apparatus.

[0109] Next, heat treatment was performed. The heat treatment was carried out in an atmosphere of a mixed gas of nitrogen and oxygen at 35 0 °C for 1 hour.

[0110] Next, an opening was formed in a desired region of the insulating film. As the method for forming the opening, a dry etching method was used.

[0111] Next, an oxide semiconductor film with a thickness of 100 nm was formed on the insulating film so as to cover the opening, and the oxide semiconductor film was processed into an island shape to form a conductive film. Further, after forming the conductive film, subsequently, the insulating film was formed by processing the insulating film in contact with the lower side of the conductive film.

[0112] As the conductive film, an oxide semiconductor film with a thickness of 10 nm, a titanium nitride film with a thickness of 50 nm, and a copper film with a thickness of 100 nm were sequentially formed. Note that as the film formation conditions of the oxide semiconductor film, the substrate temperature was set to 170 °C, oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was set to 0.6 Pa, and an alternating current power of 2.5 kw was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc to form it. Also, as the titanium nitride film and the copper film, they were formed using a sputtering apparatus.

[0113] Next, plasma treatment was performed on the oxide semiconductor film, the insulating film, and the conductive film. The plasma As a process, a PECVD apparatus was used, the substrate temperature was set to 220 °C, and it was carried out in an atmosphere of a mixed gas of argon gas and nitrogen gas. It was carried out in an atmosphere of a mixed gas of argon gas and nitrogen gas.

[0114] Next, an insulating film was formed on the oxide semiconductor film, the insulating film, and the conductive film. As the insulating film, a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were laminated and formed using a PECVD apparatus. Next, an insulating film was formed on the oxide semiconductor film, the insulating film, and the conductive film. As the insulating film, a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were laminated and formed using a PECVD apparatus. Next, an insulating film was formed on the oxide semiconductor film, the insulating film, and the conductive film. As the insulating film, a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were laminated and formed using a PECVD apparatus.

[0115] Next, a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask. Next, a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask.

[0116] Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape to form a conductive film serving as a source electrode and a drain electrode. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were respectively formed using a sputtering apparatus. Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape to form a conductive film serving as a source electrode and a drain electrode. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were respectively formed using a sputtering apparatus. Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape to form a conductive film serving as a source electrode and a drain electrode. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were respectively formed using a sputtering apparatus. Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape to form a conductive film serving as a source electrode and a drain electrode. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were respectively formed using a sputtering apparatus.

[0117] Next, an insulating film was formed on the insulating film and the conductive film. As the insulating film, an acrylic-based photosensitive resin with a thickness of 1.5 μm was used. Next, an insulating film was formed on the insulating film and the conductive film. As the insulating film, an acrylic-based photosensitive resin with a thickness of 1.5 μm was used.

[0118] Samples A1 to A3 were fabricated as described above.

[0119] [Id-Vg characteristics of the transistor] Next, the Id-Vg characteristics of the transistors of Samples A1 to A3 fabricated above were measured. The measurement conditions for the Id-Vg characteristics of the transistor were the voltage applied to the conductive film functioning as the first gate electrode (hereinafter also referred to as the gate voltage (Vg)), and the voltage applied to the conductive film functioning as the second gate electrode (also referred to as Vbg)), from -10 V to +10 V. The measurement conditions for the Id-Vg characteristics of the transistor were the voltage applied to the conductive film functioning as the first gate electrode (hereinafter also referred to as the gate voltage (Vg)), and the voltage applied to the conductive film functioning as the second gate electrode (also referred to as Vbg)), from -10 V to +10 V. The measurement conditions for the Id-Vg characteristics of the transistor were the voltage applied to the conductive film functioning as the first gate electrode (hereinafter also referred to as the gate voltage (Vg)), and the voltage applied to the conductive film functioning as the second gate electrode (also referred to as Vbg)), from -10 V to +10 V. It was applied in steps of 0.25 V up to. Also, the voltage applied to the conductive film that functions as the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the conductive film that functions as the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 20 V. The results of the Id-Vg characteristics of Sample A1, Sample A2, and Sample A3 are shown in FIGS. 8(A), (B), and (C), respectively. In FIGS. 8(A), (B), and (C), the first vertical axis represents Id (A), the second vertical axis represents the field-effect mobility (μFE (cm

[0120] / Vs)), and the horizontal axis represents Vg (V). Note that the field-effect mobility is the value measured when Vd is 20 V. As shown in FIGS. 8(A), (B), and (C), by changing the film formation conditions of the oxide semiconductor film, different tendencies are confirmed in the Id-Vg characteristics of the transistor. In particular, differences are confirmed in the shape of the mobility curve of the field-effect mobility of the transistor. From the shapes of the mobility curves of Samples A1 to A3 shown in FIGS. 8(A), (B), and (C), the minimum value, maximum value, and the difference between the maximum value and the minimum value of the field-effect mobility in the saturation region of the transistor were calculated. Here, the saturation region of the transistor was set to the range where Vg is 3 V or more and 10 V or less. This range is a gate voltage often used in applications such as displays. 2 In Sample A1, the minimum value of the field-effect mobility in the saturation region of the transistor was 9.8 cm

[0121] / Vs, and the maximum value was 28.3 cm / Vs. That is, for Sample A1, the transistor's

[0122] In the saturation region of the transistor shown in FIGS. 8(A), (B), and (C) from Samples A1 to A3, the minimum value, maximum value, and the difference between the maximum value and the minimum value of the field-effect mobility were calculated. Here, the saturation region of the transistor was set to the range where Vg is 3 V or more and 10 V or less. This range is a gate voltage often used in applications such as displays. In Sample A1, the minimum value of the field-effect mobility in the saturation region of the transistor was 9.8 cm / Vs, and the maximum value was 28.3 cm / Vs. That is, for Sample A1, the

[0123] In Sample A1, the minimum value of the field-effect mobility in the saturation region of the transistor was 9.8 cm 2 / Vs, and the maximum value was 28.3 cm 2 / Vs. That is, for Sample A1, the transistor's The difference between the minimum value and the maximum value of the field-effect mobility in the saturation region of the transistor was 18.5 cm 2 / Vs. Also, in Sample A2, the minimum value of the field-effect mobility in the saturation region of the transistor was 23.3 cm 2 / Vs, and the maximum value was 51.1 cm 2 / Vs. That is, the difference between the minimum value and the maximum value of the field-effect mobility in the saturation region of the transistor of Sample A2 was 27.8 cm / Vs. 2 Also, in Sample A3, the minimum value of the field-effect mobility in the saturation region of the transistor was 55.8 cm 2 / Vs, and the maximum value was 67.0 cm 2 / Vs. That is, the difference between the minimum value and the maximum value of the field-effect mobility in the saturation region of the transistor of Sample A3 was 11.2 cm / Vs. 2

[0124] In other words, for Sample A1, the minimum value of the field-effect mobility in the saturation region of the transistor was approximately 65.3% lower than the maximum value of the field-effect mobility. Also, for Sample A2, the minimum value of the field-effect mobility in the saturation region of the transistor was approximately 5 4.4% lower than the maximum value of the field-effect mobility. Also, for Sample A3, the minimum value of the field-effect mobility in the saturation region of the transistor was approximately 16.7% lower than the maximum value of the field-effect mobility. Thus, Sample A3 in which the transistor of one embodiment of the present invention was formed had a characteristic that the minimum value of the field-effect mobility in the saturation region of the transistor was preferably 30% or less, more preferably 20% or less, relative to the maximum value of the field-effect mobility.

[0125] ​​​​​​​ As described above, Sample A3 in which the transistor of one embodiment of the present invention was formed had a high saturation point of the transistor. The difference between the minimum and maximum field-effect mobility in the sum region is 15 cm 2 / Vs, which is an extremely low characteristic. The transistors with such characteristics have high field-effect mobility in the region of 5V or less. For example, by using a transistor as a pixel transistor in an organic EL display, This provides flow driving capability and high reliability.

[0126] <1-3. Pixel circuits of display devices> An example of applying the semiconductor device 100A shown in FIGS. 4A and 4B to a pixel circuit of a display device This will be explained with reference to FIG.

[0127] FIG. 9 is a circuit diagram showing an example in which the semiconductor device 100A is applied to a pixel circuit of a display device. This is a road map.

[0128] The semiconductor device 100A shown in FIG. 9 includes a transistor Tr1, a transistor Tr2, and a capacitor The semiconductor device 100 includes an element Cs1 and a light-emitting element 160. The semiconductor device 100A has two adjacent pixels (or sub-pixels) in the column direction. The capacitance element Cs1 functions as one of the capacitance elements shown in FIG. Although not shown, for example, the capacitance between the conductive film 120 and the conductive film 122a or the conductive It can be formed by using the capacitance between the film 112b and the conductive film 122a. Transistor Tr1 is also called a selection transistor. Transistor Tr2 is called a drive transistor. The transistor Tr2 mainly operates in the saturation region.

[0129] Also, in the circuit diagram shown in FIG. 9, a data line DL_ Y-1 for writing a data signal to a pixel, a data line DL_Y for writing a data signal to an adjacent pixel, and an anode line ANODE_X-1 for supplying a potential to a light-emitting element, and an anode line ANODE_X for supplying a potential to an adjacent light-emitting element, and a scan line GL_X for supplying a scan signal to a pixel are shown. is shown.

[0130] One of the source electrode and the drain electrode of the transistor Tr1 is electrically connected to the data line DL_Y-1. Further, the first gate electrode and the second gate electrode of the transistor Tr1 are electrically connected to the scan line GL_X. The transistor Tr1 has a function of controlling the writing of data signals.

[0131] One of the pair of electrodes of the capacitor element Cs1 is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr1. Also, the other of the pair of electrodes of the capacitor element Cs1 is electrically connected to the second gate electrode (also referred to as the back gate electrode) of the transistor Tr2. The capacitor element Cs1 has a function as a holding capacitor for holding the written data.

[0132] One of the source electrode and the drain electrode of the transistor Tr2 is electrically connected to the anode line ANODE_X-1.

[0133] One of the pair of electrodes of the light-emitting element 160 is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr2, and the other is electrically connected to the cathode line CATHODE. Note that the other of the pair of electrodes of the capacitor element Cs1 is connected to one of the pair of electrodes of the light-emitting element 160. ​​​​​​​​​​​It is electrically connected.

[0134] The above configuration is an example of an application to a pixel of a display device of the semiconductor device 100A shown in FIGS. 4(A) and 4(B). This is an example of the case.

[0135] <1-4. Configuration of Semiconductor Device> Once again, the semiconductor device 100A shown in FIGS. 4(A) and 4(B) will be described. When the semiconductor device 100A shown in FIGS. 4(A) and 4(B) is applied to a pixel of a display device, for example, the channel length (L) and channel width (W) of the transistor, or the line width of the wiring and electrodes connected to the transistor and the like can be made relatively large. For example, as compared with the case where the transistor Tr1 and the transistor Tr 2 are arranged on the same plane, as shown in FIGS. 4(A) and 4(B), at least a part of the transistor Tr 1 and the transistor Tr2 are arranged so as to overlap, whereby the line width and the like can be increased, and thus it becomes possible to reduce the variation in the processing dimensions. In addition, since either one or both of the conductive film and the insulating film can be commonly used between the transistor Tr1 and the transistor Tr2, the number of masks or the number of processes can be reduced. This is possible.

[0136] For example, in the transistor Tr1, the conductive film 120 functions as a gate electrode, the conductive film 112a functions as a source electrode, and the conductive film 112b functions as a drain electrode. Also, in the transistor Tr1, the insulating film 110 functions as a gate insulating film. Further,

[0137] in the transistor Tr2, the conductive film 112b functions as a first gate electrode, the conductive film 122a functions as a source electrode, the conductive film 122b functions as a drain electrode, and the conductive film 120 functions as a second gate insulating film. Also, in the transistor Tr2, the insulating film 110 functions as a second gate insulating film. Further, in the transistor Tr2, the conductive film 122a functions as a source electrode, the conductive film 122b functions as a drain electrode, and the conductive The film 130 functions as the second gate electrode. Also, in the transistor Tr2, the insulating film 118 functions as the first gate insulating film, and the insulating films 124 and 126 function as the second gate insulating film.

[0138] In addition, in this specification and the like, the insulating film 110 may be referred to as the first insulating film, the insulating film 118 as the second insulating film, and the insulating films 124 and 126 as the third insulating film, respectively.

[0139] Also, on the conductive film 130, an insulating film 134 and an insulating film 136 on the insulating film 134 are provided Therein. Also, the insulating films 134 and 136 are provided with an opening 184 reaching the conductive film 130 Therein. Also, a conductive film 138 is provided on the insulating film 136. Note that the conductive film 138 is open Connected to the conductive film 130 through the mouth portion 184.

[0140] Also, on the conductive film 138, an insulating film 140, an EL layer 142, and a conductive film 144 are provided Therein. The insulating film 140 covers a part of the side end portion of the conductive film 138 and has a function of preventing a short circuit of the conductive film 138 between adjacent pixels. Also, the EL layer 142 has a function of emitting light. Also, the conductive film 138, the EL layer 142, and the conductive film 144 constitute a light-emitting element 160 Therein. The conductive film 138 functions as one electrode of the light-emitting element 160, and the conductive film 144 Functions as the other electrode of the light-emitting element 160.

[0141] Thus, in one aspect of the present invention, a top-gate type transistor and a bottom-gate Type transistors can be used in combination.

[0142] As described above, a semiconductor device according to one aspect of the present invention has a stacked structure of a plurality of transistors, and the Reduce the installation area of the transistor. Also, in a plurality of transistors, by commonly using either one or both of the insulating film and the conductive film, the number of mask sheets or the number of processes can be reduced.

[0143] <1-5. Configuration of Gate Electrode> Also, as shown in FIGS. 4(A) and 4(B), the transistor Tr2 has a configuration having two gate electrodes.

[0144] Here, the effect of the configuration having two gate electrodes will be described with reference to FIGS. 4(A) and 4(B) and FIG. 10.

[0145] Note that FIG. 10 corresponds to a cross-sectional view of a cut surface between the dashed-dotted lines B1 - B2 shown in FIG. 4(A). Also, FIG. 10 includes a cross-section in the channel width (W) direction of the transistor Tr2.

[0146] As shown in FIG. 10, the oxide semiconductor film 128 is positioned to face the conductive film 112b and the conductive film 130, and is sandwiched between conductive films that function as two gate electrodes. The lengths of the conductive film 112b and the conductive film 130 in the channel width direction are each longer than the length of the oxide semiconductor film 128 in the channel width direction, and the entire oxide semiconductor film 128 is covered by the conductive film 112b and the conductive film 130 via the insulating films 118, 124, and 126.

[0147] In other words, the conductive film 112b and the conductive film 130 have regions located outside the side end portions of the oxide semiconductor film 128.

[0148] With such a configuration, the oxide semiconductor film 128 included in the transistor Tr2 can be electrically surrounded by the electric fields of the conductive film 112b and the conductive film 130. The transistor ​​​​​​​​​​ A transistor device structure that electrically surrounds an oxide semiconductor film in which a channel region is formed by the electric fields of a first gate electrode and a second gate electrode, like transistor Tr2, can be called a Surrounded channel (S-channel) structure.

[0149] Since transistor Tr2 has an S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 128 by the conductive film 112b that functions as the first gate electrode. Therefore, the current driving ability of transistor Tr2 is improved, and high on-current characteristics can be obtained. Also, since it is possible to increase the on-current, transistor Tr2 can be miniaturized. Further, transistor Tr2 has a structure in which the oxide semiconductor film 128 is surrounded by the conductive film 112b that functions as the first gate electrode and the conductive film 130 that functions as the second gate electrode, so the mechanical strength can be increased.

[0150] Note that the transistor Tr2 shown in FIG. 4(B) has a configuration in which the conductive film 130 that functions as the second gate electrode is electrically connected to the conductive film 122a that functions as the source electrode or drain electrode of the transistor Tr2, but is not limited to this. For example, a configuration in which the first gate electrode and the second gate electrode are connected may be used. In this case, by providing openings in the insulating films 118, 124, and 126, the conductive film 130 that functions as the second gate electrode is electrically continued with the conductive film 112b that functions as the first gate electrode at the openings. Therefore, the same potential is applied to the conductive film 112b and the conductive film 130.

[0151] ​​​​​​​​​​​​​​​ At this time, although the capacitive element Cs1 is not shown in FIG. 10, for example, a capacitance between a film formed simultaneously with the conductive film 112b and a film formed simultaneously with the conductive film 122a can be used for formation. On the other hand, the parasitic capacitance of the transistor Tr2 is the sum of the capacitance between the conductive film 112b and the oxide semiconductor film 128 and the capacitance between the conductive film 130 and the oxide semiconductor film 128. In total.

[0152] When the holding capacitance of the capacitive element Cs1 is small, the gate voltage value of the transistor Tr2 fluctuates greatly due to the influence of the parasitic capacitance of the transistor Tr2. Then, unevenness occurs in the display by the light-emitting element 160. Since there is a purpose of reducing the layout area of the transistor, when it is difficult to increase the holding capacitance of the capacitive element Cs1, reducing the parasitic capacitance of the transistor Tr2 is effective for stabilizing the gate voltage value of the transistor Tr2. As this means, the film thickness of the insulating film 126 may be increased, but the on-current of the transistor Tr2 becomes small. It is sufficient to increase the film thickness of the insulating film 126, but the on-current of the transistor Tr2 becomes small.

[0153] The transistor Tr2 is mainly driven in the saturation region. Comparing the on-currents in the saturation region in FIG. 8, FIG. 8(C) is the largest, followed by FIG. 8(B), and FIG. 8(A) is the smallest. When trying to obtain a certain on-current in the saturation region, when using the oxide semiconductor film of FIG. 8(B) or FIG. 8(C), it is possible to increase the film thickness of the insulating film 126 more than when using the oxide semiconductor film of FIG. 8(A). That is, in one aspect of the present invention, by using the oxide semiconductor film of FIG. 8(B) or FIG. 8(C) for the transistor Tr2, it is possible to reduce the holding capacitance of the capacitive element Cs1.

[0154] ​​​​​​​​This allows the installation area of the transistor to be reduced.

[0155] <1-6. Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0156] <Substrate> There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. A single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, etc. It is also possible to apply a substrate, an SOI substrate, etc., on which a semiconductor element is provided. The substrate 102 may be a glass substrate. In this case, the 6th generation (1500mm x 1850mm) and 7th generation (1870mm x 2200 mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800 By using large area substrates such as 10th generation (2950mm x 3400mm), It is possible to fabricate a display device of this type.

[0157] In addition, a flexible substrate is used as the substrate 102, and the semiconductor device 100A is directly mounted on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device 100A. The release layer is used to separate the semiconductor device from the substrate 102 after a part or all of the semiconductor device is completed thereon. The semiconductor device 100A can be removed and transferred to another substrate. It can also be transferred to less rigid or flexible substrates.

[0158] <Conductive film> As the conductive films 112a, 112b, 120, 122a, 122b, 130, 138, and 144, metals such as chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), or alloys containing the above metallic elements as components, or alloys formed by combining the above metallic elements can be used to form them respectively.

[0159] In addition, for the conductive films 112a, 112b, 120, 122a, 122 b, 130, 138, and 144, oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium, and zinc, oxides containing titanium and indium, oxides containing titanium, indium, and tin, oxides containing indium and zinc, oxides containing silicon, indium, and tin, oxides containing indium, gallium, and zinc, and other oxide conductors can also be applied.

[0160] In particular, for the conductive films 120 and 130, it is preferable to preferably use the above-mentioned oxide conductors. Here, the oxide conductor will be described. In this specification, etc., the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for The oxidized semiconductor that has been made conductive can be referred to as an oxide conductor. Generally, an oxide semiconductor has a large energy gap and thus has translucency to visible light. On the other hand, an oxide conductor is an oxide semiconductor that has a donor level near the conduction band. Therefore, an oxide conductor is less affected by absorption due to the donor level and has translucency to visible light comparable to that of an oxide semiconductor.

[0161] Also, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive film 112a, the conductive film 112b, the conductive film 122a, the conductive film 122b, the conductive film 13 0, the conductive film 138, and the conductive film 144. By using a Cu-X alloy film, it can be processed in a wet etching process, making it possible to suppress the manufacturing cost.

[0162] In particular, the above-mentioned Cu-X alloy film can be preferably used for any one or more of the conductive film 112a, the conductive film 112b, the conductive film 122a, the conductive film 122b, and the conductive film 130. As the Cu-X alloy film, a Cu-Mn alloy film is particularly preferable.

[0163] Also, for any one or more of the conductive film 112a, the conductive film 112b, the conductive film 120, the conductive film 122a, the conductive film 122 b, and the conductive film 130, among the above-mentioned metal elements, it is preferable to have any one or more selected particularly from aluminum, copper, titanium, tungsten, tantalum, and molybdenum.

[0164] Also, for any one or more of the conductive film 112a, the conductive film 112b, the conductive film 120, the conductive film 122a, the conductive film 122 b, and the conductive film 130, it is preferable to contain nitrogen and tantalum, so-called nitrided It is preferable to use a tantalum film. The tantalum nitride film has conductivity and a high barrier property against copper or hydrogen. Further, since the tantalum nitride film emits little hydrogen by itself, it can be most preferably used as a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 1 08.

[0165] <Insulating film> As the insulating films 106, 114, 116, 118, 124, 12 6, 134, 136, and 140, insulating layers containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used respectively.

[0166] Further, the insulating film 106 has a function as a blocking film that suppresses oxygen permeation. For example, when any one or more of the insulating films 114, 116, the oxide semiconductor film 108, the oxide semiconductor film 128, the insulating film 124, and the insulating film 126 have an excess oxygen region, oxygen permeation can be suppressed by the insulating film 106.

[0167] Note that as the insulating film in contact with either one or both of the oxide semiconductor film 108 and the oxide semiconductor film 128, an oxide insulating film is preferable, and it is more preferable to have a region (excess oxygen region) containing oxygen in excess of the stoichiometric composition. In other words, excess oxygen The oxide insulating film having an excess oxygen region is an insulating film capable of releasing oxygen.

[0168] Note that, as the oxide insulating film having the above-described excess oxygen region, for example, an insulating film may be formed in an oxygen atmosphere, the formed insulating film may be heat-treated in an oxygen atmosphere, or oxygen may be added to the formed insulating film. As a method of adding oxygen to the formed insulating film, plasma treatment is preferable. The insulating film formed by forming an insulating film in an oxygen atmosphere, heat-treating the formed insulating film in an oxygen atmosphere, or adding oxygen to the formed insulating film may be used. As a method of adding oxygen to the formed insulating film, plasma treatment is preferable. Note that, as the oxide insulating film having the above-described excess oxygen region, for example, an insulating film may be formed in an oxygen atmosphere, the formed insulating film may be heat-treated in an oxygen atmosphere, or oxygen may be added to the formed insulating film. As a method of adding oxygen to the formed insulating film, plasma treatment is preferable. Note that, as the oxide insulating film having the above-described excess oxygen region, for example, an insulating film may be formed in an oxygen atmosphere, the formed insulating film may be heat-treated in an oxygen atmosphere, or oxygen may be added to the formed insulating film. As a method of adding oxygen to the formed insulating film, plasma treatment is preferable.

[0169] In addition, hafnium oxide may be used for the insulating film that functions as the gate insulating film of the transistors Tr1 and Tr2. When hafnium oxide is used for the insulating film that functions as the gate insulating film, the following effects can be obtained. In addition, hafnium oxide may be used for the insulating film that functions as the gate insulating film of the transistors Tr1 and Tr2. When hafnium oxide is used for the insulating film that functions as the gate insulating film, the following effects can be obtained. In addition, hafnium oxide may be used for the insulating film that functions as the gate insulating film of the transistors Tr1 and Tr2. When hafnium oxide is used for the insulating film that functions as the gate insulating film, the following effects can be obtained.

[0170] Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the film thickness of the insulating film can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited thereto. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited thereto.

[0171] In addition, silicon nitride may be used for the insulating film that functions as the gate insulating film of the transistors Tr1 and Tr2. In addition, silicon nitride may be used for the insulating film that functions as the gate insulating film of the transistors Tr1 and Tr2. When used, the following effects are achieved. Silicon nitride has a higher relative dielectric constant than silicon oxide, and since the film thickness required to obtain the same capacitance as silicon oxide is large, a thick insulating film can be formed. Therefore, the breakdown voltage of transistors Tr1 and Tr2 can be suppressed from decreasing, and further, the breakdown voltage can be improved to suppress the electrostatic breakdown of transistors Tr1 and Tr2. is high, and since the film thickness required to obtain the same capacitance as silicon oxide is large, the insulating film can be made thick. Therefore, the breakdown voltage of transistors Tr1 and Tr2 can be suppressed from decreasing, and further, the breakdown voltage can be improved to suppress the electrostatic breakdown of transistors Tr1 and Tr r2.

[0172] In addition, the insulating films 110, 116, 118, 124, and 126 have the function of supplying oxygen to either one or both of the oxide semiconductor films 108 or oxide semiconductor film 128. That is, the insulating films 110, 116, 118, 124, and 126 contain oxygen. Also, the insulating films 1 10 and 124 are insulating films that can permeate oxygen. Note that the insulating film 110 also functions as a damage relaxation film for the oxide semiconductor film 108 when forming the conductive film 120 to be formed later, and the insulating film 124 also functions as a damage relaxation film for the oxide semiconductor film 128 when forming the insulating film 126 to be formed later. As the insulating films 110 and 124, silicon oxide, silicon oxynitride, etc. with a thickness of 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less can be used.

[0173] Also, the insulating films 110 and 124 preferably have a small amount of defects. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from silicon dangling bonds is preferably 3×10 spins / cm

[0174] or less. This is because if the defect density contained in the insulating films 1 14 and 124 is large, oxygen will bind to the defects, and the insulating film 114 17 spins / cm 3 Here, if the defect density contained in the insulating films 1 14 and 124 is large, oxygen will bind to the defects, and the insulating film 114 The amount of oxygen that passes through the membrane decreases.

[0175] The insulating films 110 and 124 are made of oxide insulating films with low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxide can be reduced by forming an oxide semiconductor. The energy of the upper edge of the valence band of the film (Ev_os) and the energy of the lower edge of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the energy (Ec_os). Silicon oxynitride film with low nitrogen oxide release rate or silicon oxynitride film with low nitrogen oxide release rate An aluminum film or the like can be used.

[0176] The silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectroscopy (TDS). ) is a membrane that releases more ammonia than nitrogen oxides, and is typically Ammonia emission is 1×10 18 cm -3 5x10 or more 19 cm -3 The following is the case. The amount of ammonia released above is the same as that when the temperature of the heat treatment in TDS is between 50℃ and 650℃. or the total amount in the range of 50°C to 550°C. The amount is the total amount converted to ammonia molecules in TDS.

[0177] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically N O2 or NO forms a level in the insulating films 110, 124, etc. The level is It is located within the energy gap of the conductive films 108 and 128. Therefore, the nitrogen oxides The interface between the insulating film 110 and the oxide semiconductor film 108, or the interface between the insulating film 124 and the oxide semiconductor film 1 When it diffuses to the interface of 28, the level may trap electrons on the side of the insulating films 110 and 124. As a result, the trapped electrons stay near the interface between the insulating film 110 and the oxide semiconductor film 10 8, or near the interface between the insulating film 124 and the oxide semiconductor film 128, causing the threshold voltage of the transistor to shift in the positive direction.

[0178] In addition, nitrogen oxides react with ammonia and oxygen during heat treatment. The nitrogen oxides contained in the insulating film 124 react with the ammonia contained in the insulating film 126 during heat treatment, so that the nitrogen oxides contained in the insulating film 124 are reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 124 and the oxide semiconductor film 128.

[0179] By using the above oxide insulating films as the insulating films 110 and 124, it is possible to reduce the shift of the threshold voltage of the transistor and reduce the variation in the electrical characteristics of the transistor.

[0180] Note that during the heat treatment in the manufacturing process of the transistor, typically heat treatment at 300 °C or higher and lower than 350 °C, the insulating films 110 and 124 have a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less in the spectrum obtained by measurement with an ESR of 100 K or less. Note that the split widths of the first signal and the second signal, and also the split widths of the second signal and the third signal are about 5 mT in the X-band ESR measurement. Also, the first signal with a g value of 2.037 or more and 2.039 or less, the g value The sum of the spin densities of the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.96 6 or less is 1×10 18 spins / cm 3 not satisfied, and typically 1×10 17 spins / cm 3 or more and 1×10 18 spins / c m 3 less than.

[0181] In addition, in the ESR spectrum at 100 K or less, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the g value The sum of the spin densities of the third signal with a value of 1.964 or more and 1.966 or less corresponds to the sum of the spin densities of the signals caused by nitrogen oxides (NO x is greater than 0 and 2 or less, preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include nitric oxide, nitrogen dioxide, etc. x x That is, the smaller the sum of the spin densities of the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.966 or less, the lower the content of nitrogen oxides contained in the oxide insulating film. That is, the smaller the sum of the spin densities of the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.966 or less, the lower the content of nitrogen oxides contained in the oxide insulating film. That is, the smaller the sum of the spin densities of the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.966 or less, the lower the content of nitrogen oxides contained in the oxide insulating film.

[0182] In addition, the oxide insulating film has a nitrogen concentration of 6×10 20 atoms / cm 3 or less as measured by SIMS.

[0183] The substrate temperature is 220°C or more and 350°C or less, and by using the PECVD method using silane and dinitrogen monoxide to form the oxide insulating film, a dense and hard film can be formed. ​It can be achieved.

[0184] The insulating film 114 contains at least one of nitrogen and hydrogen. Examples of the insulating film 114 include nitride insulating films. Examples of the nitride insulating film include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc., which can be formed using them. The hydrogen concentration contained in the insulating film 114 is preferably 1×10 atoms / cm 22 or more. 3 In addition, the insulating film 114 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Also, the insulating film 114 has a region in contact with the conductive film 120. Therefore, the hydrogen concentration in the source region 108s, the drain region 108d, and the conductive film 120 in contact with the insulating film 114 increases, and the carrier density of the source region 108s, the drain region 108d, and the conductive film 120 can be increased. Note that the source region 108s, the drain region 108d, and the conductive film 120 may each have a region in contact with the insulating film 114 and having the same hydrogen concentration in the film.

[0185] The insulating films 116, 118, and 126 are formed using oxide insulating films containing more oxygen than oxygen satisfying the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition releases a part of oxygen by heating. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition has an oxygen release amount, in terms of oxygen atoms, of 1. 0×10 atoms / cm 19 or more, preferably 3.0×10 3 atoms / cm 20 or more. 3 ​​​​​​​​​The above is the case. The amount of oxygen released above is when the temperature of the heat treatment in TDS is 50°C or higher 650°C or lower, or the total amount in the range of 50°C or higher and 550°C or lower. Also, the above oxygen release amount is the total amount in terms of oxygen atoms in TDS.

[0186] As the insulating films 116, 118, and 126, silicon oxide, silicon oxynitride, etc. with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less can be used. It is possible.

[0187] Also, the insulating films 116, 118, and 126 preferably have a small amount of defects. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from silicon dangling bonds is 1.5×10 spins / cm 18 spins / cm 3 less than, and further preferably 1×10 18 sp ins / cm 3 or less.

[0188] Also, since the insulating film 124 and the insulating film 126 can use insulating films of the same material, there may be a case where the interface between the insulating film 124 and the insulating film 126 cannot be clearly confirmed. Therefore, in this embodiment, the interface between the insulating film 124 and the insulating film 126 is illustrated by a dashed line.

[0189] The insulating film 134 has a function as a protective insulating film for the transistor Tr1 and the transistor Tr2. It has.

[0190] The insulating film 134 has either one or both of hydrogen and nitrogen. Or, the insulating film 13 4 has nitrogen and silicon. Also, the insulating film 134 has oxygen, hydrogen, water, alkali metal It has a function capable of blocking metals such as alkali metals and alkaline earth metals. Providing the insulating film 134 can prevent the outward diffusion of oxygen from the oxide semiconductor films 108 and 128, the outward diffusion of oxygen contained in the insulating films 110, 116, 124, and 126, and the entry of hydrogen, water, etc. from the outside into the oxide semiconductor films 108 and 128.

[0191] As the insulating film 134, for example, a nitride insulating film can be used. Examples of such nitride insulating films include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc.

[0192] <Oxide semiconductor film> As the oxide semiconductor films 108 and 128, the materials shown above can be used respectively.

[0193] When the oxide semiconductor films 108 and 128 are In-M-Zn oxides, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In > M. Examples of such atomic ratios of the metal elements of the sputtering target include In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, etc.

[0194] Also, when the oxide semiconductor films 108 and 128 are In-M-Zn oxides, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide may be a composition that satisfies In ≤ M. Examples of such atomic ratios of the metal elements of the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2 ​​​​​​​​​​​​, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3 :6, etc. are mentioned. The atomic number ratio of the metal elements of the sputtering target used for film formation may be different between the oxide semiconductor film 108 and the oxide semiconductor film 128. That's fine.

[0195] Also, the oxide semiconductor film 108 and the oxide semiconductor film 128 have an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wide energy gap, the off-current of the transistor Tr1 and the transistor Tr2 can be reduced.

[0196] Also, the thicknesses of the oxide semiconductor film 108 and the oxide semiconductor film 128 are each 3 nm or more and 2 00 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0197] Also, the hydrogen contained in the oxide semiconductor film 108 and the oxide semiconductor film 128 reacts with the oxygen bonded to the metal atom to form water, and at the same time, oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, carriers i.e., electrons, may be generated. Also, a part of the hydrogen may bond with the oxygen bonded to the metal atom to generate carriers, i.e., electrons. Therefore, a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor film 108 and the oxide semiconductor film 128 is reduced as much as possible.

[0198] Specifically, in the oxide semiconductor film 108 and the oxide semiconductor film 128, the hydrogen concentration obtained by SIMS analysis is each 2×10 or less, preferably 5 20 atoms / cm 3 or less, more preferably 1×10 ×10 19 atoms / cm 3 or less, even more preferably 1×10 19 atoms / cm 3 or less, 5×10 or less, preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, even more preferably 1×10 17 atoms / cm 3 or less, still more preferably 1×10 16 atoms / cm 3 or less.

[0199] Further, if silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor film 108 and the oxide semiconductor film 128, the oxygen deficiency in the oxide semiconductor film 108 and the oxide semiconductor film 128 increases, resulting in n-type conversion. Therefore, the silicon concentration obtained by SIMS analysis in the oxide semiconductor film 108 and the oxide semiconductor film 128 is each 2× 10 or less, preferably 2×10 10 18 atoms / cm 3 or less. 17 atoms / cm 3 Further, the carbon concentration obtained by SIMS analysis in the oxide semiconductor film 108 and the oxide semiconductor film 128 is each 2×10 or less, preferably 2×10 18 atoms / cm 3 or less. 1 7 atoms / cm 3 or less. ​​

[0200] Also, in the oxide semiconductor film 108 and the oxide semiconductor film 128, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is set to 1×10 atoms 18 / cm / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals may generate carriers when combined with the oxide semiconductor, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film 108 and the oxide semiconductor film 128.

[0201] Note that as various films such as the conductive film and the insulating film described above, they can be formed by a sputtering method, a plasma enhanced chemical vapor deposition (PECVD) method, or a thermal chemical vapor deposition (CVD) method. As the thermal CVD method, an MO CVD (Metal Organic Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like can be mentioned. Vapor Deposition)) method, a thermal CVD (Chemical Vapor Deposition) method. Note that as the thermal CVD method, an MO CVD (Metal Organic Chemical Vapor Deposit ion) method, or an ALD (Atomic Layer Deposition) method, etc.

[0202] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0203] In the thermal CVD method, a source gas and an oxidizing agent are introduced into the chamber, the inside of the chamber is set to atmospheric pressure or under reduced pressure, and the reaction is carried out near the substrate or on the substrate to deposit on the substrate, thereby forming a film.​​​​ is also acceptable.

[0204] In addition, in the ALD method, the inside of the chamber may be set to atmospheric pressure or reduced pressure, and a raw material gas for the reaction may be used to form a film.

[0205] For example, when forming a hafnium oxide film using a film forming apparatus that utilizes ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakis(dimethylamido)hafnium (TDMAH), etc.) is vaporized to obtain a raw material gas, and two types of gases, ozone (O3) as an oxidizing agent and, are used. The chemical formula of tetrakis(dimethylamido)hafnium is Hf[N(CH3)2]4. In addition, as other material liquids, there are tetrakis(ethylmethylamido)hafnium, etc.

[0206] For example, when forming an aluminum oxide film using a film forming apparatus that utilizes ALD, a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA), etc.) is vaporized to obtain a raw material gas, and two types of gases, H2O as an oxidizing agent and, are used. The chemical formula of trimethylaluminum is Al(CH3)3. In addition, as other material liquids, there are tris(dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate), etc.

[0207] For example, when forming a silicon oxide film using a film forming apparatus that utilizes ALD, hexachlorodisilane is adsorbed on the film forming surface, chlorine contained in the adsorbed substance is removed, and radicals of an oxidizing gas (O2 , nitrous oxide) are supplied to react with the adsorbed substance.

[0208] ​​​​​​For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are used to form an initial tungsten film, and then, WF6 gas and H2 gas are used to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0209] <1-7. Configuration Example 2 of Semiconductor Device> Next, a modified example of the semiconductor device 100A shown in FIGS. 4(A) and (B) will be described with reference to FIG. 11.

[0210] FIG. 11 is a cross-sectional view of a modified example of the semiconductor device 100A shown in FIG. 4(B).

[0211] FIG. 11 shows a configuration in which a conductive film 130 that functions as a second gate electrode of the transistor Tr2 included in the semiconductor device 100A and an insulating film 134 on the conductive film 130 are not provided. Also, in FIG. 11, instead of the opening 182 provided in the insulating films 124 and 126 and the opening 184 provided in the insulating films 134 and 136, an opening 183 is provided in the insulating films 124, 126, and 136. In this way, having one opening is preferable because the manufacturing process can be reduced.

[0212]

[0213] <1-8. Configuration Example 3 of Semiconductor Device> Next, a modified example of the semiconductor device 100A shown in FIGS. 4(A) and (B) will be described with reference to FIGS. 12(A) and (B) and FIGS. 13(A) and (B).

[0213] Here, the laminated structure of the oxide semiconductor film will be described.

[0214] FIGS. 12(A) and (B) show the channel length of the transistor Tr2 included in the semiconductor device 100A. It is a cross-sectional view in the (L) direction.

[0215] FIG. 12(A) shows that the oxide semiconductor film 128 of the transistor Tr2 includes an oxide semiconductor film 128a, an oxide semiconductor film 128b on the oxide semiconductor film 128a, and an oxide semiconductor film 1 28b on the oxide semiconductor film 128c. That is, the oxide semiconductor film 1 28 has a three-layer stacked structure.

[0216] FIG. 12(B) shows that the oxide semiconductor film 128 of the transistor Tr2 includes an oxide semiconductor film 128b and an oxide semiconductor film 128c on the oxide semiconductor film 128b. That is, the oxide semiconductor film 128 has a two-layer stacked structure.

[0217] Even when the oxide semiconductor film 128 has a three-layer stacked structure or when the oxide semiconductor film 128 has a two-layer stacked structure, the oxide semiconductor film 128b is formed under the same film formation conditions as the oxide semiconductor film of Sample A when producing Sample 3 with the structure of the transistor shown in FIG. 7. In such a stacked structure of a transistor, in the saturation region in the Id-Vg measurement of the transistor, the difference between the minimum value and the maximum value of the field effect mobility is smaller than the difference between the minimum value and the maximum value of the field effect mobility when the oxide semiconductor film 128b is formed under the same film formation conditions as the oxide semiconductor film of Sample A1 when producing.

[0218] An example of the band structure of the oxide semiconductor film 128 and the insulating film in contact with the oxide semiconductor film 128 is shown in FIGS. 13(A) and 13(B). FIG. 13(A) shows an example of the band structure in the film thickness direction of a stacked structure including the insulating film 118, the oxide semiconductor films 128a, 128b, 128c, and the insulating film 124. ​is. Further, FIG. 13(B) is an example of the band structure in the film thickness direction of a stacked structure having an insulating film 118, oxide semiconductor films 128b and 128c, and an insulating film 124. Note that the band structure shows the energy levels (Ec) at the lower ends of the conduction bands of the insulating film 118, oxide semiconductor films 128a, 128b, 128 c, and insulating film 124 for ease of understanding.

[0219] Further, in FIG. 13(A), a silicon oxide film is used as the insulating film 118 and the insulating film 124, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 is used as the oxide semiconductor film 128a. An oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 4:2:4.1 is used as the oxide semiconductor film 128b, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 is used as the oxide semiconductor film 128c. This is a band diagram of a configuration.

[0220] Further, in FIG. 13(B), a silicon oxide film is used as the insulating film 118 and the insulating film 124, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 4:2:4.1 is used as the oxide semiconductor film 128b. An oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 is used as the oxide semiconductor film 128c. This is a band diagram of a configuration using a metal oxide film formed using the target.

[0221] As shown in FIGS. 13(A) and 13(B), in the oxide semiconductor films 128a, 128b, and 128c, the energy levels at the lower ends of the conduction bands change smoothly. In other words, they change continuously or It can also be said to be continuously joined. In order to have such a band structure, the oxide At the interface between the oxide semiconductor film 128a and the oxide semiconductor film 128b, or between the oxide semiconductor film 128b and At the interface with the oxide semiconductor film 128c, it is assumed that there are no impurities that form defect energy levels such as trap centers or recombination centers.

[0222] In order to form a continuous junction in the oxide semiconductor films 128a, 128b, and 128c, each film needs to be continuously laminated without being exposed to the atmosphere using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber.

[0223] By adopting the configuration shown in FIGS. 13(A) and 13(B), the oxide semiconductor film 128b becomes a well, and it can be seen that in the transistor using the above-described laminated structure, the channel region is formed in the oxide semiconductor film 12 8b.

[0224] Note that by providing the oxide semiconductor films 128a and 128c, the trap energy levels can be moved farther away from the oxide semiconductor film 128b.

[0225] Also, the energy level of the trap energy level may be farther from the vacuum level than the lower end of the conduction band (Ec) of the oxide semiconductor film 128b that functions as a channel region, and electrons are likely to accumulate in the trap energy level. When electrons accumulate in the trap energy level, it becomes a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, It is preferable to adopt a configuration such that the trap energy level is closer to the vacuum level than the energy level (Ec) of the lower end of the conduction band of the oxide semiconductor film 128b. By doing so, electrons are less likely to accumulate in the trap energy level. It becomes difficult for holes to accumulate, and it is possible to increase the on-current of the transistor, and the field-effect mobility can be increased.

[0226] Further, the lower ends of the conduction bands of the oxide semiconductor films 128a and 128c are closer to the vacuum level in energy level than that of the oxide semiconductor film 128b. Typically, the lower end of the conduction band of the oxide semiconductor film 128b and the energy levels of the lower ends of the conduction bands of the oxide semiconductor films 128a and 128c have a difference of 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference in electron affinity between the oxide semiconductor films 128a and 128c and the electron affinity of the oxide semiconductor film 128b is 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less. By having such a configuration, the oxide semiconductor film 128b becomes the main path of the current and functions as the channel

[0227] region. Further, since the oxide semiconductor films 128a and 128c are oxide semiconductor films composed of one or more of the metal elements constituting the oxide semiconductor film 128b in which the channel region is formed, interface scattering hardly occurs at the interface between the oxide semiconductor film 128a and the oxide semiconductor film 128b, and also at the interface between the oxide semiconductor film 128b and the oxide semiconductor film 128c. Therefore, carrier movement is not inhibited at the interface, and the field-effect mobility of the transistor increases.

[0228] In addition, in order to prevent the oxide semiconductor films 128a and 128c from functioning as part of the channel region, a material with a sufficiently low conductivity is used. Or, in the oxide semiconductor films 128a and 1 28c, the electron affinity (the difference between the vacuum level and the energy level of the lower end of the conduction band) is the oxide semiconductor ​ Smaller than the body film 128b, and a material having an energy level at the lower end of the conduction band different from (band offset) the energy level at the lower end of the conduction band of the oxide semiconductor film 128b is used. Further, in order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, it is preferable to use a material in which the energy levels at the lower ends of the conduction bands of the oxide semiconductor films 128a and 128c are closer to the vacuum level than the energy level at the lower end of the conduction band of the oxide semiconductor film 128b. For example, it is preferable that the difference between the energy level at the lower end of the conduction band of the oxide semiconductor film 128b and the energy levels at the lower ends of the conduction bands of the oxide semiconductor films 128a and 128c is 0.2 eV or more, preferably 0.5 eV or more. The film thicknesses of the oxide semiconductor films 128a and 128c are equal to or greater than a film thickness that can suppress the constituent elements of the conductive films 122a and 122b from diffusing into the oxide semiconductor film 128b, and less than a film thickness that can suppress the supply of oxygen from the insulating film 124 to the oxide semiconductor film 128b. For example, when the film thicknesses of the oxide semiconductor films 128a and 128c are 10 nm or more, the constituent elements of the conductive films 122a and 122b can be suppressed from diffusing into the oxide semiconductor film 128b. Also, when the film thicknesses of the oxide semiconductor films 128a and 128c are 100 nm or less, oxygen can be effectively supplied from the insulating film 124 to the oxide semiconductor film 128b. When the oxide semiconductor films 128a and 128c are In-M-Zn oxides (M is Al, Ga, Y, or Sn), by having M at a higher atomic ratio than In, the energy gap of the oxide semiconductor films 128a and 128c can be increased and the electron affinity can be decreased. Thus,

[0229] The film thicknesses of the oxide semiconductor films 128a and 128c are equal to or greater than a film thickness that can suppress the constituent elements of the conductive films 122a and 122b from diffusing into the oxide semiconductor film 128b, and less than a film thickness that can suppress the supply of oxygen from the insulating film 124 to the oxide semiconductor film 128b. For example, when the film thicknesses of the oxide semiconductor films 128a and 128c are 10 nm or more, the constituent elements of the conductive films 122a and 122b can be suppressed from diffusing into the oxide semiconductor film 128b. Also, when the film thicknesses of the oxide semiconductor films 128a and 128c are 100 nm or less, oxygen can be effectively supplied from the insulating film 124 to the oxide semiconductor film 128b. When the oxide semiconductor films 128a and 128c are In-M-Zn oxides (M is Al, Ga, Y, or Sn), by having M at a higher atomic ratio than In, the energy gap of the oxide semiconductor films 128a and 128c can be increased and the electron affinity can be decreased. Thus, when the film thicknesses of the oxide semiconductor films 128a and 128c are 100 nm or less, oxygen can be effectively supplied from the insulating film 124 to the oxide semiconductor film 128b. oxygen can be effectively supplied from the insulating film 124 to the oxide semiconductor film 128b.

[0230] When the oxide semiconductor films 128a and 128c are In-M-Zn oxides (M is Al, Ga, Y, or Sn), by having M at a higher atomic ratio than In, the energy gap of the oxide semiconductor films 128 a and 128c can be increased and the electron affinity can be decreased. Thus, In the case where it is possible to control the difference in electron affinity between the compound semiconductor film 128b and the compound semiconductor film 128a by the composition of M, In addition, M is a metal element that has a strong bond with oxygen, so these elements can be By having a higher atomic ratio, oxygen deficiency is less likely to occur.

[0231] When the oxide semiconductor films 128a and 128c are made of an In-M-Zn oxide, Zn and The atomic ratio of In and M excluding O is preferably such that In is less than 50 atomic %. M is less than 50 atomic %, and more preferably In is less than 25 atomic %. In addition, M is set to be higher than 75 atomic %. Alternatively, a gallium oxide film may be used.

[0232] When the oxide semiconductor films 128a, 128b, and 128c are made of In-M-Zn oxide, Compared with the oxide semiconductor film 128b, the amount of M contained in the oxide semiconductor films 128a and 128c is The atomic ratio is large, typically compared to the above atoms contained in the oxide semiconductor film 128b. The atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher.

[0233] When the oxide semiconductor films 128a, 128b, and 128c are made of In-M-Zn oxide, The oxide semiconductor film 128b is formed by forming an oxide semiconductor film having an atomic ratio of In:M:Zn=x1:y1:z1. When the film 128a and the film 128c are In:M:Zn=x2:y2:z2 [atomic ratio], y 2 / x2 is greater than y1 / x1, and preferably y2 / x2 is greater than y1 / x1 by 1.5 More preferably, y2 / x2 is at least twice as large as y1 / x1, and Preferably, y2 / x2 is three or four times larger than y1 / x1. In the oxide semiconductor film 128b, when y1 is equal to or greater than x1, it is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor film 128b. However, when y1 becomes three times or more of x1, the field-effect mobility of the transistor using the oxide semiconductor film 128b decreases. Therefore, it is preferable that y1 is less than three times of x1. It is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor film 128b. However, when y1 is three times or more of x1, the field-effect mobility of the transistor using the oxide semiconductor film 128b decreases. Therefore, it is preferable that y1 is less than three times of x1.

[0234] When the oxide semiconductor film 128b is an In-M-Zn oxide, in the target used for forming the oxide semiconductor film 128b, if the atomic ratio of the metal elements is In:M:Zn = x1:y 1:z1, then x1 / y1 is equal to or greater than 1 / 3 and equal to or less than 6, and further preferably equal to or greater than 1 and equal to or less than 6. 、 z1 / y1 is preferably equal to or greater than 1 / 3 and equal to or less than 6, and further preferably equal to or greater than 1 and equal to or less than 6. By setting z1 / y1 to be equal to or greater than 1 and equal to or less than 6, it becomes easier to form the CAAC- OS described later as the oxide semiconductor film 128b. Representative examples of the atomic ratio of the metal elements in the target include In :M:Zn = 4:2:4.1, In:M:Zn = 1:1:1.2, In:M:Zn = 3: 1:2, etc. :M:Zn = 4:2:4.1, In:M:Zn = 1:1:1.2, In:M:Zn = 3: 1:2, etc.

[0235] Further, when the oxide semiconductor films 128a and 128c are In-M-Zn oxides, in the target used for forming the oxide semiconductor films 128a and 128c, if the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2, then x2 / y2 < x1 / y1, and it is preferable that z2 、 / y2 is equal to or greater than 1 / 3 and equal to or less than 6, and further preferably equal to or greater than 1 and equal to or less than 6. Also, by increasing the atomic ratio of M to In, it is possible to increase the energy gap and decrease the electron affinity of the oxide semiconductor films 128a and 128c. Therefore, y2 / x2 is increased, and the electron affinity is decreased. It is possible to increase the energy gap and decrease the electron affinity of the oxide semiconductor films 128a and 128c. Therefore, y2 / x2 is It is preferably 3 or more, or 4 or more. Representative examples of the atomic ratio of the target metal element include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:5, In:M:Zn = 1:3:6, In:M:Zn = 1:4:2, In:M: Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:5:5, etc. .

[0236] Note that the atomic ratios of the oxide semiconductor films 128a, 128b, and 128c each include a variation of plus or minus 40% of the above atomic ratio as an error.

[0237] Note that in FIGS. 12(A) and 12(B), the oxide semiconductor film 128 of the transistor Tr2 is illustrated as having a stacked structure of two layers and three layers. However, the oxide semiconductor film 10 8 of the transistor Tr1 may have a similar configuration.

[0238] Thus, as the semiconductor device of the present invention, it may be applied by changing the presence or absence of the second gate electrode or the stacked structure of the oxide semiconductor film. Further, the transistor according to the present embodiment can freely combine each of the above-described structures.

[0239] <1-9. Method for manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device 100A according to one aspect of the present invention will be described with reference to FIGS. 14 to 23.

[0240] Note that FIGS. 14(A), 15(A), 16(A), 17(A), 18(A), 1 9(A), 20(A), 21(A), 22(A), and 23(A) are top views for explaining the method for manufacturing the semiconductor device 100A, and FIGS. 14(B), 15(B), 16( B), FIG. 17(B), FIG. 18(B), FIG. 19(B), FIG. 20(B), FIG. 21(B), FIG. 22(B), and FIG. 23(B) are cross-sectional views taken along line A-A' in FIGS. 14(A), 15(A), 16(A), 17(A), 18(A), 19(A), 20(A), 21(A), 22(A), and 23(A), respectively. B), FIGS. 17(B), 18(B), 19(B), 20(B), 21(B), 2 2(B), and FIG. 23(B) are cross-sectional views for explaining a method of manufacturing the semiconductor device 100A .

[0241] First, an insulating film 106 is formed on a substrate 102, and an oxide semiconductor film is formed on the insulating film 106 . Then, by processing the oxide semiconductor film into an island shape, an oxide semiconductor film 108 is formed (see FIGS. 14(A)(B)).

[0242] In this embodiment, a glass substrate can be used as the substrate 102

[0243] As the insulating film 106, it can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (P LD) method, a printing method, a coating method, etc. In this embodiment , as the insulating film 106, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are formed using a PECVD apparatus

[0244] Also, after forming the insulating film 106, oxygen may be added to the insulating film 106. As the oxygen added to the insulating film 106 , there are oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc . Also, as the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method , etc. Also, after forming a film for suppressing the desorption of oxygen on the insulating film 106, oxygen may be added to the insulating film 106 through the film .

[0245] As the film for suppressing the desorption of the above-mentioned oxygen, indium, zinc, gallium, tin, aluminum , chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten Selected metal elements, alloys containing the above-described metal elements as components, alloys combining the above-described metal elements alloys, metal nitrides containing the above-described metal elements, metal oxides containing the above-described metal elements, and materials having conductivity such as metal oxynitrides containing the above-described metal elements can be formed by using them. It is possible.

[0246] In addition, when oxygen is added by plasma treatment, oxygen is excited by microwaves to generate a high-density oxygen plasma, thereby increasing the amount of oxygen added to the insulating film 106.

[0247] The oxide semiconductor film 108 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that for processing the oxide semiconductor film 108, a mask is formed on the oxide semiconductor film by a lithography process, and then a part of the oxide semiconductor film is etched using the mask to form it. Alternatively, the element-isolated oxide semiconductor film 108 may be directly formed using a printing method.

[0248] When forming the oxide semiconductor film by the sputtering method, a power supply device for generating plasma can be appropriately used, such as an RF power supply device, an AC power supply device, or a DC power supply device. Also, the sputtering gas when forming the oxide semiconductor film is appropriately used with a noble gas (typically argon), oxygen, or a mixed gas of a noble gas and oxygen. In the case of a mixed gas of a noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0249] Note that in this embodiment, as the oxide semiconductor film 108, a sputtering apparatus is used and as the sputtering target, an In-Ga-Zn metal oxide (In:Ga:Zn = Using a 4:2:4.1 [atomic ratio], an oxide semiconductor film with a thickness of 40 nm is formed. At this time, the substrate is heated to 170 °C, and argon gas with a flow rate of 140 sccm and a flow rate of 60 sccm of oxygen gas are introduced into the film formation chamber of the sputtering apparatus.

[0250] Further, after forming the oxide semiconductor film 108, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 108. The temperature of the heat treatment is typically 150 °C or higher and less than the substrate distortion point, or 250 °C or higher and 450 °C or lower, or 300 °C or higher and 450 °C or lower.

[0251] The heat treatment can be performed in an inert gas atmosphere such as helium, neon, argon, xenon, krypton, etc., or nitrogen containing inert gas. Or, after heating in an inert gas atmosphere it may be heated in an oxygen atmosphere. Note that it is preferable that the above inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time may be 3 minutes or more and 24 hours or less.

[0252] The heat treatment can use an electric furnace, an RTA device, etc. By using an RTA device it is possible to perform heat treatment at a temperature equal to or higher than the distortion point of the substrate in a short time. Therefore, the heat treatment time can be shortened.

[0253] By forming the oxide semiconductor film while heating or performing heat treatment after forming the oxide semiconductor film [[ID=…]] in the oxide semiconductor film, the hydrogen concentration obtained by secondary ion mass spectrometry is 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 or less. [[ID=…]] 5×10 18 atoms / cm3 The following, or 1×10 18 atoms / cm 3 The following, or or 5×10 17 atoms / cm 3 The following, or 1×10 16 atoms / cm 3 The following can be set as such.

[0254] Next, an insulating film and a conductive film are formed on the insulating film 106 and the oxide semiconductor film 108, and are processed into an island shape to form the insulating film 110 and the conductive film 120 (see FIGS. 15(A) and (B)).

[0255] As the insulating film 110, a silicon oxide film or a silicon oxynitride film can be formed by using the PECVD method. In this case, as the source gas, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0256] Also, as the insulating film 110, the flow rate of the oxidizing gas is made more than 20 times and less than 100 times, or 40 times or more and 80 times or less than the flow rate of the depositable gas, and the pressure in the processing chamber is made less than 100 Pa, or 50 Pa or less. By using the PECVD method, a silicon oxynitride film with a small amount of defects can be formed.

[0257] Also, as the insulating film 110, the substrate placed in the processing chamber evacuated by the PECVD apparatus is maintained at 280°C or higher and 400°C or lower, and the source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 250 Pa or lower. , under the condition of supplying high-frequency power to the electrode provided in the processing chamber, as the insulating film 110, a dense silicon oxide film or silicon oxynitride film can be formed.

[0258] Also, the insulating film 110 may be formed by using a plasma CVD method using microwaves. Microwaves refer to the frequency range from 300 MHz to 300 GHz. In microwaves, the electron temperature is low and the electron energy is small. Also, in the supplied power, the proportion used for accelerating electrons is small, and it is possible to use more for dissociation and ionization of molecules, and a plasma with high density (high-density plasma) can be excited. Therefore, the insulating film 110 with less plasma damage to the film-forming surface and deposits and fewer defects can be formed.

[0259] Also, the insulating film 110 can be formed by using a CVD method using an organic silane gas. As the organic silane gas, silicon-containing compounds such as tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), tris dimethylaminosilane (SiH(N(CH3)2)3) can be used. By using a CVD method using an organic silane gas, an insulating film 110 with high covering property can be formed.

[0260] In this embodiment, as the insulating film 110, a plasma enhanced chemical vapor deposition (PECVD) apparatus is used to form a silicon oxynitride film with a thickness of 150 nm.

[0261] Further, the conductive film 120 is preferably formed of an oxide conductor (OC). When forming the conductive film 120, oxygen is added from the conductive film 120 into the insulating film 110. When forming the conductive film 120, oxygen is added from the conductive film 120 into the insulating film 110.

[0262] As a method for forming the conductive film 120, a sputtering method is preferably used, and it is preferably formed in an atmosphere containing oxygen gas during formation. By forming the conductive film 120 in an atmosphere containing oxygen gas during formation, oxygen can be suitably added into the insulating film 110. When forming the conductive film 120, oxygen is added from the conductive film 120 into the insulating film 110. When forming the conductive film 120, oxygen is added from the conductive film 120 into the insulating film 110.

[0263] Note that, as the conductive film 120, the same material as the oxide semiconductor film 108 described above can be used. Note that, as the conductive film 120, the same material as the oxide semiconductor film 108 described above can be used.

[0264] In this embodiment, as the conductive film 120, a sputtering apparatus is used, and an In-Ga-Zn metal oxide (In:Ga:Zn = 5:1:7 [atomic number ratio]) is used as a sputtering target to form a conductive film with a film thickness of 20 nm. In this embodiment, as the conductive film 120, a sputtering apparatus is used, and an In-Ga-Zn metal oxide (In:Ga:Zn = 5:1:7 [atomic number ratio]) is used as a sputtering target to form a conductive film with a film thickness of 20 nm. In this embodiment, as the conductive film 120, a sputtering apparatus is used, and an In-Ga-Zn metal oxide (In:Ga:Zn = 5:1:7 [atomic number ratio]) is used as a sputtering target to form a conductive film with a film thickness of 20 nm.

[0265] In this embodiment, the conductive film 120 and the insulating film 110 are processed using a dry etching method. In this embodiment, the conductive film 120 and the insulating film 110 are processed using a dry etching method.

[0266] Note that, when processing the conductive film 120 and the insulating film 110, the film thickness of the oxide semiconductor film 108 in a region where the conductive film 120 does not overlap may become thin. Note that, when processing the conductive film 120 and the insulating film 110, the film thickness of the oxide semiconductor film 108 in a region where the conductive film 120 does not overlap may become thin.

[0267] Next, impurity elements are added onto the insulating film 106, the oxide semiconductor film 108, and the conductive film 120. Next, impurity elements are added onto the insulating film 106, the oxide semiconductor film 108, and the conductive film 120.

[0268] Examples of the method for adding impurity elements include an ion doping method, an ion implantation method, a plasma treatment method, etc. In the case of the plasma treatment method, plasma is generated in a gas atmosphere containing the impurity element to be added. Examples of the method for adding impurity elements include an ion doping method, an ion implantation method, a plasma treatment method, etc. In the case of the plasma treatment method, plasma is generated in a gas atmosphere containing the impurity element to be added. By causing generation and performing plasma treatment, impurity elements can be added. The above As the apparatus for generating plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0269] Note that as the source gas for impurity elements, one or more of B2H6, PH3, CH4, N2, NH3, AlH 3, AlCl3, SiH4, Si2H6, F2, HF, H2, and rare gases can be used. Alternatively, one or more of B2H6, PH3, N2, NH3, AlH3 , AlCl3, F2, HF, and H2 diluted with a rare gas can be used. Diluted with a rare gas B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 By adding one or more of the above to the oxide semiconductor film 108 and the conductive film 120, one or more of rare gases, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 108 and the conductive film 120.

[0270] Alternatively, after adding a rare gas, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, A lCl3, SiH4, Si2H6, F2, HF, and H2 may be added to the oxide semiconductor film 10 8 and the conductive film 120.

[0271] Alternatively, after adding one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2, a rare gas may be added to the oxide semiconductor film 10 8 and the conductive film 120.

[0272] The addition of impurity elements may be controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. . For example, when adding argon by ion implantation, the acceleration voltage is 10 kV or more and 100 kV Hereinafter, the dose amount is 1×10 13 ions / cm 2 or more and 1×10 16 ions / cm 2 or less is sufficient. For example, 1×10 14 ions / cm 2 is sufficient. Also, when adding phosphorus ions by ion implantation , the acceleration voltage is 30 kV, and the dose amount is 1×10 13 ions / cm 2 or more and 5×10 16 ions / cm 2 or less is sufficient. For example, 1×10 15 i ons / cm 2 is sufficient.

[0273] Also, in the present embodiment, as an impurity element, argon is added to the oxide semiconductor film 108 and the conductive film 120 using a doping device. Note that in the present embodiment, although the configuration of adding argon as an impurity element is exemplified, it is not limited thereto. For example, a configuration of adding nitrogen may be used. Also, for example, the step of adding an impurity element may not be performed.

[0274] Next, an insulating film 114 is formed on the insulating film 106, the oxide semiconductor film 108, and the conductive film 120. Note that by forming the insulating film 114, the oxide semiconductor film 10 8 that is in contact with the insulating film 114 becomes the source region 108s and the drain region 108d. Also, the oxide semiconductor film 108 that is not in contact with the insulating film 114, that is, the oxide semiconductor film 108 that is in contact with the insulating film 110 becomes the channel region 108i. Thereby, the channel region 108i, the source region 108s, And an oxide semiconductor film 108 having a drain region 108d is formed (see FIGS. 16(A)( B)).

[0275] As the insulating film 114, in the present embodiment, a silicon nitride film with a thickness of 100 n m is formed using a PECVD apparatus.

[0276] By using a silicon nitride film as the insulating film 114, hydrogen and nitrogen in the silicon nitride film enter one or both of the conductive film 12 0, the source region 108s, and the drain region 108d, and the carrier density of the conductive film 120, the source region 108s, and the drain region 108d can be increased.

[0277] Next, an insulating film 116 is formed on the insulating film 114.

[0278] As the insulating film 116, in the present embodiment, a silicon oxynitride film with a thickness of 300 n m is formed using a PECVD apparatus.

[0279] Next, after forming a mask by lithography at a desired position of the insulating film 116, a part of the insulating film 1 16 and the insulating film 114 is etched to form an opening portion 141a reaching the source region 108s and an opening portion 141b reaching the drain region 108d (see FIGS. 16( A)(B)).

[0280] As a method for etching the insulating film 116 and the insulating film 114, a wet etching method and / or a dry etching method can be appropriately used. In the present embodiment, a dry etching method is used to process the insulating film 116 and the insulating film 114.

[0281] ​Next, a conductive film is formed on the insulating film 116 so as to cover the openings 141a and 141b, and after forming a mask at a desired position by a lithography process, a part of the conductive film is etched to form the conductive films 112a and 112b (see FIGS. 16(A) and (B)).

[0282] As the conductive films 112a and 112b, in this embodiment, a sputtering apparatus is used to form a laminated film of a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm.

[0283] As a processing method for the conductive films 112a and 112b, a wet etching method and / or a dry etching method can be appropriately used. In this embodiment, the dry etching method is used to process the conductive film and form the conductive films 112a and 112b.

[0284] Through the above steps, the transistor Tr1 can be fabricated.

[0285] Note that the films (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor Tr1 can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD (atomic layer deposition) method. Alternatively, it can be formed by a coating method or a printing method . As a film formation method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may also be used. As an example of the thermal CVD method, MO CVD (metalorganic chemical vapor deposition) method can be cited.

[0286] In the thermal CVD method, the inside of the chamber is set at atmospheric pressure or reduced pressure, and a raw material gas and an oxidizing agent are simultaneously introduced into the cha It is sent into the number, reacted near or on the substrate, and deposited on the substrate to form a film. Thus, since the thermal CVD method is a film-forming method that does not generate plasma, it has the advantage that defects are not generated due to plasma damage.

[0287] Also, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and a raw material gas for reaction is introduced into the chamber and reacted, and film formation is performed by repeating this. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the raw material gas. For example, two or more types of raw material gases may be supplied to the chamber in order. At that time, after the reaction of the first raw material gas so that a plurality of types of raw material gases do not mix, an inert gas is introduced, and the second raw material gas is introduced . Alternatively, instead of introducing an inert gas, after discharging the first raw material gas by evacuation, the second raw material gas may be introduced . The first raw material gas is adsorbed and reacted on the surface of the substrate to form the first layer, and the second raw material gas introduced later is adsorbed and reacted, and the second layer is laminated on the first layer to form a thin film. By repeating this a plurality of times until the desired thickness is reached while controlling this gas introduction order, a thin film excellent in step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times of repeating gas introduction, precise film thickness adjustment is possible , and it is suitable for manufacturing a fine FET. Thermal CVD methods such as the MOCVD method can form films such as the conductive films, insulating films, oxide semiconductor films, and metal oxide

[0288] films described above. For example, when forming an In-Ga-Zn-O film 3), trimethylgallium (Ga(CH3) 3), and dimethylzinc (Zn(CH3)2). First, triethylgallium (Ga(C2H5)3) is used instead of trimethylgallium. Dimethyl zinc can also be replaced by diethyl zinc (Zn(C2H5)2). Cut.

[0289] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0290] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas, which is vaporized from other materials, and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0291] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are supplied. is fed to react with the adsorbate.

[0292] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. S and B2H6 gas are sequentially introduced to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H 2 gas. Note that SiH4 gas may be used instead of B2H6 gas.

[0293] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using an ALD-based film-forming apparatus, an In-O layer is formed using In(CH3)3 gas and O3 gas, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and further, ZnO layer is formed using Zn(CH3)2 gas and O3 gas. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H.

[0294] Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 112a and 112b.

[0295] As the insulating film 118, it can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (P LD) method, a printing method, a coating method, etc. In the present embodiment a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are formed as the insulating film 118 using a PECVD apparatus.

[0296] Also, after forming the insulating film 118, oxygen may be added to the insulating film 118. As the oxygen added to the insulating film 118 are oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. ​​There is also. As the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Also, after forming a film that suppresses the desorption of oxygen on the insulating film, oxygen is added to the insulating film 118 through the film.

[0297] As the film that suppresses the desorption of oxygen described above, indium, zinc, gallium, tin, aluminum , chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten selected metal elements, alloys containing the above-described metal elements as components, alloys combining the above-described metal elements , metal nitrides having the above-described metal elements, metal oxides having the above-described metal elements, materials having conductivity such as metal oxynitrides having the above-described metal elements can be used to form .

[0298] Also, when adding oxygen by plasma treatment, oxygen is excited by microwaves to generate a high-density oxygen plasma, thereby increasing the amount of oxygen added to the insulating film 118.

[0299] Also, the silicon nitride film used as the insulating film 118 has a laminated structure. Specifically, the silicon nitride film can have a three-layer laminated structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. As an example of the three-layer laminated structure, it can be formed as follows .

[0300] As the first silicon nitride film, for example, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 s ccm, and ammonia gas with a flow rate of 100 sccm are supplied as source gases to the reaction chamber of a PE-CVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency of 27.12 MHz Supply 2000 W of power using a radio frequency power supply and form it to a thickness of 50 nm. That's all.

[0301] As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm are used as source gases and supplied to the reaction chamber of a PECVD apparatus. Control the pressure in the reaction chamber to 100 Pa, supply 2000 W of power using a 27.12 MHz radio frequency power supply, and form it to a thickness of 300 nm.

[0302] As the third silicon nitride film, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are used as source gases and supplied to the reaction chamber of a PECVD apparatus. Control the pressure in the reaction chamber to 1 hundred Pa, supply 2000 W of power using a 27.12 MHz radio frequency power supply, and form it to a thickness of 50 nm.

[0303] Note that the substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be 350 °C or lower. By forming the insulating film 118 into a three-layer stacked structure of silicon nitride films, for example, when conductive films containing copper (Cu) are used for the conductive films 112a and 112b, the following effects can be achieved.

[0304] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive films 112a and 112b. The second silicon nitride film has a function of releasing hydrogen and can improve the breakdown voltage of the insulating film that functions as a gate insulating film. The third silicon nitride film has less hydrogen release from the third silicon nitride film and the hydrogen released from the second silicon nitride film. When using a conductive film containing copper (Cu) for the conductive films 112a and 112b, the following effects can be achieved.

[0305] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive films 112a and 112b. The second silicon nitride film has a function of releasing hydrogen and can improve the breakdown voltage of the insulating film that functions as a gate insulating film. The third silicon nitride film can reduce the hydrogen release from the third silicon nitride film and the hydrogen released from the second silicon nitride film. is small, and the hydrogen released from the second silicon nitride film Hydrogen diffusion can be suppressed.

[0306] Next, an oxide semiconductor film 128 is formed on the insulating film 118 (see FIGS. 17(A) and 17(B)).

[0307] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn = 4:2 :4.1 [atomic ratio]) is used to form an oxide semiconductor film by sputtering. Also, the substrate temperature during the formation of the oxide semiconductor film is set to room temperature (R.T.), and argon gas with a flow rate of 180 scc m and oxygen gas with a flow rate of 20 sccm are used. Then, the oxide semiconductor film is processed into a desired shape to form island-shaped oxide semiconductor films 128. Note that a wet etching apparatus is used for the formation of the oxide semiconductor film.

[0308] Next, a conductive film is formed on the insulating film 118 and the oxide semiconductor film 128, and the conductive film is processed into a desired shape to form conductive films 122a and 122b. Then, insulating films 124 and 126 are formed on the insulating film 118, the oxide semiconductor film 128, and the conductive films 122a and 122b (see FIGS. 18(A) and 18(B)).

[0309] In this embodiment, as the conductive films 122a and 122b, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm are sequentially laminated, and the laminated film is formed by sputtering.

[0310] Also, after the formation of the conductive films 122a and 122b, the surface (back channel side) of the oxide semiconductor film 128 may be cleaned. As the cleaning method, for example, an etchant such as an aqueous phosphoric acid solution As a result, impurities attached to the surface of the oxide semiconductor film 128 can be removed. Impurities (for example, elements contained in the conductive films 122a and 122b) can be removed. It should be noted that this cleaning is not necessarily required, and in some cases cleaning may not be necessary.

[0311] In addition, either one of the steps of forming the conductive films 122a and 122b and the cleaning step may be performed. In both cases, the regions of the oxide semiconductor film 128 that are exposed from the conductive films 122a and 122b are , may become thinner.

[0312] In this embodiment, a silicon oxynitride film having a thickness of 20 nm is used as the insulating film 124. 26, a silicon oxynitride film with a thickness of 200 nm is formed using the PECVD method. do.

[0313] After the insulating film 124 is formed, the insulating film 126 is successively formed without exposing the insulating film 124 to the air. After the insulating film 124 is formed, it is preferable to control the flow rate, pressure, and high frequency of the source gas without exposing the insulating film 124 to the atmosphere. By adjusting one or more of the wave power and the substrate temperature, the insulating film 126 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the film 124 and the insulating film 126. At the same time, oxygen contained in the insulating films 124 and 126 is transferred to the oxide semiconductor film 128. As a result, the amount of oxygen vacancies in the oxide semiconductor film 128 can be reduced.

[0314] In this embodiment, the insulating film 124 is formed by heating the substrate 102 at a temperature of 220° C. Silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as raw material gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 MHz. z, 100 W (as a power density of 1.6×10 -2 W / cm 2 ), the PECVD method is used to form a silicon oxynitride film.

[0315] As the insulating film 126, a substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 180 °C or higher and 350 °C or lower, and a source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower, and high-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied under the condition of forming a silicon oxide film or a silicon oxynitride film.

[0316] As the film formation conditions of the insulating film 126, by supplying high-frequency power of the above power density in the reaction chamber of the above pressure, the decomposition efficiency of the source gas in the plasma increases, oxygen radicals increase, and the oxidation of the source gas proceeds. Therefore, the oxygen content in the insulating film 126 becomes higher than the stoichiometric composition. On the other hand, for the film formed at the above temperature, since the bonding force between silicon and oxygen is weak, a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and from which a part of the oxygen desorbs by heating can be formed. Note that in the formation process of the insulating film 126, the insulating film 124 becomes a protective film of the oxide semiconductor film 128. Therefore, while reducing the damage to the oxide semiconductor film 128, with a high power density an insulating film can be formed.

[0317] In addition, in the formation process of the insulating film 126, the insulating film 124 serves as a protective film for the oxide semiconductor film 128. Therefore, while reducing the damage to the oxide semiconductor film 128, with a high power density The insulating film 126 can be formed using low high frequency power.

[0318] In the film formation conditions for the insulating film 126, the ratio of a deposition gas containing silicon to an oxidizing gas is By increasing the flow rate, it is possible to reduce the number of defects in the insulating film 126. appears at g=2.001 due to the dangling bond of silicon by ESR measurement. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 s pins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 Defects that are less than As a result, the reliability of the transistor Tr2 is improved. It can improve sexuality.

[0319] After the insulating films 124 and 126 are formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove nitrogen oxides contained in the insulating films 124 and 126. Alternatively, the first heat treatment can reduce the amount of the oxides contained in the insulating films 124 and 126. Part of the oxygen contained in the oxide semiconductor film 128 is moved to the oxide semiconductor film 128. The amount of oxygen deficiency can be reduced.

[0320] The temperature of the first heat treatment is typically less than 400°C, preferably less than 375°C, and The temperature is preferably 150° C. or higher and 350° C. or lower. The first heat treatment is carried out in an atmosphere of nitrogen, oxygen, or ultra-dry. Air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less) The reaction can be carried out under an atmosphere of air (see above) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. Heat treatment is performed using an electric furnace, RTA (Rapid Thermal Anneal), etc. It is possible.

[0321] Next, openings 182 reaching the conductive film 122a are formed in desired regions of the insulating films 124 and 126. After that, a conductive film 130 is formed on the insulating film 126 and the conductive film 122a (FIG. 19( See A)(B)).

[0322] The opening 182 is formed using a dry etching device or a wet etching device. The conductive film 130 is made of an oxide containing indium, tin, and silicon (IT SO) target (In2O3:SnO2:SiO2 = 85:10:5 [wt% ]) to form a 100 nm thick ITSO film, which is then processed into island shapes.

[0323] Through the above steps, the transistor Tr2 can be fabricated.

[0324] Next, an insulating film 126 and an insulating film 134 are formed on the conductive film 130, and an insulating film 136 is formed on the conductive film 130. Then, a laminated film is formed by applying a conductive film 130 to a desired region of the laminated film. An opening 184 is formed (see FIGS. 20(A) and 20(B)).

[0325] The insulating film 134 is a silicon oxynitride film having a thickness of 200 nm, which is deposited by the PECVD method. The insulating film 136 is a photosensitive acrylic resin film having a thickness of 1.5 μm. Form.

[0326] The opening 184 is formed using a dry etching device or a wet etching device. .

[0327] Next, a conductive film is formed on the insulating film 136 and the conductive film 130, and the conductive film is processed into an island shape. Thereby, the conductive film 138 is formed (see FIGS. 21(A) and (B)).

[0328] In the present embodiment, as the conductive film 138, an ITSO film with a thickness of 10 nm, a reflective metal film with a thickness of 200 n m (here, a metal film containing silver, palladium, and copper), and a laminated film of an ITSO film with a thickness of 10 nm are used. Further, a wet etching device is used for processing the conductive film 138.

[0329] Next, an island-shaped insulating film 140 is formed on the insulating film 136 and the conductive film 138 (see FIGS. 22(A) (B)).

[0330] As the insulating film 140, a photosensitive polyimide-based resin film with a thickness of 1.5 μm is used.

[0331] Next, an EL layer 142 is formed on the conductive film 138, and then a conductive film 144 is formed on the insulating film 140 and the EL layer 142 to form a light-emitting element 160 (see FIGS. 23(A) and (B)). Reference).

[0332] The method for forming the light-emitting element 160 will be described in detail in Embodiment 4.

[0333] Through the above steps, the semiconductor device 100A shown in FIGS. 4(A) and (B) can be formed.

[0334] From the above, when comparing the heat histories after the oxide semiconductor film 108 and the oxide semiconductor film 128 are each formed, it can be seen that the heat history of the oxide semiconductor film 108 is greater. This is because at least an insulating layer is present from after the formation of the oxide semiconductor film 108 until before the formation of the oxide semiconductor film 128. This is because the substrate is heated when the film 110, the insulating film 118, and the like are formed.

[0335] In order to improve the reliability of a transistor, a method for reducing oxygen vacancies in an oxide semiconductor film is required. While it is necessary to have a sufficient heat treatment time, in order to reduce manufacturing costs, It is effective to keep the temperature as low as possible and the heat treatment time as short as possible. In one embodiment of the present invention, as illustrated in FIG. 24, the oxide semiconductor film 128 is made of an oxide semiconductor. Oxygen is more likely to diffuse into the oxide semiconductor film 128 than into the conductive film 108. However, oxygen vacancies are reduced by heat treatment for a shorter time or at a lower temperature than in the oxide semiconductor film 108. In other words, it is possible to reduce the amount of oxygen that easily diffuses into the film, which is one aspect of the present invention. The use of a silicon film as the oxide semiconductor film 128 is effective in reducing the manufacturing cost. do.

[0336] Also, for example, consider a case where the substrate 102 or the insulating film 106 releases a large amount of hydrogen. When hydrogen diffuses into a transistor, hydrogen bonds to oxygen vacancies, increasing the number of carriers. To avoid this, the transistor Tr1, which is close to the hydrogen source, A structure with excellent reliability against diffusion is preferable. The transistor Tr1 has an oxide semiconductor film with small diffusion of elements, and the diffusion of hydrogen and oxygen is small. The transistor Tr2 has a large oxide semiconductor film, which is a barrier against hydrogen diffusion from the substrate. This is effective in reducing the deterioration. In this case, silicon nitride is placed under the transistor Tr2. Examples of films that are difficult for hydrogen to diffuse through include silicon oxide films, silicon nitride films, and aluminum oxide films. It is preferable to form

[0337] Also, for the purpose of reducing the layout area of the transistor, when it is desired to reduce the line widths of the conductive film 112a, the conductive film 112b, the conductive film 122a, and the conductive film 122b, depending on the material used for these conductive films, the resistance to thermal migration may be low. At this time, in the thermal history after the formation of the conductive film 112a, the conductive film 112b, the conductive film 122a, and the conductive film 122b, it is better to lower the upper limit of the process temperature and shorten the heat treatment time. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used. Depending on the material used for these conductive films, the resistance to thermal migration may be low. At this time, in the thermal history after the formation of the conductive film 112a, the conductive film 112b, the conductive film 122a, and the conductive film 122b, it is better to lower the upper limit of the process temperature and shorten the heat treatment time. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used. the conductive film 112a, the conductive film 112b, the conductive film 122a, and the conductive film 122b, it is better to lower the upper limit of the process temperature and shorten the heat treatment time. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used. it is better to lower the upper limit of the process temperature and shorten the heat treatment time. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used. Using a film in which oxygen easily diffuses into the film, such as the oxide semiconductor film 128, in one aspect of the present invention is effective in improving the reliability when a material with low resistance to thermal migration is used.

[0338] That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration. That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration. That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration. That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration. That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration. That is, in one aspect of the present embodiment, although a large field-effect mobility can be obtained, a transistor that is susceptible to threshold changes due to hydrogen diffusion and has weak thermal migration is used for an element that requires a designed mobility, and conversely, a transistor that has a small field-effect mobility but has a small threshold change with respect to hydrogen diffusion and is strong against thermal migration is used for an element that requires a large reliability in design. By doing so, it is possible to suitably reduce the layout area of the transistor while suppressing deterioration.

[0339] Note that the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. Note that the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0340] (Embodiment 2)

[0341] <2-1. Composition of Oxide Semiconductor Film> Hereinafter, the composition of the oxide semiconductor film according to the present invention will be described.

[0342] The oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. It is preferable that the material contains boron, silicon, titanium, or the like. , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from zinc, hafnium, tantalum, tungsten, or magnesium Or, multiple types may be included.

[0343] Here, consider a case where the oxide contains indium, element M, and zinc. , aluminum, gallium, yttrium or tin. Other elements M may be used. Available elements include boron, silicon, titanium, iron, nickel, germanium, and zinc. Cobalt, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten However, the element M can be a combination of multiple of the above elements. There are cases where this is acceptable.

[0344] First, with reference to FIGS. 25(A), 25(B), and 25(C), the oxide according to the present invention will be described. The preferred range of the atomic ratio of indium, element M, and zinc contained in the above will be described below. The atomic ratio of oxygen is not shown in FIG. 25. The terms for the atomic ratio of element M and zinc are [In], [M], and [Zn], respectively. do.

[0345] In Figures 25(A), 25(B), and 25(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line with an atomic ratio of [In]:[M]:[Zn] = (1 + α):(1 - α):2, the line with an atomic ratio of [In]:[M]:[Zn] = (1 + α):(1 - α):3, the line with an atomic ratio of [In]:[M]:[Zn] = (1 + α):(1 - α):4, and the line with an atomic ratio of [In]:[M]:[Zn] = (1 + α):(1 - α):5 are shown. .

[0346] Also, the dashed line represents the line with an atomic ratio of [In]:[M]:[Zn] = 1:1:β (β ≥ 0), the line with an atomic ratio of [In]:[M]:[Zn] = 1:2:β, the line with an atomic ratio of [In]:[M]:[Zn] = 1:3:β, the line with an atomic ratio of [In]:[M]:[Zn] = 1:4:β, the line with an atomic ratio of [In]:[M]:[Zn] = 2:1:β, and the line with an atomic ratio of [In]:[M]:[Zn] = 5:1:β are shown.

[0347] Also, the long - dashed double - dotted line represents the line with an atomic ratio of [In]:[M]:[Zn] = (1 + γ):2:(1 - γ) (-1 ≤ γ ≤ 1). Also, the oxides with an atomic ratio of [In]:[M]:[Zn] = 0:2:1 shown in FIG. 25 and the nearby values tend to have a spinel - type crystal structure.

[0348] In FIGS. 25(A) and 25(B), an example of the preferable range of the atomic ratio of indium, element M, and zinc in the oxide of one aspect of the present invention is shown.

[0349] As an example, FIG. 26 shows the crystal structure of InMZnO 4 where [In]:[M]:[Zn] = 1:1:1. Also, FIG. 26 shows InMZn It is the crystal structure of O4. In the layer containing M, Zn, and oxygen shown in Fig. 26 (hereinafter referred to as the (M,Zn) layer), the metal element represents element M or zinc. In this case, it is assumed that the ratio of element M and zinc is equal. Element M and zinc are substitutable, and the arrangement is irregular. In the layer containing M, Zn, and oxygen shown in Fig. 26 (hereinafter referred to as the (M,Zn) layer), the metal element represents element M or zinc. In this case, it is assumed that the ratio of element M and zinc is equal. Element M and zinc are substitutable, and the arrangement is irregular. In the layer containing M, Zn, and oxygen shown in Fig. 26 (hereinafter referred to as the (M,Zn) layer), the metal element represents element M or zinc. In this case, it is assumed that the ratio of element M and zinc is equal. Element M and zinc are substitutable, and the arrangement is irregular. In the layer containing M, Zn, and oxygen shown in Fig. 26 (hereinafter referred to as the (M,Zn) layer), the metal element represents element M or zinc. In this case, it is assumed that the ratio of element M and zinc is equal. Element M and zinc are substitutable, and the arrangement is irregular.

[0350] InMZnO4 has a layered crystal structure (also referred to as a layered structure). As shown in Fig. 26, for the layer containing indium and oxygen (hereinafter referred to as the In layer), the layer containing element M, zinc, and oxygen ((M,Zn) layer) is 2 with respect to 1. InMZnO4 has a layered crystal structure (also referred to as a layered structure). As shown in Fig. 26, for the layer containing indium and oxygen (hereinafter referred to as the In layer), the layer containing element M, zinc, and oxygen ((M,Zn) layer) is 2 with respect to 1. InMZnO4 has a layered crystal structure (also referred to as a layered structure). As shown in Fig. 26, for the layer containing indium and oxygen (hereinafter referred to as the In layer), the layer containing element M, zinc, and oxygen ((M,Zn) layer) is 2 with respect to 1.

[0351] Also, indium and element M are mutually substitutable. Therefore, when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. In that case, it has a layered structure where the In layer is 1 and the (In,M,Zn) layer is 2. Also, indium and element M are mutually substitutable. Therefore, when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. In that case, it has a layered structure where the In layer is 1 and the (In,M,Zn) layer is 2. Also, indium and element M are mutually substitutable. Therefore, when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. In that case, it has a layered structure where the In layer is 1 and the (In,M,Zn) layer is 2.

[0352] The oxide with an atomic number ratio of [In]:[M]:[Zn]=1:1:2 has a layered structure where the In layer is 1 and the (M,Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the oxide crystallizes, the ratio of the (M,Zn) layer to the In layer increases. The oxide with an atomic number ratio of [In]:[M]:[Zn]=1:1:2 has a layered structure where the In layer is 1 and the (M,Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the oxide crystallizes, the ratio of the (M,Zn) layer to the In layer increases. The oxide with an atomic number ratio of [In]:[M]:[Zn]=1:1:2 has a layered structure where the In layer is 1 and the (M,Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the oxide crystallizes, the ratio of the (M,Zn) layer to the In layer increases. The oxide with an atomic number ratio of [In]:[M]:[Zn]=1:1:2 has a layered structure where the In layer is 1 and the (M,Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the oxide crystallizes, the ratio of the (M,Zn) layer to the In layer increases.

[0353] However, in the oxide, when the number of layers of the (M,Zn) layer is non-integer with respect to 1 In layer, there may be a case where there are multiple types of layered structures where the number of layers of the (M,Zn) layer is integer with respect to 1 In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, there may be a layered structure where the (M,Zn) layer is 2 and the (M,Zn) layer is 3 with respect to 1 In layer. However, in the oxide, when the number of layers of the (M,Zn) layer is non-integer with respect to 1 In layer, there may be a case where there are multiple types of layered structures where the number of layers of the (M,Zn) layer is integer with respect to 1 In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, there may be a layered structure where the (M,Zn) layer is 2 and the (M,Zn) layer is 3 with respect to 1 In layer. However, in the oxide, when the number of layers of the (M,Zn) layer is non-integer with respect to 1 In layer, there may be a case where there are multiple types of layered structures where the number of layers of the (M,Zn) layer is integer with respect to 1 In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, there may be a layered structure where the (M,Zn) layer is 2 and the (M,Zn) layer is 3 with respect to 1 In layer. However, in the oxide, when the number of layers of the (M,Zn) layer is non-integer with respect to 1 In layer, there may be a case where there are multiple types of layered structures where the number of layers of the (M,Zn) layer is integer with respect to 1 In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, there may be a layered structure where the (M,Zn) layer is 2 and the (M,Zn) layer is 3 with respect to 1 In layer. However, in the oxide, when the number of layers of the (M,Zn) layer is non-integer with respect to 1 In layer, there may be a case where there are multiple types of layered structures where the number of layers of the (M,Zn) layer is integer with respect to 1 In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, there may be a layered structure where the (M,Zn) layer is 2 and the (M,Zn) layer is 3 with respect to 1 In layer.

[0354] For example, when forming an oxide film using a sputtering apparatus, a film with an atomic ratio deviated from the atomic ratio of the target is formed. In particular, depending on the substrate temperature during film formation, the [Zn] in the film may be smaller than that of the target.

[0355] In addition, there may be cases where multiple phases coexist in the oxide (such as two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic ratio close to an atomic ratio of [In]:[M]:[Zn]=0:2:1, two phases of a spinel-type crystal structure and a layered crystal structure tend to coexist. Also, at an atomic ratio close to an atomic ratio indicating [In]:[M]: [Zn]=1:0:0, two phases of a perovskite-type crystal structure and a layered crystal structure tend to coexist. When multiple phases coexist in the oxide , there are cases where grain boundaries (also referred to as grain boundaries) are formed between different crystal structures.

[0356] Also, by increasing the indium content in the oxide, the carrier mobility (electron mobility) of the oxide can be increased. Therefore, an oxide with a high indium content has a higher carrier mobility compared to an oxide with a low indium content.

[0357] On the other hand, when the indium and zinc contents in the oxide are low, the carrier mobility becomes low. Therefore, at an atomic ratio indicating [In]:[M]:[Zn]=0:1:0 and atomic ratios close to it (for example, region C shown in FIG. 25(C)), the insulating property increases.

[0358] Therefore, the oxide of one aspect of the present invention preferably has an atomic ratio shown in region A of FIG. 25(A), which tends to have a layered structure with high carrier mobility and few grain boundaries.

[0359] In addition, region B shown in FIG. 25(B) has [In]:[M]:[Zn] ranging from 4:2:3 to 4. 1 and its vicinity values are shown. The vicinity values include, for example, an atomic ratio of [In]:[M] :[Zn]=5:3:4. The oxide having the atomic ratio shown in region B is particularly an excellent oxide with high crystallinity and high carrier mobility.

[0360] Note that the condition for the oxide to form a layered structure is not uniquely determined by the atomic ratio. The difference in the difficulty of forming a layered structure depends on the atomic ratio. On the other hand, even with the same atomic ratio depending on the formation conditions, it may or may not form a layered structure. Therefore, the region shown in the figure is a region showing the atomic ratio at which the oxide has a layered structure, and the boundaries of regions A to C are not strict.

[0361] Subsequently, the case of using the above oxide in a transistor will be described.

[0362] Note that by using the above oxide in a transistor, carrier scattering at grain boundaries can be reduced so that a transistor with high field-effect mobility can be realized. Also a highly reliable transistor can be realized.

[0363] In addition, it is preferable to use an oxide with a low carrier density in the transistor. For example, the oxide has a carrier density of less than 8×10 11 cm -3 preferably less than 1×10 11 cm -3 more preferably less than 1×10 10 cm -3 and less than 1×10 9 cm -3 or more That's all that is required.

[0364] In addition, an oxide that is highly pure and true or substantially highly pure and true has few carrier generation sources, so that the carrier density can be reduced. Also, an oxide that is highly pure and true or substantially highly pure and true has a low density of defect levels, so the trap level density may also be low.

[0365] In addition, the charge trapped in the trap level of the oxide takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide with a high trap level density may have unstable electrical characteristics.

[0366]

[0366] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide. Also, in order to reduce the impurity concentration in the oxide, it is preferable to reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0367]

[0368] Here, the effects of various impurities in the oxide will be described.

[0368] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide, defect levels are formed in the oxide. For this reason, the concentration of silicon or carbon in the oxide and the concentration of silicon or carbon near the interface between the oxide and the substrate (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×1 ry Ion Mass Spectrometry) is 2×1 0 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less. .

[0369] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. .

[0370] In addition, when nitrogen is contained in the oxide, electrons as carriers are generated, and the carrier density increases, making it easy to become n-type. As a result, a transistor using an oxide containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide is less than 5×10 5×10 19 atoms / cm 3 in SIMS, preferably 5×10 18 atoms / cm 3 or less , more preferably 1×10 18 atoms / cm 3 or less, and even more preferably 5×10 17 atoms / cm 3 or less.

[0371] In addition, hydrogen contained in the oxide reacts with oxygen that binds to metal atoms to form water, so oxygen It may form a defect. When hydrogen enters the oxygen defect, carriers, i.e., electrons, may be generated. In some cases, a part of hydrogen may combine with oxygen that binds to a metal atom to generate carriers, i.e., electrons. Therefore, a transistor using an oxide containing hydrogen tends to have normal-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide as much as possible. Specifically, in the oxide, the hydrogen concentration obtained by SIMS is less than 1×10 atoms / cm 20 3 preferably less than 1×10 19 atoms / cm 3 18 3 more preferably less than 5×10 18 atoms / cm 3

[0372] o o

[0373] By using an oxide with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0373] <2-2. Carrier density of oxide semiconductor film> Next, the carrier density of the oxide semiconductor film will be described below.

[0374] Factors affecting the carrier density of the oxide semiconductor film include oxygen defects (V o ) in the oxide semiconductor film, or impurities in the oxide semiconductor film, etc.

[0375] o When the number of oxygen defects in the oxide semiconductor film increases, when hydrogen binds to the oxygen defect (this state is also referred to as V H), the density of defect levels increases. Or, when there are many impurities in the oxide semiconductor filmWhen it becomes like this, the density of defect levels increases due to the impurities. Therefore, By controlling the density of defect levels in the oxide semiconductor film, the carrier density of the oxide semiconductor film can be controlled. .

[0376] Here, consider a transistor using an oxide semiconductor film in the channel region.

[0377] When aiming to suppress the negative shift of the threshold voltage of the transistor or to reduce the off-current of the transistor, it is preferable to lower the carrier density of the oxide semiconductor film. When lowering the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered and the density of defect levels may be lowered. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of a high-purity intrinsic oxide semiconductor film is less than 8×10 cm −20 cm−3, preferably less than 1× 15 cm -3 −20 10 11 cm -3 −20 10 cm -3 −20 - 9 cm -3 −20 or more.

[0378] On the other hand, when aiming to improve the on-current of the transistor or to improve the field-effect mobility of the transistor, it is preferable to increase the carrier density of the oxide semiconductor film. When increasing the carrier density of the oxide semiconductor film, the impurity concentration of the oxide semiconductor film may be slightly increased or the density of defect levels of the oxide semiconductor film may be slightly increased. Alternatively, it is preferable to make the band gap of the oxide semiconductor film smaller. For example, in the case of a transistor When increasing the carrier density of the oxide semiconductor film, the impurity concentration of the oxide semiconductor film may be slightly increased, or the density of defect levels of the oxide semiconductor film may be slightly increased. Or it is preferable to make the band gap of the oxide semiconductor film smaller. For example, in the case of a transistor In the range where the on / off ratio of the Id-Vg characteristics can be obtained, an oxide semiconductor film with a slightly higher impurity concentration or an oxide semiconductor film with a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor film with a large electron affinity and a correspondingly small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. When an oxide semiconductor film with a larger electron affinity is used, the threshold voltage of the transistor becomes lower.

[0379] The carrier density of a substantially intrinsic oxide semiconductor film is preferably 1×10 5 cm -3 or more and less than 1×10 18 cm -3 It is more preferably 1×10 7 cm -3 or more and 1×10 17 cm -3 or less, even more preferably 1×10 9 cm -3 or more and 5×10 16 cm -3 or less, even more preferably 1×10 1 0 cm -3 or more and 1×10 16 cm -3 or less, even more preferably 1×10 11 cm -3 or more 1×10 15 cm -3 or less is even more preferable.

[0380] Also, by using the above-described substantially intrinsic oxide semiconductor film, the reliability of the transistor may be improved. Here, with reference to FIG. 27, the reason why the reliability of a transistor using an oxide semiconductor film in the channel region is improved will be explained. FIG. 27 shows a transistor using an oxide semiconductor film in the channe l region. region. This is a diagram for explaining the energy band in a transistor used in the NEL region.

[0381] In FIG. 27, GE represents the gate electrode, GI represents the gate insulating film, OS represents the oxide semiconductor film , and SD represents the source electrode or the drain electrode, respectively. That is, FIG. 27 shows an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source electrode or the drain electrode in contact with the oxide semiconductor film.

[0382] In FIG. 27, a silicon oxide film is used as the gate insulating film, and In-Ga-Zn oxide is used for the oxide semiconductor film. [[ID=I5]] The transition level (εf) of the defect that can be formed in the silicon oxide film is formed at a position about 3.1 eV away from the lower end of the conduction band of the gate insulating film. When the gate voltage (Vg) is 30 V, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is formed at a position about 3.6 eV away from the lower end of the conduction band of the gate insulating film. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage. For example, by increasing the gate voltage, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film becomes lower. In FIG. 27, the white circles represent electrons (carriers), and the Xs in FIG. 27 represent the defect levels in the silicon oxide film. As shown in FIG. 27, when a gate voltage is applied and carriers are thermally excited, for example, the carriers are trapped at the defect levels (Xs in the figure), and the charged state of the defect levels changes from positive (“+”) to neutral (“0”). That is, the Fermi level of the silicon oxide film (Ef) changes.

[0383] As shown in FIG. 27, in a state where a gate voltage is applied, when carriers are thermally excited, for example, the carriers are trapped at the defect levels (Xs in the figure), and the charged state of the defect levels changes from positive (“+”) to neutral (“0”). That is, the Fermi level of the silicon oxide film When the value obtained by adding the energy of the above-described thermal excitation to Ef) is higher than the transition level (εf) of the defect, the charge state of the defect level in the silicon oxide film changes from a positive state to a neutral state, and the threshold voltage of the transistor will vary in the positive direction.

[0384] In addition, when oxide semiconductor films with different electron affinities are used, the depth at which the Fermi level is formed at the interface between the gate insulating film and the oxide semiconductor film may be different. When an oxide semiconductor film with a large electron affinity is used, the lower end of the conduction band of the gate insulating film becomes relatively high in the vicinity of the interface between the gate insulating film and the oxide semiconductor film. In this case, the defect levels (X in FIG. 27) that can be formed in the gate insulating film also become relatively high, so the energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film becomes large. As this energy difference increases, the amount of charge trapped in the gate insulating film decreases. For example, the change in the charge state of the defect levels that can be formed in the above-described silicon oxide film decreases, and the variation in the threshold voltage of the transistor in gate bias temperature (GBT) stress can be reduced.

[0385] In addition, a transistor using an oxide semiconductor film in the channel region can reduce carrier scattering at grain boundaries, etc., so a transistor with a high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0386] In addition, the charge trapped in the defect levels of the oxide semiconductor film may take a long time to disappear and may behave like a fixed charge. Therefore, an oxide with a high defect level density A transistor in which a channel region is formed in a semiconductor film may have unstable electrical characteristics.

[0387] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film. Further, in order to reduce the impurity concentration in the oxide semiconductor film, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0388] Here, the influence of each impurity in the oxide semiconductor film will be described.

[0389] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor film, defect levels are formed in the oxide semiconductor film. Therefore, the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon near the interface with the oxide semiconductor film (the concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry ) are set to 2 × 10 atoms / cm 18 or less, preferably 2 × 10 3 atoms / cm 17 or less. 3

[0390] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor film, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor film containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, reducing the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film ​​​​​is preferable. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2 ×10 16 atoms / cm 3 or less.

[0391] In addition, in the oxide semiconductor film, when nitrogen is contained, electrons as carriers are generated, and the carrier density increases and it tends to become n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration in the oxide semiconductor film is less than 5×10 atoms / cm in SIMS, preferably 19 5×10 3 atoms / cm or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 18 atoms / cm 3 or less, and still more preferably 5×10 17 atoms / cm 3 or less.

[0392] In addition, hydrogen contained in the oxide semiconductor film may react with oxygen bonded to metal atoms to form water, thus forming oxygen vacancies. When hydrogen enters the oxygen vacancies, carriers, i.e., electrons, may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate carriers, i.e., electrons. Therefore, a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor film is reduced as much as possible. Specifically, in the oxide semiconductor film used, hydrogen is preferably reduced as much as possible.​ , the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 atoms / cm 19 , more preferably less than 5×10 3 atoms / cm 18 , still more preferably less than 1×10 3 atoms / cm 18 , and even more preferably less than 1×10 3 atoms / cm

[0393] When an oxide semiconductor film with sufficiently reduced impurities is used for the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0394] In addition, the oxide semiconductor film preferably has an energy gap of 2 eV or more, or 2.5 eV or more.

[0395] In addition, the thickness of the oxide semiconductor film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and still more preferably 3 nm or more and 60 nm or less.

[0396] <2-3. Structure of Oxide Semiconductor Film> Next, the structure of the oxide semiconductor film will be described.

[0397] The oxide semiconductor film can be classified into a single-crystalline oxide semiconductor film and other non-single-crystalline oxide semiconductor films. Examples of the non-single-crystalline oxide semiconductor film include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like OS), and polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like OS). Examples of the non-single-crystalline oxide semiconductor film include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like OS), and polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like OS). (a US-like oxide semiconductor), and an amorphous oxide semiconductor and the like.

[0398] From another perspective, the oxide semiconductor film can be divided into an amorphous oxide semiconductor film and other crystalline oxide semiconductor films. Examples of the crystalline oxide semiconductor film include a single crystal oxide semiconductor film, CAAC-OS, a polycrystalline oxide semiconductor film, and nc-OS.

[0399] An amorphous structure is generally an isotropic, metastable state in which the arrangement of atoms is not fixed, the bond angles are flexible, and there is short-range order but no long-range order, and so on. That is, a stable oxide semiconductor film cannot be called a completely amorphous oxide semiconductor film. Also, an anisotropic (for example, having a periodic structure in a minute region) oxide semiconductor film cannot be called a completely amorphous oxide semiconductor film. On the other hand, a-like OS is anisotropic but has an unstable structure with voids (also called voids). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor film.

[0400]

[0401]

[0402]

[0403] [CAAC-OS] First, CAAC-OS will be described.

[0402] CAAC-OS is a type of oxide semiconductor film having a plurality of c-axis oriented crystal parts (also called pellets).

[0403] CAAC-OS is a highly crystalline oxide semiconductor film. The crystallinity of the oxide semiconductor film is affected by impurities CAAC-OS is designed to be free from impurities and defects. It can also be said that the oxide semiconductor film has few defects (such as oxygen vacancies).

[0404] Note that the impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more likely to be present than metal elements constituting the oxide semiconductor film. An element that has a strong bond to oxygen can remove oxygen from the oxide semiconductor film and become an element of the oxide semiconductor film. In addition, heavy metals such as iron and nickel, and aluminum Carbon dioxide and other carbon-dioxide species have large atomic radii (or molecular radii), so they are difficult to form oxide semiconductor films. This disrupts the atomic arrangement and causes a decrease in crystallinity.

[0405] [nc-OS] Next, we will explain nc-OS.

[0406] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0407] The nc-OS is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS has a lower density of defect states than the a-like OS and the amorphous oxide semiconductor film. However, in the case of nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS.

[0408] [a-like OS] The a-like OS is an oxide film with a structure between the nc-OS and the amorphous oxide semiconductor film. It is a semiconductor film.

[0409] a-like OS has a loose or low-density region. Since a-like OS has a loose structure, it is an unstable structure.

[0410] Also, since a-like OS has a loose structure, it has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0411] For example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 Therefore, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 Also, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / c m 3

[0412] In addition, when there is no single crystal with the same composition, by combining single crystals with different compositions at an arbitrary ratio, the density corresponding to the single crystal in the desired composition can be estimated. ​​​​​​​​​The density corresponding to the single crystal of the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals having different compositions. However, the density is preferably estimated by combining as few types of single crystals as possible. That is, it is sufficient that at least one of the crystal parts present in the film has c-axis orientation. Further, among the crystal parts present in the film, if there are a plurality of crystal parts having c-axis orientation, the density may be estimated using the weighted average with respect to the ratio of the plurality of crystal parts having c-axis orientation.

[0413] As described above, the oxide semiconductor film has various structures, and each has various characteristics. Note that in the oxide semiconductor film of one embodiment of the present invention, two or more of an amorphous oxide semiconductor film, an a-like OS, an nc-OS, and a CAAC-OS may be mixed. An example in that case is shown below.

[0414] The oxide semiconductor film of one embodiment of the present invention can be made into an oxide semiconductor film including two types of crystal parts. That is, it is an oxide semiconductor film in which two types of crystal parts are mixed. One of the crystal parts ( also referred to as the first crystal part) is a crystal part having orientation in the film thickness direction (also referred to as the film surface direction, the surface of the film to be formed, or the direction perpendicular to the surface of the film), that is, a crystal part having c-axis orientation. The other one of the crystal parts ( also referred to as the second crystal part) is a crystal part that is oriented in various directions without having c-axis orientation. That is, it is a crystal part that is randomly oriented. That is, it is a crystal part that is oriented in various directions without having c-axis orientation. That is, it is a crystal part that is oriented in various directions without having c-axis orientation.

[0415] Note that hereinafter, for ease of explanation, the crystal part having c-axis orientation is described separately as the first crystal part, and the crystal part not having c-axis orientation is described as the second crystal part. However, there may be cases where these cannot be distinguished because there are no differences in crystallinity, crystal size, etc. That is, the oxide semiconductor film of one embodiment of the present invention can also be expressed without distinguishing these. That is, the oxide semiconductor film of one embodiment of the present invention can also be expressed without distinguishing these. That is, the oxide semiconductor film of one embodiment of the present invention can also be expressed without distinguishing these.

[0416] For example, the oxide semiconductor film of one embodiment of the present invention has a plurality of crystal parts, and among the crystal parts present in the film, it is sufficient that at least one of the crystal parts has c-axis orientation. Further, among the crystal parts present in the film, Among the crystal parts, the crystal parts having no c-axis orientation may be present in a larger proportion than the crystal parts having c-axis orientation. As an example, in the observation image by a transmission electron microscope in the cross-section in the film thickness direction of the oxide semiconductor film of one aspect of the present invention, a plurality of crystal parts are observed, and among the plurality of crystal parts, the second crystal part having no c-axis orientation may be observed more than the first crystal part having c-axis orientation. In other words, in the oxide semiconductor film of one aspect of the present invention, the proportion of the second crystal part having no c-axis orientation is large. By increasing the proportion of the second crystal part having no c-axis orientation in the oxide semiconductor film, the following excellent effects can be achieved. When there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, the second crystal part having no c-axis orientation can become an oxygen diffusion path. Therefore, when there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, oxygen can be supplied to the first crystal part having c-axis orientation through the second crystal part having no c-axis orientation. Therefore, the amount of oxygen deficiency in the film of the oxide semiconductor film can be reduced. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. Among the plurality of crystal parts, the second crystal part having no c-axis orientation may be observed more than the first crystal part having c-axis orientation. In other words, in the oxide semiconductor film of one aspect of the present invention, the proportion of the second crystal part having no c-axis orientation is large.

[0417] By increasing the proportion of the second crystal part having no c-axis orientation in the oxide semiconductor film, the following excellent effects can be achieved. The following excellent effects can be obtained.

[0418] When there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, the second crystal part having no c-axis orientation can be an oxygen diffusion path. Therefore, when there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, oxygen can be supplied to the first crystal part having c-axis orientation through the second crystal part having no c-axis orientation. Therefore, the amount of oxygen deficiency in the film of the oxide semiconductor film can be reduced. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. When there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, the second crystal part having no c-axis orientation can be an oxygen diffusion path. Therefore, when there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, oxygen can be supplied to the first crystal part having c-axis orientation through the second crystal part having no c-axis orientation. Therefore, the amount of oxygen deficiency in the film of the oxide semiconductor film can be reduced. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. When there is a sufficient oxygen supply source in the vicinity of the oxide semiconductor film, oxygen can be supplied to the first crystal part having c-axis orientation through the second crystal part having no c-axis orientation. Therefore, the amount of oxygen deficiency in the film of the oxide semiconductor film can be reduced. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. Therefore, the amount of oxygen deficiency in the film of the oxide semiconductor film can be reduced. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility. By applying such an oxide semiconductor film to the semiconductor film of a transistor, it becomes possible to have high reliability and obtain high field-effect mobility.

[0419] In addition, the first crystal part has an orientation of a specific crystal plane with respect to the film thickness direction. Therefore, for the oxide semiconductor film including the first crystal part, when X-ray diffraction (XRD) measurement is performed in a direction substantially perpendicular to the upper surface of the film, a diffraction peak derived from the first crystal part is confirmed at a predetermined diffraction angle (2θ). On the other hand, when the oxide semiconductor film is the second When X-ray diffraction (XRD) measurement is performed in a direction substantially perpendicular to the upper surface of the film for the oxide semiconductor film including the first crystal part, a diffraction peak derived from the first crystal part is confirmed at a predetermined diffraction angle (2θ). On the other hand, when the oxide semiconductor film is the second When X-ray diffraction (XRD) measurement is performed in a direction substantially perpendicular to the upper surface of the film for the oxide semiconductor film including the first crystal part, a diffraction peak derived from the first crystal part is confirmed at a predetermined diffraction angle (2θ). On the other hand, when the oxide semiconductor film is the second When X-ray diffraction (XRD) measurement is performed in a direction substantially perpendicular to the upper surface of the film for the oxide semiconductor film including the first crystal part, a diffraction peak derived from the first crystal part is confirmed at a predetermined diffraction angle (2θ). On the other hand, when the oxide semiconductor film is the second Even if it has the crystal part of 1, the diffraction peak may not be sufficiently confirmed due to the scattering of X-rays by the support substrate or the increase in background. Note that the height (intensity) of the diffraction peak increases according to the existence ratio of the first crystal part contained in the oxide semiconductor film, and can also be an index for estimating the crystallinity of the oxide semiconductor film. is proportional to the proportion of the first crystalline part present in the oxide semiconductor film and can also serve as an indicator for estimating the crystallinity of the oxide semiconductor film.

[0420] In addition, electron diffraction can be cited as one of the methods for evaluating the crystallinity of the oxide semiconductor film. For example, when performing electron diffraction measurement on the cross section and observing the electron diffraction pattern of the oxide semiconductor film of one aspect of the present invention, a first region having a diffraction spot due to the first crystal part and a second region having a diffraction spot due to the second crystal part are observed.

[0421] The first region having a diffraction spot due to the first crystal part is derived from a crystal part having c-axis orientation. On the other hand, the second region having a diffraction spot due to the second crystal part is derived from a crystal part having no orientation or a crystal part randomly oriented in all directions. Therefore, depending on the beam diameter of the electron beam used for electron diffraction, that is, the area of the observation region, different patterns may be confirmed. In this specification, etc., electron diffraction measured with an electron beam having a beam diameter of 1 nmΦ or more and 100 nmΦ or less is called nano-beam electron diffraction (NBED: Nano Beam Electron Diffraction). However, the crystallinity of the oxide semiconductor film of one aspect of the present invention may be evaluated by a method different from NBED. Examples of the method for evaluating the crystallinity of the oxide semiconductor film include electron diffraction, X-ray diffraction, and neutral electron diffraction. Among electron diffractions, in addition to NBED shown above, transmission electron microscopy

[0422] However, the crystallinity of the oxide semiconductor film of one aspect of the present invention may be evaluated by a method different from NBED. As an example of the method for evaluating the crystallinity of the oxide semiconductor film, electron diffraction, X-ray diffraction, and neutral electron diffraction can be cited. Among electron diffractions, in addition to NBED shown above, transmission electron microscopy electron diffraction, etc. can be mentioned. Among electron diffractions, in addition to NBED shown above, transmission electron microscopy ​​​​A mirror (TEM: Transmission Electron Microscopy), a scanning electron microscope (SEM: Scanning Electron Microscop y), convergent beam electron diffraction (CBED: Convergent Beam Electron Diffraction), selected area electron diffraction (SAED: Selected Area Electron Diffraction), etc. can be preferably used.

[0423] Also, in NBED, in the condition of increasing the beam diameter of the electron beam (for example, 25 nm Φ or more 100 nm Φ or less, or 50 nm Φ or more and 100 nm Φ or less) of the nanobeam electron diffraction pa tern, a ring-shaped pattern is confirmed. Also, the ring-shaped pattern may have a luminance distribution in the radial direction. On the other hand, in NBED, in the electron diffraction image under the condition of sufficiently reducing the beam diameter of the electron beam (for example, 1 nm Φ or more and 10 nm Φ or less), a plurality of spots distributed in the circumferential direction (also referred to as the θ direction) are confirmed at the position of the above ring-shaped pattern. That is, the ring-shaped pattern observed under the condition of increasing the beam diameter of the electron beam is formed by the aggregate of the above plurality of spots.

[0424] <2-4. Evaluation of crystallinity of oxide semiconductor film> Hereinafter, samples (Samples X1 to X3 ) in which three oxide semiconductor films with different conditions were formed were prepared and evaluated for crystallinity. First, the preparation methods of Samples X1 to X3 will be described.

[0425] [Sample X1] Sample X1 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. ​​​​​​. When the oxide semiconductor film contains indium, gallium, and zinc. Oxidation of sample X1 As the formation conditions of the oxide semiconductor film of sample X1, the substrate was heated to 170 °C, and argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm were introduced into the chamber of the sputtering apparatus. The pressure was set to 0.6 Pa, and an AC power of 2.5 kW was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) containing indium, gallium, and zinc to form it. The oxygen flow ratio under the production conditions of sample X1 is 30%.

[0426] [Sample X2] Sample X2 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. As the formation conditions of the oxide semiconductor film of sample X2, the substrate was heated to 130 °C, and argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus to form it. The oxygen flow ratio under the production conditions of sample X2 is 10%. In addition, as the conditions other than the substrate temperature and the oxygen flow ratio, the same conditions as those of sample X1 shown above were used.

[0427] [Sample X3] Sample X3 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. As the formation conditions of the oxide semiconductor film of sample X3, the substrate was at room temperature (R.T.), and argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus to form it. The oxygen flow ratio under the production conditions of sample X3 is 10%. In addition, as the conditions other than the substrate temperature and the oxygen flow ratio, the same conditions as those of sample X1 shown above were used.

[0428] Table 1 shows the conditions for forming samples X1 to X3.

[0429] [Table 1]

[0430] Next, the crystallinity of the prepared samples X1 to X3 was evaluated. The crystallinity was evaluated by cross-sectional TEM observation, XRD measurement, and electron beam diffraction.

[0431] [Cross-sectional TEM observation] 28, 29, and 30 show the cross-sectional TEM observation results of samples X1 to X3. 28(A) and (B) are cross-sectional TEM images of sample X1, and FIGS. 29(A) and (B) are cross-sectional TEM images of sample X2. 30(A) and (B) are cross-sectional TEM images of sample X3.

[0432] Also, Figure 28(C) shows a high-resolution transmission electron microscope (HR-TEM) image of the cross section of sample X1. 29(C) is a cross-sectional HR-TEM image of sample X2. Figure 30(C) is a cross-sectional HR-TEM image of sample X3. -Spherical aberration correction (SCA) is used for TEM image observation. A high-resolution TEM image using the spherical aberration correction function can be obtained. This is called a Cs-corrected high-resolution TEM image. Observation was performed using an atomic resolution analytical electron microscope such as JEM-ARM200F manufactured by Komatsu Corporation. This can be done.

[0433] As shown in FIGS. 28 and 29, in Samples X1 and X2, atoms are arranged in layers in the film thickness direction. In particular, the HR-TEM image shows crystals arranged in layers. The crystal part is easy to observe. Also, as shown in FIG. 30, in sample X3, it is difficult to confirm that the atoms are arranged in layers in the film thickness direction.

[0434] [XRD Measurement] Next, the XRD measurement results of each sample will be described.

[0435] The XRD measurement results of sample X1 are shown in FIG. 31(A), the XRD measurement results of sample X2 are shown in FIG. 32(A), and the XRD measurement results of sample X3 are shown in FIG. 33(A), respectively.

[0436] In the XRD measurement, the powder method (also called the θ-2θ method), which is a type of the out-of-plane method, was used. The θ-2θ method is a method of measuring the X-ray diffraction intensity by changing the incident angle of the X-ray and setting the angle of the detector provided opposite to the X-ray source to be the same as the incident angle. Note that the X-ray is incident from an angle of about 0.40° from the film surface, and a type of the out-of-plane method, GIXRD (Grazing-Incidence XRD) method (also called the thin film method or the Seemann-Bohlin method), which measures the X-ray diffraction intensity by changing the angle of the detector, may be used. The vertical axis in FIGS. 31(A), 32(A), and 33(A) indicates the diffraction intensity in arbitrary units, and the horizontal axis indicates the angle 2θ.

[0437] As shown in FIGS. 31(A) and 32(A), in samples X1 and X2, a peak in the diffraction intensity is confirmed at around 2θ = 31°. On the other hand, as shown in FIG. 33(A), in sample X3, it is difficult to confirm a peak in the diffraction intensity at around 2θ = 31°, or the peak in the diffraction intensity at around 2θ = 31° is extremely small, or there is no peak in the diffraction intensity at around 2θ = 31°.

[0438] Note that the diffraction angle (around 2θ = 31°) at which the peak of the diffraction intensity was observed coincides with the diffraction angle of the (009) plane in the structural model of single-crystal InGaZn O4. Therefore, in samples X1 and sample X2, since the above peak was observed, it can be confirmed that a crystal part (hereinafter also referred to as a crystal part having c-axis orientation or a first crystal part) in which the c-axis is oriented in the film thickness direction is included. (Hereinafter, it is also referred to as a crystal part having c-axis orientation or a first crystal part) is included. Regarding sample X3, it is difficult to determine from the XRD measurement whether a crystal part having c-axis orientation is included.

[0439] [Electron beam diffraction] Next, the results of electron beam diffraction measurement for samples X1 to X3 will be described. In the electron beam diffraction measurement, an electron beam diffraction pattern is obtained when the electron beam is incident perpendicularly to the cross section of each sample. Also, the beam diameter of the electron beam was set to two values, 1 nmΦ and 100 nmΦ.

[0440] In electron beam diffraction, not only the beam diameter of the incident electron beam but also the thicker the sample, the information in the depth direction appears in the electron beam diffraction pattern. Therefore, by not only reducing the beam diameter of the electron beam but also reducing the thickness in the depth direction of the sample, information on a more local region can be obtained. On the other hand, when the thickness in the depth direction of the sample is too thin (for example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. information in the depth direction appears in the electron beam diffraction pattern. Therefore, by not only reducing the beam diameter of the electron beam but also reducing the thickness in the depth direction of the sample, information on a more local region can be obtained. On the other hand, when the thickness in the depth direction of the sample is too thin (for example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. local region can be obtained. On the other hand, when the thickness in the depth direction of the sample is too thin (for example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. When the thickness in the depth direction of the sample is too thin (for example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. For example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. For example, when the thickness in the depth direction of the sample is 5 nm or less), only information on an extremely fine region can be obtained. Therefore, when crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. When crystals exist in an extremely fine region, the obtained electron beam diffraction pattern may be the same as that of a single crystal. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. When not aiming to analyze an extremely fine region, the thickness in the depth direction of the sample is, for example, 10 nm or more and 100 nm or less. ​It is preferably 10 nm or more and 50 nm or less in tabular form.

[0441] The electron diffraction patterns of sample X1 are shown in FIGS. 31(B) and (C), and those of sample X2 are shown in FIGS. 32(B) and (C), and the electron diffraction pattern of sample X3 is shown in FIGS. 33(B) and (C), respectively. Each is shown.

[0442] Note that the electron diffraction patterns shown in FIGS. 31(B) and (C), FIGS. 32(B) and (C), and FIGS. 33(B) and (C) are image data with the contrast adjusted so that the electron diffraction pattern is clear. Also, in FIGS. 31(B) and (C), FIGS. 32(B) and (C), and FIGS. 33(B) and (C ), the brightest central spot is due to the incident electron beam and is the center of the electron diffraction pattern (also called the direct spot or transmitted wave). ) The center of the electron diffraction pattern (also called the direct spot or transmitted wave). ).

[0443] Also, as shown in FIG. 31(B), when the beam diameter of the incident electron beam is 1 nmΦ, a plurality of spots distributed in a circular shape are observed, so it can be seen that the oxide semiconductor film contains a plurality of crystal parts that are extremely minute and have crystal orientations in all directions. Also, as shown in FIG. 31(C), when the beam diameter of the incident electron beam is 100 nmΦ, the diffraction spots from these plurality of crystal parts are continuous, and it can be confirmed that the brightness is averaged to form a ring-shaped diffraction pattern. Also, in FIG. 31(C), two ring-shaped diffraction patterns with different radii can be confirmed. Here, the smaller-diameter one is called the first ring and the second ring. It can be confirmed that the first ring has a higher brightness than the second ring. Also, two bright spots (first region) with high brightness are confirmed at positions overlapping the first ring. . are confirmed.

[0444] The radial distance from the center of the first ring approximately coincides with the radial distance from the center of the diffraction spot of the (009) plane in the structural model of single-crystalline InGaZnO4. Also, the first region is a diffraction spot due to the c-axis orientation.

[0445] Also, as shown in Fig. 31(C), since a ring-shaped diffraction pattern is observed, it can also be said that there are crystal parts (hereinafter also referred to as crystal parts having no c-axis orientation or second crystal parts) oriented in all directions in the oxide semiconductor film.

[0446] Also, since the two first regions are symmetrically arranged with respect to the center point of the electron diffraction pattern and have similar brightness, it is inferred that they have two-fold symmetry. Also, as described above, since the two first regions are diffraction spots due to the c-axis orientation, the direction of the straight line connecting the two first regions and passing through the center coincides with the direction of the c-axis of the crystal part. In Fig. 31(C), since the vertical direction is the film thickness direction, it can be seen that there are crystal parts in the oxide semiconductor film whose c-axes are oriented in the film thickness direction.

[0447] Thus, it can be confirmed that the oxide semiconductor film of sample X1 is a film in which crystal parts having c-axis orientation and crystal parts having no c-axis orientation are mixed.

[0448] In the electron diffraction patterns shown in Figs. 32(B)(C) and 33(B)(C) as well, the results are generally the same as those of the electron diffraction pattern shown in Fig. 3 1(B)(C). However, the brightness of the two spots (first regions) due to the c-axis orientation is in the order of sample X1, sample X2, and sample X3. It is suggested that the proportion of the crystal part having a bright c-axis orientation is high in this order.

[0449] [Method for Quantifying Crystallinity of Oxide Semiconductor Film] Next, an example of a method for quantifying the crystallinity of an oxide semiconductor film will be described with reference to FIGS. 34 to 36. Explain.

[0450] First, an electron beam diffraction pattern is prepared (see FIG. 34(A)).

[0451] Note that FIG. 34(A) is an electron beam diffraction pattern measured for an oxide semiconductor film with a thickness of 100 nm and a beam diameter of 100 nm. FIG. 34(B) is an electron beam diffraction pattern after adjusting the contrast of the electron beam diffraction pattern shown in FIG. 34(A). In FIG. 34(B), two clear spots (the first region

[0452] ) are observed above and below the direct spot. These two spots (the first region) are diffraction spots corresponding to (00l) in the structural model of InGaZnO4, i.e., caused by the crystal part having a c-axis orientation. On the other hand, apart from the above first region, a ring-shaped pattern with low brightness (the second region) is seen overlapping approximately concentrically with the first region. This is due to the fact that when the electron beam diameter is 100 nm, the brightness of the diffraction spots of the crystal part without c-axis orientation (the second crystal part) is averaged and becomes ring-shaped. Here, in the electron beam diffraction pattern, a first region having diffraction spots caused by the crystal part having a c-axis orientation and a second region having diffraction spots caused by the second crystal part are observed overlapping. Therefore, a line profile including the first region and a line

[0453] including the second region are observed overlapping. Therefore, a line profile including the first region and a line profile including the second region are observed overlapping. Thus, a line profile including the first region and a line By obtaining and comparing the in-profile, it becomes possible to quantify the crystallinity of the oxide semiconductor film. This is achieved.

[0454] First, the line profile including the first region and the line profile including the second region will be described with reference to FIG. 35. This will be described with reference to FIG. 35.

[0455] FIG. 35 is a diagram in which auxiliary lines of regions A-A', regions B-B', and regions C-C' are added to the simulation pattern of electron diffraction obtained when an electron beam is irradiated onto the (100) plane of the InGaZnO4 structural model. The regions A-A' shown in FIG. 35 include two diffraction spots due to the first crystal part having c-axis orientation and a straight line passing through the direct spot. Also, the regions B-B' and regions C-C' shown in FIG. 35 include a straight line passing through the direct spot and a region where diffraction spots due to the first crystal part having c-axis orientation are not observed. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. This is a diagram with auxiliary lines added to the simulation pattern of electron diffraction obtained when an electron beam is irradiated onto the (100) plane of the InGaZnO4 structural model.

[0456] The regions A-A' shown in FIG. 35 include two diffraction spots due to the first crystal part having c-axis orientation and a straight line passing through the direct spot. Also, the regions B-B' and regions C-C' shown in FIG. 35 include a straight line passing through the direct spot and a region where diffraction spots due to the first crystal part having c-axis orientation are not observed. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. The regions A-A' shown in FIG. 35 include two diffraction spots due to the first crystal part having c-axis orientation and a straight line passing through the direct spot. Also, the regions B-B' and regions C-C' shown in FIG. 35 include a straight line passing through the direct spot and a region where diffraction spots due to the first crystal part having c-axis orientation are not observed. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. The regions A-A' shown in FIG. 35 include two diffraction spots due to the first crystal part having c-axis orientation and a straight line passing through the direct spot. Also, the regions B-B' and regions C-C' shown in FIG. 35 include a straight line passing through the direct spot and a region where diffraction spots due to the first crystal part having c-axis orientation are not observed. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. The regions A-A' shown in FIG. 35 include two diffraction spots due to the first crystal part having c-axis orientation and a straight line passing through the direct spot. Also, the regions B-B' and regions C-C' shown in FIG. 35 include a straight line passing through the direct spot and a region where diffraction spots due to the first crystal part having c-axis orientation are not observed. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. The angle at which the regions A-A' intersect with the regions B-B' or the regions C-C' is in the vicinity of 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, and more preferably 33° or more and 35° or less. This is good.

[0457] The line profile has a tendency as shown in FIG. 36 according to the structure of the oxide semiconductor film. FIG. 36 is a diagram explaining the image diagram of the line profile for each structure, the relative luminance R, and the full width at half maximum (FWHM) of the spectrum due to the c-axis orientation obtained from the electron diffraction pattern. The line profile has a tendency as shown in FIG. 36 according to the structure of the oxide semiconductor film. FIG. 36 is a diagram explaining the image diagram of the line profile for each structure, the relative luminance R, and the full width at half maximum (FWHM) of the spectrum due to the c-axis orientation obtained from the electron diffraction pattern. The line profile has a tendency as shown in FIG. 36 according to the structure of the oxide semiconductor film. FIG. 36 is a diagram explaining the image diagram of the line profile for each structure, the relative luminance R, and the full width at half maximum (FWHM) of the spectrum due to the c-axis orientation obtained from the electron diffraction pattern. This is a diagram explaining the image diagram of the line profile for each structure, the relative luminance R, and the full width at half maximum (FWHM) of the spectrum due to the c-axis orientation obtained from the electron diffraction pattern.

[0458] The relative luminance R shown in FIG. 36 is the value obtained by dividing the integrated intensity of the luminance in region A-A' by the integrated intensity of the luminance in region B- B' or the integrated intensity of the luminance in region C-C'. Note that, as the integrated intensity of the luminance in region A-A', region B-B', and region C-C', the background luminance caused by the direct spot appearing at the center position is removed. By calculating the relative luminance R, the strength of the c-axis orientation can be quantitatively defined. For example, as shown in FIG. 36, in a single-crystal oxide semiconductor film, the peak intensity of the diffraction spot due to the first crystal part having c-axis orientation in region A-A' is high, and no diffraction spot due to the first crystal part having c-axis orientation is seen in region B-B' and

[0459] region C-C'. Therefore, the relative luminance R becomes extremely large, exceeding 1. Also, the relative luminance R decreases in the order of single crystal, CA AC (details of CAAC will be described later), only CAAC, CAAC+Nanocrystal, Nanocrystal, and Amorphous. In particular, for Nanocrystal and amorphous having no specific orientation, the relative luminance R is 1.

[0460]

[0461] Also, the higher the periodicity of the crystal structure, the higher the intensity of the spectrum due to the first crystal part having c-axis orientation, and the smaller the full width at half maximum of the spectrum. Therefore, the full width at half maximum of the single crystal is the smallest, and the full width at half maximum increases in the order of only CAAC, CAAC+Nanocrystal, Nanocrys tal, and the full width at half maximum is very large in amorphous, resulting in a profile called a halo. [Analysis by line profile]

[0461] [Analysis by line profile] As described above, the intensity ratio between the integrated intensity of luminance in the first region and the integrated intensity of luminance in the second region is important information in terms of estimating the proportion of the crystalline part having orientation. Therefore, analysis by line profile was performed from the electron diffraction patterns of the samples X1 to X3 shown above.

[0462] The analysis results by the line profile of sample X1 are shown in FIGS. 37(A1)(A2), the analysis results by the line profile of sample X2 are shown in FIGS. 37(B1)(B2), and the analysis results by the line profile of sample X3 are shown in FIGS. 37(C1)(C2), respectively.

[0463]

[0464] Note that FIG. 37(A1) is an electron diffraction pattern with regions A-A', B-B', and C-C' marked on the electron diffraction pattern shown in FIG. 31(C), FIG. 37(B1) is an electron diffraction pattern with regions A-A', B-B', and C-C' marked on the electron diffraction pattern shown in FIG. 32(C), and FIG. 37(C1) is an electron diffraction pattern with regions A-A', B-B', and C-C' marked on the electron diffraction pattern shown in FIG. 33(C).

[0465] In addition, regions A-A', B-B', and C-C' can be obtained by normalizing with the luminance of the direct spot that appears at the center position of the electron diffraction pattern. Also, by this, relative comparison between each sample can be performed.

[0466] In addition, when calculating the luminance profile, subtracting the component of the luminance caused by inelastic scattering etc. from the sample as the background enables more accurate comparison. ​ Here, since the luminance component due to inelastic scattering has a profile that is extremely broad in the radial direction, the background luminance may be calculated by linear approximation. For example, a straight line may be drawn along the skirts on both sides of the target peak, and the region located on the lower luminance side than the straight line may be subtracted as the background. Here, from the data obtained by subtracting the background by the above method, the integrated intensities of the luminance in regions A - A', region B - B', and region C - C' were calculated. Then, the value obtained by dividing the integrated intensity of the luminance in region A - A' by the integrated intensity of the luminance in region B - B' or the integrated intensity of the luminance in region C -

[0467] C' was determined as the relative luminance R. Figure 38 shows the relative luminance R of samples X1 to X3. In Figure 38, in the spectra located on the left and right of the direct spot in the luminance profiles shown in Figure 37( A2), Figure 37(B2), and Figure 37(C2), the values obtained by dividing the integrated intensity of the luminance in region A - A' by the integrated intensity of the luminance in region B - B', and the value obtained by dividing the integrated intensity of the luminance in region A - A' by the integrated intensity of the luminance in region C - C' were determined respectively.

[0468] Calculated from the results shown in Figure 38, the integrated intensities of samples X1 to X3 are as follows. · Integrated intensity of sample X1 = 25.00 · Integrated intensity of sample X2 = 3.04 · Integrated intensity of sample X3 = 1.05 Note that the above integrated intensities were the average values at four positions. Thus, the integrated intensities are high in the order of sample

[0469] X1, sample X2, and sample X3. · Integrated intensity of sample X1 = 25.00 · Integrated intensity of sample X2 = 3.04 · Integrated intensity of sample X3 = 1.05 Note that the above integrated intensities were the average values at four positions. Thus, the integrated intensities are high in the order of sample X1, sample X2, sample X3.

[0470] When the oxide semiconductor film of one embodiment of the present invention is used as the semiconductor film in which the channel of the transistor is formed it is preferable to use an oxide semiconductor film having an intensity ratio such that the relative luminance R exceeds 1 and is 40 or less, preferably exceeds 1 and is 10 or less, more preferably exceeds 1 and is 3 or less. By using such an oxide semiconductor film as the semiconductor film, it is possible to achieve both high stability of electrical characteristics and high field-effect mobility in a region where the gate voltage is low.

[0471] <2-5. Proportion of crystal part> The proportion of the crystal part in the oxide semiconductor film can be estimated by analyzing the cross-sectional TEM image.

[0472] First, the method of image analysis will be described. As the method of image analysis, a two-dimensional fast Fourier transform (FFT) process is performed on a TEM image captured with high resolution to obtain an FFT image. A mask process is performed on the obtained FFT image to leave the range having periodicity and remove the rest. Then, the masked FFT image is subjected to a two-dimensional inverse fast Fourier transform (IFFT) process to obtain an FFT filtering image.

[0473] As a result, a real-space image in which only the crystal part is extracted can be obtained. Here, the proportion of the crystal part can be estimated from the ratio of the area of the remaining image. Also, by subtracting the remaining area from the area of the region used in the calculation (also referred to as the area of the original image), the proportion of the part other than the crystal part can be estimated.

[0474] ​​​​​​​​​​​​The cross-sectional TEM image of sample X1 is shown in Fig. 39(A1), and the cross-sectional TEM image of sample X1 after image analysis is shown respectively. Also, the cross-sectional TEM image of sample X2 is shown in Fig. 39(B1), and the image obtained after image analysis of the cross-sectional TEM image of sample X2 is shown in Fig. 39(B2). Also, the cross-sectional TEM image of sample X3 is shown in Fig. 39(C1), and the image obtained after image analysis of the cross-sectional TEM image of sample X3 is shown in Fig. 39(C2) respectively.

[0475] In the image obtained after image analysis, the region shown in white in the oxide semiconductor film corresponds to the region containing the crystalline part with orientation, and the region shown in black corresponds to the region containing the non-oriented crystalline part or the region containing crystalline parts oriented in various directions.

[0476] From the result shown in Fig. 39(A2), the ratio of the area excluding the region containing the crystalline part with orientation in sample X1 was about 43.1%. Also, from the result shown in Fig. 39(B2), the ratio of the area excluding the region containing the crystalline part with orientation in sample X2 was about 61.7%. Moreover, from the result shown in Fig. 39(C2), the ratio of the area excluding the region containing the crystalline part with orientation in sample X3 was about 89.5%. When the ratio of the part excluding the crystalline part with orientation in the oxide semiconductor film estimated in this way is

[0477] 5% or more and less than 40%, the oxide semiconductor film is a film with extremely high crystallinity, it is difficult to create oxygen deficiency, and since the electrical characteristics are very stable, it is preferable. On the other hand, when the ratio of the part excluding the crystalline part with orientation in the oxide semiconductor film is 40% or more and less than 100%, preferably 60% or more and 90% or less, the oxide semiconductor film has a crystalline part with orientation and an orientation part without orientation, and when it is in this case, The crystal part without the crystal structure is mixed at an appropriate ratio, and the stability of the electrical characteristics and the high mobility are achieved at the same time. This can be done.

[0478] Here, it can be clearly confirmed by a cross-sectional TEM image or by image analysis of the cross-sectional TEM image. The region excluding the crystal part is called the Lateral Growth Buffer Region. It can also be referred to as n(LGBR).

[0479] <2-6. Oxygen diffusion into oxide semiconductor films> Next, the results of evaluating the ease of diffusion of oxygen into the oxide semiconductor film will be described.

[0480] Here, the following three samples (samples Y1 to Y3) were prepared.

[0481] [Sample Y1] First, a 50 nm thick oxide film was formed on a glass substrate using the same method as in the sample X1. Next, a silicon oxynitride film having a thickness of about 30 nm was formed on the oxide semiconductor film. a silicon oxynitride film having a thickness of about 100 nm, and a silicon oxynitride film having a thickness of about 20 nm. The oxide semiconductor film was formed by laminating the oxide semiconductor film by plasma CVD. The silicon oxynitride film may be referred to as an OS and the silicon oxynitride film may be referred to as a GI.

[0482] Next, heat treatment was carried out in a nitrogen atmosphere at 350° C. for 1 hour.

[0483] Subsequently, a 5 nm thick In-Sn-Si oxide film was formed by sputtering.

[0484] Subsequently, oxygen was added to the silicon oxynitride film. The substrate temperature was set to 40°C using a welding device, and oxygen gas ( 16 O) and oxygen gas with a flow rate of 100 sccm ( 18 O) were introduced into the chamber, and the pressure was set to 15 P a. 4500 W of RF power was supplied for 600 sec between the parallel plate electrodes installed in the ashing device so that a bias was applied to the substrate side. Note that the reason for using oxygen gas ( 18 O) is that oxygen ( 16 O) is contained at the main component level in the silicon oxynitride film, so that the added oxygen can be accurately measured by the oxygen addition treatment. .

[0485] Subsequently, a silicon nitride film with a thickness of about 100 nm was formed by plasma CVD method.

[0486] [Sample Y2] Sample Y2 is a sample with different film formation conditions for the oxide semiconductor film of Sample Y1. Sample Y2 was formed with an oxide semiconductor film having a thickness of about 50 nm in the same manner as Sample X2 shown above.

[0487] [Sample Y3] Sample Y3 is a sample with different film formation conditions for the oxide semiconductor film of Sample Y1. Sample Y3 was formed with an oxide semiconductor film having a thickness of about 50 nm in the same manner as Sample X3 shown above.

[0488] Samples Y1 to Y3 were fabricated through the above processes.

[0489] [SIMS Analysis] For Samples Y1 to Y3, the concentration of O was measured by SIMS (Secondary Ion Mass S 18 pectrometry) analysis. Note that in the SIMS analysis, Samples Y1 to Y3 prepared above were evaluated without heat treatment, and the samples The conditions are such that the samples Y1 to Y3 are heat-treated at 350°C for 1 hour in a nitrogen atmosphere, and the sample Y1 The conditions are such that the samples Y1 to Y3 are heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and these three conditions are set.

[0490] The SIMS measurement results are shown in FIGS. 24(A), (B), and (C). Note that FIG. 24(A) shows the SIMS measurement results of the sample Y1 , FIG. 24(B) shows the SIMS measurement results of the sample Y2, and FIG. 24 (C) shows the SIMS measurement results of the sample Y3.

[0491] Also, in FIGS. 24(A), (B), and (C), the analysis results of the regions containing GI and OS are shown . FIGS. 24(A), (B), and (C) are the results of SIMS analysis from the substrate side (also called SSDP (Substrate Side Depth Profile)-SIMS).

[0492] Also, in FIGS. 24(A), (B), and (C), the thick dashed line represents the profile of the sample without heat treatment, the thin dashed line represents the profile of the sample heat-treated at 350°C, and the solid line represents the profile of the sample heat-treated at 450°C.

[0493] In each of the samples Y1 to Y3, it can be confirmed that O has diffused into GI and that O 18 has diffused into OS. Also, it can be confirmed that O has diffused to a deeper position in the order of sample Y1, sample Y2, and sample Y3 . Also, by performing heat treatment at 350°C and 4 18 50°C, it can be confirmed that O has diffused to an even deeper position . 18 . 18

[0494] ​​​​​​From the above results, it can be seen that an oxide semiconductor film in which a crystalline part with orientation and a crystalline part without orientation coexist and the proportion of the crystalline part with orientation is low is a film through which oxygen easily permeates, in other words, is a film in which oxygen easily diffuses. It can also be confirmed that by performing heat treatment at 350 °C and 450 °C, oxygen in the GI film diffuses into the OS.

[0495] The above results indicate that the higher the proportion (density) of the crystalline part with orientation, the more difficult it is for oxygen to diffuse in the thickness direction, and the lower the density, the easier it is for oxygen to diffuse in the thickness direction. Regarding the ease of oxygen diffusion in the oxide semiconductor film, it can be considered as follows. In an oxide semiconductor film in which a crystalline part with orientation and an extremely fine crystalline part without orientation coexist, the region (LGBR) other than the crystalline part that can be clearly observed in the cross-sectional observation image is a region where oxygen easily diffuses, that is, it can be a diffusion path for oxygen. Therefore, when there is a sufficient oxygen supply source near the oxide semiconductor film, oxygen is likely to be supplied to the crystalline part with orientation through the LGBR, so it is considered that the amount of oxygen deficiency in the film can be reduced.

[0496] In an oxide semiconductor film in which a crystalline part with orientation and an extremely fine crystalline part without orientation coexist, in the region (LGBR) other than the crystalline part that can be clearly observed in the cross-sectional observation image, oxygen easily diffuses, that is, it can be a diffusion path for oxygen. Therefore, when there is a sufficient oxygen supply source near the oxide semiconductor film, oxygen is likely to be supplied to the crystalline part with orientation through the LGBR, so it is considered that the amount of oxygen deficiency in the film can be reduced. In an oxide semiconductor film in which a crystalline part with orientation and an extremely fine crystalline part without orientation coexist, the region (LGBR) other than the crystalline part that can be clearly observed in the cross-sectional observation image is a region where oxygen easily diffuses, that is, it can be a diffusion path for oxygen. Therefore, when there is a sufficient oxygen supply source near the oxide semiconductor film, oxygen is likely to be supplied to the crystalline part with orientation through the LGBR, so it is considered that the amount of oxygen deficiency in the film can be reduced. Therefore, it is a region where oxygen easily diffuses, that is, it can be a diffusion path for oxygen. Therefore, when there is a sufficient oxygen supply source near the oxide semiconductor film, oxygen is likely to be supplied to the crystalline part with orientation through the LGBR, so it is considered that the amount of oxygen deficiency in the film can be reduced. For example, when an oxide film that easily releases oxygen is provided in contact with the oxide semiconductor film and heat treatment is performed, the oxygen released from the oxide film diffuses in the thickness direction of the oxide semiconductor film by the LGBR. And through the LGBR, oxygen can be supplied laterally to the crystalline part with orientation. As a result, oxygen can be sufficiently distributed to the crystalline part with orientation of the oxide semiconductor film and other regions, and the oxygen deficiency in the film can be effectively reduced.

[0497] For example, when an oxide film that easily releases oxygen is provided in contact with the oxide semiconductor film and heat treatment is performed, the oxygen released from the oxide film diffuses in the thickness direction of the oxide semiconductor film by the LGBR. And through the LGBR, oxygen can be supplied laterally to the crystalline part with orientation. As a result, oxygen can be sufficiently distributed to the crystalline part with orientation of the oxide semiconductor film and other regions, and the oxygen deficiency in the film can be effectively reduced. And through the LGBR, oxygen can be supplied laterally to the crystalline part with orientation. As a result, oxygen can be sufficiently distributed to the crystalline part with orientation of the oxide semiconductor film and other regions, and the oxygen deficiency in the film can be effectively reduced. As a result, oxygen can be sufficiently distributed to the crystalline part with orientation of the oxide semiconductor film and other regions, and the oxygen deficiency in the film can be effectively reduced. As a result, oxygen can be sufficiently distributed to the crystalline part with orientation of the oxide semiconductor film and other regions, and the oxygen deficiency in the film can be effectively reduced. [[ID=]43] ​​​

[0498] For example, if there are hydrogen atoms in the oxide semiconductor film that are not bonded to metal atoms, these may bond with oxygen atoms to form OH and become immobilized. Therefore, by forming the film at a low temperature, a state in which hydrogen atoms are trapped in oxygen vacancies (V o ) (referred to as V H) is formed in a certain amount (for example, about 1×10 o cm 17 ), thereby suppressing the generation of OH -3 . In addition, since V H generates carriers, a state in which a certain amount of carriers exists in the oxide semiconductor film o is achieved. As a result, an oxide semiconductor film with an increased carrier density can be formed. Also, during film formation, oxygen vacancies are simultaneously formed, but the oxygen vacancies can be reduced by introducing oxygen through LGBR as described above. By such a method, an oxide semiconductor film with a relatively high carrier density and sufficiently reduced oxygen vacancies can be formed.

[0499] In addition, regions other than the crystalline part having orientation form extremely fine crystal parts that do not have orientation during film formation, so distinct crystal grain boundaries cannot be confirmed in the oxide semiconductor film. Also, the fine crystal parts are located between a plurality of crystalline parts having orientation. The fine crystal parts grow horizontally due to the heat during film formation and bond to adjacent crystalline parts having orientation. Also, the fine crystal parts also function as regions that generate carriers. As a result, an oxide semiconductor film having such a configuration is considered to be able to significantly improve its field-effect mobility when applied to a transistor.

[0500] ​​​In addition, after forming an oxide semiconductor film and forming an oxide insulating film such as a silicon oxide film thereon, In addition, it is preferable to perform plasma treatment in an oxygen atmosphere. Besides supplying oxygen, the hydrogen concentration can be reduced. For example, during plasma processing At the same time, fluorine remaining in the chamber may also be doped into the oxide semiconductor film. Fluorine exists as negatively charged fluorine atoms and positively charged hydrogen atoms. The atoms bond with each other through Coulomb forces to generate HF, which is then released from the oxide during the plasma treatment. As a result, the hydrogen concentration in the oxide semiconductor film is reduced. In addition, in the plasma treatment, oxygen atoms and hydrogen atoms are bonded to form H2O, which is deposited on the film. It may also be released outside.

[0501] In addition, a structure in which a silicon oxide film (or a silicon oxynitride film) is stacked on an oxide semiconductor film The fluorine in the silicon oxide film bonds with the hydrogen in the film, forming an electrically neutral HF Since the Si-F bond can exist as a Si-F bond, it does not affect the electrical properties of the oxide semiconductor film. Although this may occur, it also becomes electrically neutral. It is thought that this does not affect the diffusion of elements.

[0502] Due to the above-described mechanism, oxygen vacancies in the oxide semiconductor film are reduced, and the metal in the film is It is believed that the reliability can be improved by reducing hydrogen atoms that are not bonded to metal atoms. In addition, when the carrier density of the oxide semiconductor film is higher than a certain level, the electrical characteristics are improved. It is thought that this is the case.

[0503] <2-7. Method for forming oxide semiconductor film> Hereinafter, a method for forming an oxide semiconductor film according to an aspect of the present invention will be described.

[0504] An oxide semiconductor film according to an aspect of the present invention can be formed by a sputtering method in an atmosphere containing oxygen. It can be formed.

[0505] The substrate temperature during film formation is preferably in the range of room temperature or higher and 150°C or lower, more preferably 50°C or higher and 150°C or lower, still more preferably 100°C or higher and 150°C or lower, and typically 130°C. By setting the temperature of the substrate within the above range, the ratio of the crystalline portion having orientation and the crystalline portion having no orientation can be controlled. It can be controlled.

[0506] In addition, the flow rate ratio (oxygen partial pressure) of oxygen during film formation is 1% or more and less than 33%, preferably 5% or more and 30% or less, more preferably 5% or more and 20% or less, still more preferably 5% or more and 15% or less and typically 10%. By reducing the oxygen flow rate, a larger amount of the crystalline portion having no orientation can be included in the film. It can be included.

[0507] Therefore, by setting the substrate temperature and the oxygen flow rate during film formation within the above ranges, an oxide semiconductor film in which the crystalline portion having orientation and the crystalline portion having no orientation are mixed can be obtained. Also, by setting the substrate temperature and the oxygen flow rate within the above ranges, it becomes possible to control the abundance ratio of the crystalline portion having orientation and the crystalline portion having no orientation. It can be obtained. It becomes possible.

[0508] The oxide target that can be used for forming the oxide semiconductor film is not limited to the In-Ga-Zn-based oxide, and for example, an In-M-Zn-based oxide (M is Al, Ga, Y, or Sn) can be applied. It can be applied.

[0509] ​​ Further, when forming an oxide semiconductor film including a crystal portion that is an oxide semiconductor film using a sputtering target containing a polycrystalline oxide having a plurality of crystal grains, an oxide semiconductor film having crystallinity is more likely to be obtained than when using a sputtering target that does not contain a polycrystalline oxide. The following is an explanation of a consideration in the film formation mechanism of the oxide semiconductor film. The sputtering target has a plurality of crystal grains, and the crystal grains have a layered structure, and when there is an interface that is likely to split in the crystal grains, by colliding ions with the sputtering target, the crystal grains may split to obtain plate-shaped or pellet-shaped sputtering particles. It is considered that an oxide semiconductor film containing nanocrystals is formed by the deposition of the obtained plate-shaped or pellet-shaped sputtering particles on a substrate. Further, by heating the substrate, the bonding or rearrangement of the nanocrystals on the substrate surface proceeds, and it is considered that an oxide semiconductor film including a crystal portion having orientation is more likely to be formed. Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition).

[0510] Hereinafter, a consideration in the film formation mechanism of the oxide semiconductor film will be described. When the sputtering target has a plurality of crystal grains and the crystal grains have a layered structure and there is an interface that is likely to split in the crystal grains, by colliding ions with the sputtering target, the crystal grains may split to obtain plate-shaped or pellet-shaped sputtering particles. It is considered that an oxide semiconductor film containing nanocrystals is formed by the deposition of the obtained plate-shaped or pellet-shaped sputtering particles on a substrate. Further, by heating the substrate, the bonding or rearrangement of the nanocrystals on the substrate surface proceeds, and it is considered that an oxide semiconductor film including a crystal portion having orientation is more likely to be formed. The sputtering target has a plurality of crystal grains, and the crystal grains have a layered structure, and when there is an interface that is likely to split in the crystal grains, by colliding ions with the sputtering target, the crystal grains may split to obtain plate-shaped or pellet-shaped sputtering particles. When the obtained plate-shaped or pellet-shaped sputtering particles are deposited on a substrate, it is considered that an oxide semiconductor film containing nanocrystals is formed. Further, by heating the substrate, the bonding or rearrangement of the nanocrystals on the substrate surface proceeds, and it is considered that an oxide semiconductor film including a crystal portion having orientation is more likely to be formed. Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition). When the obtained plate-shaped or pellet-shaped sputtering particles are deposited on a substrate, it is considered that an oxide semiconductor film containing nanocrystals is formed. Further, by heating the substrate, the bonding or rearrangement of the nanocrystals on the substrate surface proceeds, and it is considered that an oxide semiconductor film including a crystal portion having orientation is more likely to be formed. Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition). Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic

[0511] Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition). Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition). Note that although the method of forming by sputtering method has been described here, it is particularly preferable to use the sputtering method because the control of crystallinity is easy. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. may be used. As an example of the thermal CVD method, there is MOCVD (Metal Organic Chemic al Vapor Deposition). Examples include the AL (Aluminum) Vapor Deposition method.

[0512] This embodiment can be implemented in appropriate combination with at least some parts thereof and other embodiments described in this specification.

[0513] (Embodiment 3) In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 40 to 47.

[0514] <3-1. Configuration Example 1 of Semiconductor Device> FIG. 40(A) is a top view of a semiconductor device 200 according to one aspect of the present invention, and FIG. 40(B) corresponds to a cross-sectional view of a cut surface between the dashed-dotted line A1-A2 shown in FIG. 40(A). Note that FIG. 40(B) includes a cross-section in the channel length (L) direction of the transistor Tr1 and a cross-section in the channel length (L) direction of the transistor Tr2. 40(B) includes a cross-section in the channel length (L) direction of the transistor Tr1 and a cross-section in the channel length (L) direction of the transistor Tr2.

[0515] The semiconductor device 200 shown in FIGS. 40(A) and 40(B) includes a transistor Tr1 and a transistor Tr2 at least partially overlapping with the transistor Tr1. Note that both the transistors Tr1 and Tr2 are top-gate type transistors. By providing a region where the transistor Tr1 and the transistor Tr2 at least partially overlap with each other, the layout area of the transistors can be reduced.

[0516] By providing a region where the transistor Tr1 and the transistor Tr2 at least partially overlap with each other, the layout area of the transistors can be reduced.

[0517] The transistor Tr1 includes an insulating film 106 on a substrate 102, an oxide semiconductor film 108 on the insulating film 106, an insulating film 110 on the oxide semiconductor film 108, and a conductive film 120 on the insulating film 110. ​​​​​It has an insulating film 106, an oxide semiconductor film 108, and an insulating film 114 on the conductive film 120. Also, similar to Embodiment 1, the oxide semiconductor film 108 overlaps with the conductive film 120 and has a channel region 108i in contact with the insulating film 110, a source region 108s in contact with the insulating film 114 and a drain region 108d in contact with the insulating film 114.

[0518] Also, the transistor Tr1 has an insulating film 116 on the insulating film 114, and a conductive film 112a that is electrically connected to the oxide semiconductor film 108 through an opening 141a provided on the insulating film 114 and the insulating film 116, a conductive film 112b that is electrically connected to the oxide semiconductor film 108 through an opening 141b provided in the insulating film 114 and the insulating film 116, and an insulating film 118 on the insulating film 116, the conductive film 112a, and the conductive film 112b.

[0519] Also, the transistor Tr2 has a conductive film 112b, an insulating film 118 on the conductive film 112b, an oxide semiconductor film 208 on the insulating film 118, an insulating film 210b on the oxide semiconductor film 208, a conductive film 212b on the insulating film 210b, and an insulating film 214 on the oxide semiconductor film 208 and the conductive film 212b. Also, similar to the oxide semiconductor film 108, the oxide semiconductor film 208 has a channel region 208i that overlaps with the conductive film 212b and is in contact with the insulating film 210b, a source region 208s in contact with the insulating film 214, and a drain region 208d in contact with the insulating film 214.

[0520] Also, the transistor Tr2 has an insulating film 216 on the insulating film 214, and a conductive film 218a provided on the insulating film 216 and electrically connected to the oxide semiconductor film 208. It includes a conductive film 218b that is provided and electrically connected to the oxide semiconductor film 208.

[0521] Note that as shown in FIGS. 40(A) and (B), the oxide semiconductor film 108 and the oxide semiconductor film 20 8 have an overlapping region with each other.

[0522] The oxide semiconductor film 108 can have the same configuration as that shown in Embodiment 1. The oxide semiconductor film 208 can have the same configuration as the oxide semiconductor film 128 shown in Embodiment 1.

[0523] Therefore, it becomes possible to form a high field-effect mobility of the transistor Tr2.

[0524] For example, by using the above transistor with a high field-effect mobility in a gate driver that generates a gate signal of a display device, a display device with a narrow frame width (also referred to as a narrow-frame) can be provided. Also, by using the above transistor with a high field-effect mobility in a source driver (particularly, a demultiplexer connected to the output terminal of a shift register included in the source driver) that supplies a signal from a signal line of a display device, a display device with a small number of wirings connected to the display device can be provided. Further, by using the above transistor with a high field-effect mobility in either one or both of a selection transistor and a drive transistor of a pixel circuit of a display device, a display device with high display quality can be provided.

[0525] Although not shown in the semiconductor device 100A shown in FIG. 40, for the capacitance element Cs1, the capacitance between the film formed simultaneously with the conductive film 112b and the film formed simultaneously with the conductive film 212b ​​​​​​​​​The insulating film forming the capacitance can be formed at the same time as the insulating film 118. and / or one of a film formed simultaneously with the insulating film 210b. do.

[0526] In one aspect of the present invention, the insulating film forming this capacitance is formed at the same time as the insulating film 118. When trying to obtain a certain on-current in the saturation region, the oxide semiconductor The oxide semiconductor of the transistor measured in FIG. 8(B) or FIG. 8(C) is present in the film 208. By using a conductive film, the oxide semiconductor film of the transistor measured in FIG. The thickness of the film formed simultaneously with the insulating film 210b can be increased compared to when using the insulating film 210b. do.

[0527] That is, the transistor Tr2 is connected to the transistor measured in FIG. 8(B) or FIG. 8(C). By using an oxide semiconductor film included in the transistor, the storage capacitance of the capacitor Cs1 is reduced. This allows the footprint of the transistor to be reduced.

[0528] The semiconductor device 200 shown in FIGS. 40(A) and 40(B) is suitable for use in a pixel circuit of a display device. By using the arrangement shown in FIGS. 40(A) and 40(B), the pixel density of the display device can be increased. For example, it is possible to increase the pixel density of a display device to over 1000 ppi. Even when the pixel density of the display device exceeds 2000 ppi, the same applies to the display device shown in Figs. 40(A) and (B). By using the arrangement shown in FIG. 1, the aperture ratio of the pixel can be increased.

[0529] When the semiconductor device 200 shown in FIG. 40(A)(B) is applied to a pixel circuit of a display device, In this case, the pixel circuit can have the same configuration as that shown in FIG.

[0530] Also, when applying the semiconductor device 200 shown in FIGS. 40(A) and (B) to the pixels of a display device, for example the channel length (L) and channel width (W) of the transistor, or the line width of the wiring and electrodes connected to the transistor, e...

Claims

Claim 1: A display device comprising a substrate, a first transistor having a region located above the substrate, a second transistor having a region located above the substrate, and a light-emitting element having a region located above the substrate, a first semiconductor layer having a channel formation region of the first transistor, a first conductive layer having a region functioning as a gate electrode of the first transistor, a second conductive layer electrically connected to a source or a drain of the first transistor, a second semiconductor layer having a channel formation region of the second transistor, a third conductive layer having a region functioning as a gate electrode of the second transistor, a fourth conductive layer electrically connected to a source or a drain of the second transistor, a fifth conductive layer electrically connected to the fourth conductive layer and having a region functioning as one of a pair of electrodes of the light-emitting element, a sixth conductive layer having a region functioning as the other of the pair of electrodes of the light-emitting element, a first insulating layer having a region located above the first conductive layer and a region located below the second conductive layer, a second insulating layer having a region located between the second conductive layer and the second semiconductor layer, a third insulating layer having a region located above the third conductive layer and a region located below the fourth conductive layer, a fourth insulating layer having a region located between the fourth conductive layer and the fifth conductive layer, a fifth insulating layer having a region located between the fifth conductive layer and the sixth conductive layer, wherein the second conductive layer has a region in contact with the second insulating layer, in a plan view, the second semiconductor layer has a shape in which a width in a direction along a channel length of the second transistor is larger than a width in a direction along a channel width of the second transistor, in a plan view, the second conductive layer has a region overlapping with an entire channel formation region of the second transistor of the second semiconductor layer via the second insulating layer, in a plan view, the second semiconductor layer has an overlap with a light-emitting region of the light-emitting element, and the light-emitting element emits light upward. Claim 2: A display device comprising a substrate, a first transistor having a region located above the substrate, a second transistor having a region located above the substrate, and a light-emitting element having a region located above the substrate, A first semiconductor layer having a channel formation region of the first transistor; A first conductive layer having a region that functions as a gate electrode of the first transistor; A second conductive layer electrically connected to a source or a drain of the first transistor; A second semiconductor layer having a channel formation region of the second transistor; A third conductive layer having a region that functions as a gate electrode of the second transistor; A fourth conductive layer electrically connected to a source or a drain of the second transistor; A fifth conductive layer electrically connected to the fourth conductive layer and having a region that functions as one of a pair of electrodes of the light-emitting element; A sixth conductive layer having a region that functions as the other of a pair of electrodes of the light-emitting element; A first insulating layer having a region disposed above the first conductive layer and a region disposed below the second conductive layer; A second insulating layer having a region disposed between the second conductive layer and the second semiconductor layer; A third insulating layer having a region disposed above the third conductive layer and a region disposed below the fourth conductive layer; A fourth insulating layer having a region disposed between the fourth conductive layer and the fifth conductive layer; A fifth insulating layer having a region disposed between the fifth conductive layer and the sixth conductive layer, and The second conductive layer has a region in contact with the second insulating layer, In a plan view, the second semiconductor layer has a shape in which a width in a direction along the channel length of the second transistor is larger than a width in a direction along the channel width of the second transistor, In a plan view, the second conductive layer has a region overlapping the entire second semiconductor layer via the second insulating layer, In a plan view, the second semiconductor layer has an overlap with a light-emitting region of the light-emitting element, A display device that emits light of the light-emitting element upward.

3. A substrate, a first transistor having a region located above the substrate, a second transistor having a region located above the substrate, and a light-emitting element having a region located above the substrate, and A first semiconductor layer having a channel formation region of the first transistor; A first conductive layer having a region that functions as a gate electrode of the first transistor; A second conductive layer electrically connected to a source or a drain of the first transistor; A second semiconductor layer having a channel formation region of the second transistor; A third conductive layer having a region functioning as a gate electrode of the second transistor; A fourth conductive layer electrically connected to a source or a drain of the second transistor; A fifth conductive layer electrically connected to the fourth conductive layer and having a region functioning as one of a pair of electrodes of the light-emitting element; A sixth conductive layer having a region functioning as the other of the pair of electrodes of the light-emitting element; A first insulating layer having a region disposed above the first conductive layer and a region disposed below the second conductive layer; A second insulating layer having a region disposed between the second conductive layer and the second semiconductor layer; A third insulating layer having a region disposed above the third conductive layer and a region disposed below the fourth conductive layer; A fourth insulating layer having a region disposed between the fourth conductive layer and the fifth conductive layer; A fifth insulating layer having a region disposed between the fifth conductive layer and the sixth conductive layer; The second conductive layer has a region in contact with the second insulating layer; In plan view, the second semiconductor layer has a shape in which a width in a direction along a channel length of the second transistor is larger than a width in a direction along a channel width of the second transistor; In plan view, the second conductive layer has a region overlapping the entire channel formation region of the second transistor of the second semiconductor layer via the second insulating layer; In plan view, the first semiconductor layer and the second semiconductor layer do not overlap; In plan view, the second semiconductor layer overlaps with a light-emitting region of the light-emitting element; A display device that emits light of the light-emitting element upward. A substrate, a first transistor having a region located above the substrate, a second transistor having a region located above the substrate, and a light-emitting element having a region located above the substrate; A first semiconductor layer having a channel formation region of the first transistor; A first conductive layer having a region functioning as a gate electrode of the first transistor; A second conductive layer electrically connected to a source or a drain of the first transistor; A second semiconductor layer having a channel formation region of the second transistor; A third conductive layer having a region functioning as a gate electrode of the second transistor; A fourth conductive layer electrically connected to the source or drain of the second transistor; A fifth conductive layer electrically connected to the fourth conductive layer and having a region that functions as one of a pair of electrodes of the light-emitting element; A sixth conductive layer having a region that functions as the other of the pair of electrodes of the light-emitting element; A first insulating layer having a region disposed above the first conductive layer and a region disposed below the second conductive layer; A second insulating layer having a region disposed between the second conductive layer and the second semiconductor layer; A third insulating layer having a region disposed above the third conductive layer and a region disposed below the fourth conductive layer; A fourth insulating layer having a region disposed between the fourth conductive layer and the fifth conductive layer; A fifth insulating layer having a region disposed between the fifth conductive layer and the sixth conductive layer, and the second conductive layer has a region in contact with the second insulating layer, in a plan view, the second semiconductor layer has a shape in which the width in a direction along the channel length of the second transistor is larger than the width in a direction along the channel width of the second transistor, in a plan view, the second conductive layer has a region overlapping the entire second semiconductor layer via the second insulating layer, in a plan view, the first semiconductor layer and the second semiconductor layer do not overlap, in a plan view, the second semiconductor layer overlaps with the light-emitting region of the light-emitting element, A display device that emits light of the light-emitting element upward.

Images