3D Memory Device with Backside Interconnection Structure

Abstract

To provide a three-dimensional memory device with a backside interconnect structure.SOLUTION: An embodiment of a three-dimensional memory device and a method for forming the same are disclosed. In one example, the three-dimensional memory device comprises: a substrate; a memory stack including conductor layers and dielectric layers which are alternately arranged above the substrate; a plurality of channel structures each vertically penetrating the memory stack; a semiconductor layer provided above the plurality of channel structures and in contact with the plurality of channel structures; a plurality of source contacts provided above the memory stack and in contact with the semiconductor layer; a plurality of contacts passing through the semiconductor layer; and a backside interconnect layer provided above the semiconductor layer including a source line mesh in plan view. The plurality of source contacts are distributed below the source line mesh and in contact with the source line mesh. A first set of the plurality of contacts is distributed below the source line mesh and in contact with the source line mesh.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of priority of International Application No. PCT / CN2020 / 084600, filed on April 14, 2020, with the title "THREE - DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT", and International Application No. PCT / CN2020 / 084603, filed on April 14, 2020, with the title "METHOD FOR FORMING THREE - DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT", which are hereby incorporated by reference in their entirety.

[0002] Embodiments of the present disclosure relate to three - dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0003] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cells approaches the lower limit, planar processes and fabrication techniques become difficult and the cost increases. As such, the memory density of planar memory cells is approaching the upper limit.

[0004] 3D memory architectures can address this density limit of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of a 3D memory device and a method for forming the same are disclosed herein.

[0006] In one example, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers above the substrate, a plurality of channel structures each penetrating the memory stack in a vertical direction, a semiconductor layer above the plurality of channel structures and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts is distributed below and in contact with the source line mesh.

[0007] In another example, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers above the substrate, a plurality of channel structures each penetrating the memory stack in a vertical direction, a semiconductor layer above the plurality of channel structures and in contact with the plurality of channel structures, a plurality of source contacts in contact with the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. Each of the channel structures is below and horizontally aligned with each of the source contacts. The source line mesh is above and in contact with each of the source contacts.

[0008] In yet another example, a method for forming a 3D memory device is disclosed. Peripheral circuitry is formed on a first substrate. A plurality of channel structures are formed that each vertically penetrate a memory stack that is on a front side of a second substrate. The first substrate and the second substrate are bonded face-to-face, whereby the channel structures are above the peripheral circuitry. The second substrate is thinned. A plurality of contacts are formed that pass through the thinned second substrate and a plurality of source contacts are formed that contact the thinned second substrate. A source line mesh is formed on a back side of the thinned second substrate, and the source line mesh is above and in contact with the plurality of source contacts and a first set of the plurality of contacts.

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and further to enable one skilled in the art to make and use the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010]

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DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure are described with reference to the accompanying drawings.

[0012] Although specific configurations and arrangements are described, it will be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may be employed in various other applications.

[0013] References in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc., should be noted to indicate that the described embodiments may have certain features, structures, or characteristics, but not all embodiments necessarily include the certain features, structures, or characteristics. Further, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in relation to one embodiment, it will be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments, whether explicitly described or not.

[0014] Generally, terms can be understood at least in part from their usage in context. For example, at least in part depending on the context, the phrase "one or more" as used herein can be used to describe a feature, structure, or characteristic in the singular sense or to describe a combination of features, structures, or characteristics in the plural sense. Similarly, here too, articles such as "a", "an", or "the" in the English language can be understood as conveying the use of the singular or the plural at least in part depending on the context. In addition, the phrase "based on" can be understood not necessarily to convey an exclusive set of elements, but rather, here too at least in part depending on the context, to allow for the presence of additional elements not necessarily explicitly described.

[0015] The meanings of "above", "higher than", and "directly above" in the present disclosure should be immediately understood to be interpreted in the broadest sense such that "above" means not only "directly above" something, but also "above" something with intermediate features or layers in between, and "higher than" or "directly above" means not only "higher than" or "directly above" something, but also can include the meaning of being "higher than" or "directly above" something without intermediate features or layers in between (i.e., directly above something).

[0016] Spatial relative terms such as "lower", "below", "lower side", "upper", "upper side", and similar terms may be used herein to facilitate the description when describing the relationship between one element or feature and another element or feature, as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in addition to, or operating in, the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or in some other orientation), and the spatial relative descriptors used herein may likewise be construed accordingly.

[0017] As used herein, the term "substrate" refers to the material to which subsequent material layers are added. A pattern can be formed on the substrate itself. The material added on the substrate can be patterned or left unpatterned. Further, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0018] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend across the entire underlying or overlying structure, or can have an extent smaller than the extent of the underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure, or between pairs of horizontal planes at the top and bottom surfaces. A layer can extend along horizontal, vertical, and / or tapered surfaces. A substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can also include a plurality of layers. For example, an interconnect layer can include one or more conductor layers and contact layers (wherein interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0019] As used herein, the phrase "nominal / nominally" refers to a desired or target value of a characteristic or parameter for a component or process operation that is set at the design stage of a product or process, along with a range of values above and / or below the desired value. The range of values can be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on the particular technology node associated with the semiconductor device of the subject matter. Based on the particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0020] As used herein, the term "3D memory device" refers to a semiconductor device having a vertical orientation string of memory cell transistors (referred to herein as a "memory string", such as a NAND memory string) on a horizontally oriented substrate such that the memory string extends in a direction perpendicular to the substrate. As used herein, the phrase "vertical / perpendicularly" means being nominally perpendicular to the outer surface of the substrate.

[0021] In some 3D memory devices, the peripheral circuits and the memory array are stacked to reduce wafer area and increase memory cell density. For example, a direct bonding technique has been proposed for fabricating some 3D NAND memory devices (e.g., having 96 or more layers) by connecting the peripheral devices and the memory array face-to-face on different substrates. The memory array substrate is then thinned to form silicon through-vias (VIAs) called "TSVs" that lead to vertical interconnects through the substrate, and is pad-out by wire bonding pads on the back side of the thinned substrate. However, since only wire bonding pads and TSVs are formed on the back side of the thinned substrate (i.e., the top surface of the bonded 3D memory device), a substantial amount of the area on the back side of the thinned substrate is wasted.

[0022] Various embodiments according to the present disclosure provide a 3D memory device having a backside interconnect structure that better utilizes the backside region and optimizes metal routing. Some or all of the source lines, source select gate (SSG) lines, and power lines can be moved as a "backside interconnect structure" from the front side of the memory array substrate (i.e., the center of the bonded 3D memory device) to the back side of the memory array substrate (i.e., the top surface of the bonded 3D memory device). In some embodiments, the backside source lines enable source contacts to also be formed on the back side of the memory array substrate, which can avoid leakage current and parasitic capacitance between the word lines and source contacts on the front side through the memory stack. The various backside interconnect structures are arranged and configured in different layouts, such as a mesh (e.g., a shape like a comb) or parallel straight lines, to optimize metal routing, reduce the overall resistance based on different memory array structures, and further improve the electrical performance of the 3D memory device.

[0023] FIG. 1 illustrates a plan view of a cross section of an exemplary 3D memory device 100 having a central staircase region according to some embodiments of the present disclosure. As shown in FIG. 1, the memory stack of the 3D memory device 100 can include two core array regions 106A and 106B having channel structures 110 therein, and a staircase region 104 between the first lateral core array regions 106A and 106B in the plan view. Note that FIG. 1 includes an x-axis and a y-axis to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. The 3D memory device 100, according to some embodiments, includes a central staircase region 104 that laterally separates the memory stack into two parts in the x-direction (e.g., the word line direction), i.e., a first core array region 106A and a second core array region 106B, each of those core array regions including an array of channel structures 110.

[0024] In some embodiments, the 3D memory device 100 also includes parallel insulating structures 108 (e.g., gate line slits (GLS)) in the y-direction (e.g., bit line direction), each extending laterally in the x-direction to separate the core array regions 106A and 106B and the array of channel structures 110 therein into blocks 102. The 3D memory device 100 further includes drain select gate (DSG) cuts 112 (sometimes also referred to as top select gate (TSG) cuts) that are parallel in the y-direction in block 102, which can further separate block 102 into fingers. It is understood that the layout of the staircase region and the core array region is not limited to the example of FIG. 1 and may include any other suitable layout, such as having side staircase regions at the edges of the memory stack in other examples.

[0025] The cross-section of the 3D memory device 100 is at the front side of the 3D memory device 100 where the channel structure 110 is formed. In some embodiments, the 3D memory device 100 is flipped upside down and bonded to another semiconductor device, such as a peripheral device having peripheral circuits to smooth the operation of the 3D memory device 100. Thus, the back side of the 3D memory device 100 becomes the top surface of the bonded device and can be used for pad out. As detailed below, the region of the back side of the 3D memory device 100 (i.e., the top surface of the bonded device) can be used to form various back side interconnect structures in various layouts in addition to bonding pads, optimize metal routing, reduce the overall resistance, and also reduce the leakage current and parasitic capacitance of the front side of the 3D memory device 100.

[0026] FIG. 2A illustrates a plan view of a cross-section of an exemplary 3D memory device 200 having a backside interconnect structure, according to some embodiments of the present disclosure. The 3D memory device 200 may be an example of the 3D memory device 100 after flip-chip bonding, and FIG. 2A shows an example of the backside of the 3D memory device 100 after flip-chip bonding. As shown in FIG. 2A, the memory stack of the 3D memory device 200 includes, according to some embodiments, two core array regions 206A and 206B having a channel structure (not shown) therein, and a staircase region 204 between the core array regions 206A and 206B in the x direction (e.g., word line direction) in the plan view. In some embodiments, the 3D memory device 200 further includes a peripheral region 208 outside the core array region 206A or 206B of the memory stack in the plan view. In the y direction (e.g., bit line direction), FIG. 2A shows the backside interconnect structure in one block 202 of the 3D memory device 200, which may be repeated any suitable number of times in a plurality of blocks.

[0027] In some embodiments, the 3D memory device 200 includes a source line mesh 210 in the plan view. As shown in FIG. 2A, the source line mesh 210 has a comb-like shape according to some embodiments. For example, the source line mesh 210 may include shaft source lines 214 extending laterally in the y direction (e.g., bit line direction) in one of the core array regions 206A and 206B. The source line mesh 210 may also include a plurality of parallel tooth source lines 212 extending laterally from the shaft source lines 214 in one of the core array regions 206A in the x direction (e.g., word line direction), through the staircase region 204, to the other core array region 206B. In some embodiments, the source line mesh 210 is within the core array regions 206A and 206B and the staircase region 204, and extends, for example, in the x direction across the core array regions 206A and 206B and the staircase region 204, but not in the peripheral region 208.

[0028] The 3D memory device 200 can include backside source contacts 216 (e.g., in the form of VIA contacts) within the core array regions 206A and 206B, but not within the staircase region 204 or the peripheral region 208. For example, the backside source contacts 216 can be evenly distributed across the core array region 206A or 206B. In some embodiments, the backside source contacts 216 are distributed to be below and in contact with the source line mesh 210. For example, the backside source contacts 216 can be evenly distributed to be below and in contact with the source line mesh 210 within the core array region 206A or 206B. That is, the distance (in the x direction and / or y direction) between adjacent backside source contacts 216 is the same within the core array region 206A or 206B. In some embodiments, the backside source contacts 216 are distributed to be below and in contact with the tooth source lines 212 of the source line mesh 210, but not so for the shaft source lines 214 of the source line mesh 210. In some examples, it is understood that the backside source contacts 216 in the form of VIA contacts can be replaced by one or more source wall-shaped contacts, i.e., interconnect lines.

[0029] The 3D memory device 200 can further include multiple sets of contacts 218, 226, 230, such as through-silicon contacts (TSCs). In some embodiments, the contact 218 is distributed to contact the source line mesh 210 below the source line mesh 210 in the stepped region 204 and in a part of the core array regions 206A and 206B. Since the contact 218 can be a TSC that penetrates the silicon substrate, according to some embodiments, the contact 218 is distributed below the peripheral portion of the source line mesh 210 (including the portion of the stepped region 204) to avoid overlapping with the channel structure of the central portion of the source line mesh 210 within the core array regions 206A and 206B and to contact the peripheral portion. For example, as shown in FIG. 2A, the contact 218 can be distributed below and in contact with the shaft source lines 214 and the outermost tooth source lines 212 of the source line mesh 210 within the core array regions 206A and 206B. The contact 218 can also be distributed below each tooth source line 212 of the source line mesh 210 in the stepped region 204 and in contact with each tooth source line 212.

[0030] As described in detail below, each backside source contact 216 may be electrically connected to a common source of the NAND memory strings in block 202 (e.g., an array common source (ASC)), and the source line mesh 210 electrically connects each backside source contact 216 and is then electrically connected to the common source of the NAND memory strings in block 202. Similarly, each contact 218 may be electrically connected to the peripheral circuits of the 3D memory device 200, and the source line mesh 210 electrically connects each contact 218 and is then electrically connected to the peripheral circuits of the 3D memory device 200. As a result, the peripheral circuits are electrically connected to the common source of the NAND memory strings in block 202 and can control and / or sense the common source through the metal routing including the backside contacts 218, the source line mesh 210, and the backside source contacts 216 of the 3D memory device 200. The layout of the contacts 218, the source line mesh 210, and the backside source contacts 216, e.g., the comb-like shape of the source line mesh 210, as well as the plurality of distributed contacts 218 and backside source contacts 216, can reduce the overall resistance of the metal routing.

[0031] In some embodiments, the 3D memory device 200 includes, in a plan view, another backside interconnect structure - a power line mesh 220. As shown in FIG. 2A, the power line mesh 220 has a comb-like shape according to some embodiments. For example, the power line mesh 220 may include shaft power lines 224 that extend horizontally in the y direction (e.g., the bit line direction) in the peripheral region 208. The power line mesh 220 may also include a plurality of parallel tooth power lines 222 that extend horizontally from the shaft power lines 224 in the peripheral region 208 in the x direction (e.g., the word line direction), through one core array region 206B, through the staircase region 204, and to the other core array region 206A. In some embodiments, the power line mesh 220 is within the peripheral region 208, the core array regions 206A and 206B, and the staircase region 204, and extends in the x direction from the peripheral region 208, for example, across the core array regions 206A and 206B and the staircase region 204. In some embodiments, the tooth power lines 222 are alternately arranged with the tooth source lines 212 in the y direction.

[0032] In some embodiments, contact 226 is distributed to contact the power line mesh 220 below the power line mesh 220 within the staircase region 204 and the peripheral region 208, but not within the core array regions 206A and 206B. Since contact 226 may be a TSC that penetrates the silicon substrate, according to some embodiments, contact 226 is absent from core array regions 206A and 206B and avoids overlapping with the channel structures of core array regions 206A and 206B. For example, as shown in FIG. 2A, contact 226 may be distributed to contact below and in contact with a portion of the shaft power line 224 in the peripheral region 208 and the tooth power line 222 in the staircase region 204. In some examples, it is understood that contact 226 may be distributed to either the peripheral region 208 or the staircase region 204, but not both. That is, contact 226 can be distributed to at least one of the staircase region 204 or the peripheral region 208 outside the memory array in the plan view.

[0033] Each contact 226 may be electrically connected to the power lines of the peripheral circuit of the 3D memory device 200, and the power line mesh 220 electrically connects each contact 226 and then is electrically connected to the power lines of the peripheral circuit of the 3D memory device 200. The power supply may be electrically connected to the power line mesh 220 through a bonding pad (not shown), and power can be supplied to the 3D memory device 200 through the metal routing including the contact 226 and the power line mesh 220 on the back side of the 3D memory device 200. The bonding pad is part of the back side interconnect structure and can be electrically connected to the power line mesh 220 through contact 226. The layout of contact 226 and power line mesh 220, for example, the comb-like shape of power line mesh 220, as well as the plurality of distributed contacts 226, can reduce the overall resistance of the metal routing.

[0034] In some embodiments, the 3D memory device 200 includes, in a plan view, yet another backside interconnect structure - a plurality of SSG lines 228. Each SSG line 228 may extend in the x direction (e.g., word line direction) across two core array regions 206A and 206B and the staircase region 204. In some embodiments, the SSG lines 228 are evenly distributed parallel to each other in the y direction (e.g., bit line direction) in the plan view. The SSG lines 228, the tooth power lines 222, and the tooth source lines 212 may be parallel. As shown in FIG. 2A, each SSG line 228 may be sandwiched between two tooth power lines 222 in the y direction. It is understood that the arrangement configurations of the SSG lines 228, the tooth power lines 222, and the tooth source lines 212 may be different in other examples. For example, the SSG lines 228, the tooth power lines 222, and the tooth source lines 212 may be alternately arranged with each other in the y direction.

[0035] In some embodiments, contact 230 is distributed in the plan view to be below the SSG lines 228 of the core array regions 206A and 206B and in contact with the SSG lines 228, but not so in the staircase region 204 and the peripheral region 208. For example, as shown in FIG. 2A, at least one contact 230 in the core array region 206A and at least one contact 230 in the core array region 206B are below each SSG line 228 and in contact with each SSG line 228. The SSG in the memory stack of the 3D memory device 200 may be cut in the staircase region 204 and become two unconnected parts in the core array regions 206A and 206B respectively. Each contact 230 may be electrically connected to a part of the SSG of the 3D memory device 200 in the respective core array region 206A or 206B. Thus, by extending upward over the staircase region 204 between the two core array regions 206A and 206B in the x direction and electrically connecting the contacts 230 in each core array region 206A or 206B, the SSG lines 228 can electrically connect the two unconnected parts of the SSG in the core array regions 206A and 206B. That is, the two unconnected parts of the SSG in the core array regions 206A and 206B can be "bridged" across the staircase region 204 by a metal routing including the SSG lines 228 and the contacts 230 on the back side of the 3D memory device 200. The layout of the contacts 230 and the SSG lines 228, for example, a plurality of parallel SSG lines 228 and a plurality of distributed contacts 230, can reduce the overall resistance of the metal routing.

[0036] The backside interconnect structure is not limited to the example of FIG. 2A and may include any other suitable layout according to the design of the 3D memory device, such as electrical performance specifications (e.g., voltage and resistance). As shown in FIG. 2A, it is also understood that additional backside interconnect structures may be disposed on the same surface as the source line mesh 210, the power line mesh 220, and the SSG line 228. For example, bonding pads (not shown) for wire bonding may also be disposed on the backside of the 3D memory device 200, such as in the peripheral region 208. One or more of the backside interconnect structures shown in FIG. 2A may not be disposed on the backside of the 3D memory device in other examples and may be replaced, for example, by a corresponding frontside interconnect structure disposed on the frontside of the 3D memory device.

[0037] FIG. 2B illustrates a plan view of a cross section of another exemplary 3D memory device 201 with a backside interconnect structure according to some embodiments of the present disclosure. The 3D memory device 201 may be substantially the same as the 3D memory device 200 of FIG. 2A, except that the 3D memory device 201 does not include the SSG line 228 and the contact 230 of FIG. 2A. FIG. 2C illustrates a plan view of a cross section of yet another exemplary 3D memory device 203 with a backside interconnect structure according to some embodiments of the present disclosure. The 3D memory device 203 may be substantially the same as the 3D memory device 200 of FIG. 2A, except that the 3D memory device 203 does not include the SSG line 228, the power line mesh 220, and the contacts 230 and 226 of FIG. 2A. Further, by removing the power line mesh 220, the source line mesh 210 in the 3D memory device 203 can have two parallel shaft source lines 214 in the core array regions 206A and 206B, respectively.

[0038] Figure 3 illustrates a side cross-sectional view of an exemplary 3D memory device 300 with a backside interconnect structure, according to some embodiments of the present disclosure. The 3D memory device 300 may be an example of the 3D memory devices 200, 201, and 203 of FIGS. 2A-2C. FIGS. 2A-2C may be illustrated as a plan view of the AA plane of the 3D memory device 300 of FIG. 3, i.e., a plan view of a cross-section within the backside of the 3D memory device 300. In some embodiments, the 3D memory device 300 is a bonded chip comprising a first semiconductor structure 302 and a second semiconductor structure 304 stacked on the first semiconductor structure 302. The first semiconductor structure 302 and the second semiconductor structure 304 are connected at a bonding interface 306 therebetween, according to some embodiments. As shown in FIG. 3, the first semiconductor structure 302 may include a substrate 301 that can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0039] The first semiconductor structure 302 of the 3D memory device 300 can include peripheral circuits 308 on a substrate 301. Note that an x-axis, a y-axis, and a z-axis are included in FIG. 3 to illustrate the spatial relationships of the components within the 3D memory device 300. The substrate 301 includes two lateral surfaces that extend laterally in the x-y plane, namely, a surface on the front side of the wafer and a back surface on the back side opposite the front side of the wafer. The x-direction and the y-direction are two orthogonal directions within the wafer plane, that is, the x-direction is the word line direction and the y-direction is the bit line direction. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether one component (e.g., a layer or a device) is "above", "higher than", or "lower than" another component (e.g., a layer or a device) of a semiconductor device (e.g., the 3D memory device 300) is determined with respect to the substrate (e.g., the substrate 301) of the semiconductor device in the z-direction (a vertical direction perpendicular to the x-y plane) when the substrate is positioned at the bottommost plane of the semiconductor device in the z-direction. The same concept for describing spatial relationships is applied throughout this disclosure.

[0040] In some embodiments, the peripheral circuit 308 is configured to control and sense the 3D memory device 300. The peripheral circuit 308 can be any suitable digital, analog, and / or mixed-signal control and sensing circuit used to facilitate the operation of the 3D memory device 300, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 308 can be well regarded as including transistors formed "on" the substrate 301, with all or part of the transistors formed within the substrate 301 (e.g., below the top surface of the substrate 301) and / or directly on top of the substrate 301. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) can also be formed within the substrate 301. The transistors are fast according to some embodiments using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.). In some examples, it is understood that the peripheral circuit 308 can further include any other circuit compatible with an advanced logic process, including logic circuits such as processors and programmable logic devices (PLDs), or memory circuits such as static random access memory (SRAM). In some embodiments, the peripheral circuit 308 comprises one or more power lines for supplying power (e.g., voltage) to the peripheral circuit 308.

[0041] In some embodiments, the first semiconductor structure 302 of the 3D memory device 300 further includes an interconnect layer (not shown) above the peripheral circuit 308 for communicating electrical signals with the peripheral circuit 308. The interconnect layer can include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and VIA contacts. As used herein, the term "interconnect" can, in a broad sense, include any suitable type of interconnect, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which the interconnect lines and VIA contacts can be formed. That is, the interconnect layer can include interconnect lines and VIA contacts within the plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0042] As shown in FIG. 3, the first semiconductor structure 302 of the 3D memory device 300 can further include a bonding layer 310 at the bonding interface 306 and above the interconnect layer and the peripheral circuit 308. The bonding layer 310 can include a plurality of bonding contacts 311 and a dielectric that electrically insulates the bonding contacts 311. The bonding contacts 311 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining region of the bonding layer 310 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 311 and the surrounding dielectric within the bonding layer 310 can be used for hybrid bonding.

[0043] Similarly, as shown in FIG. 3, the second semiconductor structure 304 of the 3D memory device 300 can also include a bonding layer 312 at the bonding interface 306 and also above the bonding layer 310 of the first semiconductor structure 302. The bonding layer 312 can include a plurality of bonding contacts 313 and a dielectric that electrically insulates the bonding contacts 313. The bonding contacts 313 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 312 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 313 and the surrounding dielectric within the bonding layer 312 can be used for hybrid bonding. The bonding contacts 313 are in contact with the bonding contacts 311 at the bonding interface 306 in some embodiments.

[0044] As will be described in detail below, the second semiconductor structure 304 can be bonded on top of the first semiconductor structure 302 facing each other at the bonding interface 306. In some embodiments, the bonding interface 306 is disposed between the bonding layers 310 and 312 as a result of a hybrid bonding (also referred to as a "metal / dielectric hybrid bonding"), which is a direct bonding technique (i.e., forming a bond between surfaces without using an intermediate layer such as solder or an adhesive) and can simultaneously obtain metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 306 is the location where the bonding layers 312 and 310 contact and bond. In practice, the bonding interface 306 can be a layer having a specific thickness including the top surface of the bonding layer 310 of the first semiconductor structure 302 and the bottom surface of the bonding layer 312 of the second semiconductor structure 304.

[0045] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 further includes an interconnect layer (not shown) above the bonding layer 312 for transferring electrical signals. The interconnect layer can include a plurality of interconnects such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0046] In some embodiments, the 3D memory device 300 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 3, the second semiconductor structure 304 of the 3D memory device 300 can include an array of channel structures 324 that function as an array of NAND memory strings. As shown in FIG. 3, each channel structure 324 can vertically penetrate a plurality of pairs each including a conductor layer 316 and a dielectric layer 318. The alternately arranged conductor layers 316 and dielectric layers 318 are part of the memory stack 314. The number of pairs of conductor layers 316 and dielectric layers 318 in the memory stack 314 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 300. In some examples, it is understood that the memory stack 314 can have a multi-deck architecture (not shown) including a plurality of memory decks stacked on top of each other. The number of pairs of conductor layers 316 and dielectric layers 318 in each memory deck may be the same or different.

[0047] The memory stack 314 can include a plurality of conductor layers 316 and dielectric layers 318 arranged alternately. The conductor layers 316 and dielectric layers 318 within the memory stack 314 may be alternately arranged in the vertical direction. In other words, except for those at the top or bottom of the memory stack 314, each conductor layer 316 can be adjacent to two dielectric layers 318 on both sides, and each dielectric layer 318 can be adjacent to two conductor layers 316 on both sides. The conductor layer 316 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductor layer 316 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductor layer 316 extends horizontally as a word line and can end in one or more staircase structures of the memory stack 314. In some embodiments, the topmost conductor layer 316 functions as an SSG for controlling the source of the NAND memory string. The dielectric layer 318 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0048] As shown in FIG. 3, the second semiconductor structure 304 of the 3D memory device 300 can also include a first semiconductor layer 320 above the memory stack 314 and a second semiconductor layer 322 above the first semiconductor layer 320 and in contact with the first semiconductor layer 320. The dopant type in each of the semiconductor layers 320 and 322 can be different in different embodiments. The semiconductor layers 320 and 322 can be regarded as a single semiconductor layer when the semiconductor layers 320 and 322 have the same type of dopant. It is understood that the number of semiconductor layers may be different in other examples and is not limited to the example shown in FIG. 3.

[0049] In some embodiments, each channel structure 324 includes a channel hole filled with a semiconductor layer (e.g., as semiconductor channel 328) and a composite dielectric layer (e.g., as memory film 326). In some embodiments, semiconductor channel 328 includes silicon such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, memory film 326 is a composite layer including a tunnel layer, a storage layer (also referred to as a “charge trap layer”), and a blocking layer. The remaining space of channel structure 324 may be partially or fully filled with a capping layer including a dielectric material such as silicon oxide and / or voids. Channel structure 324 can have a cylindrical shape (e.g., a column shape). The capping layer of memory film 326, semiconductor channel 328, tunnel layer, storage layer, and blocking layer are radially arranged and configured in this order from the center towards the outer surface of the column in some embodiments. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, memory film 326 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0050] In some embodiments, channel structure 324 further includes a channel plug 329 at the bottom (e.g., the lower end) of channel structure 324. As used herein, the “upper end” of a component (e.g., channel structure 324) is the end farther in the z-direction from substrate 301, and the “lower end” of a component (e.g., channel structure 324) is the end closer to substrate 301 in the z-direction when substrate 301 is positioned within the bottom plane of 3D memory device 300. Channel plug 329 can include a semiconductor material (e.g., polysilicon). In some embodiments, channel plug 329 functions as the drain of a NAND memory string.

[0051] As shown in FIG. 3, each channel structure 324 can penetrate through conductor layers 316 and dielectric layers 318 that are alternately arranged in the vertical direction with the memory stack 314 and the first semiconductor layer 320. In some embodiments, the first semiconductor layer 320 surrounds a part of the channel structure 324 and is in contact with a semiconductor channel 328 containing polysilicon. That is, the memory film 326 is interrupted by a part of the channel structure 324 that abuts against the first semiconductor layer 320 according to some embodiments, and exposes the semiconductor channel 328 that should be in contact with the surrounding first semiconductor layer 320. In some embodiments, each channel structure 324 can penetrate further vertically into the second semiconductor layer 322. It is understood that the structure at the top of the channel structure 324 and its relative positions with respect to the semiconductor layers 320 and 322 are not limited to the example of FIG. 3 and may be different in other examples.

[0052] As shown in FIG. 3, the second semiconductor structure 304 of the 3D memory device 300 can further include an insulating structure 330 that penetrates vertically through the alternately arranged conductor layers 316 and dielectric layers 318 of each memory stack 314. Each insulating structure 330 extends laterally and can also separate the channel structure 324 into a plurality of blocks. That is, the memory stack 314 is divided into a plurality of memory blocks by the insulating structure 330, and thereby, the array of channel structures 324 can be separated into each memory block. Different from the slit structure of the existing 3D NAND memory device described above including the front-side ACS contact, the insulating structure 330 does not contain a contact therein (that is, does not function as a source contact), and thus, according to some embodiments, does not introduce parasitic capacitance and leakage current caused by the conductor layer 316 (including the word line). In some embodiments, each insulating structure 330 includes an opening (for example, a slit) filled with one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 330 can be filled with silicon oxide.

[0053] Instead of having a front - side source contact, the 3D memory device 300 can include a back - side source contact 332 that is above the memory stack 314 and in contact with a second semiconductor layer 322. The back - side source contact 332 can be an example of the back - side source contact 216 of FIGS. 2A - 2C. The source contact 332 and the memory stack 314 (and the insulating structure 330 therethrough) can be disposed on the opposite side of the semiconductor layer 322 (thinned substrate), and thus can be regarded as a “back - side” source contact. In some embodiments, the source contact 332 further penetrates into the second semiconductor layer 322 and is electrically connected to the semiconductor channel 328 of the channel structure 324 through the semiconductor layers 320 and 322. It is understood that the depth to which the source contact 332 penetrates into the second semiconductor layer 322 can be different in different examples. In some embodiments where the second semiconductor layer 322 is an N - well, the source contact 332 is also referred to as a back - side “N - well pickup”. The source contact 332 can include any suitable type of contact. In some embodiments, the source contact 332 includes a VIA contact (as the back - side source contact 216 of FIGS. 2A - 2C). In some embodiments, the source contact 332 includes a laterally extending wall - shaped contact. The source contact 332 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., titanium nitride (TiN)).

[0054] As shown in FIG. 3, the 3D memory device 300 can further include a BEOL backside interconnect layer 333 that is on and in contact with a source contact 332 for pad out, e.g., for transferring electrical signals between the 3D memory device 300 and an external circuit. The backside interconnect layer 333 can also include examples of backside interconnect structures described above in FIGS. 2A-2C. In some embodiments, the backside interconnect layer 333 includes one or more ILD layers 334 on a second semiconductor layer 322 and a redistribution layer 336 on the ILD layer 334. The upper end portion of the source contact 332 is, in some embodiments, coplanar with the top surface of the ILD layer 334 and the bottom surface of the redistribution layer 336, and the source contact 332 penetrates vertically through the ILD layer 334 into the second semiconductor layer 322. The ILD layer 334 in the backside interconnect layer 333 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

[0055] The rewiring layer 336 within the backside interconnect layer 333 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the rewiring layer 336 includes Al. Although not shown in FIG. 3, it is understood that the rewiring layer 336 can be patterned to form various types of backside interconnect structures described herein, such as the source line mesh 210, power line mesh 220, and SSG lines 228 of FIG. 2A. In one example, the source contact 332 can be below the source line mesh 210 in the rewiring layer 336 and in contact with the source line mesh 210. In some embodiments, the backside interconnect layer 333 further includes a passivation layer 338 as the outermost layer for passivation and protection of the 3D memory device 300. A portion of the rewiring layer 336 can be exposed from the passivation layer 338 as a bonding pad 340. That is, the backside interconnect layer 333 of the 3D memory device 300 can also include a bonding pad 340 for wire bonding and / or bonding with an interposer. Although not shown in FIGS. 2A-2C, the bonding pad 340 can also be part of the backside interconnect structure in some examples.

[0056] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 further includes contacts 342 and 344 that pass through the second semiconductor layer 322. Since the second semiconductor layer 322 may be a thinned substrate, in some embodiments, the contacts 342 and 344 are TSCs. Contact 342 may be an example of contact 218 or 226 of FIGS. 2A and 2B. In some embodiments, contact 342 penetrates through the second semiconductor layer 322 and the ILD layer 334 to contact a redistribution layer 336 (e.g., including source line mesh 210 and power line mesh 220). For example, the source of a NAND memory string can be electrically connected to contact 342 (e.g., as contact 218 of FIGS. 2A-2C) through semiconductor layers 320 and 322, source contact 332, and redistribution layer 336 (e.g., having source line mesh 210 of FIGS. 2A-2C). That is, contact 342 (either contact 218 or 226) is below and can contact the source line mesh 210 or the power line mesh 220, respectively, in the redistribution layer 336. Although not shown in FIG. , as an example of contact 230 of FIG. 2A, the 3D memory device 300 may further include a contact (e.g., an example of contact 230 of FIG. 2A) that further penetrates into the memory stack 314 to contact one of the conductor layers 316 (i.e., SSG) of the memory stack 314. The contact (e.g., as contact 230 of FIG. 2A) is below the SSG line 228 in the redistribution layer 336 and can contact the SSG line 228.

[0057] In some embodiments, contact 344 contacts bonding pad 340 through second semiconductor layer 322 and ILD layer 334. Each of contacts 342 and 344 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN). In some embodiments, at least contact 344 further includes a spacer (e.g., a dielectric layer) for electrically insulating contact 344 from second semiconductor layer 322.

[0058] In some embodiments, the 3D memory device 300 further includes peripheral contacts 346 and 348 that each extend perpendicular to the second semiconductor layer 322 outside of each memory stack 314. Each peripheral contact 346 or 348 can have a depth deeper than the depth of the memory stack 314 such that it extends vertically from the bonding layer 312 in the peripheral region corresponding to, for example, the peripheral regions 208 and the stepped regions 204 of FIGS. 2A-2C, or the peripheral regions of the core array regions 206A and 206B where the contacts 218 are disposed, to the second semiconductor layer 322. In some embodiments, the peripheral contact 346 is below and in contact with the contact 342 such that the source line mesh 210 or the power line mesh 220 is electrically connected to the peripheral circuit 308 within the first semiconductor structure 302. In one example, the source of the NAND memory string can be electrically connected through the redistribution layer 336 (including, for example, the source line mesh 210), the contact 342 (such as the contact 218), and the peripheral contact 346 to a part of the peripheral circuit 308 for controlling / sensing the source of the NAND memory string. In another example, the power supply can be electrically connected through the redistribution layer 336 (including, for example, the power line mesh 220), the contact 342 (such as the contact 226), and the peripheral contact 346 to the power line of the peripheral circuit 308 for supplying power to the 3D memory device 300. In some embodiments, the peripheral contact 348 is below and in contact with the contact 344 such that the peripheral circuit 308 within the first semiconductor structure 302 is electrically connected to the bonding pad 340 for pad out through at least the contact 344 and the peripheral contact 348. The peripheral contacts 346 and 348 can each include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0059] As shown in FIG. 3, 3D memory device 300 also includes various local contacts (also referred to as "C1") as part of the interconnect structure and is in direct contact with the structures within memory stack 314. In some embodiments, the local contacts include channel local contacts 350 that are each below and in contact with the lower end of each respective channel structure 324. Each channel local contact 350 can be electrically connected to a bit line contact (not shown) for bit line fanout. In some embodiments, the local contacts further include word line local contacts 352 that are each below and in contact with each respective conductor layer 316 (including word lines) in the staircase structure of memory stack 314 for word line fanout. Local contacts such as channel local contacts 350 and word line local contacts 352 can be electrically connected to the peripheral circuit 308 of the first semiconductor structure 302 through at least bonding layers 312 and 310. Local contacts such as channel local contacts 350 and word line local contacts 352 can each include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0060] FIG. 4 is a plan view illustrating a cross-section of yet another exemplary 3D memory device 400 having a backside interconnect structure according to some embodiments of the present disclosure. 3D memory device 400 may be an example of 3D memory device 100 after flip-chip bonding, and FIG. 4 shows an example of the backside of 3D memory device 100 after flip-chip bonding. As shown in FIG. 4, the memory stack of 3D memory device 400 includes, according to some embodiments, two core array regions 406A and 406B having a channel structure 408 therein, and a staircase region 404 between core array regions 406A and 406B in the x-direction (e.g., word line direction) in the plan view. In the y-direction (e.g., bit line direction), FIG. 4 shows the backside interconnect structure in one block 402 of 3D memory device 400, which may be repeated any suitable number of times in a plurality of blocks.

[0061] In some embodiments, 3D memory device 400 includes a source line mesh 410 in the plan view. In some embodiments, source line mesh 410 is within core array regions 406A and 406B and staircase region 404. As shown in FIG. 4, source line mesh 410 includes, according to some embodiments, a plurality of parallel source lines 412 that extend horizontally in the x-direction (e.g., word line direction) across staircase region 404 and core array regions 406A and 406B, respectively, similar to the tooth source lines 212 of source line mesh 210 of FIGS. 2A-2C. Different from source line mesh 210 having a single shaft source line 214 of FIGS. 2A and 2B, source line mesh 410 may also include a plurality of parallel source lines 414 that extend horizontally in the y-direction (e.g., bit line direction) in the plan view. Parallel source lines 414 may be disposed within core array regions 406A and 406B and staircase region 404 as shown in FIG. 4. It is understood that in some examples, source lines 414 may not be disposed within staircase region 404 and may be disposed only within core array regions 406A and 406B.

[0062] The 3D memory device 400 can include backside source contacts 416 (e.g., in the form of VIA contacts) within the core array regions 406A and 406B, but not within the staircase region 404. For example, the backside source contacts 416 can be evenly distributed across the core array region 406A or 406B. As shown in FIG. 4, in some embodiments, each channel structure 408 is below each respective one of the backside source contacts 416 and is laterally aligned therewith. That is, each channel structure 408 is overlapped with each respective backside source contact 416 directly above the channel structure 408, thereby reducing the resistance between the source of the NAND memory string and the backside source contact 416. In some embodiments, since the channel structures 408 are arranged and configured in an array having rows and columns, the backside source contacts are also arranged and configured in an array having rows and columns. Each source line 414 or 412 can contact each of the backside source contacts 416 in a row or column of the array in a plan view. In some embodiments, each source line 414 extending in the y direction can contact each of the backside source contacts 416 in a column. In some examples, each source line 412 extending in the x direction may contact each of the backside source contacts 416 in a row. In some embodiments, each source line 414 or 412 contacts each of the backside source contacts 416 in two adjacent rows or columns of the array in a plan view. For example, as shown in FIG. 4, each source line 414 extending in the y direction may contact each of the backside source contacts 416 in two adjacent columns. Although not shown, similarly, in other examples, each source line 412 extending in the x direction may contact each of the backside source contacts 416 in two adjacent rows.

[0063] The 3D memory device 400 can further include contacts 418, such as TSCs. In some embodiments, the contacts 418 are distributed to contact the source line mesh 410 below the source line mesh 410 in the staircase region 404 and in parts of the core array regions 406A and 406B. Since the contacts 418 can be TSCs that penetrate the silicon substrate, the contacts 418 are distributed to contact the peripheral part (including the part of the staircase region 404) below the peripheral part of the source line mesh 410 so as to avoid overlapping with the channel structure 408 in the central part of the source line mesh 410 within the core array regions 406A and 406B according to some embodiments. For example, as shown in FIG. 4, the contacts 418 can be distributed to contact the outermost source lines 412 and 414 within the core array regions 406A and 406B below the source lines 412 and 414. The contacts 418 can also be distributed to contact the source line 414 below the source line 414 within the staircase region 404.

[0064] As described in detail below, each backside source contact 416 may be electrically connected to the source of a respective NAND memory string, and the source line mesh 410 electrically connects each backside source contact 416 and is then electrically connected to the source of the NAND memory string. Similarly, each contact 418 may be electrically connected to the peripheral circuit of the 3D memory device 400, and the source line mesh 410 electrically connects each contact 418 and is then electrically connected to the peripheral circuit of the 3D memory device 400. As a result, the peripheral circuit is electrically connected to the source of the NAND memory string and can control and / or sense the source through a metal routing including the backside contacts 418, the source line mesh 410, and the backside source contacts 416 on the backside of the 3D memory device 400. Compared with the examples of FIGS. 2A-2C, the layout of the contacts 418, the source line mesh 410, and the backside source contacts 416, for example, the array of backside source contacts 416 corresponding to the array of channel structures 408, and the source lines 414 that contact the backside source contacts 416 within two adjacent columns in each of the core array regions 406A and 406B, can further reduce the overall resistance of the metal routing.

[0065] FIG. 5 illustrates a side cross-sectional view of another exemplary 3D memory device 500 having a backside interconnect structure, according to some embodiments of the present disclosure. The 3D memory device 500 may be an example of the 3D memory device 400 of FIG. 4. The 3D memory 500 is similar to the 3D memory device 300 of FIG. 3, except for the arrangement configuration of the source contacts 502. As shown in FIG. 5, each channel structure 324 is below and laterally (e.g., in both the x and y directions) aligned with a respective source contact 502 (e.g., an example of the backside source contact 416 of FIG. 4) that contacts the semiconductor layer 322. It is understood that details of other same structures in both the 3D memory devices 500 and 300 are not repeated for ease of explanation.

[0066] Figures 6A - 6D illustrate a processing process for forming an exemplary 3D memory device with a backside interconnect structure according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of a method 700 for forming an exemplary 3D memory device with a backside interconnect structure according to some embodiments of the present disclosure. The examples of 3D memory devices shown in FIGS. 6A - 6D and FIG. 7 include the 3D memory devices 200, 201, 203, and 400 shown in FIGS. 2A - 2C and FIG. 4. FIGS. 6A - 6D and FIG. 7 are described together. It is understood that the operations shown in method 700 are not exhaustive, and other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of these operations may be performed simultaneously or in an order different from that shown in FIG. 7.

[0067] Referring to FIG. 7, method 700 begins with operation 702 where a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 6A, a peripheral circuit 604 having a plurality of transistors is formed on a first silicon substrate 602 using a plurality of processes including, but not limited to, photolithography, etching, thin - film deposition, thermal growth, implantation, chemical - mechanical polishing (CMP), and any other suitable processes.

[0068] Method 700 proceeds to operation 704 as illustrated in FIG. 7, where a plurality of channel structures each penetrating a memory stack in a vertical direction are formed on the front side of a second substrate. In some embodiments, the memory stack includes two core - array regions having channel structures and a staircase region between the two core - array regions in a first lateral direction in a plan view. As illustrated in FIG. 6A, an array of channel structures 608 each penetrating a memory stack in a vertical direction is formed on the front side of a second silicon substrate 606.

[0069] As illustrated in FIG. 7, method 700 proceeds to operation 706 where the first substrate and the second substrate are bonded face-to-face, whereby the channel structure is above the peripheral circuit. The bonding may include a hybrid bonding. As illustrated in FIGS. 6A and 6B, the second silicon substrate 606 and the components formed thereon (e.g., channel structure 608) are inverted and bonded face-up, i.e., face-to-face, with the first silicon substrate 602 and the components formed thereon (e.g., peripheral circuit 604), thereby forming a bonding interface 609 between silicon substrates 602 and 606 in some embodiments.

[0070] As illustrated in FIG. 7, method 700 proceeds to operation 708 where the second substrate is thinned. The thinning is performed from the backside of the second substrate. As illustrated in FIG. 6B, the second silicon substrate 606 (shown in FIG. 6A) is thinned from the backside to become a semiconductor layer 610 (i.e., the thinned second silicon substrate 606) by using CMP, grinding, dry etching, and / or wet etching.

[0071] As illustrated in FIG. 7, method 700 proceeds to operation 710 where a plurality of contacts are formed through a second substrate that has been thinned, and a plurality of source contacts are formed to contact the thinned second substrate. The contacts and source contacts are formed from the back side of the thinned second substrate. In some embodiments, each of the channel structures is below and laterally aligned with each respective source contact of the source contacts. In some embodiments, the source contacts are arranged and configured in an array having rows and columns. As illustrated in FIG. 6C, back side source contact 612 is formed from the back side of semiconductor layer 610 and contacts semiconductor layer 610. In some embodiments, each channel structure 608 is below and laterally aligned with each respective back side source contact 612. A plurality of TSCs 614, 616, and 618 may be formed from the back side of semiconductor layer 610 through semiconductor layer 610. In some embodiments, TSC 616 further penetrates into the memory stack and contacts the SSG within the memory stack.

[0072] As illustrated in FIG. 7, method 700 proceeds to operation 712 where a source line mesh is formed on the backside of the thinned second substrate such that the source line mesh is above and in contact with a plurality of source contacts and a first set of the plurality of contacts. In some embodiments, the source line mesh includes a plurality of parallel source lines each extending laterally within a plan view. In some embodiments, the source line mesh is above and in contact with each of the source contacts. In some embodiments, each of the source lines is in contact with each of the source contacts within a row or column of the array in the plan view. In some embodiments, each of the source lines is in contact with each of the source contacts within two adjacent rows or columns of the array in the plan view. As illustrated in FIG. 6D, source line mesh 620 is formed on the backside of semiconductor layer 610 such that source line mesh 620 is above and in contact with backside source contacts 612 and further TSC 614. The layout of source line mesh 620, backside source contacts 612, and TSC 614 can vary in different examples, such as in the examples shown in FIGS. 2A-2C and FIG. 4.

[0073] As illustrated in FIG. 7, method 700 proceeds to operation 714 where a plurality of SSG lines are formed on the backside of the thinned second substrate such that the SSG lines are above and in contact with a second set of the plurality of source contacts. In some embodiments, each of the SSG lines extends in a first lateral direction across two core array regions and a staircase region, and the second set of contacts is distributed within the core array region in the plan view. In some embodiments, the SSG lines are evenly distributed parallel to a second lateral direction perpendicular to the first lateral direction in the plan view. As illustrated in FIG. 6D, SSG line 624 is formed on the backside of semiconductor layer 610 such that SSG line 624 is above and in contact with TSC 616. The layout of SSG line 624 and TSC 616 can vary in different examples, such as in the example shown in FIG. 2A.

[0074] As illustrated in FIG. 7, method 700 proceeds to operation 716 where a power line mesh is formed on the backside of the thinned second substrate such that the power line mesh is above and in contact with a third set of a plurality of source contacts. In some embodiments, the third set of contacts is distributed in the plan view within at least one of a staircase region or a peripheral region outside the memory array. As illustrated in FIG. 6D, a power line mesh 622 is formed on the backside of semiconductor layer 610 such that the power line mesh 622 is above and in contact with TSC 618. The layout of power line mesh 622 and TSC 618 may vary in different examples, such as in the examples shown in FIGS. 2A and 2B. Although operations 712, 714, and 716 have been described above as three sequential operations, it is understood that operations 712, 714, and 716 may be performed in the same processing process. For example, one or more of source line mesh 620, power line mesh 622, and SSG line 624 may be patterned and formed in the same processing process.

[0075] According to one aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers above the substrate, a plurality of channel structures each penetrating the memory stack in a vertical direction, a semiconductor layer above the plurality of channel structures and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts passing through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts is distributed below and in contact with the source line mesh.

[0076] In some embodiments, the memory stack includes two core array regions having a channel structure and a staircase region between the two core array regions in a first lateral direction in a plan view.

[0077] In some embodiments, the backside interconnect layer further includes a plurality of SSG lines in a plan view, and a second set of contacts is distributed below the SSG lines and in contact with the SSG lines.

[0078] In some embodiments, each of the SSG lines extends in a first lateral direction across the two core array regions and the staircase region, and the second set of contacts is distributed within the core array regions in a plan view.

[0079] In some embodiments, each of the second set of contacts further penetrates into the memory stack and contacts one of the conductor layers of the memory stack.

[0080] In some embodiments, the SSG lines are evenly distributed parallel to a second lateral direction perpendicular to the first lateral direction in a plan view.

[0081] In some embodiments, the backside interconnect layer further includes a power line mesh in a plan view, and a third set of contacts is distributed below the power line mesh and in contact with the power line mesh.

[0082] In some embodiments, the third set of contacts is distributed within at least one of the staircase region or a peripheral region outside the memory array in a plan view.

[0083] In some embodiments, the power line mesh has a comb-like shape.

[0084] In some embodiments, the backside interconnect layer further includes bonding pads electrically connected to the power line mesh through the third set of contacts.

[0085] In some embodiments, the source line mesh has a comb-like shape.

[0086] According to another aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers located above the substrate, a plurality of channel structures each penetrating the memory stack in a vertical direction, a semiconductor layer located above the plurality of channel structures and in contact with the plurality of channel structures, a plurality of source contacts in contact with the semiconductor layer, and a backside interconnect layer located above the semiconductor layer and including a source line mesh in a plan view. Each of the channel structures is located below a respective one of the source contacts and is laterally aligned with the respective source contact. The source line mesh is located above each of the source contacts and is in contact with each of the source contacts.

[0087] In some embodiments, the 3D memory device further includes a plurality of contacts that pass through the semiconductor layer, are distributed below the source line mesh, and are in contact with the source line mesh.

[0088] In some embodiments, the memory stack includes one or more core array regions having channel structures, and the contacts are distributed outside the core array regions in a plan view.

[0089] In some embodiments, the source line mesh includes a plurality of parallel source lines each extending laterally in a plan view.

[0090] In some embodiments, the source contacts are arranged in an array, and each of the source lines is in contact with each of the source contacts within a row or column of the array in a plan view.

[0091] In some embodiments, each of the source lines is in contact with each of the source contacts within two adjacent rows or columns of the array in a plan view.

[0092] In yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. Peripheral circuitry is formed on a first substrate. A plurality of channel structures are formed that vertically penetrate a memory stack, each of which is on a front side of a second substrate. The first substrate and the second substrate are bonded face-to-face, whereby the channel structures are above the peripheral circuitry. The second substrate is thinned. A plurality of contacts are formed through the thinned second substrate and a plurality of source contacts are formed that contact the thinned second substrate. A source line mesh is formed on a back side of the thinned second substrate, whereby the source line mesh is above and in contact with the plurality of source contacts and a first set of the plurality of contacts.

[0093] In some embodiments, the memory stack includes two core array regions having channel structures and a staircase region between the two core array regions in a first lateral direction in a plan view.

[0094] In some embodiments, a plurality of SSG lines are formed on a back side of the thinned second substrate, whereby the SSG lines are above and in contact with a second set of the plurality of contacts.

[0095] In some embodiments, each of the SSG lines extends in a first lateral direction across the two core array regions and the staircase region, and the second set of contacts is distributed within the core array regions in a plan view.

[0096] In some embodiments, the SSG lines are evenly distributed parallel to a second lateral direction perpendicular to the first lateral direction in a plan view.

[0097] In some embodiments, a power line mesh is formed on a back side of the thinned second substrate, whereby the power line mesh is above and in contact with a third set of the plurality of contacts.

[0098] In some embodiments, the source line mesh includes a plurality of parallel source lines, each extending laterally within a plan view.

[0099] In some embodiments, each of the channel structures is below each of the source contacts, aligned laterally with each of the source contacts, and the source line mesh is above each of the source contacts and in contact with each of the source contacts.

[0100] In some embodiments, the source contacts are arranged in an array, and each of the source lines is in contact with each of the source contacts within a row or column of the array in the plan view.

[0101] In some embodiments, each of the source lines is in contact with each of the source contacts within two adjacent rows or columns of the array in the plan view.

[0102] The foregoing description of specific embodiments will clarify the general nature of the present disclosure so that within the knowledge of the art, without departing from the general concept of the present disclosure and without undue experimentation, such specific embodiments can be readily modified and / or adapted to various applications. Accordingly, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It will be understood that the language or terminology herein is for the purpose of description and thus the language or terminology herein should be interpreted by those skilled in the art in light of the teachings and guidance.

[0103] Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation form of a specified function and the relationship thereof. The boundaries of these functional building blocks are arbitrarily defined herein for the convenience of description. Alternative boundaries can be defined as long as the specified function and its relationship are properly executed.

[0104] The summary of the invention and the terms of the abstract may define one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor, and thus are not intended to limit the present disclosure and the appended claims in any form.

[0105] The scope and extent of the present disclosure should not be limited by the above exemplary embodiments, but should be defined only by the claims and their equivalents.

Description of Reference Numerals

[0106] 100 3D memory device 102 Block 104 Staircase region 106A, 106B Core array region 108 Insulating structure 110 Channel structure 200 3D memory device 201 3D memory device 202 Block 203 3D memory device 204 Staircase region 206A, 206B Core array region 208 Peripheral region 210 Source line mesh 212 Parallel tooth source line 214 Shaft source line 216 Backside source contact 218, 226, 230 Contact 220 Power line mesh 222 Tooth power line 224 Shaft power line 228 SSG line 230 Contact 300 3D memory device 301 Substrate 302 First semiconductor structure 304 Second semiconductor structure 306 Bonding interface 308 Peripheral circuit 310 Bonding layer 311 Bonding Contact 312 Bonding layer 313 Bonded Contact 314 Memory Stack 316 Top conductive layer 318 Dielectric Layer 320, 322 Semiconductor layer 324 Channel Structure 326 Memory Film 328 Semiconductor Channels 329 Channel Plug 330 Insulation Structure 332 source contact, backside source contact 333 Backside Interconnect Layer 334 ILD layer 336 Redistribution layer 338 Passivation Layer 340 Bonding Pad 342, 344 Contact 346, 348 Peripheral Contact 350 Channel Local Contacts 352 Word Line Local Contact 400 3D memory devices 402 Block 404 Stairs area 406A, 406B Core array area 408 Channel Structure 410 Source Line Mesh 412 parallel source lines 414 Parallel Source Lines 416 Backside Source Contact 418 Contacts 500 3D memory devices 502 Source Contact 602 First silicon substrate 604 Peripheral Circuit 606 Second silicon substrate 608 Channel Structure 609 Joint interface 610 Semiconductor layer 612 Backside source contact 614, 616, 618 TSC 620 Source line mesh 622 Power line mesh 624 SSG line 700 Method

Claims

1. A three-dimensional (3D) memory device comprising: a memory stack including alternating conductor layers and dielectric layers below a first side of a second semiconductor layer; a channel structure extending vertically through the memory stack and into the second semiconductor layer; a source contact in contact with a second side of the second semiconductor layer opposite the first side; a backside interconnect layer above the second side of the second semiconductor layer and including an interlayer dielectric (ILD) layer and a source line mesh on the ILD layer, wherein the source contact is distributed below the source line mesh and the source contact extends through the ILD layer and into the second semiconductor layer.

2. The 3D memory device of claim 1, wherein the memory stack comprises a core array region and at least a portion of the source contact is within the core array region.

3. The 3D memory device of claim 1, further comprising a first semiconductor layer between the memory stack and the second semiconductor layer, each of the channel structures comprising a semiconductor channel and a memory film surrounding a portion of the semiconductor channel, the first semiconductor layer surrounding a portion of the channel structure and in contact with the semiconductor channel.

4. The 3D memory device of claim 3, wherein the memory film comprises a first portion and a second portion distributed on opposite sides of the first semiconductor layer, the first portion of the memory film being within the second semiconductor layer and the second portion of the memory film being within the memory stack.

5. The 3D memory device of claim 1, wherein the source contact comprises a via contact.

6. The 3D memory device of claim 1, wherein the source contact comprises a metal layer and an adhesive layer surrounding the metal layer.

7. The 3D memory device of claim 1, further comprising a gate line slit extending vertically through the memory stack, a portion of the source contact being above the gate line slit, and one portion of the source contact and the gate line slit overlapping along a first lateral direction.

8. The 3D memory device of claim 1, further comprising a contact passing through the second semiconductor layer, a first set of the contacts being in contact with the source line mesh.

9. The 3D memory device according to claim 8, wherein the memory stack includes two core array regions having the channel structure and a staircase region between the two core array regions in a first lateral direction in a plan view.

10. The 3D memory device according to claim 8, wherein the backside interconnect layer further includes a source select gate (SSG) line in a plan view, and a second set of the contacts are distributed below the SSG line and in contact with the SSG line.

11. The 3D memory device according to claim 8, wherein the backside interconnect layer further includes a power line mesh in a plan view, and a third set of the contacts are distributed below the power line mesh and in contact with the power line mesh.

12. The 3D memory device according to claim 11, wherein each of the power line mesh and the source line mesh has a comb-like shape.

13. A three-dimensional (3D) memory device, comprising: a memory stack including alternating conductor layers and dielectric layers below a first side of a second semiconductor layer; a channel structure extending into the second semiconductor layer through the memory stack in a vertical direction; a source contact in contact with a second side of the second semiconductor layer opposite to the first side, the source contact including a metal layer and an adhesive layer surrounding the metal layer; a backside interconnect layer above the second side of the second semiconductor layer, including an interlayer dielectric (ILD) layer and a source line mesh on the ILD layer, wherein the source contact is distributed below the source line mesh and extends into the second semiconductor layer through the ILD layer; a first semiconductor layer between the memory stack and the second semiconductor layer, wherein each of the channel structures includes a semiconductor channel and a memory film surrounding a part of the semiconductor channel, and the first semiconductor layer surrounds a part of the channel structure and is in contact with the semiconductor channel.

14. The 3D memory device according to claim 13, wherein the memory stack includes a core array region, and at least a part of the source contact is within the core array region.

15. The memory film includes a first portion and a second portion distributed on the opposite side of the first semiconductor layer. The first portion of the memory film is within the second semiconductor layer, and the second portion of the memory film is within the memory stack. The 3D memory device according to claim 13.

16. The memory stack further includes a gate line slit extending vertically therethrough. A part of the source contact is above the gate line slit, and a part of one of the source contacts overlaps with the gate line slit along a first lateral direction. The 3D memory device according to claim 13.

17. The 3D memory device according to claim 13, further comprising a contact passing through the second semiconductor layer, and a first set of the contacts being in contact with the source line mesh.

18. The backside interconnect layer further includes a source select gate (SSG) line in a plan view, and a second set of the contacts is distributed below the SSG line and in contact with the SSG line. The 3D memory device according to claim 17.

19. A method for forming a three-dimensional (3D) memory device, comprising: forming a memory stack including alternating conductive layers and dielectric layers below a first side of a second semiconductor layer; forming a channel structure extending into the second semiconductor layer vertically through the memory stack; forming a source contact in contact with a second side of the second semiconductor layer opposite to the first side; and forming a backside interconnect layer above the second side of the second semiconductor layer, including an interlayer dielectric (ILD) layer and a source line mesh on the ILD layer, wherein the source contact is distributed below the source line mesh and extends into the second semiconductor layer through the ILD layer.

20. forming a peripheral circuit on a first substrate; forming the memory stack and the channel structure on a second substrate; bonding the first substrate and the second substrate face to face, wherein the channel structure and the peripheral circuit are between the first substrate and the second substrate; and thinning the second substrate to form a semiconductor layer. Forming the ILD layer on the semiconductor layer; The method according to claim 19, further comprising forming the source contact and the source line mesh on the ILD layer.

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