Semiconductor Devices

Abstract

This semiconductor device comprises: a substrate; a conductive part that is formed on the main surface of the substrate; a semiconductor chip that is disposed on the main surface of the substrate; a control device that controls the semiconductor chip; a sealing resin that covers the semiconductor chip, the control device, and the conductive part; and a first lead that is joined to the conductive part and that is partially exposed from the sealing resin. The conductive part includes a first pad and a second pad which are disposed so as to be apart from each other. The first lead is joined to the first pad and the second pad.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] As one of various semiconductor devices, there is what is called an IPM (Intelligent Power Module). This semiconductor device includes a semiconductor chip, a control chip that controls the semiconductor chip, and a sealing resin that covers the semiconductor chip and the control chip (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A plurality of types of signals are input to the control chip, and a plurality of types of signals are output from the chip. As the number of signals increases, it is necessary to increase the number of conduction paths connected to the control chip. However, with the method of configuring these conduction paths by a plurality of metal leads as in the prior art, further high integration of the semiconductor device may become difficult.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that enables higher integration than in the prior art.

Means for Solving the Problems

[0006] The semiconductor device provided by the first aspect of the present disclosure includes a substrate having a substrate front surface and a substrate back surface facing opposite sides in the thickness direction, a conductive portion made of a conductive material formed on the substrate front surface, a semiconductor chip disposed on the substrate front surface, a control device disposed on the substrate front surface for controlling the semiconductor chip, at least a part of the substrate, and a sealing resin covering the semiconductor chip, the control device, and the conductive portion, and a first lead joined to the conductive portion via a conductive bonding material and having a part exposed from the sealing resin. The conductive portion includes a first pad and a second pad disposed apart from each other. The first lead is joined to the first pad and the second pad.

Advantages of the Invention

[0007] According to the above configuration, a conductive portion is formed on the substrate front surface. Therefore, a conduction path to an electronic component disposed on the substrate front surface can be configured by the conductive portion. Therefore, it is possible to achieve thinning and high density of the conduction path as compared with the case where the conduction path is configured by, for example, a metal lead. Further, the first lead is joined to the first pad and the second pad via a conductive bonding material. Thereby, noise input to the first pad via the connection wiring is discharged to the outside from the first lead. Thus, it is suppressed that noise is input to other electronic components via the second pad and the connection wiring connected thereto. Therefore, the influence by noise is suppressed as compared with the case where the first lead is joined to one pad.

[0008] Other features and advantages of the present disclosure will become clearer from the following detailed description with reference to the accompanying drawings.

Brief Description of the Drawings

[0009]

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MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.

[0011] In the present disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed above a certain object B" include "a certain object A is directly formed on a certain object B" and "a certain object A is formed on a certain object B with another object intervening between the certain object A and the certain object B". Similarly, unless otherwise specified, "a certain object A is disposed on a certain object B" and "a certain object A is disposed above a certain object B" include "a certain object A is directly disposed on a certain object B" and "a certain object A is disposed on a certain object B with another object intervening between the certain object A and the certain object B". Similarly, unless otherwise specified, "a certain object A is located above a certain object B" includes "a certain object A is in contact with a certain object B and a certain object A is located above a certain object B" and "a certain object A is located above a certain object B with another object intervening between the certain object A and the certain object B". Further, unless otherwise specified, "a certain object A overlaps a certain object B when viewed in a certain direction" includes "a certain object A overlaps all of a certain object B" and "a certain object A overlaps a part of a certain object B".

[0012] <First Embodiment> Figures 1 to 10 show an example of a semiconductor device according to the present disclosure. The semiconductor device A1 of the present embodiment includes a plurality of leads 1, a substrate 2, a plurality of joints 25, conductive parts 3, four semiconductor chips 4, four control devices 5, a plurality of passive elements 6, a plurality of wires 71, a plurality of wires 72, and a sealing resin 8. In the present embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used, for example, in applications such as air conditioners and motor control devices.

[0013] FIG. 1 is a perspective view showing a semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view showing the semiconductor device A1 and is a view through the encapsulating resin 8. In FIG. 3, the outer shape of the encapsulating resin 8 is shown by an imaginary line (two-dot chain line). FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 3. FIGS. 6 to 9 are partially enlarged views of FIG. 3. FIG. 10 is a plan view showing the substrate 2.

[0014] For convenience of explanation, the thickness direction (plan view direction) of the substrate 2 is defined as the z direction, and the direction along one side of the substrate 2 orthogonal to the z direction (left-right direction in FIGS. 2 to 4) is defined as the x direction. Further, the direction orthogonal to the z direction and the x direction (up-down direction in FIGS. 2 to 4) is defined as the y direction. The z direction is an example of the "thickness direction".

[0015] The substrate 2 is plate-shaped and has a rectangular shape that is long in the x direction when viewed in the z direction. The thickness (dimension in the z direction) of the substrate 2 is, for example, about 0.1 mm to 1.0 mm. Note that each dimension of the substrate 2 is not limited. The substrate 2 is made of an insulating material. The material of the substrate 2 is not particularly limited. As the material of the substrate 2, for example, a material having a higher thermal conductivity than the material of the encapsulating resin 8 is preferable. Examples of the material of the substrate 2 include ceramics such as alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and alumina containing zirconia.

[0016] The substrate 2 has a substrate front surface 21 and a substrate back surface 22. The substrate front surface 21 and the substrate back surface 22 are surfaces facing opposite sides in the z direction and are both flat surfaces orthogonal to the z direction. The substrate front surface 21 is the surface facing upward in FIG. 5. A conductive portion 3 and a plurality of bonding portions 25 are formed on the substrate front surface 21, and a plurality of leads 1 and a plurality of electronic components are mounted thereon. The plurality of electronic components include four semiconductor chips 4, four control devices 5, and a plurality of passive elements 6. The substrate back surface 22 is the surface facing downward in FIG. 5. As shown in FIG. 4, the substrate back surface 22 is exposed from the encapsulating resin 8. The shapes of the substrate front surface 21 and the substrate back surface 22 are both rectangular. Note that the shape of the substrate 2 is not limited.

[0017] The conductive part 3 is formed on the substrate 2. In the present embodiment, the conductive part 3 is formed on the main surface 21 of the substrate 2. The conductive part 3 is made of a conductive material. The conductive material constituting the conductive part 3 is not particularly limited. Examples of the conductive material of the conductive part 3 include those containing silver (Ag), copper (Cu), gold (Au), etc. In the following description, the case where the conductive part 3 contains silver will be described as an example. Note that the conductive part 3 may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the conductive part 3 may contain Ag-Pt or Ag-Pd. The forming method of the conductive part 3 is not limited, and for example, it is formed by firing a paste containing these metals. The thickness of the conductive part 3 is not particularly limited, and is, for example, about 5 μm to 30 μm.

[0018] The shape etc. of the conductive part 3 are not particularly limited. In the present embodiment, as shown in FIG. 10 for example, the conductive part 3 includes a plurality of pads 31, a plurality of pads 32, and a plurality of connection wirings 33. Each pad 31 is, for example, rectangular, and any one of the control device 5, the passive element 6, and the wire 72 is conductively joined thereto. Note that the shape of the pad 31 is not limited. The pads 31 are arranged spaced apart from each other.

[0019] Each pad 32 is, for example, rectangular, and is conductively joined to a lead 15 (described later). Note that the shape of the pad 32 is not limited. The pads 32 are arranged spaced apart from each other. In the present embodiment, the plurality of pads 32 are formed at an end on one side in the y direction (the upper side in FIG. 10) or at both ends in the x direction on the substrate main surface 21 of the substrate 2. As shown in FIGS. 6 to 9, the plurality of pads 32 include pads 32a, 32b, 32c, 32d, 32e, 32f, 32g, and 32h. The pad 32a and the pad 32b are joined to the same lead 1 (lead 15a described later). The pad 32c and the pad 32d are joined to the same lead 1 (lead 15b described later). The pad 32e and the pad 32f are joined to the same lead 1 (lead 15c described later). The pad 32g and the pad 32h are joined to the same lead 1 (lead 15d described later).

[0020] Each connection wiring 33 is connected to a pad 31 and another pad 31, or is connected to a pad 31 and a pad 32. In the present embodiment, as shown in FIGS. 6 to 9, some of the connection wirings 33 overlap the control device 5 in a view from the z direction. That is, the connection wiring 33 is disposed between the substrate main surface 21 of the substrate 2 and the control device 5. Also, some of the connection wirings 33 overlap the passive element 6 in a view from the z direction. That is, the connection wiring 33 is disposed between the substrate main surface 21 of the substrate 2 and the passive element 6.

[0021] As shown in FIG. 10, a plurality of joints 25 are formed on the substrate 2. In the present embodiment, the plurality of joints 25 are formed closer to the other side in the y direction (the lower side in FIG. 10) on the main surface 21 of the substrate 2. The material of the joint 25 is not particularly limited, and for example, it is made of a material capable of joining the substrate 2 and the lead 1. The joint 25 is made of, for example, a conductive material. The conductive material constituting the joint 25 is not particularly limited. Examples of the conductive material of the joint 25 include those containing silver (Ag), copper (Cu), gold (Au), etc. In the following description, the case where the joint 25 contains silver will be described as an example. The joint 25 in this example contains the same material as the conductive material constituting the conductive portion 3. Note that the joint 25 may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the joint 25 may contain Ag-Pt or Ag-Pd. The formation method of the joint 25 is not limited, and for example, like the conductive portion 3, it is formed by firing a paste containing these metals. The thickness of the joint 25 is not particularly limited, and is about 5 μm to 30 μm, for example.

[0022] In this embodiment, as shown in FIG. 10, the plurality of joints 25 includes two joints 251, two joints 252, two joints 253, and one joint 254. The joints 251, 252, 253, and 254 are spaced apart from each other. The two joints 251 are respectively formed near both ends in the x direction on the main surface 21 of the substrate. A lead 11 (described later) is joined to each joint 251. The joint 254 is formed at the center in the x direction on the main surface 21 of the substrate. A lead 14 (described later) is joined to the joint 254. One joint 253 is formed between one joint 251 (the right side in FIG. 10) and the joint 254 in the x direction on the main surface 21 of the substrate. The other joint 253 is formed between the other joint 251 (the left side in FIG. 10) and the joint 254 in the x direction on the main surface 21 of the substrate. A lead 13 (described later) is joined to each joint 253. One joint 252 is formed so as to surround one joint 253 between one joint 251 and the joint 254. The other joint 252 is formed so as to surround the other joint 253 between the other joint 251 and the joint 254. A lead 12 (described later) is joined to each joint 252. Note that the shapes and arrangements of the joints 251, 252, 253, and 254 are not limited.

[0023] The plurality of leads 1 is composed of a metal and has, for example, a higher thermal conductivity than the substrate 2. The metal constituting the lead 1 is not particularly limited and may be, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). Further, the plurality of leads 1 may be nickel (Ni) plated. The plurality of leads 1 may be formed, for example, by pressing a mold against a metal plate or by patterning a metal plate by etching. Note that the method for forming the plurality of leads 1 is not limited. The thickness of each lead 1 is not particularly limited and is, for example, about 0.4 mm to 0.8 mm. The leads 1 are spaced apart from each other.

[0024] In this embodiment, the plurality of leads 1 includes two leads 11, two leads 12, two leads 13, one lead 14, and a plurality of leads 15. The leads 11, 12, 13, and 14 constitute a conduction path to the semiconductor chip 4. The plurality of leads 15 constitutes a conduction path to the control device 5 or the passive element 6.

[0025] The two leads 11 are arranged on the substrate 2, and in this embodiment, they are arranged on the main surface 21 of the substrate. The lead 11 is an example of the "third lead". Each lead 11 is joined to the joint portion 25 via a joining material 75. The joining material 75 may be any material that can join the lead 11 to the joint portion 25. From the viewpoint of efficiently transferring the heat from the lead 11 to the substrate 2, it is preferable that the joining material 75 has a higher thermal conductivity. For example, silver paste, copper paste, solder, etc. are used. However, the joining material 75 may also be an insulating material such as an epoxy resin or a silicone resin. Also, when the joint portion 25 is not formed on the substrate 2, the lead 11 may be directly joined to the substrate 2. Each lead 11 is joined to a joint portion 251. When distinguishing between the two leads 11, the one joined to one joint portion 251 (the right joint portion 251 in FIG. 10) is defined as the lead 11a, and the one joined to the other joint portion 251 (the left joint portion 251 in FIG. 10) is defined as the lead 11b. The semiconductor chip 4a is joined to the lead 11a, and the semiconductor chip 4c is joined to the lead 11b.

[0026] The configuration of the lead 11 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 11 is divided into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114 for explanation.

[0027] The joint portion 111 has a front surface 111a and a back surface 111b. The front surface 111a and the back surface 111b are surfaces facing opposite sides in the z direction, and both are flat surfaces orthogonal to the z direction. The front surface 111a is the surface facing upward in FIG. 5. The semiconductor chip 4 is joined to the front surface 111a. The back surface 111b is the surface facing downward in FIG. 5. The back surface 111b is joined to the joint portion 25 by the joining material 75. The inclined connection portion 113 and the parallel connection portion 114 are covered by the encapsulating resin 8. The inclined connection portion 113 is connected to the joint portion 111 and the parallel connection portion 114, and is inclined with respect to the joint portion 111 and the parallel connection portion 114. The parallel connection portion 114 is connected to the inclined connection portion 113 and the protruding portion 112, and is parallel to the joint portion 111. The protruding portion 112 is connected to the end of the parallel connection portion 114 and is the portion of the lead 11 protruding from the encapsulating resin 8. The protruding portion 112 protrudes on the side opposite to the joint portion 111 in the y direction. The protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent toward the side where the front surface 111a of the joint portion 111 faces in the z direction.

[0028] The two leads 12 are arranged on the substrate 2, and in the present embodiment, they are arranged on the substrate main surface 21. The lead 12 is an example of the "third lead". Each lead 12 is joined to the joint portion 252 via the joining material 75. When distinguishing between the two leads 12, the one joined to one joint portion 252 (the right joint portion 252 in FIG. 10) is referred to as lead 12a, and the one joined to the other joint portion 252 (the left joint portion 252 in FIG. 10) is referred to as lead 12b. The configuration of the lead 12 is not particularly limited. In the present embodiment, the configuration of the lead 12 is the same as that of the lead 11. The semiconductor chip 4b is joined to the lead 12a, and the semiconductor chip 4d is joined to the lead 12b.

[0029] The two leads 13 are arranged on the substrate 2, and in this embodiment, they are arranged on the main surface 21 of the substrate. Each lead 13 is joined to the joint portion 253 via the joining material 75. When distinguishing the two leads 13, the one joined to one joint portion 253 (the right joint portion 253 in FIG. 10) is designated as lead 13a, and the one joined to the other joint portion 253 (the left joint portion 253 in FIG. 10) is designated as lead 13b. The configuration of the lead 13 is not particularly limited. In this embodiment, the configuration of the lead 13 is the same as that of the lead 11. The semiconductor chip 4 is not joined to the lead 13.

[0030] The lead 14 is arranged on the substrate 2, and in this embodiment, it is arranged on the main surface 21 of the substrate. The lead 14 is joined to the joint portion 254 via the joining material 75. The configuration of the lead 14 is not particularly limited. In this embodiment, the configuration of the lead 14 is the same as that of the lead 11. The semiconductor chip 4 is not joined to the lead 14.

[0031] The plurality of leads 15 are each arranged on the substrate 2, and in this embodiment, they are arranged on the main surface 21 of the substrate. Each lead 15 is joined to the pad 32 of the conductive portion 3 via the conductive joining material 76. The conductive joining material 76 may be any material that can join the lead 15 to the pad 32 and electrically connect the lead 15 and the pad 32. For example, silver paste, copper paste, solder, etc. are used as the conductive joining material 76. The overall shape of each lead 15 is strip-shaped.

[0032] The configuration of the lead 15 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 15 is divided into a joining portion 151, a protruding portion 152, an inclined connection portion 153, and a parallel connection portion 154 for explanation.

[0033] The joint portion 151 has a front surface 151a and a back surface 151b. The front surface 151a and the back surface 151b face opposite sides in the z direction and are both flat surfaces orthogonal to the z direction. The front surface 151a faces upward in FIG. 5. The back surface 151b faces downward in FIG. 5. The back surface 151b is joined to the pad 32 by the conductive joint material 76. The inclined connection portion 153 and the parallel connection portion 154 are covered by the encapsulating resin 8. The inclined connection portion 153 is connected to the joint portion 151 and the parallel connection portion 154 and is inclined with respect to the joint portion 151 and the parallel connection portion 154. The parallel connection portion 154 is connected to the inclined connection portion 153 and the protruding portion 152 and is parallel to the joint portion 151. The protruding portion 152 is connected to the end of the parallel connection portion 154 and is the portion of the lead 15 that protrudes from the encapsulating resin 8. The protruding portion 152 protrudes on the side opposite to the joint portion 151 in the y direction. The protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent toward the side where the front surface 151a of the joint portion 151 faces in the z direction.

[0034] As shown in FIGS. 3, 6 to 9, the plurality of leads 15 include leads 15a, 15b, 15c, 15d. The leads 15a, 15b, 15c, 15d are each joined to two pads 32 arranged spaced apart from each other. The leads 15a, 15b, 15c, 15d are an example of the "first lead".

[0035] As shown in FIG. 6, lead 15a is joined to both pad 32a and pad 32b. Pads 32a and 32b are examples of the “first pad” and the “second pad”. The joint portion 151 of lead 15a includes a wide portion 151c located at the end on the side opposite to the protruding portion 152. The wide portion 151c has a width dimension that is twice or more as large as that of other portions. Pads 32a and 32b are arranged side by side in the x direction at the end on one side (the upper side in FIG. 6) in the y direction on the main surface 21 of the substrate, and are joined to the wide portion 151c of lead 15a. Pad 32a is electrically connected to lead 53 (described later), which is the analog power supply terminal of control device 5d (described later), via connection wiring 33 and pad 31. Pad 32b is electrically connected to lead 53, which is the analog power supply terminal of control device 5c (described later), via connection wiring 33 and pad 31. That is, lead 15a is electrically connected to the analog power supply terminals of control devices 5c and 5d.

[0036] As shown in FIG. 8, lead 15c is joined to both pad 32e and pad 32f. Pads 32e and 32f are examples of the “first pad” and the “second pad”. As shown in FIG. 5, the joint portion 151 of lead 15c includes a first end portion 151d on the protruding portion 152 side and a second end portion 151e on the side opposite to the protruding portion 152. Pads 32e and 32f are arranged side by side in a direction slightly inclined with respect to the y direction at the end on one side (the upper side in FIG. 8) in the y direction on the main surface 21 of the substrate, and are arranged such that the first end portion 151d and the second end portion 151e of lead 15c are spaced apart from each other. Pad 32e is joined to the second end portion 151e, and pad 32f is joined between the first end portion 151d and the second end portion 151e. Pad 32e is electrically connected to lead 53, which is the analog power supply terminal of control device 5a (described later), via connection wiring 33 and pad 31. Pad 32f is electrically connected to lead 53, which is the analog power supply terminal of control device 5b (described later), via connection wiring 33 and pad 31. That is, lead 15c is electrically connected to the analog power supply terminals of control devices 5a and 5b.

[0037] As shown in FIG. 7, lead 15b is joined to both pad 32c and pad 32d. Pad 32c and pad 32d are an example of the “first pad” and the “second pad”. The joint portion 151 of lead 15b includes a first end portion 151d on the protruding portion 152 side and a second end portion 151e on the side opposite to the protruding portion 152, similar to the joint portion 151 of lead 15c. Pad 32c and pad 32d are arranged side by side in a direction slightly inclined with respect to the x direction at an end on one side (the upper side in FIG. 7) in the y direction on the main surface 21 of the substrate, and the first end portion 151d and the second end portion 151e of lead 15b are arranged side by side in a direction in which they are separated from each other. Pad 32c is joined to the second end portion 151e, and pad 32d is joined between the first end portion 151d and the second end portion 151e. Pad 32c is electrically connected to lead 53, which is the ground terminal of control device 5c, via connection wiring 33 and pad 31. Pad 32d is electrically connected to lead 53, which is the ground terminal of control device 5d, via connection wiring 33 and pad 31. That is, lead 15b is electrically connected to the ground terminals of control device 5c and control device 5d.

[0038] As shown in FIG. 9, lead 15d is joined to both pad 32g and pad 32h. Pads 32g and 32h are examples of the "first pad" and the "second pad". Similar to the joint portion 151 of lead 15c, the joint portion 151 of lead 15d includes a first end 151d on the protruding portion 152 side and a second end 151e on the side opposite to the protruding portion 152. Pads 32g and 32h are arranged side by side in the y direction at one end in the x direction (the right side in FIG. 9) on the main surface 21 of the substrate, and the first end 151d and the second end 151e of lead 15d are arranged side by side in a direction in which they are separated from each other. Pad 32g is joined to the second end 151e, and pad 32h is joined between the first end 151d and the second end 151e. Pad 32g is electrically connected to lead 53, which is the ground terminal of control device 5b, via connection wiring 33 and pad 31. Pad 32h is electrically connected to lead 53, which is the ground terminal of control device 5a, via connection wiring 33 and pad 31. That is, lead 15d is electrically connected to the ground terminals of control devices 5a and 5b.

[0039] Note that the shape of the joint portion 151 of each lead 15 is appropriately designed according to the arrangement of the pads 32 to be joined. The shapes of the joint portions 151 of leads 15a, 15b, 15c, and 15d are appropriately designed according to the respective arrangements of the two pads 32 to be joined.

[0040] The four semiconductor chips 4 are respectively arranged on any one of the leads 1. When the four semiconductor chips 4 are described separately, they are respectively referred to as semiconductor chip 4a, semiconductor chip 4b, semiconductor chip 4c, and semiconductor chip 4d. When not distinguished, they are simply referred to as semiconductor chip 4. The type and function of the semiconductor chip 4 are not particularly limited. In this embodiment, the case where the semiconductor chip 4 is a power transistor that controls power will be described as an example. The semiconductor chip 4 is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor) made of a SiC (silicon carbide) substrate. Note that the semiconductor chip 4 may be a MOSFET made of a Si (silicon) substrate instead of a SiC substrate, and may include, for example, an IGBT element. Further, it may be a MOSFET including GaN (gallium nitride). In this embodiment, the case where the semiconductor device A1 includes four semiconductor chips 4 is shown, but this is an example, and the number of semiconductor chips 4 is not limited.

[0041] The semiconductor chip 4 is in the shape of a rectangular plate when viewed in the z direction, and includes an element main surface 41, an element back surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The element main surface 41 and the element back surface 42 face opposite sides in the z direction. The element main surface 41 is the surface facing upward in FIG. 5. The element back surface 42 is the surface facing downward in FIG. 5. As shown in FIG. 3, the source electrode 43 and the gate electrode 44 are arranged on the element main surface 41. Further, the drain electrode 45 is arranged on the element back surface 42. Note that the shapes and arrangements of the source electrode 43, the gate electrode 44, and the drain electrode 45 are not limited.

[0042] As shown in FIGS. 3 and 5, the semiconductor chip 4a is disposed on the lead 11a. As shown in FIG. 5, the semiconductor chip 4a is bonded to the lead 11a by a conductive bonding material (not shown) with the back surface 42 of the element facing the lead 11a. Thereby, the drain electrode 45 of the semiconductor chip 4a is conductively connected to the lead 11a by the conductive bonding material. As the conductive bonding material, for example, silver paste, copper paste, solder, or the like is used. Further, as shown in FIG. 3, the source electrode 43 of the semiconductor chip 4a is conductively connected to the lead 12a by the wire 71. The wire 71 is made of, for example, aluminum (Al) or copper (Cu). Note that the material, wire diameter, and number of the wires 71 are not limited. The semiconductor chip 4b is disposed on the lead 12a as shown in FIG. 3. The semiconductor chip 4b is bonded to the lead 12a by a conductive bonding material (not shown) with the back surface 42 of the element facing the lead 12a. Thereby, the drain electrode 45 of the semiconductor chip 4b is conductively connected to the lead 12a by the conductive bonding material. Further, the source electrode 43 of the semiconductor chip 4b is conductively connected to the lead 14 by the wire 71. Thereby, a bridge circuit in which the source electrode 43 of the semiconductor chip 4a and the drain electrode 45 of the semiconductor chip 4b are connected is formed.

[0043] As shown in FIG. 3, the source electrode 43 and the gate electrode 44 of the semiconductor chip 4a are conductively connected to the control device 5a via the wire 72 and the conductive portion 3, respectively. The wire 72 is made of, for example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the like. Note that the material, wire diameter, and number of the wires 72 are not limited. The control device 5a inputs a drive signal to the gate electrode 44 of the semiconductor chip 4a. Further, the source electrode 43 and the gate electrode 44 of the semiconductor chip 4b are conductively connected to the control device 5b via the wire 72 and the conductive portion 3, respectively. The control device 5b inputs a drive signal to the gate electrode 44 of the semiconductor chip 4b. A DC voltage is applied between the lead 11a and the lead 14, and a drive signal is input to the gate electrodes 44 of the semiconductor chips 4a and 4b, whereby a switching signal whose voltage is switched according to the drive signal is output from the lead 12a.

[0044] As shown in FIG. 3, the semiconductor chip 4c is disposed on the lead 11b. The semiconductor chip 4c is bonded to the lead 11b by a conductive bonding material (not shown) with the back surface 42 of the element facing the lead 11b. Thereby, the drain electrode 45 of the semiconductor chip 4c is conductively connected to the lead 11b by the conductive bonding material. Further, the source electrode 43 of the semiconductor chip 4c is conductively connected to the lead 12b by the wire 71. As shown in FIG. 3, the semiconductor chip 4d is disposed on the lead 12b. The semiconductor chip 4d is bonded to the lead 12b by a conductive bonding material (not shown) with the back surface 42 of the element facing the lead 12b. Thereby, the drain electrode 45 of the semiconductor chip 4d is conductively connected to the lead 12b by the conductive bonding material. Further, the source electrode 43 of the semiconductor chip 4d is conductively connected to the lead 14 by the wire 71. Thereby, a bridge circuit is formed in which the source electrode 43 of the semiconductor chip 4c and the drain electrode 45 of the semiconductor chip 4d are connected.

[0045] The source electrode 43 and the gate electrode 44 of the semiconductor chip 4c are conductively connected to the control device 5c via the wire 72 and the conductive portion 3, respectively. The control device 5c inputs a drive signal to the gate electrode 44 of the semiconductor chip 4c. Further, the source electrode 43 and the gate electrode 44 of the semiconductor chip 4d are conductively connected to the control device 5d via the wire 72 and the conductive portion 3, respectively. The control device 5d inputs a drive signal to the gate electrode 44 of the semiconductor chip 4d. A DC voltage is applied between the lead 11b and the lead 14, and a drive signal is input to the gate electrodes 44 of the semiconductor chips 4c and 4d, whereby a switching signal whose voltage is switched according to the drive signal is output from the lead 12b.

[0046] The four control devices 5 each control the driving of the semiconductor chips 4 and are arranged on the main surface 21 of the substrate 2. When the four control devices 5 are described separately, they are referred to as the control device 5a, the control device 5b, the control device 5c, and the control device 5d, respectively. When not distinguished, they are simply referred to as the control device 5. The control device 5a controls the driving of the semiconductor chip 4a. The control device 5b controls the driving of the semiconductor chip 4b. The control device 5c controls the driving of the semiconductor chip 4c. The control device 5d controls the driving of the semiconductor chip 4d. As shown in FIG. 5, the control device 5 is located between the semiconductor chip 4 and the lead 15 in the x-direction view. Also, as shown in FIG. 3, in the y-direction view, the control device 5a overlaps the semiconductor chip 4a, the control device 5b overlaps the semiconductor chip 4b, the control device 5c overlaps the semiconductor chip 4c, and the control device 5d overlaps the semiconductor chip 4d. Note that the arrangement of the control devices 5a to 5d is not limited.

[0047] The control device 5 includes a control chip (not shown), a die pad, a plurality of wires, a plurality of leads 53, and a resin 54. The control chip is an integrated circuit that controls the driving of the semiconductor chip 4 and outputs a driving signal for driving the semiconductor chip 4. The die pad and the plurality of leads 53 are plate-like members made of, for example, copper (Cu). The die pad has the control chip mounted thereon. Each lead 53 is electrically connected to the control chip by a wire. The resin 54 covers the entire control chip and wires and a part of each lead 53 and is made of an insulating material such as an epoxy resin or a silicone gel.

[0048] As shown in FIGS. 6 to 9, each lead 53 is arranged at both ends of the resin 54 in the y direction with an interval in the x direction. Each lead 53 extends along the y direction, and a part of each lead projects from both side surfaces of the resin 54 in the y direction. The part of each lead 53 protruding from the resin 54 is conductively joined to the pad 31 of the conductive portion 3. In the present embodiment, the control device 5 is an SOP (Small Outline Package) type package. Note that the package type of the control device 5 is not limited to the SOP type, and may be other types of packages such as a QFP (Quad Flat Package) type or an SOJ (Small Outline J - lead Package) type. Each lead 53 is joined to the pad 31 of the conductive portion 3 via a conductive bonding material 76.

[0049] Note that the size, shape, number of leads, etc. of the control device 5 are not limited. Also, the control device 5 may include a plurality of control chips or may include circuit chips other than control chips.

[0050] In the present embodiment, some of the connection wirings 33 overlap the control device 5 in a view in the z direction and are arranged between the substrate main surface 21 of the substrate 2 and the opposing surface of the control device 5. Since the control chip of the control device 5 is covered by the resin 54, the control chip is prevented from contacting the connection wiring 33. When the control chip is directly arranged on the substrate 2 instead of the control device 5, if the connection wiring 33 is arranged so as to overlap the control device 5, the control chip will contact the connection wiring 33, so it is necessary to arrange the connection wiring 33 in a detour.

[0051] A plurality of passive elements 6 are arranged on the substrate main surface 21 of the substrate 2 and are conductively joined to the conductive portion 3 or the lead 1. The passive element 6 is, for example, a resistor, a capacitor, an inductor, a diode, or the like. The passive element 6 includes a shunt resistor 6a.

[0052] The shunt resistor 6a is disposed across the leads 12 and 13 and is conductively joined to the leads 12 and 13. The shunt resistor 6a outputs, from the lead 13, a current shunted from the current flowing through the lead 12.

[0053] The other passive elements 6 are conductively joined to the pads 31 of the conductive portion 3 and are conductively connected to the control device 5 via the connection wiring 33 and the pads 31, or are conductively connected to the lead 15 via the connection wiring 33 and the pads 32. Note that the type, arrangement position, and number of each passive element 6 are not limited.

[0054] The encapsulating resin 8 covers at least the entirety of the four semiconductor chips 4, the four control devices 5, the plurality of passive elements 6, and the wires 71 and 72, a part of each of the plurality of leads 1, and a part of the substrate 2. The material of the encapsulating resin 8 is not particularly limited, and for example, an insulating material such as an epoxy resin or a silicone gel is appropriately used.

[0055] The encapsulating resin 8 has a resin front surface 81, a resin back surface 82, and four resin side surfaces 83. The resin front surface 81 and the resin back surface 82 are surfaces facing opposite sides in the z direction and are both flat surfaces orthogonal to the z direction. The resin front surface 81 is the surface facing upward in FIG. 5. The resin back surface 82 is the surface facing downward in FIG. 5. Each resin side surface 83 is connected to the resin front surface 81 and the resin back surface 82, respectively, and faces the x direction or the y direction. As shown in FIG. 4, the back surface 22 of the substrate 2 is exposed from the resin back surface 82 of the encapsulating resin 8. In the present embodiment, as shown in FIG. 5, the back surface 22 of the substrate and the resin back surface 82 are flush with each other.

[0056] Next, an example of a method for manufacturing the semiconductor device A1 will be described below with reference to FIG. 11. Note that the manufacturing method described below is one means for realizing the semiconductor device A1 and is not limited thereto.

[0057] As shown in FIG. 11, the manufacturing method of this example includes a conductive portion forming step (step S1), a lead frame bonding step (step S2), a semiconductor chip mounting step (step S3), a control device mounting step (step S4), a wire connection step (step S5), a resin forming step (step S6), and a frame cutting step (step S7).

[0058] In the conductive portion forming step (step S1), first, a substrate 2 is prepared. The substrate 2 is made of, for example, ceramic. Next, a conductive portion 3 and a plurality of bonding portions 25 are formed on the main surface 21 of the substrate 2. In this example, the conductive portion 3 and the plurality of bonding portions 25 are formed collectively. For example, after printing a metal paste and then firing it, a conductive portion 3 and a plurality of bonding portions 25 containing a metal such as silver (Ag) as a conductive material are obtained.

[0059] In the lead frame bonding step (step S2), first, a bonding paste is printed on the plurality of bonding portions 25, and a conductive bonding paste is printed on the plurality of pads 32 of the conductive portion 3. The bonding paste and the conductive bonding paste are, for example, Ag paste or solder paste. Next, a lead frame is prepared. The lead frame includes a plurality of leads 1 and further has a frame to which the plurality of leads 1 are connected. Note that the shape of the lead frame and the like are not limited in any way. Next, leads 11, 12, 13, 14 among the plurality of leads 1 are faced to the plurality of bonding portions 25 via the bonding paste. Also, a plurality of leads 15 among the plurality of leads 1 are faced to the conductive portion 3 (the plurality of pads 32) via the conductive bonding paste. For example, after heating and then cooling the bonding paste and the conductive bonding paste, a bonding material 75 is formed by the bonding paste, and a conductive bonding material 76 is formed by the conductive bonding paste. Thereby, the leads 11, 12, 13, 14 are bonded to the plurality of bonding portions 25 via the bonding material 75, and the plurality of leads 15 are bonded to the conductive portion 3 via the conductive bonding material 76.

[0060] In the semiconductor chip mounting process (step S3), first, a conductive bonding paste is printed at predetermined positions on leads 11a, 11b and leads 12a, 12b. The conductive bonding paste is, for example, an Ag paste or a solder paste. Next, semiconductor chip 4a is attached to the conductive bonding paste printed on lead 11a, semiconductor chip 4b is attached to the conductive bonding paste printed on lead 12a, semiconductor chip 4c is attached to the conductive bonding paste printed on lead 11b, and semiconductor chip 4d is attached to the conductive bonding paste printed on lead 12b. Then, by heating and then cooling the conductive bonding paste, for example, a conductive bonding material is formed by the conductive bonding paste. Thereby, semiconductor chip 4a is joined to lead 11a via the conductive bonding material, semiconductor chip 4b is joined to lead 12a via the conductive bonding material, semiconductor chip 4c is joined to lead 11b via the conductive bonding material, and semiconductor chip 4d is joined to lead 12b via the conductive bonding material. Also, by the same process, shunt resistor 6a is joined to leads 12a and 13a and to leads 12b and 13b via the conductive bonding material.

[0061] In the control device mounting process (step S4), a conductive bonding paste is printed on pad 31 of conductive part 3. The conductive bonding paste is, for example, an Ag paste or a solder paste. Next, each lead 53 of control devices 5a to 5d is attached to the conductive bonding paste. Then, by heating and then cooling the conductive bonding paste, for example, each lead 53 of control devices 5a to 5d is joined to pad 31 via the conductive bonding material. Also, by the same process, other passive element 6 is joined to pad 31 of conductive part 3 via the conductive bonding material.

[0062] In the wire connection step (step S5), first, a plurality of wires 71 are connected. In this example, for instance, by means of the wedge bonding technique, wire materials made of aluminum (Al) are sequentially connected. Thereby, a plurality of wires 71 are obtained. Next, a plurality of wires 72 are connected. In this example, for instance, by means of the capillary bonding technique, wire materials made of gold (Au) are sequentially connected. Thereby, a plurality of wires 72 are obtained.

[0063] In the resin forming step (step S6), for example, a part of the lead frame, a part of the substrate 2, semiconductor chips 4a to 4d, control devices 5a to 5d, a plurality of passive elements 6, and a plurality of wires 71, 72 are surrounded by a mold. Next, a liquid resin material is injected into the space defined by the mold. Then, by curing this resin material, a sealing resin 8 is obtained.

[0064] In the frame cutting step (step S7), appropriate positions of the parts of the lead frame exposed from the sealing resin 8 are cut. Thereby, a plurality of leads 1 are separated from each other. After that, if necessary, through processes such as bending the plurality of leads 1, the semiconductor device A1 described above is obtained.

[0065] Next, the operation and effect of the semiconductor device A1 will be described.

[0066] According to this embodiment, a conductive portion 3 is formed on the main surface 21 of the substrate 2. The control device 5 is conductively joined to the pad 31 of the conductive portion 3. Thereby, a conduction path to the control device 5 can be configured by the conductive portion 3 formed on the main surface 21 of the substrate. Therefore, it is possible to reduce the line width and increase the density of the conduction path as compared with the case where the conduction path is configured by, for example, a metal lead. Further, each of the leads 15a is joined to both the pad 32a and the pad 32b via a conductive joining material 76. Thereby, noise input from, for example, the control device 5d to the pad 32a via the connection wiring 33 is discharged to the outside from the lead 15a. Therefore, it is suppressed that the noise is input to the control device 5c via the pad 32b and the connection wiring 33 connected thereto. Therefore, the influence of noise is suppressed as compared with the case where the lead 15 is joined to one pad 32 that also serves as the pad 32a and the pad 32b. The same applies to the pad 32c and the pad 32d joined to the lead 15b, the pad 32e and the pad 32f joined to the lead 15c, and the pad 32g and the pad 32h joined to the lead 15d.

[0067] FIG. 12 is a schematic diagram for explaining the relationship between the connection state of the pad 32 and the lead 15 and the noise transmission state. The direction of the arrow in the figure indicates the noise transmission direction, and the thickness of the arrow indicates the magnitude of the transmitted noise.

[0068] FIG. (a) of the figure shows a state in which two connection wirings 33 are connected to one pad 32, and the pad 32 is connected to the lead 15 via a conductive joining material 76. As shown in the figure, noise input to the pad 32 via one of the connection wirings 33 is discharged to the outside via the conductive joining material 76 and the lead 15. However, since it is hindered by the resistance component of the conductive joining material 76, the noise also flows to the other connection wiring 33 and is input to the electronic component to which the connection wiring 33 is connected.

[0069] Figure (b) shows a state in which pads 32a and 32b, each connected to connection wiring 33, are connected to lead 15a via conductive bonding material 76 respectively. As shown in this figure, the noise input to pad 32a via one connection wiring 33 is discharged to the outside via conductive bonding material 76 and lead 15a. A part of the noise also flows to pad 32b via conductive bonding material 76, but is blocked by the resistance component of conductive bonding material 76, so the transmission of noise via pad 32b and the connection wiring 33 connected thereto is suppressed.

[0070] As described above, the connection state shown in Figure (b) can suppress the flow of noise generated by the electronic component to other electronic components that are electrically connected to the same lead 15 as the electronic component, compared to the connection state shown in Figure (a), and can suppress the influence of noise.

[0071] Also, according to the present embodiment, the bonding portion 151 of lead 15a includes a wide portion 151c located at the end on the opposite side of the protruding portion 152. The wide portion 151c is suitable for bonding to pads 32a and 32b arranged side by side in the x direction orthogonal to the extending direction (y direction) of lead 15a at the y-direction end of the main surface 21 of the substrate. Also, the bonding portion 151 of lead 15b extends in a strip shape. The bonding portion 151 is suitable for bonding to pads 32c and 32d arranged surrounded by other pads 32, pads 31, and connection wiring 33. The same applies to lead 15c. Also, the bonding portion 151 of lead 15d extends in a strip shape. The bonding portion 151 is suitable for bonding to pads 32g and 32h arranged side by side in the y direction at the x-direction end of the main surface 21 of the substrate.

[0072] Also, according to the present embodiment, a part of the connection wiring 33 of the conductive portion 3 is arranged overlapping the control device 5 in the z-direction view. Therefore, compared with the case of arranging the conduction path in a detour so as not to overlap the control device 5, shortening of the conduction path is possible, and the degree of freedom in designing the conduction path increases. Therefore, high integration of the semiconductor device A1 can be promoted.

[0073] Further, according to the present embodiment, since the plurality of leads 1 have a higher thermal conductivity than the substrate 2, it is possible to suppress a decrease in heat dissipation from the semiconductor chip 4 that may be reduced by the adoption of the substrate 2. Also, each semiconductor chip 4 is directly joined to the lead 11 or the lead 12 by a conductive joining material. Thus, the semiconductor chip 4 and the lead 11 (12) can be electrically connected, and heat from the semiconductor chip 4 can be more efficiently transferred to the lead 11 (12). Also, since the plurality of leads 1 are exposed from the sealing resin 8, an electrical connection path from the outside to the semiconductor chip 4 is constituted, and the heat dissipation characteristics of the semiconductor chip 4 can be further ensured. Further, a joining portion 25 is formed on the substrate 2, and the leads 11 to 14 are joined to the substrate 2 via the joining portion 25. For example, with respect to the surface roughness of the main surface 21 of the substrate 2 made of ceramic, the surface of the joining portion 25 can be finished smoother. Thereby, it is possible to suppress the occurrence of unintended minute voids or the like in the heat transfer path from the leads 11 to 14 to the substrate 2, and heat dissipation of the semiconductor chip 4 or the like can be further promoted. Also, the back surface 22 of the substrate 2 is exposed from the sealing resin 8. Thereby, heat transferred from the semiconductor chip 4 or the like to the substrate 2 can be more efficiently dissipated to the outside.

[0074] Also, according to the present embodiment, since the conductive portion 3 and the joining portion 25 contain the same conductive material, it is possible to integrally form the conductive portion 3 and the joining portion 25 on the substrate 2. This is preferable for improving the manufacturing efficiency of the semiconductor device A1. Also, the plurality of leads 15 are joined to the pads 32 of the conductive portion 3 via the conductive joining material 76. Thereby, the plurality of leads 15 can be more firmly fixed to the substrate 2.

[0075] In the present embodiment, the case where the substrate 2 is a non-laminated substrate has been described, but the substrate 2 may be, for example, a multilayer substrate of a PCB. In this case, since the conductive portion 3 can be arranged in a plurality of layers, more complex wiring can be performed, and the degree of freedom in wiring design increases.

[0076] In addition, in the present embodiment, although the case where a plurality of pads 32 electrically connected to the analog power supply terminal or the ground terminal of the control device 5 are joined to the same lead 15 has been described, the present invention is not limited to this. For example, a plurality of pads 32 electrically connected to the digital power supply terminal of the control device 5 may be joined to the same lead 15, or a plurality of pads 32 electrically connected to the signal terminal of the control device 5 may be joined to the same lead 15.

[0077] In addition, in the present embodiment, although the case where the pad 32a and the pad 32b are not connected in the conductive portion 3 has been described, the present invention is not limited to this. As shown in FIG. 13, the pad 32a and the pad 32b may be connected by a connection portion 34. The connection portion 34 is included in the conductive portion 3 and is made of a conductive material. The connection portion 34 is disposed between the pad 32a and the pad 32b, and one end in the x direction is connected to the pad 32a and the other end is connected to the pad 32b. The dimension of the connection portion 34 in the y direction is sufficiently small as compared with the dimensions of the pad 32a and the pad 32b in the y direction. Therefore, the impedance of the connection portion 34 with respect to high-frequency components is sufficiently high as compared with the conduction path between the pads 32a and 32b via the conductive bonding material 76 and the lead 15a. Therefore, transmission of noise between the pad 32a and the pad 32b through the connection portion 34 is suppressed. According to this modification, even when either one of the pads 32a and 32b cannot be joined to the lead 15a, the pad 32a and the pad 32b are connected by the connection portion 34 and conduction is ensured, so that an open defect can be prevented.

[0078] Note that the shape of the connection portion 34 is not limited to that shown in FIG. 13. Instead of connecting the pad 32a and the pad 32b at the shortest distance, the connection portion 34 may have a shape with a detoured path, for example, as shown in FIG. 14. The connection portion 34 according to this modified example has a U-shaped with one side in the y direction (upper side in FIG. 14) open, and is arranged on the other side in the y direction (lower side in FIG. 14) with respect to the pad 32a and the pad 32b. One end of the connection portion 34 is connected to the pad 32a, and the other end is connected to the pad 32b. The connection portion 34 includes a portion that does not overlap the lead 15a in the view in the z direction. According to this modified example, the impedance of the connection portion 34 with respect to high-frequency components can be further increased. Also, when the lead 15a is joined, the liquefied conductive joining material 76 can be prevented from flowing along the connection portion 34 and connecting the pad 32a and the pad 32b. The shape of the connection portion 34 may be a more complex shape (for example, a zigzag shape). Note that when the distance between two pads 32 is sufficiently separated, such as between the pad 32c and the pad 32d (see FIG. 7), the pad 32e and the pad 32f (see FIG. 8), and the pad 32g and the pad 32h (see FIG. 9), there is no need to detour the path of the connection portion 34 or make it a complex shape as in this modified example.

[0079] FIGS. 15 to 18 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiments are denoted by the same reference numerals as in the above embodiments.

[0080] <Second Embodiment> FIG. 15 is a diagram for explaining a semiconductor device A2 according to the second embodiment of the present disclosure. FIG. 15 is a partially enlarged plan view showing the semiconductor device A2 and corresponds to FIGS. 6 to 9. Note that in FIG. 15, the sealing resin 8 is omitted. In the semiconductor device A2 of this embodiment, the arrangement position of the pad 32b and the shape of the lead 15a are different from those in the first embodiment.

[0081] In the semiconductor device A2 according to this embodiment, the arrangement position of the pad 32b is a position separated from the pad 32a in the x direction, and in the x direction, it is on the side opposite to the pad 32a with respect to the control device 5d. Further, the joint portion 151 of the lead 15a includes a first branched end portion 151f and a second branched end portion 151g that branch on the side opposite to the protruding portion 152. The pad 32a is joined to the first branched end portion 151f, and the pad 32b is joined to the second branched end portion 151g.

[0082] Also in this embodiment, a conductive portion 3 is formed on the substrate main surface 21 of the substrate 2, and the control device 5 is conductively joined to the pad 31 of the conductive portion 3. As a result, the conduction path to the control device 5 can be configured by the conductive portion 3 formed on the substrate main surface 21, so that it is possible to reduce the line width and increase the density of the conduction path. Further, the lead 15a is joined to both the pad 32a and the pad 32b via a conductive joining material 76. Thereby, transmission of noise between the pad 32a and the pad 32b via the conductive joining material 76 and the lead 15a is suppressed.

[0083] Further, according to this embodiment, the joint portion 151 of the lead 15a includes a first branched end portion 151f and a second branched end portion 151g that branch on the side opposite to the protruding portion 152, the pad 32a is joined to the first branched end portion 151f, and the pad 32b is joined to the second branched end portion 151g. The joint portion 151 is suitable for joining to the pads 32a and 32b that are arranged apart from each other.

[0084] <Third Embodiment> FIG. 16 is a diagram for explaining a semiconductor device A3 according to the third embodiment of the present disclosure. FIG. 16 is a simplified plan view showing the semiconductor device A3. In FIG. 16, only the members necessary for explaining the semiconductor device A3 are shown, and the description of other members is omitted. Also, the shapes and arrangements of the members described are simplified. The semiconductor device A3 of this embodiment is different from the first embodiment in that the lead 15 is joined to four pads 32.

[0085] In the semiconductor device A1 according to the first embodiment, the lead 15a is joined to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c, and the lead 15c is joined to the pad 32e electrically connected to the control device 5a and the pad 32f electrically connected to the control device 5b. That is, the four control devices 5 were connected to the two leads 15, two by two. On the other hand, in the semiconductor device A3 according to the third embodiment, the lead 15a is joined to the four pads 32 of the pads 32a, 32b, 32e, and 32f. That is, the four control devices 5 are connected to one lead 15a. In the present embodiment, the pad 32c or the pad 32d is an example of the "third pad". Note that the arrangement positions of the pads 32a, 32b, 32e, and 32f, and the shapes of the connection wirings 33 respectively connected to the pads 32a, 32b, 32e, and 32f are not limited, and are appropriately designed in accordance with the arrangements and shapes of the other pads 32, pads 31, and connection wirings 33. Further, the shape of the lead 15a is not limited, and is designed to have a shape corresponding to the arrangement of the pads 32a, 32b, 32e, and 32f. The substrate 2 may be a multilayer substrate, and a part of the connection wiring 33 may be arranged in a layer other than the substrate main surface 21.

[0086] Also in the present embodiment, the conductive portion 3 is formed on the substrate main surface 21 of the substrate 2, and the control device 5 is conductively joined to the pad 31 of the conductive portion 3. Thereby, since the conduction path to the control device 5 can be configured by the conductive portion 3 formed on the substrate main surface 21, it is possible to reduce the line width and increase the density of the conduction path. Further, the lead 15a is joined to the four pads 32 of the pads 32a, 32b, 32e, and 32f via the conductive joining materials 76, respectively. Thereby, the transmission of noise between the pads 32a, 32b, 32c, and 32d via the conductive joining materials 76 and the lead 15a is suppressed.

[0087] In the first embodiment, the case where one lead 15 is joined to two pads 32 and in the third embodiment, the case where one lead 15 is joined to four pads 32 have been described, but the present invention is not limited to this. Each lead 15 may be joined to three pads 32 or may be joined to five or more pads 32.

[0088] <Fourth Embodiment> FIG. 17 is a diagram for explaining a semiconductor device A4 according to a fourth embodiment of the present disclosure. FIG. 17 is a simplified plan view showing the semiconductor device A4. In FIG. 17, only the members necessary for explaining the semiconductor device A4 are shown, and the description of other members is omitted. Also, the shapes and arrangements of the members shown are simplified. The semiconductor device A4 of the present embodiment is different from the first embodiment in that the lead 15 is joined to two pads 32 that are electrically connected to different leads 53 of the same control device 5, respectively.

[0089] In the semiconductor device A1 according to the first embodiment, the lead 15a was joined to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c. That is, the lead 15a was connected to two control devices 5. On the other hand, in the semiconductor device A4 according to the fourth embodiment, the lead 15a is joined to the pads 32a and 32b electrically connected to different leads 53 of the control device 5d, respectively. That is, the lead 15a is connected to different leads 53 of the same control device 5. The pad 32a is electrically connected to the lead 53a, which is the analog power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. The pad 32b is electrically connected to the lead 53b, which is the digital power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. That is, the lead 15a is electrically connected to the analog power supply terminal and the digital power supply terminal of the control device 5d. Note that the arrangement positions of the pads 32a and 32b and the shape of the connection wiring 33 connected to the pads 32a and 32b are not limited, and are appropriately designed in accordance with the arrangements and shapes of the other pads 32, pads 31, and connection wiring 33. Further, the shape of the lead 15a is not limited, and is designed to have a shape corresponding to the arrangement of the pads 32a and 32b. The substrate 2 may be a multilayer substrate, and a part of the connection wiring 33 may be arranged in a layer other than the substrate main surface 21.

[0090] Also in this embodiment, the conductive portion 3 is formed on the substrate main surface 21 of the substrate 2, and the control device 5 is conductively joined to the pad 31 of the conductive portion 3. Thereby, since the conduction path to the control device 5 can be constituted by the conductive portion 3 formed on the substrate main surface 21, it is possible to reduce the line width and increase the density of the conduction path. Further, the lead 15a is joined to both the pad 32a and the pad 32b via the conductive joining material 76, respectively. Thereby, transmission of noise between the pad 32a and the pad 32b via the conductive joining material 76 and the lead 15a is suppressed.

[0091] In the present embodiment, the case where the pad 32a is electrically connected to the lead 53a which is an analog power supply terminal and the pad 32b is electrically connected to the lead 53b which is a digital power supply terminal has been described, but the present invention is not limited thereto. The pads 32a and 32b may be electrically connected to other leads 53. For example, the pad 32a may be electrically connected to the lead 53 which is an analog ground terminal, and the pad 32b may be electrically connected to the lead 53 which is a digital ground terminal.

[0092] <Fifth Embodiment> FIG. 18 is a diagram for explaining a semiconductor device A5 according to the fifth embodiment of the present disclosure. FIG. 18 is a simplified plan view showing the semiconductor device A5. In FIG. 18, only the members necessary for explaining the semiconductor device A5 are described, and the description of other members is omitted. Further, the shapes and arrangements of the described members are also simplified. The semiconductor device A5 of the present embodiment is different from the first embodiment in that one of the two pads 32 to which the lead 15 is joined is electrically connected to another lead 15.

[0093] In the semiconductor device A1 according to the first embodiment, the lead 15a was joined to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c. That is, the lead 15a was connected to two control devices 5. On the other hand, in the semiconductor device A5 according to the fifth embodiment, the pad 32b is electrically connected not to the control device 5 but to the lead 15e. That is, the lead 15a is connected to the control device 5d and the lead 15e. The pad 32a is electrically connected to the lead 53a, which is the analog power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. The pad 32b is electrically connected to the lead 15e via the connection wiring 33 and the pad 32i. The pad 32i is one of the plurality of pads 32 and is arranged adjacent to the pad 32b. The lead 15e is one of the plurality of leads 15 and is joined to the pad 32i via the conductive bonding material 76. That is, the lead 15a is electrically connected to the control device 5d and the lead 15e. In the present embodiment, the lead 15e is an example of the "second lead", and the pad 32b is an example of the "first pad". The lead 15e is connected to, for example, a capacitor outside the semiconductor device A5. The control device 5d of the semiconductor device A5 does not have a function of detecting the voltage of the analog power supply, and the voltage of the analog power supply input from the lead 15a cannot be detected inside the semiconductor device A5. However, by detecting the voltage between the terminals of the capacitor connected to the lead 15e that is electrically connected to the lead 15a, the voltage of the analog power supply can be detected outside the semiconductor device A5.

[0094] Also in the present embodiment, the conductive portion 3 is formed on the substrate main surface 21 of the substrate 2, and the control device 5 is conductively joined to the pad 31 of the conductive portion 3. Thereby, since the conduction path to the control device 5 can be constituted by the conductive portion 3 formed on the substrate main surface 21, it is possible to achieve thinning and high density of the conduction path. Further, the lead 15a is joined to both the pad 32a and the pad 32b via the conductive bonding material 76, respectively. Thereby, transmission of noise between the pad 32a and the pad 32b via the conductive bonding material 76 and the lead 15a is suppressed.

[0095] In the present embodiment, the case where the pad 32a is electrically connected to the control device 5d and the pad 32b is electrically connected to the pad 32i joined to the lead 15e has been described. However, the present invention is not limited to this. Any of the plurality of pads 32 to which the lead 15 is joined may be electrically connected only to the passive element 6 via the connection wiring 33 and the pad 31, or may be electrically connected to the pad 31 to which one end of the wire is joined via the connection wiring 33.

[0096] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed and changed in various ways.

[0097] Appendix 1. A substrate having a substrate front surface and a substrate back surface facing opposite sides in the thickness direction, A conductive part formed on the substrate front surface, A semiconductor chip disposed on the substrate front surface, A control device disposed on the substrate front surface and controlling the semiconductor chip, A sealing resin covering at least a part of the substrate, the semiconductor chip, the control device, and the conductive part, A conductive bonding material, A first lead joined to the conductive part via the conductive bonding material and having a part exposed from the sealing resin, and wherein the conductive part includes a first pad and a second pad disposed apart from each other, and the first lead is joined to the first pad and the second pad. A semiconductor device. Appendix 2. The conductive part further includes a connecting part connecting the first pad and the second pad, and the connecting part includes a portion having a smaller dimension in a direction orthogonal to the thickness direction as compared with the first pad and the second pad. The semiconductor device according to Appendix 1. Appendix 3. The semiconductor device according to Supplementary Note 2, wherein the connection portion has a higher impedance than the conduction path between the first pad and the second pad via the conductive bonding material and the first lead. Supplementary Note 4. The semiconductor device according to Supplementary Note 2 or 3, wherein the connection portion includes a portion that does not overlap with the first lead in a view in the thickness direction. Supplementary Note 5. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion. The bonding portion includes a wide portion located at an end portion opposite to the protruding portion. The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the first pad and the second pad are bonded to the wide portion. Supplementary Note 6. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion. The bonding portion includes a first end portion on the protruding portion side and a second end portion on the side opposite to the protruding portion. The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the first pad and the second pad are arranged side by side in a direction in which the first end portion and the second end portion are separated from each other. Supplementary Note 7. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion. The bonding portion includes a first branched end portion and a second branched end portion that branch on the side opposite to the protruding portion. The first pad is bonded to the first branched end portion. The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the second pad is bonded to the second branched end portion. Supplementary Note 8. The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first pad and the second pad are electrically connected to the control device. Supplementary Note 9. The first pad is electrically connected to the analog power supply terminal of the control device. The semiconductor device according to appended note 8, wherein the second pad is electrically connected to a digital power supply terminal of the control device. Appended note 10. Further comprising a second lead bonded to the conductive portion and partially exposed from the encapsulating resin, The semiconductor device according to any one of appended notes 1 to 7, wherein the first pad is electrically connected to the second lead. Appended note 11. A second semiconductor chip disposed on the main surface of the substrate, A second control device disposed on the main surface of the substrate and controlling the second semiconductor chip, Further comprising: The first pad is electrically connected to the control device, The semiconductor device according to any one of appended notes 1 to 7, wherein the second pad is electrically connected to the second control device. Appended note 12. The conductive portion further includes a third pad, The semiconductor device according to any one of appended notes 1 to 11, wherein the first lead is bonded to the third pad. Appended note 13. Further comprising a third lead disposed on the main surface of the substrate, having a higher thermal conductivity than the substrate, and partially exposed from the encapsulating resin, The semiconductor device according to any one of appended notes 1 to 12, wherein the semiconductor chip is disposed on the third lead. Appended note 14. Further comprising a bonding portion formed on the main surface of the substrate and including a conductive material constituting the conductive portion, The semiconductor device according to appended note 13, wherein the third lead is bonded to the bonding portion. Appended note 15. The semiconductor device according to any one of appended notes 1 to 14, wherein the semiconductor chip is a power transistor that controls power. Appended note 16. The semiconductor device according to any one of appended notes 1 to 15, wherein the semiconductor chip includes a back surface electrode bonded to the first lead. Supplementary Note 17. The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the back surface of the substrate is exposed from the encapsulating resin. Supplementary Note 18. The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the substrate is made of ceramic.

Explanation of Reference Numerals

[0098] A1, A2, A3, A4, A5: Semiconductor device 1, 11, 11a, 11b, 12, 12a, 12b: Lead 13, 13a, 13b, 14, 15, 15a to 15e: Lead 111: Joint portion 111a: Main surface 111b: Back surface 112: Protruding portion 113: Inclined connection portion 114: Parallel connection portion 151: Joint portion 151a: Main surface 151b: Back surface 151c: Wide portion 151d: First end portion 151e: Second end portion 151f: First branched end portion 151g: Second branched end portion 152: Protruding portion 153: Inclined connection portion 154: Parallel connection portion 2: Substrate 21: Substrate main surface 22: Substrate back surface 25, 251 to 254: Joint portion 3: Conductive portion 31: Pad 32, 32a to 32i: Pad 33: Connection wiring 34: Connection portion 4, 4a, 4b, 4c, 4d: Semiconductor chip 41: Element main surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5, 5a, 5b, 5c, 5d: Control device 53, 53a, 53b: Lead 6: Passive element 6a: Shunt resistor 71, 72: Wire 75: Bonding material 76: Conductive bonding material 8: Encapsulating resin 81: Resin main surface 82: Resin back surface 83: Resin side surface

Claims

1. a substrate having a substrate front surface and a substrate back surface facing opposite sides in the thickness direction; a conductive portion made of a conductive material formed on the substrate front surface; a semiconductor chip and a second semiconductor chip disposed on the substrate front surface; a control device disposed on the substrate front surface for controlling the semiconductor chip; a second control device disposed on the substrate front surface for controlling the second semiconductor chip; a sealing resin covering at least a part of the substrate, the semiconductor chip, the control device, and the conductive portion; a conductive bonding material; a first lead bonded to the conductive portion via the conductive bonding material and having a part exposed from the sealing resin; comprising; the conductive portion includes a first pad and a second pad disposed apart from each other; the first lead is bonded to the first pad and the second pad; the first pad is electrically connected to the control device; the second pad is electrically connected to the second control device; a semiconductor device.

2. a substrate having a substrate front surface and a substrate back surface facing opposite sides in the thickness direction; a conductive portion made of a conductive material formed on the substrate front surface; a semiconductor chip disposed on the substrate front surface; a control device disposed on the substrate front surface for controlling the semiconductor chip; a sealing resin covering at least a part of the substrate, the semiconductor chip, the control device, and the conductive portion; a conductive bonding material; a first lead bonded to the conductive portion via the conductive bonding material and having a part exposed from the sealing resin; comprising; the conductive portion includes a first pad and a second pad disposed apart from each other; the control device includes a first terminal and a second terminal; the first lead is bonded to the first pad and the second pad; the first pad and the second pad are electrically connected to the control device; the first pad is electrically connected to the first terminal; the second pad is electrically connected to the second terminal; a semiconductor device.

3. the first terminal is an analog power supply terminal; the second terminal is a digital power supply terminal, the semiconductor device according to claim 2.

4. a substrate having a substrate front surface and a substrate back surface facing opposite sides in the thickness direction; a conductive portion made of a conductive material formed on the substrate front surface; a semiconductor chip disposed on the substrate front surface; A control device that is disposed on the main surface of the substrate and controls the semiconductor chip; At least a part of the substrate, a sealing resin that covers the semiconductor chip, the control device, and the conductive portion; A conductive bonding material; A first lead that is bonded to the conductive portion via the conductive bonding material and a part of which is exposed from the sealing resin; A second lead that is bonded to the conductive portion and a part of which is exposed from the sealing resin; Comprising; The conductive portion includes a first pad and a second pad that are spaced apart from each other; The first lead is bonded to the first pad and the second pad; The first pad is electrically connected to the second lead; A semiconductor device.

5. The conductive portion further includes a connection portion that connects the first pad and the second pad, The semiconductor device according to any one of claims 1 to 4, wherein the connection portion includes a portion having a smaller dimension in a direction orthogonal to the thickness direction as compared with the first pad and the second pad.

6. The semiconductor device according to claim 5, wherein the impedance of the connection portion is higher than that of a conduction path between the first pad and the second pad via the conductive bonding material and the first lead.

7. The semiconductor device according to claim 5 or 6, wherein the connection portion includes a portion that does not overlap the first lead in a view in the thickness direction.

8. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion, The bonding portion includes a wide portion located at an end opposite to the protruding portion, The semiconductor device according to any one of claims 1 to 7, wherein the first pad and the second pad are bonded to the wide portion.

9. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion, The bonding portion includes a first end portion on the protruding portion side and a second end portion on the side opposite to the protruding portion, The semiconductor device according to any one of claims 1 to 7, wherein the first pad and the second pad are arranged side by side in a direction in which the first end portion and the second end portion are spaced apart from each other.

10. The first lead is strip-shaped and includes a protruding portion that protrudes and extends from the sealing resin, and a bonding portion that is bonded to the conductive portion, The bonding portion includes a first branched end portion and a second branched end portion that are branched on the side opposite to the protruding portion, The first pad is joined to the first branch end, The second pad is joined to the second branch end. The semiconductor device according to any one of claims 1 to 7. **Claim 11** The conductive portion further includes a third pad, The first lead is joined to the third pad. The semiconductor device according to any one of claims 1 to 10. **Claim 12** Further provided with a third lead disposed on the main surface of the substrate, having a higher thermal conductivity than the substrate, and a part of which is exposed from the encapsulating resin, The semiconductor chip is disposed on the third lead. The semiconductor device according to any one of claims 1 to 11. **Claim 13** Further provided with a joint portion formed on the main surface of the substrate and including a conductive material constituting the conductive portion, The third lead is joined to the joint portion. The semiconductor device according to claim 12. **Claim 14** The semiconductor chip is a power transistor that controls power. The semiconductor device according to any one of claims 1 to 13. **Claim 15** The semiconductor chip includes a back surface electrode joined to the first lead. The semiconductor device according to any one of claims 1 to 14. **Claim 16** The back surface of the substrate is exposed from the encapsulating resin. The semiconductor device according to any one of claims 1 to 15. **Claim 17** The substrate is made of ceramic. The semiconductor device according to any one of claims 1 to 16.

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