Electronic circuit

Abstract

[Problem] To realize a switched resistor having a small circuit area and low power consumption. [Solution] This electronic circuit comprises a differential signal output circuit that outputs a differential signal. The differential signal output circuit has a first output terminal, a second output terminal, a first switch, a second switch, a third switch, a fourth switch, and a short switch. The first output terminal and the second output terminal output signals. The first switch connects between the first output terminal and a first power supply. The second switch connects between the second output terminal and a second power supply. The third switch connects between the first output terminal and the second power supply. The fourth switch connects between the second output terminal and the first power supply. The short switch connects between the first output terminal and the second output terminal.

Description

[Technical Field]

[0001] The present disclosure relates to electronic circuits. [Background technology]

[0002] Conventionally, a typical switched register configuration operates in a binary fashion, with each switch operating in a counter-intuitive manner. In this binary operation, the resistor in the DAC (Digital to Analog Converter) is connected to either the positive or negative power supply, resulting in a constant current flow and increased power consumption. One method involves providing a switch in the downstream operational amplifier to short-circuit the input differential and separate it from the upstream current source and DAC, but this method requires, for example, a sample-and-hold circuit to sample the input voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-160990 Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, the present disclosure provides an electronic circuit including a switched resistor that has a small circuit area and consumes small power.

[0005] According to one embodiment, an electronic circuit includes a differential signal output circuit that outputs a differential signal. The differential signal output circuit includes a first output terminal, a second output terminal, a first switch, a second switch, a third switch, a fourth switch, and a short switch. The first output terminal and the second output terminal output signals. The first switch is connected between the first output terminal and a first power supply. The second switch is connected between the second output terminal and a second power supply. The third switch is connected between the first output terminal and the second power supply. The fourth switch is connected between the second output terminal and the first power supply. The short switch is connected between the first output terminal and the second output terminal.

[0006] The first switch and the second switch may be MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) having the same polarity, and their gates may be connected to each other. Also, the third switch and the fourth switch may be MOSFETs having the same polarity, and their gates may be connected to each other. Not limited to this, each switch can also be replaced with a circuit that operates as various switches.

[0007] It may further include a first resistor having a first terminal connected to the first switch and the third switch and a second terminal connected to the first output terminal, and a second resistor having a first terminal connected to the second switch and the fourth switch and a second terminal connected to the second output terminal, and the short switch may be connected between the first terminal of the first resistor and the first terminal of the second resistor.

[0008] It may further include a bias terminal for applying a bias voltage, and the short switch may include a fifth switch connected between the first terminal of the first resistor and the bias terminal, and a sixth switch connected between the first terminal of the second resistor and the bias terminal.

[0009] The fifth switch and the sixth switch may be MOSFETs having the same polarity, and their gates may be connected to each other.

[0010] The bias terminal may be grounded.

[0011] The circuit may further include a seventh switch connected to the bias terminal, and the bias terminal may be grounded via the seventh switch.

[0012] The power supply may further include a seventh switch connected to the bias terminal, and the bias terminal may be connected to a bias voltage via the seventh switch.

[0013] The first power supply, the first switch, and the fourth switch may be connected via a third resistor, and the second power supply, the second switch, and the third switch may be connected via a fourth resistor.

[0014] The short switch may further include a bias terminal that applies a bias voltage, and the short switch may include a fifth switch connected between the bias terminal and the first terminal via a fifth resistor, and a sixth switch connected between the bias terminal and the second terminal via a sixth resistor.

[0015] The fifth switch and the sixth switch may be MOSFETs having the same polarity, and their gates may be connected to each other.

[0016] The bias terminal may be grounded.

[0017] The circuit may further include a seventh switch connected to the bias terminal, and the bias terminal may be grounded via the seventh switch.

[0018] The power supply may further include a seventh switch connected to the bias terminal, and the bias terminal may be connected to a bias voltage via the seventh switch.

[0019] The first switch and the second switch may operate in synchronization, and the third switch and the fourth switch may operate in synchronization with the first switch and the second switch so as not to be turned on at the same timing.

[0020] The fifth switch and the sixth switch may operate in synchronization.

[0021] The short switch and the seventh switch may be exclusively controlled.

[0022] The first switch, the second switch, the third switch, the fourth switch, and the short switch may be controlled by a ternary input signal.

[0023] The input signal may have three values indicating a first state in which the first switch and the second switch are on, the third switch and the fourth switch are off, and the short switch is off; a second state in which the first switch, the second switch, the third switch, and the fourth switch are off, and the short switch is on; and a third state in which the first switch and the second switch are off, the third switch and the fourth switch are on, and the short switch is off.

[0024] The differential signal output circuit may include a plurality of the differential signal output circuits, the first output terminals of the plurality of differential signal output circuits being connected to each other, the second output terminals of the plurality of differential signal output circuits being connected to each other, and the first output terminal and the second output terminal being connected to an inverting input terminal and a non-inverting input terminal of a differential amplifier, respectively.

[0025] The plurality of differential signal output circuits may output signals corresponding to multiple bits. [Brief explanation of the drawings]

[0026] [Figure 1]Circuit diagram of an electronic circuit according to an embodiment. [Figure 2] Timing chart of a switch according to an embodiment. [Figure 3] Circuit diagram showing an example of a switch of an electronic circuit according to an embodiment. [Figure 4] Circuit diagram showing an example of a switch of an electronic circuit according to an embodiment. [Figure 5] Circuit diagram showing an example of a switch of an electronic circuit according to an embodiment. [Figure 6] Circuit diagram of an electronic circuit according to an embodiment. [Figure 7] Circuit diagram of an electronic circuit according to an embodiment. [Figure 8] Timing chart of a switch according to an embodiment. [Figure 9] Circuit diagram of an electronic circuit according to an embodiment. [Figure 10] Circuit diagram of an electronic circuit according to an embodiment. [Figure 11] Circuit diagram of an electronic circuit according to an embodiment. [Figure 12] Circuit diagram showing an example of an encoder. [Figure 13] Circuit diagram showing another example of an encoder. [Figure 14] Diagram showing the truth table of the encoder of FIG. 13.

Mode for Carrying Out the Invention

[0027] Hereinafter, embodiments in the present disclosure will be described with reference to the drawings. The drawings are for illustrative purposes only, and the shapes, sizes of each part in the actual device, or the size ratios with other configurations do not have to be as shown in the drawings. Also, since the drawings are drawn in a simplified manner, configurations necessary for implementation other than those shown in the drawings shall be appropriately provided.

[0028] [[ID=5*]](First Embodiment) FIG. 1 shows a circuit diagram of an electronic circuit according to an embodiment. The electronic circuit 1 includes a differential signal output circuit 10 and a differential amplifier 20.

[0029] The differential signal output circuit 10 includes an input terminal IN, a first output terminal VP and a second output terminal VN and a bias input terminal VB, and includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a first resistor R1, and a second resistor R2.

[0030] The differential signal output circuit 10 is appropriately connected to a first power supply and a second power supply that output a first voltage Vrefp and a second voltage Vrefn, respectively. These power supplies may be, for example, power supplies shared with the differential amplifier 20.

[0031] The differential signal output circuit 10 generates a differential signal based on a digital signal encoded in three values and outputs this differential signal to an external differential amplifier 20. The differential signal output circuit 10 is a circuit that operates as a DAC that converts an encoded single-bit digital signal into an analog signal based on the first voltage Vrefp and the second voltage Vrefn.

[0032] The first switch SW1 is connected between the first power supply and the first output terminal VP via the first resistor R1. When the first switch SW1 is in the on state, it connects the first power supply and the first output terminal VP via the first resistor R1, and when it is in the off state, it releases this connection.

[0033] The second switch SW2 is connected between the second power supply and the second output terminal VN via the second resistor R2. When the second switch SW2 is in the on state, it connects the second power supply and the second output terminal VN via the second resistor R2, and when it is in the off state, it releases this connection.

[0034] The third switch SW3 is connected between the second power supply and the first output terminal VP via the first resistor R1. When the third switch SW3 is in the on state, it connects the second power supply and the first output terminal VP via the first resistor R1, and when it is in the off state, it releases this connection.

[0035] The fourth switch SW4 is connected between the first power supply and the second output terminal VN via the second resistor R2. When the fourth switch SW4 is in the on state, it connects the first power supply and the second output terminal VN via the second resistor R2, and when it is in the off state, it releases this connection.

[0036] The fifth switch SW5 is connected between the bias input terminal VB and the first output terminal VP via the first resistor R1. When the fifth switch SW5 is in the on state, it connects the bias input terminal VB and the first output terminal VP via the first resistor R1, and when it is in the off state, it releases this connection.

[0037] The sixth switch SW6 is connected between the bias input terminal VB and the second output terminal VN via the second resistor R2. When the sixth switch SW6 is in the on state, it connects the bias input terminal VB and the second output terminal VN via the second resistor R2, and when it is in the off state, it releases this connection.

[0038] The fifth switch SW5 and the sixth switch SW6 are switches that short-circuit the first output terminal VP and the second output terminal VN (via a resistor), and in the present disclosure, these two switches may be collectively referred to as a short switch.

[0039] One end of the first resistor R1 is connected to the first switch SW1, the third switch SW3, and the fifth switch SW5, and the other end is connected to the first output terminal VP.

[0040] One end of the second resistor R2 is connected to the second switch SW2, the fourth switch SW4, and the sixth switch SW6, and the other end is connected to the second output terminal VN. The second resistor R2 may have, for example, the same resistance value as the first resistor R1.

[0041] For example, a binary digital signal is encoded and a signal changed to ternary is input to the input terminal IN. Based on the encoded signal input to the input terminal IN, the states of the above-mentioned switches are switched.

[0042] The first output terminal VP and the second output terminal VN are connected to the non-inverting input terminal and the inverting input terminal of the differential amplifier 20 outside, respectively.

[0043] The bias input terminal VB is a terminal for inputting a bias voltage applied at the node when the first output terminal VP and the second output terminal VN are short-circuited by the fifth switch SW5 and the sixth switch SW6. In the present embodiment, for example, the bias input terminal VB is connected to the ground voltage. More specifically, a voltage equal to (equivalent to) the common voltage of the fully differential amplifier (differential amplifier 20) is applied to the bias input terminal VB.

[0044] The differential amplifier 20 includes impedances between the non-inverting input terminal and the inverting output terminal, and between the inverting input terminal and the non-inverting output terminal, respectively. When the differential signal output from the differential signal output circuit 10 is input, the differential amplifier 20 amplifies and outputs the differential signal. The output is connected to, for example, the differential resistance of an audio speaker.

[0045] While explaining the operation of the differential signal output circuit 10 of this electronic circuit 1, a more detailed configuration will also be described.

[0046] FIG. 2 is a timing chart showing the relationship between the signals input to the differential signal output circuit 10 and the states of the respective switches. Although it is a timing chart, it is shown clearly for the sake of explanation, and the actual time when each signal is input and the period in this figure do not have a proportional relationship. That is, for example, the period of "0" shown in FIG. 2 may be a shorter period than other periods.

[0047] From the upper row, the encoded signal, that is, the state of the input signal, the states of the first switch SW1 and the second switch SW2, the states of the fifth switch SW5 and the sixth switch SW6, and the states of the third switch SW3 and the fourth switch SW4 are shown. As shown in the lowermost row, depending on the state of the input signal, it will be described below as the first state, the second state, and the third state.

[0048] When the encoded signal is +1, that is, in the first state, the first switch SW1 and the second switch SW2 are on, the fifth switch SW5 and the sixth switch SW6 are off, and the third switch SW3 and the fourth switch SW4 are off.

[0049] 3 is a diagram showing the connection state of the differential signal output circuit 10 in the first state described above. Solid lines indicate connected paths, and dotted lines indicate unconnected paths. In the first state, the first power supply is connected to the first output terminal VP via the first resistor R1, and the second power supply is connected to the second output terminal VN via the second resistor R2.

[0050] As a result, when a signal of +1 is input, for example, a first voltage on the positive side is input to the non-inverting terminal of the differential amplifier 20 as an analog signal via the first resistor R1, and a second voltage on the negative side is input to the inverting terminal as an analog signal via the second resistor R2.

[0051] For example, if the input digital signal is +1, it is converted by the encoder into a signal of +1. As a result, when the digital input is +1, the differential signal output circuit 10 outputs a signal whose positive and negative polarities are not inverted to the differential amplifier 20.

[0052] Next, when the encoded signal is 0, i.e., in the second state, as shown in FIG. 2, the first switch SW1 and the second switch SW2 are off, the fifth switch SW5 and the sixth switch SW6 are on, and the third switch SW3 and the fourth switch SW4 are off.

[0053] 4 is a diagram showing the connection state of the differential signal output circuit 10 in the second state described above. As in FIG. 3, solid lines indicate connected paths and dotted lines indicate unconnected paths. In the second state, the first power supply and the second power supply are disconnected by the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4.

[0054] On the one hand, when the fifth switch SW5 and the sixth switch SW6 are turned on, the first output terminal VP and the second output terminal VN are short-circuited via the first resistor R1 and the second resistor R2. Also, the first output terminal VP and the second output terminal VN become a common voltage designed by the operation of the differential amplifier 20. And a voltage equivalent to the common voltage of the differential amplifier 20 is applied to the connection node of the fifth switch SW5 and the sixth switch SW6 via the bias input terminal VB. For example, when the common voltage of the differential amplifier 20 is set to the ground voltage, the configuration as shown in FIG. 4 becomes effective.

[0055] The input digital signal is converted into a signal of 0 by the encoder when, for example, it switches from +1 to 0, or from 0 to +1, or when there is no digital signal input. From this, at the timing when the digital input switches or when there is no digital input, the differential signal output circuit 10 shorts the first output terminal VP and the second output terminal VN. In other words, in this case, by short-circuiting the input terminals of the differential amplifier 20 and disconnecting them from the power supply, unnecessary power consumption is suppressed. That is, in a state where signal output is unnecessary, by encoding the signal input to the input terminal IN as 0 for as long as possible, the power consumption reduction effect can be increased.

[0056] Next, when the encoded signal is -1, that is, in the third state, as shown in FIG. 2, the first switch SW1 and the second switch SW2 are off, the fifth switch SW5 and the sixth switch SW6 are off, and the third switch SW3 and the fourth switch SW4 are on.

[0057] FIG. 5 is a diagram showing the connection state of the differential signal output circuit 10 in the above-described third state. Similar to FIG. 3, solid lines indicate connected paths and dotted lines indicate unconnected paths. In the third state, the first power supply is connected to the second output terminal VN via the second resistor R2, and the second power supply is connected to the first output terminal VP via the first resistor R1.

[0058] As a result, when a signal of -1 is input, for example, a first positive voltage is input to the inverting terminal of the differential amplifier 20 as an analog signal via a first resistor R1, and a second negative voltage is input to the non-inverting terminal as an analog signal via a second resistor R2.

[0059] For example, if the input digital signal is 0, it is converted by the encoder into a signal of −1. As a result, when the digital input is 0, the differential signal output circuit 10 outputs a signal whose positive and negative polarities are inverted to the differential amplifier 20.

[0060] To summarize these results, the differential signal output circuit 10 outputs an analog signal with no polarity reversal when the digital input is 1, and outputs an analog signal with polarity reversal when the digital input is 0. Furthermore, when there is no switching or input, the output terminals are short-circuited.

[0061] Each switch may be configured, for example, by a metal-oxide-semiconductor field-effect transistor (MOSFET). The characteristics of this MOSFET may be set in any way as long as the above switching operation is properly realized.

[0062] On the other hand, the first switch SW1 and the second switch SW2 operate in synchronization, the third switch SW3 and the fourth switch SW4 operate in synchronization, and the fifth switch SW5 and the sixth switch SW6 operate in synchronization. For this reason, for example, the first switch SW1 and the second switch SW2 may be provided as MOSFETs of the same polarity (n-type / p-type), with their gates connected to each other. Similarly, the third switch SW3 and the fourth switch SW4, and the fifth switch SW5 and the sixth switch SW6 may also be configured with the same polarity and their gates connected to each other.

[0063] The configuration of the switch is not limited to a MOSFET, and may be, for example, a bipolar transistor that can perform the same operation.

[0064] As described above, the differential signal output circuit 10 operates as a DAC that appropriately converts a digital signal into an analog signal and outputs it. At the timing of digital signal switching or when no digital signal is being input, the differential amplifier 20 is disconnected from the power supply voltage, thereby preventing the generation of excess signal current and reducing power consumption (current consumption).

[0065] Furthermore, by switching the switch in this second state, it is possible to maintain the feedback ratio of the differential amplifier 20 at a predetermined value, and to suppress changes in the feedback ratio that depend on the input data. This is a particularly effective characteristic when a differential signal output circuit 10 is provided in parallel as shown in FIG. 11, which will be described later.

[0066] Furthermore, since the switches in the differential signal output circuit 10 transition states appropriately based on the timing of signal switching, even when part of the circuit, for example, the differential amplifier 20, is disconnected, a sample-and-hold circuit or the like that holds the voltage is not required.

[0067] The differential signal output circuit 10 according to this embodiment may be configured as a circuit that outputs a differential signal to be output to an audio amplifier, for example.

[0068] (Second embodiment) 6 is a circuit diagram showing an electronic circuit 1 according to a second embodiment. The differential signal output circuit 10 is configured such that the fifth switch SW5 and the sixth switch SW6, i.e., the short switches, are not connected to the bias input terminal VB.

[0069] In this case, the short switch does not have to be configured with two switches, the fifth switch SW5 and the sixth switch SW6, but can be replaced by a single switch. The operation is the same as in the first embodiment. That is, the state of each switch is switched depending on the input ternary signal, and the connection state of the circuit transitions in the same way as in Figures 3 to 5.

[0070] Since the connection node of the bias voltage and the fifth switch SW5 and the sixth switch SW6 is not connected, the potential between the output terminals cannot be set to a predetermined value. On the other hand, compared with the above-described embodiment, for example, one short switch can be reduced, and furthermore, extra wiring for connecting to the bias voltage can be removed, so that it is possible to reduce the installation area and suppress effects such as parasitics in the switch.

[0071] (Third Embodiment) FIG. 7 is a circuit diagram showing the electronic circuit 1 according to the third embodiment. The differential signal output circuit 10 is the same as that in the first embodiment in terms of the point grounded at the connection node of the fifth switch SW5 and the sixth switch SW6, but includes a seventh switch SW7 between this connection node and the ground point.

[0072] FIG. 8 is a diagram showing each state according to the present embodiment and the states of the respective switches. As shown in FIG. 8, the seventh switch SW7 operates so as to be in a state opposite to that of the fifth switch SW5 and the sixth switch SW6.

[0073] In the first state and the third state, the fifth switch SW5 and the sixth switch SW6 are turned off, while the seventh switch SW7 is turned on. On the other hand, in the second state, the seventh switch SW7 is turned off. Thus, a configuration may be adopted in which a switch is provided between the bias input terminal VB and an external potential.

[0074] For example, when a plurality of differential signal output circuits 10 are provided in parallel as shown in FIG. 11 described later, by operating the seventh switch SW7 in a state opposite to that of the fifth switch SW5 and the sixth switch SW6, the influence from other differential signal output circuits 10 can be reduced.

[0075] That is, when the seventh switch SW7 is on, the floating voltage between the fifth switch SW5 and the sixth switch SW6 is connected to the bias input terminal VB, and thus becomes the bias voltage, which is the ground voltage in this embodiment. When the second state is reached, when the seventh switch SW7 is turned off, the potential between the output terminals transitions to an appropriate voltage with reference to the ground voltage (more specifically, the common voltage of the differential amplifier 20).

[0076] This voltage transition has little impact on other circuits (such as the differential signal output circuit 10) because the seventh switch SW7 is off. Similarly, it is also less affected by other circuits.

[0077] As described above, according to this embodiment, the DAC operates in the same manner as in the previous embodiments, and it is possible to reduce the impact on other circuits and the influence from other circuits.

[0078] Note that the seventh switch SW7 is provided outside the differential signal output circuit 10 in the drawing, but it may also be provided inside the differential signal output circuit 10.

[0079] (Fourth Embodiment) FIG. 9 is a circuit diagram showing the electronic circuit 1 according to the fourth embodiment. The electronic circuit 1 further includes an amplifier 30 connected to the bias input terminal VB in addition to the configuration of the previous embodiments. As shown in this figure, a voltage having a predetermined voltage value other than the ground potential may be connected as the bias voltage. When the common voltage of the differential amplifier 20 does not match the ground voltage, the differential signal output circuit 10 is preferably configured to be connected to a power supply that applies a bias voltage equivalent to such a differential amplifier 20.

[0080] The amplifier 30 is, for example, a circuit that outputs a predetermined voltage (preferably, the same voltage as the common voltage of the differential amplifier 20) between the first voltage Vrefp and the second voltage Vrefn. This amplifier 30 is connected, for example, to the node between the fifth switch SW5 and the sixth switch SW6 via the seventh switch SW7. The switching of each switch is the same as that shown in FIG. 8.

[0081] By being connected in this way, it becomes possible to more appropriately set the floating voltage between the first output terminal VP and the second output terminal VN in the second state. The description of the amplifier is given as an example, and instead of an amplifier, a predetermined voltage source may be connected.

[0082] In this embodiment, the amplifier 30 is shown as being connected via the seventh switch SW7, but this is shown as an example. The amplifier 30 may be in a state where it is connected to the connection node between the fifth switch SW5 and the sixth switch SW6 without passing through a switch, for example, connected as shown in FIG. 1. Also in the following embodiments, the presence or absence of this seventh switch SW7 is not similarly restricted by the description of the embodiment itself, and it can be appropriately selected whether to install it or not.

[0083] (Fifth Embodiment) In each of the above-described embodiments, a resistor was always connected to the output terminal, but these configurations are not limited thereto.

[0084] FIG. 10 is a circuit diagram showing the electronic circuit 1 according to the fifth embodiment. The differential signal output circuit 10 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 instead of the first resistor R1 and the second resistor R2.

[0085] The third resistor R3 is connected between the first power supply and the first switch SW1 and the fourth switch SW4.

[0086] The fourth resistor R4 is connected between the second power supply and the second switch SW2 and the third switch SW3.

[0087] By providing the third resistor R3 and the fourth resistor R4 in this way, it is possible to perform operations equivalent to those of the above-described embodiments in the first and third states.

[0088] The fifth resistor R5 is connected between the fifth switch SW5 and the first output terminal VP, the first switch SW1, and the third switch SW3.

[0089] The sixth resistor R6 is connected between the sixth switch SW6 and the second output terminal VN, the second switch SW2, and the fourth switch SW4.

[0090] By providing the fifth resistor R5 and the sixth resistor R6 in this way, it is possible to perform the same operation as in the above-described embodiments in the second state.

[0091] The third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 may be resistors having the same resistance value, for example.

[0092] As described above, the position of the resistor is not limited to the position in the above-described embodiment, and may be set at a different position as in this embodiment.

[0093] (Implementation example) For example, a plurality of differential signal output circuits 10 in each of the above-described embodiments may be provided in parallel. By using the differential signal output circuits 10 operating as a plurality of DACs in this manner, the electronic circuit 1 can operate as an amplifier equipped with a DAC that supports multi-bits.

[0094] FIG. 11 is a diagram showing the configuration of an electronic circuit 1 according to an embodiment.

[0095] The electronic circuit 1 includes a plurality of differential signal output circuits 10A, 10B, 10C, . . . , 10X, and 10Y. Each differential signal output circuit 10 is connected to an encoder 40 and receives an input signal coded into ternary values from the encoder 40. Each differential signal output circuit 10 generates an analog signal based on the signal input from the encoder 40 and outputs this analog signal to a differential amplifier 20.

[0096] Each differential signal output circuit 10 has any of the configurations of the differential signal output circuits 10 described in the above-mentioned embodiments. Each differential signal output circuit 10 may operate as a DAC corresponding to each bit.

[0097] For example, the encoder 40 may receive a multiplexed signal for controlling appropriate outputs for each DAC, and the encoder 40 may output a multiplexed signal for outputting a coded signal for each DAC.

[0098] In this way, it is possible to appropriately convert a multi-bit digital signal into an analog signal by providing a plurality of differential signal output circuits 10. By using the differential signal output circuit 10 according to each of the above-described embodiments, the effects described in each embodiment can be achieved.

[0099] (Encoder example) Although the gist of this disclosure is the DAC using a ternary signal in each of the above-described embodiments, for reference, an example of an encoder circuit that generates a ternary signal from a digital signal will be described. Note that this circuit is shown as an example, and other circuits may be used as long as they can properly obtain a ternary signal. The above-described embodiments are not restricted by this description.

[0100] Fig. 12 is a circuit diagram showing an example of a circuit for converting a binary signal into a ternary signal. An input signal P is a binary signal, taking the value of 0 or 1. In the explanation of Fig. 12 and Fig. 13 described later, encoding of a signal for one DAC will be explained. If necessary, the same number of encoders as the number of DACs are provided.

[0101] The AND circuit receives the negation of signal P and the negation of signal P via a delay circuit. This output is signal Q. The exclusive OR circuit receives the negation of signal P and the negation of signal P via a delay circuit. This output is signal R.

[0102] The encoder outputs signals with Q and R in the ones and tens digits, respectively. If this 2-bit signal RQ is expressed in two's complement notation, it can be made to correspond to the states shown in Figures 2 and 8.

[0103] If P is in the steady state of 0, then Q = (not P) and (not P) = 1 and 1 = 1, and R = P exor (not P) = 0 exor 1 = 1, which is encoded as RQ = (11)2 = -1.

[0104] When P rises from 0 to 1, before the delay circuit outputs the negation of P, Q = (not P) and (not P') = 0 and 1 = 0, R = P exor (not P') = 1 exor 1 = 0, and is encoded as RQ = (00)2 = 0. Here, P' is the state of P before the transition.

[0105] If P is in the steady state of 1, then Q = 0 and 0 = 0, R = 1 exor 0 = 1, which is encoded as RQ = (01)2 = +1.

[0106] When P falls from 1 to 0, before the delay circuit outputs the negation of P, Q = 1 and 0, R = 0 exor 0 = 0, and this is encoded as RQ = (00)2 = 0.

[0107] That is, the 0 and 1 states of P are encoded as -1 and +1, respectively, and the rising and falling timings are encoded as 0. In this manner, the input signal of the differential signal output circuit 10 of the present disclosure can be generated.

[0108] Also, if the signal value of P is lower than the reference voltage of 0, for example, if there is no input to P, it may output 0. This can be achieved by cutting off the power supply to each logic gate, so that 0 is output to Q and R.

[0109] Such an encoder circuit may be provided in the encoder 40 of FIG. 11 to generate input signals for the differential signal output circuit 10 corresponding to each bit.

[0110] 13 is a diagram showing another example of an encoder. Signals P and N, which indicate two values, positive and negative, are input to the encoder. The signals P and N are, for example, signals that are prohibited from being 1 at the same time.

[0111] A NOR circuit receives inputs P and N and outputs Q. An encoder, for example, has two AND circuits, one of which receives inputs of the negation of P and N and outputs R. The other of which receives inputs of the negation of P and N and outputs S.

[0112] FIG. 14 shows a truth table for the logic circuit shown in FIG.

[0113] If both P and N are 0, then the output is Q = not (P or N) = not (0 or 0) = 1, R = (not P) and N = (not 0) and 0 = 0, S = P and (not N) = 0 and (not 0) = 0. This state corresponds to the 0 in the encoded signal, e.g., in FIG. 2.

[0114] If P is 0 and N is 1, then the output is Q = not (0 or 1) = 0, R = (not 0) and 1 = 1, and S = 0 and (not 1) = 0. This state corresponds, for example, to +1 in the encoded signal.

[0115] If P is 1 and N is 0, then the output is Q = not (1 or 0) = 0, R = (not 1) and 0 = 0, and S = 1 and (not 0) = 1. This state corresponds, for example, to -1 in the encoded signal.

[0116] Considering this output, for example, by connecting output Q to the fifth switch SW5 and sixth switch SW6 of each DAC, output R to the first switch SW1 and second switch SW2 of each DAC, and output S to the third switch SW3 and fourth switch SW4 of each DAC, it is possible to match the encoding to three values with the switching of each switch in the DAC.

[0117] Compared to the example in Figure 12, the electronic circuit 1 that controls the DAC does not require a signal to decode the encoded signal. On the other hand, a circuit is required to propagate the high / low states of the three signals. These can be selected appropriately in consideration of the circuit connection area, parasitic capacitance, etc.

[0118] However, these encoders are merely given as examples and do not affect the configuration of the electronic circuit 1 in this disclosure. In other words, the encoder can be arbitrarily selected from among those shown above in order to obtain appropriate input and output.

[0119] The above-described embodiment may be modified as follows.

[0120] (1) A differential signal output circuit that outputs a differential signal, a first output terminal for outputting a signal; a second output terminal for outputting a differential signal of the first output terminal; a first switch connected between the first output terminal and a first power supply; a second switch connected between the second output terminal and a second power supply; a third switch connected between the first output terminal and the second power supply; a fourth switch connected between the second output terminal and the first power supply; a short switch connected between the first output terminal and the second output terminal; a differential signal output circuit having An electronic circuit comprising:

[0121] (2) the first switch and the second switch are MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) having the same polarity, and their gates are connected to each other; the third switch and the fourth switch are MOSFETs having the same polarity, and their gates are connected to each other; (1) The electronic circuit according to (1).

[0122] (3) a first resistor having a first terminal connected to the first switch and the third switch and a second terminal connected to the first output terminal; a second resistor having a first terminal connected to the second switch and the fourth switch and a second terminal connected to the second output terminal; Equipped with the short switch is connected between the first terminal of the first resistor and the first terminal of the second resistor; The electronic circuit according to (1) or (2)

[0123] (4) a bias terminal for applying a bias voltage; Furthermore, The short switch is A fifth switch connected between the first terminal of the first resistor and the bias terminal; A sixth switch connected between the first terminal of the second resistor and the bias terminal; Comprising; The electronic circuit according to (3).

[0124] (5) The fifth switch and the sixth switch are MOSFETs having the same polarity, and their gates are connected to each other. The electronic circuit according to (4).

[0125] (6) The bias terminal is grounded. The electronic circuit according to (4) or (5).

[0126] (7) A seventh switch connected to the bias terminal; Further comprising; The bias terminal is grounded via the seventh switch. The electronic circuit according to (4) or (5).

[0127] (8) A seventh switch connected to the bias terminal; Further comprising; The bias terminal is connected to a bias voltage via the seventh switch. The electronic circuit according to (4) or (5).

[0128] (9) The first power supply, the first switch and the fourth switch are connected via a third resistor; The second power supply, the second switch and the third switch are connected via a fourth resistor. The electronic circuit according to (1) or (2).

[0129] (10) A bias terminal for applying a bias voltage; Further comprising; The short switch is a fifth switch connected between the bias terminal and the first terminal via a fifth resistor, a sixth switch connected between the bias terminal and the second terminal via a sixth resistor, and includes the electronic circuit according to (9).

[0130] (11) The fifth switch and the sixth switch are MOSFETs having the same polarity, and their gates are connected to each other. the electronic circuit according to (4).

[0131] (12) The bias terminal is grounded. the electronic circuit according to (4) or (5).

[0132] (13) a seventh switch connected to the bias terminal, further includes The bias terminal is grounded via the seventh switch. the electronic circuit according to (4) or (5).

[0133] (14) a seventh switch connected to the bias terminal, further includes The bias terminal is connected to a bias voltage via the seventh switch. the electronic circuit according to (4) or (5).

[0134] (15) The first switch and the second switch operate synchronously. The third switch and the fourth switch operate synchronously so as not to turn on at the same timing as the first switch and the second switch. the electronic circuit according to any one of (1) to (14).

[0135] (16) The fifth switch and the sixth switch operate in synchronization. The electronic circuit according to (4) or (10).

[0136] (17) The short switch and the seventh switch are exclusively controlled. An electronic circuit according to any one of (7), (8), (12), and (13).

[0137] (18) the first switch, the second switch, the third switch, the fourth switch, and the short switch are controlled by a ternary input signal; An electronic circuit according to any one of (1) to (17).

[0138] (19) The input signal is a first state in which the first switch and the second switch are turned on, the third switch and the fourth switch are turned off, and the short switch is turned off; a second state in which the first switch, the second switch, the third switch, and the fourth switch are turned off and the short switch is turned on; a third state in which the first switch and the second switch are turned off, the third switch and the fourth switch are turned on, and the short switch is turned off; It has three values indicating (18) The electronic circuit according to (18).

[0139] (20) a plurality of the differential signal output circuits; the first output terminals of the plurality of differential signal output circuits are connected to each other, the second output terminals of the plurality of differential signal output circuits are connected to each other, the first output terminal and the second output terminal are respectively connected to an inverting input terminal and a non-inverting input terminal of a differential amplifier; An electronic circuit according to any one of (1) to (19).

[0140] (twenty one) the plurality of differential signal output circuits output signals corresponding to multiple bits; (20) The electronic circuit according to (20).

[0141] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents. [Explanation of symbols]

[0142] 1:Electronic circuit, 10: differential signal output circuit, 20: differential amplifier, 30: Amplifier, 40: Encoder, SW1, SW2, SW3, SW4, SW5, SW6, SW7: Switches, R1, R2, R3, R4, R5, R6: Resistance

Claims

1. A differential signal output circuit for outputting a differential signal, comprising: a first output terminal and a second output terminal for outputting signals; a first switch having one end connected to the first output terminal and the other end connected to a first power supply; a second switch having one end connected to the second output terminal and the other end connected to a second power supply; a third switch having one end connected to the first output terminal and the other end connected to the second power supply; a fourth switch having one end connected to the second output terminal and the other end connected to the first power supply; a fifth switch having one end connected to one end of the first switch and one end of the third switch; a sixth switch having one end connected to one end of the second switch and one end of the fourth switch, and the other end connected to the other end of the fifth switch; a bias terminal connected to the other end of the fifth switch and the other end of the sixth switch; a differential signal output circuit having the above; a seventh switch connected to the bias terminal; characterized in that: the bias terminal is connected to a bias voltage through the seventh switch; the fifth switch and the sixth switch operate synchronously; the seventh switch operates exclusively with the fifth switch and the sixth switch; the bias voltage is the same voltage as the common voltage of an operational amplifier circuit to which the first output terminal and the second output terminal are connected; an electronic circuit.

2. The first switch and the second switch are MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) having the same polarity, and their gates are connected to each other; The third switch and the fourth switch are MOSFETs having the same polarity, and their gates are connected to each other; The electronic circuit according to Claim 1.

3. A first resistor having one end connected to one end of the first switch, one end of the third switch and one end of the fifth switch, and the other end connected to the first output terminal; A second resistor having one end connected to one end of the second switch, one end of the fourth switch and one end of the sixth switch, and the other end connected to the second output terminal; The electronic circuit according to Claim 1 or Claim 2, further comprising the above.

4. The fifth switch and the sixth switch are MOSFETs having the same polarity, and their gates are connected to each other; The electronic circuit according to any one of Claims 1 to 3.

5. The bias terminal is grounded, The electronic circuit according to any one of Claims 1 to 4.

6. A third resistor connected between the first power supply and the other ends of the first switch and the fourth switch, A fourth resistor connected between the second power supply and the other ends of the second switch and the third switch, The electronic circuit according to any one of Claims 1 to 5, further comprising:

7. A fifth resistor connected between one end of the fifth switch and one ends of the first switch and the third switch, A sixth resistor connected between one end of the sixth switch and one ends of the second switch and the fourth switch, Comprising: The electronic circuit according to Claim 6.

8. The first switch and the second switch operate synchronously, The third switch and the fourth switch operate synchronously so as not to turn on at the same timing as the first switch and the second switch, The electronic circuit according to any one of Claims 1 to 7.

9. The first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are controlled by a three-valued input signal, The electronic circuit according to any one of Claims 1 to 8.

10. The input signal is A first state in which the first switch and the second switch are on, the third switch and the fourth switch are off, and the fifth switch and the sixth switch are off, A second state in which the first switch, the second switch, the third switch and the fourth switch are off, and the fifth switch and the sixth switch are on, A third state in which the first switch and the second switch are off, the third switch and the fourth switch are on, and the fifth switch and the sixth switch are off, Having three values indicating: The electronic circuit according to Claim 9.

11. Comprising a plurality of the differential signal output circuits, The first output terminals of the plurality of differential signal output circuits are connected to each other, The second output terminals of the plurality of differential signal output circuits are connected to each other, The first output terminal and the second output terminal are respectively connected to the inverting input terminal and the non-inverting input terminal of a differential amplifier, The electronic circuit according to any one of Claims 1 to 10.

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