Display devices, electronic equipment

Abstract

To suppress the deterioration in electric characteristic in a transistor with an oxide semiconductor layer or a semiconductor device including the transistor.SOLUTION: In a transistor including an oxide semiconductor as a channel layer, a silicon layer is provided in contact with a surface of an oxide semiconductor layer. The silicon layer is provided in contact with at least a region where a channel is formed in the oxide semiconductor layer, and a source electrode layer and a drain electrode layer are provided in contact with a region where the silicon layer is not provided in the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a transistor using an oxide semiconductor layer and a semiconductor device including the transistor. The present invention relates to a device and a method for manufacturing the same. [Background technology]

[0002] There are many types of metal oxides and they are used for various purposes. Indium oxide is well known as It is a material that has been developed and is used as a transparent electrode material required for liquid crystal displays, etc. do.

[0003] Some metal oxides exhibit semiconducting properties. Generally, metal oxides are insulators. However, it is known that metal oxides can become semiconductors depending on the combination of elements that make up the oxide. It is being done.

[0004] For example, metal oxides that exhibit semiconductor properties include tungsten oxide, tin oxide, and indium oxide. These metal oxides, which exhibit semiconducting properties, are used in the channel formation region. Thin film transistors that achieve this are already known (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) contains In, Ga, and Zn It is known as a multi-component oxide semiconductor (Non-Patent Documents 2 to 4).

[0006] Then, the oxide semiconductor composed of the above-mentioned In-Ga-Zn-based oxide is used as a thin film transistor. It has been confirmed that it can be used as a channel layer for thin film transistors (also called TFTs). Patent document 5, non-patent documents 5 and 6).

[0007] However, in the case of an oxide semiconductor, damage caused by an etchant or plasma in the device manufacturing process, and the semiconductor characteristics are likely to vary due to the incorporation of elements such as hydrogen, resulting in problems such as variations and deterioration in the electrical characteristics of the device.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0009]

Non-Patent Document 1

Non-Patent Document 2

Non-patent document 3

Non-patent document 4

Non-patented document 5

Non-patent document 6

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, one aspect of the present invention is to suppress variations and deterioration in electrical characteristics in a transistor having an oxide semiconductor layer or a semiconductor device including the transistor. This is one of the problems.

Means for Solving the Problems

[0011] To solve the above problems, one aspect of the present invention is to provide a configuration in which a silicon layer is provided in contact with the surface of an oxide semiconductor layer in a transistor using an oxide semiconductor as a channel layer. In this case, the silicon layer functions as a protective film that reduces the incorporation of hydrogen or the like into the oxide semiconductor layer, functions as a protective film for the oxide semiconductor layer in the manufacturing process, and can suppress variations and deterioration in the electrical characteristics of the transistor.

[0012] Also, one aspect of the present invention is to provide a configuration in which the silicon layer is provided in contact with at least the region where a channel is formed in the oxide semiconductor layer, and the source electrode layer and the drain electrode layer are provided in contact with at least a part of the portion of the oxide semiconductor layer where the silicon layer is not in contact.

[0013] ​​​​​​​Also, in one aspect of the present invention, a low-resistance region that functions as a source region or a drain region is provided in at least a part of a region in the oxide semiconductor layer where no silicon layer is provided. A source electrode layer and a drain electrode layer may be provided in contact with the low-resistance region.

[0014] Also, one aspect of the present invention provides a transistor including a gate electrode, a gate insulating layer provided on the gate electrode, an oxide semiconductor layer provided on the gate insulating layer and overlapping the gate electrode, a silicon layer provided in contact with the surface of the oxide semiconductor layer, a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. Further, the source electrode layer and the drain electrode layer may be provided in contact with at least a part of the surface of the oxide semiconductor layer where no silicon layer is provided. Also, a first low-resistance region that functions as a source region may be provided in a region of the oxide semiconductor layer in contact with the source electrode layer, and a second low-resistance region that functions as a drain region may be provided in a region of the oxide semiconductor layer in contact with the drain electrode layer.

[0015] Also, one aspect of the present invention provides a transistor including a gate electrode, a gate insulating layer provided on the gate electrode, an oxide semiconductor layer provided on the gate insulating layer and overlapping the gate electrode, a silicon layer provided in contact with a part of the surface of the oxide semiconductor layer, a first metal oxide layer and a second metal oxide layer provided in contact with at least a part of the surface of the oxide semiconductor layer where no silicon layer is provided, a source electrode layer electrically connected to the first metal oxide layer, and a drain electrode layer electrically connected to the second metal oxide layer.

[0016] In addition, one aspect of the present invention provides a transistor having a gate electrode, a gate insulating layer provided on the gate electrode, a source electrode layer and a drain electrode layer provided on the gate insulating layer, an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer and provided on the gate electrode via the gate insulating layer, and a silicon layer provided in contact with the surface of the oxide semiconductor layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, performing plasma treatment on the exposed portion of the oxide semiconductor layer to form a low-resistance region, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In this specification, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content.

[0017] In addition, one aspect of the present invention provides a transistor having a gate electrode, a gate insulating layer provided on the gate electrode, a source electrode layer and a drain electrode layer provided on the gate insulating layer, an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer and provided on the gate electrode via the gate insulating layer, and a silicon layer provided in contact with the surface of the oxide semiconductor layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, performing plasma treatment on the exposed portion of the oxide semiconductor layer to form a low-resistance region, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In this specification, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content.

[0018] In addition, one aspect of the present invention provides a transistor having a gate electrode, a gate insulating layer provided on the gate electrode, a source electrode layer and a drain electrode layer provided on the gate insulating layer, an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer and provided on the gate electrode via the gate insulating layer, and a silicon layer provided in contact with the surface of the oxide semiconductor layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, performing plasma treatment on the exposed portion of the oxide semiconductor layer to form a low-resistance region, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer. In this specification, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content. In addition, one aspect of the present invention provides a method of manufacturing a transistor, including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer so as to overlap the gate electrode, forming a silicon layer so as to cover the oxide semiconductor layer, etching the silicon layer to expose a part of the oxide semiconductor layer, performing plasma treatment on the exposed portion of the oxide semiconductor layer to form a low-resistance region, forming a conductive film on the silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer.

[0019] In this specification, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content. ​​​​​Preferably, Rutherford backscattering spectroscopy (RBS) is used. rd Backscattering Spectrometry) and hydrogen forward scattering (HFS: Hydrogen Forward Scattering) In this case, the concentration range is 50 to 70 atomic % for oxygen, 0.5 to 15 atomic % for nitrogen, and 0.5 to 15 atomic % for silicon. It refers to a material containing 25 to 35 atomic % of silicon and 0.1 to 10 atomic % of hydrogen. Silicon nitride oxide is a material whose composition contains more nitrogen than oxygen, Preferably, the oxygen concentration range is 5 to 30 when measured using RBS and HFS. atomic %, nitrogen 20-55 atomic %, silicon 25-35 atomic %, hydrogen 10-30 atomic % of silicon oxynitride or silicon nitride oxide. When the total of the atoms is 100 atomic %, the content ratio of nitrogen, oxygen, silicon and hydrogen is It is included in the above range.

[0020] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to a device that includes a display device, a semiconductor circuit, and an electronic device. In this document, the term "display device" includes a light-emitting device and a liquid crystal display device. The liquid crystal display device includes a liquid crystal element. The light-emitting element has a luminance controlled by a current or a voltage. This category includes elements that emit light, specifically inorganic EL (Electro Luminescence) These include elements such as LEDs, organic EL elements, and LED elements.

[0021] In this specification, B is formed on A, or B is formed on A. When explicitly stating "A", it is not limited to B being formed directly on A. This also includes cases where there is no direct contact between A and B, i.e., there is another object between A and B. Let's say. [Effects of the Invention]

[0022] According to one embodiment of the present invention, in a transistor having a channel layer formed of an oxide semiconductor, By providing a silicon layer on the surface of the nitride semiconductor layer, the electrical characteristics of the transistor can be improved. This can suppress deterioration of the properties. [Brief explanation of the drawings]

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Embodiments for Carrying Out the Invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention The present invention is not limited to the following embodiments, and may be modified in any form without departing from the spirit of the invention. It will be apparent to those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. It should not be construed as being limited to the description of the embodiment shown below. The configurations according to the above embodiments can be implemented in appropriate combinations. In the configuration of the present invention, the same parts or parts having similar functions are designated by the same reference numerals, and their repetition The explanation of repetition will be omitted.

[0025] (Embodiment 1) In this embodiment, an example of a structure of a transistor included in a semiconductor device will be described with reference to the drawings. This will be explained in light of the above.

[0026] The transistor 120 shown in FIG. 1 includes a gate (gate wiring and gate The gate electrode (hereinafter referred to as "gate electrode 102") is provided on the gate electrode 102. a gate insulating layer 104 formed on the insulating layer 104; and an oxide semiconductor layer 108 formed on the gate insulating layer 104. a silicon layer 112 provided on the surface of the oxide semiconductor layer 108 so as to be in contact with the surface of the oxide semiconductor layer 108; A source (including a source wiring and a source electrode (hereinafter referred to as a source electrode)) electrically connected to the compound semiconductor layer 108 The drain (the drain wiring and the drain electrode) (hereinafter referred to as "drain electrode layer 116b") (see FIG. 1).

[0027] In FIG. 1, FIG. 1(A) shows a top view, and FIG. 1(B) shows A1 in FIG. 1(A). Fig. 1(C) shows a cross section between A2 and B2 in Fig. 1(A). This shows:

[0028] At least a portion of the oxide semiconductor layer 108 is in contact with the gate electrode 10 via the gate insulating layer 104. 2, and a layer (channel) forming the channel region of the transistor 120. It functions as a channel layer.

[0029] The oxide semiconductor layer 108 may be formed using an oxide material having semiconductor properties. , InMO3(ZnO) m An oxide semiconductor having a structure represented by (m>0) can be used. In particular, it is preferable to use an In-Ga-Zn-O based oxide semiconductor. Sodium (Ga), iron (Fe), nickel (Ni), manganese (Mn) and cobalt (Co ) represents one or more metal elements selected from the group consisting of M and Ga. In addition, when the above metal elements other than Ga are contained, such as Ga and Ni or Ga and Fe, In addition to the metal element contained as M in the oxide semiconductor, impurity elements may also be contained. Those containing Fe, Ni or other transition metal elements, or oxides of said transition metals as elements In this specification, InMO3(ZnO) m Acids with structures represented by (m>0) Among oxide semiconductors, oxide semiconductors with a structure containing at least Ga as M are called In-Ga-Z The thin film is also called an In—Ga—Zn—O-based non-single-crystal film.

[0030] In addition to the above, oxide semiconductors that can be used for the oxide semiconductor layer 108 include In—Sn— Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In—O-based, Sn—O-based, and Zn—O-based oxide semiconductors can be used.

[0031] The silicon layer 112 is made of an oxide semiconductor at least in the region overlapping with the gate electrode 102. The silicon layer 112 is provided on the surface of the layer 108 so as to be in contact with the oxide semiconductor. The conductive layer 108 is provided on a part of the surface thereof so as to be in contact with the conductive layer 108. The source electrode layer 116a and the drain electrode layer 111 are formed in the area where the silicon layer 112 is not formed. Here, the oxide semiconductor layer 108 is provided with a shielding film 6b. The silicon layer 112 is not provided in the regions spaced apart from each other, and the silicon layer 112 is provided in each of the regions. 10B, the source electrode layer 116a and the drain electrode layer 116b are provided in contact with each other.

[0032] The silicon layer 112 is preferably made of i-type (intrinsic) silicon. "i-type silicon" refers to silicon that contains impurities that give it p-type or n-type properties. 1 x 10 each 17 atoms / cm 3 The oxygen and nitrogen concentrations are less than 1 x10 20 atoms / cm 3 This refers to silicon with a concentration of Impurity elements such as phosphorus (P) or boron (B) are added to the capacitor within the above range. The concentration of these impurities contained in the silicon layer 112 may be determined by the secondary ions. Secondary Ion Mass Spectrosc (SIMS) Measurements can be performed using a fluoroscopy.

[0033] The crystalline state of the silicon layer 112 may be amorphous silicon, microcrystalline silicon, or the like. The silicon layer 112 can be silicon or polycrystalline (poly)silicon. Among these crystal structures, two or more crystal structures (e.g., amorphous structure and microcrystalline structure (or The polycrystalline structure may be included.

[0034] The silicon layer 112 can be formed by a method such as CVD, sputtering, vapor deposition, or coating. The thickness of the silicon layer 112 is 1 nm or more and 500 nm or less. Preferably, it can be set to 10 nm or more and 100 nm or less.

[0035] For example, in an atmosphere that does not contain hydrogen, such as an argon atmosphere, or an atmosphere with a low hydrogen content, In this case, the silicon layer 112 is formed by sputtering, so that the film of the silicon layer 112 The hydrogen concentration in the silicon layer 112 is reduced, and the oxide is formed due to the hydrogen contained in the silicon layer 112. Fluctuations in the semiconductor characteristics of the semiconductor layer 108 can be reduced.

[0036] When the silicon layer 112 is formed by sputtering, a direct current (DC) sputtering device is used. (It is also preferable to use a pulse DC sputtering device that applies a bias in a pulsed manner.) By using a DC sputtering system, it is possible to produce a large This is because the protective layer is made of silicon oxide or silicon nitride. This is a major advantage over using an insulating layer such as a silicon oxide layer. When forming an insulating layer such as a silicon nitride layer by sputtering (using an insulating target), This is because, in the case of using RF sputtering, it is necessary to use RF sputtering, which is difficult to scale up.

[0037] When the silicon layer 112 is formed using a DC sputtering device, a silicon target, Alternatively, a silicon target doped with an impurity such as boron can be used.

[0038] As shown in FIG. 1, the back channel side of the oxide semiconductor layer 108 (opposite to the gate electrode 102) By providing the silicon layer 112 so as to contact the surface of the silicon layer 112, the silicon layer 112 is protected. The oxide semiconductor layer 108 can be prevented from being contaminated with hydrogen or the like by functioning as a protective film. As a result, the semiconductor characteristics of the oxide semiconductor layer 108 may be changed due to the inclusion of elements such as hydrogen. As a result, the electrical characteristics of the transistor having the oxide semiconductor layer 108 as a channel layer are improved. This makes it possible to suppress variations and deterioration in properties.

[0039] In addition, a source electrode layer 116a and a drain electrode layer 116b are provided over the oxide semiconductor layer 108. In this case, the silicon layer 112 functions as a channel protection layer (channel stop layer). Therefore, when the silicon layer 112 is not provided in contact with the oxide semiconductor layer 108, Compared with the case of the channel etch type, the characteristics change due to the exposure of the oxide semiconductor layer 108 is The silicon layer 112 can be made to function actively as a channel protection layer. In this case, it is preferable to form the silicon layer 112 as a dense film. By forming the silicon layer 112 using this material, a dense film can be formed.

[0040] The silicon layer 112 is formed in at least the region where a channel is formed in the oxide semiconductor layer 108. The silicon layer 112 may be provided so as to be in contact with the surface of the silicon oxide film. A silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film may be formed. The insulating film provided on the layer 112 is formed by film formation using a sputtering method or a CVD method. Alternatively, it may be provided by oxidizing (including natural oxidation) or nitriding the surface of the silicon layer 112. To oxidize or nitride the surface of the silicon layer 112, plasma treatment may be performed in an oxygen atmosphere or a nitrogen atmosphere.

[0041] In FIG. 1, the source electrode layer 116a functions as the source of the transistor 120, and the drain electrode layer 116b functions as the drain of the transistor 120. Note that depending on the driving method of the transistor 120, the source electrode layer 116a may function as the drain, and the drain electrode layer 116b may function as the source.

[0042] In the structure shown in FIG. 1, as the material provided in contact with the surface of the oxide semiconductor layer 108, in addition to silicon, germanium, silicon germanium in which germanium is added to silicon, or silicon carbide (SiC) may be used.

[0043] Next, the effects when a silicon layer is provided in contact with the oxide semiconductor layer will be described based on computer simulation. Here, the hydrogen blocking effects of amorphous silicon (a-Si) and amorphous silicon oxide (a-SiO2) were verified.

[0044] <Calculation method> First, by classical molecular dynamics simulation, at a temperature T = 27°C and a pressure P = 1 atm, the equations of motion of each atom were numerically solved to track the motion of the atoms. Then, from the mean square displacement of H obtained from the calculation results, the diffusion coefficient D of H was obtained from Einstein's formula (Equation (1)). The larger this diffusion coefficient D is, the easier it is to diffuse. ​

[0045]

number

[0046] <Calculation model and calculation conditions> a-Si:H model ( (See Figure 27(A)) and 60 atoms of H (10 atom%) in 540 atoms of a-SiO2. We prepared an a-SiO2:H model (see Figure 27(B)) with a three-dimensional periodic boundary. By imposing boundary conditions, it is a model for calculating the bulk.

[0047] In the classical molecular dynamics method used in this calculation, an empirical potential that characterizes the interatomic interactions is The force acting on each atom is evaluated by defining the following. In the a-Si:H model, Tersoff The Born-Mayer potential was used for the a-SiO2:H model. Using the r-Huggins potential and the Morse potential, a-SiO2 and hydrogen In the interaction between atoms (between silicon and hydrogen atoms, between oxygen and hydrogen atoms), Lenn The calculation program used was the Hardt-Jones potential. Simulation software "Materials Explorer 5.0" was used. .

[0048] In each calculation model, the temperature T = 27°C, the pressure P = 1 atm, and the time interval Classical molecular dynamics simulations were performed with a width of 0.2 fsec x 5 million steps.

[0049] <Calculation results and discussion> The calculated mean square displacement of H atoms in a-Si and the mean square displacement of H atoms in a-SiO2 The self-displacements are shown in Fig. 28(A) respectively. In Fig. 28(A), the diffusion coefficients D of H atoms of each calculation model obtained from the region (70 psec to 100 psec) where the slope of the graph is almost constant are shown in Fig. 28(B). From Fig. 28(B), it can be seen that the diffusion coefficient of H atoms in a-Si is smaller than that of H atoms in a-SiO2, and it is found that H atoms in a-Si are less likely to diffuse than H atoms in a-SiO2. That is, it is considered that the a-Si film has a higher effect of preventing hydrogen incorporation compared to the a-SiO2 film.

[0050] Next, in the structure shown in Fig. 1, the shapes of the oxide semiconductor layer 108 and the silicon layer 112 will be described. In the following description, the width (Wb) of the silicon layer 112 and the width (Wc) of the oxide semiconductor layer 108 refer to the lengths of the silicon layer 112 and the oxide semiconductor layer 108 in the channel width direction, respectively. Also, the length (Lb) of the silicon layer 112 and the length (Lc) of the oxide semiconductor layer 108 refer to the lengths of the silicon layer 112 and the oxide semiconductor layer 108 in the channel length direction, respectively. The channel length direction refers to the direction substantially parallel to the direction in which carriers move in the transistor 120 (the direction connecting the source electrode layer 116a and the drain electrode layer 116b), and the channel width direction refers to the direction substantially perpendicular to the channel length direction.

[0051] The transistor shown in Fig. 1 shows a case where the width (Wb) of the silicon layer 112 is made larger than the width (Wc) of the oxide semiconductor layer 108, and the silicon layer 112 is provided so as to straddle (cross) both ends of the oxide semiconductor layer 108 in the channel width direction. Also, the ​​​​​​​​​​​​​​​The length (Lb) of the silicon layer 112 is set to be smaller than the length (Lc) of the oxide semiconductor layer 108. Two regions that are not covered with the silicon layer 112 are provided in the channel length direction, and the two regions are spaced apart from each other. The source electrode layer 116a and the drain electrode layer 116b are electrically connected to the region where the gate electrode 116a is provided. By providing the oxide semiconductor layer 108 in this manner, The leakage current caused by changes in the semiconductor properties of the surface can be reduced.

[0052] Note that the structure of the transistor described in this embodiment is not limited to that shown in FIG.

[0053] In FIG. 1, the length (Lc) of the oxide semiconductor layer 108 is increased to Although the transistor 120 is shown to be configured so as to extend over the edge of the gate electrode 102, 3, the length (Lc) of the oxide semiconductor layer 108 is reduced. Alternatively, the entire oxide semiconductor layer 108 may be disposed on the gate electrode 102. In FIG. 3, FIG. 3(A) shows a top view, and FIG. 3(B) shows a top view of FIG. 3(A). 1 shows a cross-sectional view taken along line A1-B1 in FIG.

[0054] 1 and 3, in the region overlapping with the oxide semiconductor layer 108, The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is set to the width (Wd) of the oxide semiconductor layer 108. It may be formed so that it is larger than (Wc) (see Figures 4(A) and (B)). The transistor 122 and the transistor 123 shown in FIG. 1B are formed on the silicon layer 1. The region of the oxide semiconductor layer 108 that is not in contact with the source electrode layer 116a and the drain electrode layer 116b is Since the oxide semiconductor layer 108 can be covered with the electrode layer 116b, the oxide semiconductor layer 108 is protected and reliability is improved. In addition, the oxide semiconductor layer 108 and the source electrode layer 1 The contact area between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b is increased. The contact resistance between the source electrode layer 116a and the drain electrode layer 116b can be reduced. do.

[0055] The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is the channel width The length of the source electrode layer 116a and the drain electrode layer 116b in the direction

[0056] The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is set to be equal to that of the silicon layer 11. 2 (Wb), or the width (Wb) of the source electrode layer 116a and the drain electrode layer 116b may be larger than the width (Wb) of the Only one width (Wd) of the oxide semiconductor layer 108 is set to the width (Wc) of the oxide semiconductor layer 108. The width (Wb) of the silicon layer 112 may be larger than the width (Wb) of the silicon layer 112.

[0057] In the structure shown in this embodiment mode, a black hole is formed above and / or below the silicon layer 112. A light-shielding portion such as a block matrix may be provided to shield the silicon layer 112 from light. By configuring the silicon layer 112 to be light-shielding, the silicon layer 112 is not irradiated with light. This can suppress variations in the electrical characteristics of the transistors caused by the gate When a light-shielding material is used for the gate electrode 102, the gate electrode 102 is formed on the upper side of the silicon layer 112 (gate electrode A light-shielding portion such as a black matrix may be provided on the opposite side to 102.

[0058] Next, an example of a method for manufacturing the transistor illustrated in FIGS. 1A to 1C will be described with reference to FIGS.

[0059] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. A gate insulating layer 104 is formed, and then an oxide semiconductor layer 106 is formed on the gate insulating layer 104. (See Figure 2(A)).

[0060] The substrate 100 may be any substrate having an insulating surface, and for example, a glass substrate may be used. Alternatively, the substrate 100 may be an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate. The surface of an insulating substrate made of an insulating material, or a semiconductor substrate made of a semiconductor material such as silicon, is covered with an insulating material. The surface of a conductive substrate made of a conductor such as metal or stainless steel is covered with an insulating material. In addition, plastic can be used as long as it can withstand the heat treatment in the manufacturing process. A block substrate can also be used.

[0061] The gate electrode 102 is formed by forming a conductive film on the entire surface of the substrate 100 and then by photolithography. The insulating film can be formed by etching the conductive film.

[0062] The gate electrode 102 is made of aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (Tungsten), or the like. It can be made of conductive materials such as stainless steel (W) and titanium (Ti). When aluminum is used as an electrode, aluminum itself has low heat resistance and is prone to corrosion. Therefore, it is preferable to form the conductive film by combining it with a heat-resistant conductive material.

[0063] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). selected from Mo, Cr, Nd, and Sc an element, an alloy containing the above-mentioned element, an alloy containing a combination of the above-mentioned elements, or The film can be formed from a nitride containing the element. and aluminum (or copper) are laminated to form wiring and electrodes.

[0064] The gate electrode 102 is made of a material that is transparent to visible light and highly conductive. Such a material may be, for example, indium tin oxide (Indium Tin Oxide). indium tin oxide (ITO), indium tin oxide with silicon oxide (ITSO), Organic indium, organic tin, zinc oxide (ZnO), etc. can be used.

[0065] The gate insulating layer 104 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. The insulating film can be formed of a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or the like. These films may be laminated by using, for example, a sputtering method. The film thickness can be formed to be 10 nm or more and 500 nm or less.

[0066] The oxide semiconductor layer 106 may be formed using an In—Ga—Zn—O-based oxide semiconductor. In this case, an oxide semiconductor target containing In, Ga, and Zn (e.g., In 2O3:Ga2O3:ZnO=1:1:1) by sputtering method. A compound semiconductor layer 106 can be formed.

[0067] The conditions for the sputtering method are, for example, a distance between the substrate 100 and the target of 30 mm or more and a distance between the substrate 100 and the target of 50 mm or more. 00mm or less, pressure between 0.01Pa and 2.0Pa, DC power supply 0.25k W or more and 5.0kW or less, temperature 20℃ or more and 200℃ or less, atmosphere argon, oxygen The atmosphere may be a mixture of argon and oxygen.

[0068] In the sputtering method, when a pulsed direct current (DC) power source is used, dust can be reduced, and the film thickness distribution becomes uniform, which is preferable. Also, the film thickness of the oxide semiconductor layer 106 can be set to about 5 nm or more and 20 0 nm or less.

[0069] When forming an In-Ga-Zn-O-based non-single crystal film as the oxide semiconductor layer 106, insulating impurities may be included in the oxide semiconductor target containing In, Ga, and Zn. Examples of such impurities include insulating oxides typified by silicon oxide, germanium oxide, and aluminum oxide, insulating nitrides typified by silicon nitride and aluminum nitride, or insulating oxynitrides such as silicon oxynitride and aluminum oxynitride. These insulating oxides or insulating nitrides are added at a concentration that does not impair the electrical conductivity of the oxide semiconductor. By including insulating impurities in the oxide semiconductor layer 106, crystallization of the oxide semiconductor layer 106 can be suppressed. By suppressing the crystallization of the oxide semiconductor layer 106,

[0070] the characteristics of the thin film transistor can be stabilized. Also, by including impurities such as silicon oxide in the In-Ga-Zn-O based oxide semiconductor, crystallization or generation of fine crystal grains of the oxide semiconductor can be prevented even when heat treatment is performed at 200°C or higher and 600 °C or lower. In addition to the above, other oxide semiconductors applicable to the oxide semiconductor layer 106 include In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S

[0071] O-based, etc. O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S ​n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -O-based, Sn-O-based, and Zn-O-based oxide semiconductors can be used. By adding impurities that suppress crystallization and maintain an amorphous state to the oxide semiconductor, The characteristics of the thin film transistor can be stabilized. Insulating oxides such as germanium oxide and aluminum oxide, silicon nitride, Insulating nitrides such as aluminum, silicon oxynitride, aluminum oxynitride, etc. Examples include insulating oxynitrides such as silicon dioxide.

[0072] Next, the oxide semiconductor layer 106 is etched to form an island-shaped oxide semiconductor layer 108 ( At this time, the island-shaped oxide semiconductor layer 108 is formed on at least the gate electrode 10 The oxide semiconductor layer 106 is etched so as to remain above the insulating film 2.

[0073] Next, a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see FIG. 2C). ).

[0074] The silicon layer 110 can be formed by sputtering. DC welding using a silicon target or a boron-doped silicon target under atmospheric pressure The silicon layer 110 can be formed by sputtering. However, it is not limited to this. The silicon layer 110 may be formed by a CVD method or the like. At the interface between the conductor layer 108 and the silicon layer 110, In some cases, a thin mixed layer (for example, silicon oxide) may be formed.

[0075] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (see Fig. 2(D ). At this time, the silicon layer 110 is etched so that the island-shaped silicon layers 112 remain in at least the region overlapping with the gate electrode 102. Also, the silicon layer 110 is etched so as to expose at least a part of the oxide semiconductor layer 108. As the etching, for example, wet etching using TMAH (Tetra Methyl Ammonium Hydroxide) can be applied. In this case, the etching selectivity between the oxide semiconductor layer 108 and the silicon layer 110 can be increased, and the silicon layer 110 can be etched well with little etching of the oxide semiconductor layer 108. Also, damage to the oxide semiconductor layer 108 can be reduced.

[0076] Note that the etching selectivity means, for example, the difference between the etching rate of layer A and the etching rate of layer B when etching layer A and layer B. That is, a large etching selectivity means that there is a sufficient difference in the etching rates. Next, a conductive film 11 4 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112 (see Fig. 2(E)). The conductive film 114 is a metal containing an element selected from aluminum (Al), copper (Cu ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), formed using a sputtering method, a vacuum evaporation method, or the like.

[0077]

[0078]

[0079] ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc). ​​​​​​​​ An alloy composed of the above elements as components, or a material composed of a nitride or the like composed of the above elements as components can be formed

[0080] For example, the conductive film 114 can be formed with a single-layer structure of a molybdenum film or a titanium film Also, the conductive film 114 may be formed with a laminated structure. For example, a laminated structure of an aluminum film and a titanium film can be used. Also, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated in sequence may be used. Also, a three-layer structure in which a molybdenum film, an aluminum film, and a molybdenum film are laminated in sequence may be used. Also, as the aluminum film used in these laminated structures, an aluminum (Al-Nd) film containing neodymium may be used. Furthermore, the conductive film 114 may have a single-layer structure of an aluminum film containing silicon

[0081] Also, as the conductive film 114, a material having light transmittance for visible light and high conductivity may be used to form. As such a material, for example, indium tin oxide (Indium Tin Oxide: ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide (ZnO), etc. can be used

[0082] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b (see Fig. 2(F)). At this time, depending on the etching conditions, the silicon layer 112 may also be etched and the film may be reduced when the conductive film 114 is etched . Here, the case where the silicon layer 112 is also etched and the film is reduced when the conductive film 114 is etched is shown . (see Fig. 2(F)). At this time, depending on the etching conditions, the silicon layer 112 may also be etched and the film may be reduced when the conductive film 114 is etched

[0083] In the above process, the silicon layer 112 functions as a channel protection layer (channel stop layer) that suppresses the etching of the oxide semiconductor layer 108 during the etching of the conductive film 114. In the oxide semiconductor layer 108, in the region where the silicon layer 112 is not provided, the oxide semiconductor layer 108 may be thinned simultaneously with the etching of the conductive film 114. Thus, by providing the silicon layer 112 in contact with the oxide semiconductor layer 108, it is possible to suppress the incorporation of unintended elements such as hydrogen into the oxide semiconductor layer 108 from the outside. Through the above process, the transistor 120 can be fabricated.

[0084] Also, a protective insulating layer may be formed to cover the transistor 120. As the protective insulating layer, for example, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed using a CVD method, a sputtering method, or the like. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b. In the process of FIG. 2, after forming the oxide semiconductor layer 108, in a nitrogen atmosphere or an air atmosphere, at a temperature of 100°C or higher and 600°C or lower, typically 200°C or higher and 400°C or lower.

[0085] Through the above process, the transistor 120 can be fabricated.

[0086] Also, a protective insulating layer may be formed to cover the transistor 120. As the protective insulating layer, for example, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed using a CVD method, a sputtering method, or the like. For example, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b. Also, in the process of FIG. 2, after forming the oxide semiconductor layer 108, in a nitrogen atmosphere or an air atmosphere, at a temperature of 100°C or higher and 600°C or lower, typically 200°C or higher and 400°C or lower. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b. After forming the source electrode layer 116a and the drain electrode layer 116b, the exposed portion of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film on the silicon layer 112 located in the region between the source electrode layer 116a and the drain electrode layer 116b.

[0087] In the process of FIG. 2, after forming the oxide semiconductor layer 108, in a nitrogen atmosphere or an air atmosphere, at a temperature of 100°C or higher and 600°C or lower, typically 200°C or higher and 400°C or lower. In a nitrogen atmosphere or an air atmosphere, at a temperature of 100°C or higher and 600°C or lower, typically 200°C or higher and 400°C or lower. It is preferable to perform heat treatment. For example, heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the island-shaped oxide semiconductor layer 108. The oxide semiconductor layer 108 is advantageous in that it can release strain that inhibits carrier movement. It's important.

[0088] The timing of the heat treatment is not particularly limited as long as it is performed after the oxide semiconductor layer 106 is formed. First, the silicon layer 110 is formed, and then the island-shaped silicon layer 112 is formed. Then, the conductive film 11 After forming the source electrode layer 116a and the drain electrode layer 116b, or The heat treatment may be performed after forming a protective insulating layer. The oxide semiconductor layer 108 and the silicon layer 112 are mixed at the interface between the layer 108 and the silicon layer 112. A thin layer (eg, an oxide of silicon) may be formed.

[0089] Thereafter, various electrodes and wiring are formed to complete a semiconductor device equipped with a transistor 120. Complete.

[0090] In FIG. 2, the silicon layer 110 is formed after the oxide semiconductor layer 108 is formed. However, the oxide semiconductor layer 106 and the silicon layer 110 are stacked in succession. Then, a plurality of masks are used to pattern the silicon layer 112 and the oxide semiconductor layer 108. The manufacturing method in this case will be described with reference to FIG.

[0091] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. Then, an oxide semiconductor layer 106 and a silicon dioxide film are formed on the gate insulating layer 104. After forming the silicon layer 110 by laminating it in order, a resist mask 175 is selectively formed ( 25A). The gate insulating layer 104 to the silicon layer 110 or the oxide semiconductor layer Preferably, layers 106 through silicon layer 110 are deposited in succession.

[0092] Next, the resist mask 175 was used to remove the insulating film from the silicon layer 110 and the oxide semiconductor layer 106. The necessary portions are etched to form island-shaped oxide semiconductor layers 108 and silicon layers 111. (See FIG. 25(B)). After that, the resist mask 175 is removed.

[0093] Next, a resist mask 176 is formed on the silicon layer 111. The exposed silicon layer 111 is etched using the etching method. 12 is formed (see FIG. 25(C)).

[0094] Next, a conductive film 11 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. After forming the conductive film 114 (see FIG. 25(D)), the conductive film 114 is etched to form the source electrode Then, a layer 116a and a drain electrode layer 116b are formed (see FIG. 25E).

[0095] Through the above steps, a transistor 124 as shown in FIG. The transistor 124 shown by 26 has a width (Wb) of the silicon layer 112 and a width (Wb) of the oxide semiconductor layer 10 26 shows the case where the widths (Wc) of the respective portions 8 are set equal to each other. 26(A) shows a top view, and FIG. 26(B) shows the area between A1 and B1 in FIG. 26(A). 26(C) shows a cross-sectional view taken along the line A2-B2 in FIG. 26(A). are.

[0096] Thus, by continuously forming the oxide semiconductor layer 106 and the silicon layer 110, damage caused by an etchant, plasma, or the like to the surface of the oxide semiconductor layer 106 can be reduced.

[0097] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0098] (Embodiment 2) In this embodiment, a method and configuration for manufacturing a transistor different from those in the above Embodiment 1 will be described with reference to the drawings.

[0099] First, a gate electrode 102 is formed on a substrate 100, and then a gate insulating layer 104 is formed on the gate electrode 102. Subsequently, an oxide semiconductor layer 106 and a silicon layer 110 are sequentially stacked and formed on the gate insulating layer 104, and then a resist mask 171 is selectively formed (see Fig. 5(A)). It is preferable to form a continuous film from the gate insulating layer 104 to the silicon layer 110 or from the oxide semiconductor layer 106 to the silicon layer 110. Therefore, in the following, the description of overlapping parts will be omitted, and different points will be described in detail.

[0100] First, a gate electrode 102 is formed on a substrate 100, and then a gate insulating layer 104 is formed on the gate electrode 102. Subsequently, an oxide semiconductor layer 106 and a silicon layer 110 are sequentially stacked and formed on the gate insulating layer 104, and then a resist mask 171 is selectively formed (see Fig. 5(A)). It is preferable to form a continuous film from the gate insulating layer 104 to the silicon layer 110 or from the oxide semiconductor layer 106 to the silicon layer 110. Subsequently, after the resist mask 171 is formed, the silicon layer 110 is etched using the resist mask 171 to form an island-shaped silicon layer 111 (see Fig. 5(B)). Here, an alkaline etchant is used. It is preferable to form a continuous film from the gate insulating layer 104 to the silicon layer 110 or from the oxide semiconductor layer 106 to the silicon layer 110.

[0101] Next, the silicon layer 110 is etched using the resist mask 171 to form an island-shaped silicon layer 111 (see Fig. 5(B)). Here, an alkaline etchant is used. Perform wet etching. By using an alkaline etching solution, the etching selectivity between the oxide semiconductor layer 106 and the silicon layer 110 can be increased, and the silicon layer 110 can be selectively etched. As the alkaline etching solution, for example, TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) can be used. The etching selectivity between the oxide semiconductor layer 106 and the silicon layer 110 can be increased, and the silicon layer 110 can be selectively etched. As the alkaline etching solution, for example, TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) can be used. ide, tetramethylammonium hydroxide) can be used. ide, tetramethylammonium hydroxide) can be used.

[0102] Next, using the resist mask 171, the oxide semiconductor layer 106 is etched to form island-shaped oxide semiconductor layers 108 (see FIG. 5(C)). Here, wet etching is performed using an acidic etching solution. By using an acidic etching solution, the etching selectivity between the oxide semiconductor layer 106 and the silicon layer 111 can be increased, and the oxide semiconductor layer 106 can be selectively etched. As the acidic etching solution, for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as mixed acid for aluminum) can be used. Next, using the resist mask 171, the oxide semiconductor layer 106 is etched to form island-shaped oxide semiconductor layers 108 (see FIG. 5(C)). Here, wet etching is performed using an acidic etching solution. By using an acidic etching solution, the etching selectivity between the oxide semiconductor layer 106 and the silicon layer 111 can be increased, and the oxide semiconductor layer 106 can be selectively etched. As the acidic etching solution, for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as mixed acid for aluminum) can be used. As the acidic etching solution, for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as mixed acid for aluminum) can be used. As the acidic etching solution, for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as mixed acid for aluminum) can be used. As the acidic etching solution, for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as mixed acid for aluminum) can be used.

[0103] Next, using the resist mask 171, the silicon layer 111 is etched to form island-shaped silicon layers 112 (see FIG. 5(D)). Here, wet etching is performed again using an alkaline etching solution. By using an alkaline etching solution, the etching selectivity between the oxide semiconductor layer 108 and the silicon layer 111 can be increased, and the silicon layer 111 can be selectively etched. Here, the etching proceeds isotropically, and the side surface of the silicon layer 111 is etched (side etching). As the alkaline etching solution, for example, TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) can be used. Next, using the resist mask 171, the silicon layer 111 is etched to form island-shaped silicon layers 112 (see FIG. 5(D)). Here, wet etching is performed again using an alkaline etching solution. By using an alkaline etching solution, the etching selectivity between the oxide semiconductor layer 108 and the silicon layer 111 can be increased, and the silicon layer 111 can be selectively etched. As the alkaline etching solution, for example, TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) can be used. Here, the etching proceeds isotropically, and the side surface of the silicon layer 111 is etched (side etching). As the alkaline etching solution, for example, TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) can be used. As the potassium-based etching solution, for example, TMAH (Tetra Methyl Amm onium Hydroxide, tetramethylammonium hydroxide) can be used. This is possible.

[0104] Thus, by etching the silicon layer continuously after etching the oxide semiconductor layer, it is possible to etch the oxide semiconductor layer and the silicon layer without adding a mask. Therefore, the process can be simplified.

[0105] Next, after forming a conductive film on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112, the conductive film is etched to form the source electrode layer 116a and the drain electrode layer 116 b (see Fig. 5(E)). b is formed (see Fig. 5(E)).

[0106] Through the above steps, a transistor 130 as shown in Fig. 6 can be fabricated. Note that in Fig. 6, Fig. 6(A) shows a top view, Fig. 6(B) shows a cross-sectional view between A1 - B1 in Fig. 6(A), and Fig. 6(C) shows a cross-sectional view between A2 - B2 in Fig. 6(A). view is shown.

[0107] When the manufacturing method shown in Fig. 5 is used, as shown in Fig. 6, the width (Wb ) of the silicon layer 112 becomes smaller than the width (Wc) of the oxide semiconductor layer 108, and the length (Lb) of the silicon layer 112 becomes smaller than the length (Lc) of the oxide semiconductor layer 108.

[0108] In the manufacturing process of Fig. 5, by continuously forming the oxide semiconductor layer 106 and the silicon layer 110, damage caused by an etching agent, plasma, etc. on the surface of the oxide semiconductor layer 106 It is possible to reduce the addition of impurities. By providing a silicon layer having an etching selectivity with respect to the oxide semiconductor layer on the oxide semiconductor layer, even when etching the oxide semiconductor layer and the silicon layer, the process can be simplified without adding a mask. After forming the transistor 130, a protective insulating layer may be formed so as to cover the transistor 130. Also, in the process of FIG. 5, after forming the oxide semiconductor layer 108, heat treatment may be performed in a nitrogen atmosphere or an air atmosphere. Note that the method for manufacturing the transistor 130 shown in FIG. 6 is not limited to the method shown in FIG. 5. For example, after performing up to FIG. 5(C), the resist mask 171 is isotropically reduced by performing ashing on the resist mask 171 with oxygen plasma to expose a part of the silicon layer 111, and then the exposed portion of the silicon layer 111 is etched to form the silicon layer 112. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0109]

[0110]

[0111]

[0112] (Embodiment 3) In this embodiment, a transistor and a method for manufacturing the same, which are different from those in the above Embodiments 1 and 2, will be described with reference to the drawings. Note that the manufacturing process (applicable materials, etc.) shown in this embodiment is common to that in the above Embodiment 1 in many parts. Therefore, in the following, descriptions of overlapping parts will be omitted, and different points will be described in detail.

[0113] The transistor 140 shown in FIG. 7 includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, an oxide semiconductor layer 108 provided on the gate insulating layer 104, a silicon layer 112 provided so as to be in contact with the surface of the oxide semiconductor layer 108, a source electrode layer 116a and a drain electrode layer 116b provided so as to be in contact with the surface of the oxide semiconductor layer 108, and low-resistance regions 109a, 109b are provided in regions of the oxide semiconductor layer 108 that are in contact with the source electrode layer 116a and the drain electrode layer 116b. That is, the transistor 140 shown in this embodiment has a configuration in which low-resistance regions

[0114] 109a, 109b are added to regions of the oxide semiconductor layer 108 where the silicon layer 112 is not provided in the configuration shown in the above embodiment. In FIG. 7, FIG. 7(A) shows a top view, and FIG. 7(B) shows a cross-sectional view taken along A1-B1 in FIG. 7(A). In the oxide semiconductor layer 108, the low-resistance regions 109a, 109b can be provided by making the region oxygen-deficient (in an oxygen-deficient state as compared with the region where the silicon layer 112 is in contact). The oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon. In FIG. 7, FIG. 7(A) shows a top view, and FIG. 7(B) shows a cross-sectional view taken along A1-B1 in FIG. 7(A). In addition, the low-resistance regions 109a, 109b may be provided by selectively adding hydrogen to the oxide semiconductor layer 108.

[0115] The low-resistance regions 109a, 109b can be provided by making the oxide semiconductor layer 108 oxygen-deficient (in an oxygen-deficient state compared to the region where the silicon layer 112 is in contact). Oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon. The oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon. The oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon. The oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon. That is, the low-resistance regions 109a, 109b can be provided by making the oxide semiconductor layer 108 oxygen-deficient (in an oxygen-deficient state compared to the region where the silicon layer 112 is in contact). Oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon.

[0116] Alternatively, the low-resistance regions 109a, 109b may be provided by selectively adding hydrogen to the oxide semiconductor layer 108. That is, the low-resistance regions 109a, 109b can be provided by making the oxide semiconductor layer 108 oxygen-deficient (in an oxygen-deficient state compared to the region where the silicon layer 112 is in contact). Oxygen deficiency can be provided by selectively performing plasma treatment on the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided with a reducing gas such as hydrogen or argon.

[0117] The low resistance regions 109a and 109b are the source and drain regions of the transistor 140. The source electrode layer 116a is provided in contact with the low resistance region 109a. The drain electrode layer 116b is provided in contact with the region 109b, thereby 8 and the source electrode layer 116a and the drain electrode layer 116b. This can be done.

[0118] Next, an example of a method for manufacturing the transistor illustrated in FIGS. 7A to 7C will be described with reference to FIGS.

[0119] First, the steps shown in FIGS. 2(A) to 2(D) are carried out to etch the silicon layer 112. The resist mask 172 used in the step 172 is left (see FIG. 8(A)).

[0120] Next, the oxide semiconductor layer 108 is treated with a reducing agent such as hydrogen or argon using the resist mask 172. The oxide semiconductor layer 108 is subjected to plasma treatment using a reactive gas, and the low-resistance regions 109a and 109b are formed in the oxide semiconductor layer 108. (See FIG. 8(B)).

[0121] Next, a conductive film 11 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. 8C. Note that the conductive film 114 is formed on the oxide semiconductor layer 108 to reduce the resistance of the oxide semiconductor layer 108. It is formed so as to contact the regions 109a and 109b.

[0122] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. (See FIG. 8(D)).

[0123] Through the above steps, the transistor 140 can be manufactured.

[0124] After the transistor 140 is formed, a protective insulating layer is formed to cover the transistor 140. It may be formed. Also, in the process of FIG. 8, after forming the oxide semiconductor layer 108, nitrogen heat treatment may be performed in an atmosphere or in an air atmosphere.

[0125] Note that in FIGS. 7 and 8, low resistance regions 109a and 109b are provided in the oxide semiconductor layer 108 to reduce the contact resistance between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b is shown, but it is not limited to this.

[0126] As in the transistor 141 shown in FIGS. 9(A) and (B), between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b, a first metal oxide layer 11 5a and a second metal oxide layer 115b may be provided respectively. Note that in FIG. 9, FIG. 9(A) shows a top view, and FIG. 9(B) shows a cross-sectional view taken along A1 - B1 in FIG. 9(A). is shown.

[0127] The first metal oxide layer 115a and the second metal oxide layer 115b may be formed of a metal oxide having at least a lower resistance than the oxide semiconductor layer 108.

[0128] Also, the first metal oxide layer 115a and the second metal oxide layer 115b can be formed of the same material as the oxide semiconductor layer 1 08 and under different film formation conditions. For example, as the oxide semiconductor layer 108, the first metal oxide layer 115a, and the second metal oxide layer 115b, an In - Ga - Zn - O - based non - single crystal film is used. When the In - Ga - Zn - O - based non - single crystal film of the first metal oxide layer 115a and the second metal oxide layer 115b is considered, the ratio of the oxygen gas flow rate to the argon gas flow rate in the film formation conditions of the In - Ga - Zn - O - based non - single crystal film of the first metal oxide layer 115a and the second metal oxide layer 115b is higher than that of the In - Ga - Zn - O - based non - single crystal film of the oxide semiconductor layer 108 Ga - Zn - O - based non - single crystal film, and the argon gas flow rate of the In - Ga - Zn - O - based non - single crystal film of the first metal oxide layer 115a and the second metal oxide layer 115b is lower than that of the In - Ga - Zn - O - based non - single crystal film of the oxide semiconductor layer 108. Also, the argon gas flow rate of the In - Ga - Zn - O - based non - single crystal film of the first metal oxide layer 115a and the second metal oxide layer 115b is lower than that of the In - Ga - Zn - O - based non - single crystal film of the oxide semiconductor layer 108. Set the condition such that the ratio of the oxygen gas flow rate in the film formation condition is large. Specifically, for the first metal oxide layer 115a and the In-Ga-Zn-O based polycrystalline film of the second metal oxide layer 115b the film formation conditions are in a rare gas (such as argon or helium) atmosphere (or 10% or less of oxygen gas, 90% or more of argon gas), and the film formation conditions of the In-Ga-Zn-O based polycrystalline film of the oxide semiconductor layer 108 are in an oxygen mixed atmosphere (the oxygen gas flow rate is higher than the rare gas flow rate). It can be made.

[0129] In this way, by providing the first metal oxide layer 115a and the second metal oxide layer 115b between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b respectively, the injection barrier of carriers from the source electrode layer 116a and the drain electrode layer 116b can be reduced, so that the contact resistance between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b can be reduced. 116b can be reduced.

[0130] Note that the first metal oxide layer 115a and the second metal oxide layer 115b are formed by sequentially laminating a metal oxide layer and a conductive film 114 on the silicon layer 112 and the oxide semiconductor layer 108 after performing the steps up to FIGS. 2(A) to (D), and etching in the same manner as the conductive film 114. It can be formed. At this time, depending on the etching conditions and the material selected, the conductive film 11 4 and the metal oxide layer, or the conductive film 114, the metal oxide layer, and the oxide semiconductor layer 108 may be etched simultaneously.

[0131] Also, as in the transistor 142 shown in FIG. 9(C), low resistance regions 109a and 109b are provided in the oxide semiconductor layer 108, and the first metal oxide layer 115a and the second metal oxide layer​​​​ It may be configured to provide the layer 115b.

[0132] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0133] (Embodiment 4) In this embodiment, a transistor different from those in the above-described Embodiments 1 to 3 and a method for manufacturing the same will be described with reference to the drawings. Note that the manufacturing steps (applicable materials, etc.) shown in this embodiment are common to those in Embodiment 1 in many parts. Therefore, in the following, descriptions of overlapping parts will be omitted, and different points will be described in detail. The transistor 150 shown in FIGS. 10(A) and 10(B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and a gate insulating layer 104 provided on the source electrode layer 116a and the drain electrode layer 116b and located above the gate electrode 102 and in the region between the source electrode layer 116a and the drain electrode layer 116b. The transistor 150 also includes an oxide semiconductor layer 108 provided on the gate insulating layer 104 and a silicon layer 112 provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The description of overlapping parts will be omitted, and different points will be described in detail.

[0134] The transistor 150 shown in FIGS. 10(A) and 10(B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and a gate insulating layer 104 provided on the source electrode layer 116a and the drain electrode layer 116b and located above the gate electrode 102 and in the region between the source electrode layer 116a and the drain electrode layer 116b. The transistor 150 also includes an oxide semiconductor layer 108 provided on the gate insulating layer 104 and a silicon layer 112 provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The transistor 150 shown in FIGS. 10(A) and 10(B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and a gate insulating layer 104 provided on the source electrode layer 116a and the drain electrode layer 116b and located above the gate electrode 102 and in the region between the source electrode layer 116a and the drain electrode layer 116b. The transistor 150 also includes an oxide semiconductor layer 108 provided on the gate insulating layer 104 and a silicon layer 112 provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view.

[0135] That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical (stacking order) of the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108 is reversed compared to the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a bottom gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The figure is shown, and FIG. 10(B) shows a cross-sectional view of A1-B1 in FIG. 10(A). .

[0136] As shown in FIGS. 10(A) and (B), by providing the silicon layer 112 so as to be in contact with the back channel side (the surface on the side opposite to the gate electrode 102) of the oxide semiconductor layer 108, hydrogen can be prevented from mixing into the oxide semiconductor layer 108. As a result, fluctuations in the semiconductor characteristics of the oxide semiconductor layer 108 caused by the mixing of hydrogen are suppressed, and ultimately, fluctuations in the characteristics of the transistor having the oxide semiconductor layer 108 as the channel layer can be suppressed.

[0137] Also, as in the transistor 151 shown in FIG. 10(C), metal oxide layers 115a and 115b may be provided between the source electrode layer 116a and the drain electrode layer 116b and the oxide semiconductor layer 108. By providing the metal oxide layers 115a and 115b, the contact resistance between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b can be reduced.

[0138] Next, an example of a method for manufacturing the transistor shown in FIGS. 10(A) and (B) will be described with reference to FIG. 11 .

[0139] First, the gate electrode 102 is formed on the substrate 100, and then the gate insulating layer 104 is formed on the gate electrode 102. After that, the source electrode layer 116a and the drain electrode layer 116b are formed on the gate insulating layer 104 (see FIG. 11(A)).

[0140] Next, the oxide semiconductor layer 106 is formed so as to cover the source electrode layer 116a and the drain electrode layer 116b (see FIG. 11(B)). ​​​​​​

[0141] Next, the oxide semiconductor layer 106 is etched to form an island-shaped oxide semiconductor layer 108 ( see FIG. 11(C)). At this time, the oxide semiconductor layer 106 is etched so that the island-shaped oxide semiconductor layer 108 remains above at least the gate electrode 1 02.

[0142] Next, a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see FIG. 11(D) ).

[0143] Next, the silicon layer 110 is etched to form an island-shaped silicon layer 112 (see FIG. 11( E)).

[0144] Through the above steps, the transistor 150 can be fabricated.

[0145] Note that after forming the transistor 150, a protective insulating layer may be formed to cover the transistor 150. Also, in the steps of FIG. 11, after forming the oxide semiconductor layer 108, heat treatment may be performed in a nitrogen atmosphere or an air atmosphere.

[0146] Also, when fabricating the transistor shown in FIG. 10(C), in FIG. 11(A), a conductive film constituting the source electrode layer 116a and the drain electrode layer 116b and a metal oxide layer constituting the metal oxide layers 115a, 115b are sequentially laminated on the gate insulating layer 104, and then etched. Also, the structure shown in FIG. 10(C) shows a case where the metal oxide layers 115a, 1 15b are also etched simultaneously when the oxide semiconductor layer 106 is etched to form the island-shaped oxide semiconductor layer 108. 15b are also etched simultaneously when the oxide semiconductor layer 106 is etched to form the island-shaped oxide semiconductor layer 108.

[0147] In addition, in FIG. 11, an island-shaped silicon layer 112 is formed so as to completely cover the oxide semiconductor layer 108, but the present invention is not limited to this. The silicon layer 112 may be provided so as to be in contact with the region where the channel is formed in at least the oxide semiconductor layer 108. For example, as in the transistor 152 shown in FIG. 12, the silicon layer 112 can be provided so as to be in contact with a part of the oxide semiconductor layer 108. In FIG. 12, the silicon layer 112 is formed so as to be in contact with a part of the oxide semiconductor layer 108 (formed so as not to be in contact with the source electrode layer 116a and the drain electrode layer 1 16b), and a case where a protective insulating layer 119 is provided on the silicon layer 112, the oxide semiconductor layer 108, the source electrode layer 116a, and the drain electrode layer 116b is shown.

[0148] As the protective insulating layer 119, for example, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed using a CVD method, a sputtering method, or the like.

[0149] In FIG. 12, FIG. 12(A) shows a top view, and FIG. 12(B) shows a cross-sectional view taken along line A1 - B1 in FIG. 12(A).

[0150] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0151] (Embodiment 5) In this embodiment, a manufacturing process of a display device, which is an example of a usage form of a semiconductor device including the transistors shown in the above Embodiments 1 to 4, will be described with reference to the drawings. Note that in this​​​​​​​​ Some of the manufacturing processes (applicable materials, etc.) shown in the embodiments are common to those in Embodiment 1 in many parts. Therefore, in the following, the description of overlapping parts will be omitted, and the differences will be described in detail. In the following description, FIGS. 15 to 19 show top views, and FIGS. 13 and 14 show cross-sectional views between A3 - B3 and A4 - B4 in FIGS. 15 to 19.

[0152] First, wirings and electrodes (gate wiring including gate electrode 102, capacitor wiring 308, first terminal 321) are formed on a substrate 100 having an insulating surface, and then a gate insulating layer 104 and an oxide semiconductor layer 106 are successively formed (see FIGS. 13(A) and 15). The capacitor wiring 308 and the first terminal 321 can be formed simultaneously using the same material as the gate electrode 102.

[0153]

[0154] Next, after etching the oxide semiconductor layer 106 to form an island - shaped oxide semiconductor layer 108 (see FIG. 16), a silicon layer 110 is formed so as to cover the oxide semiconductor layer 108 (see FIG. 13(B)). At this time, the oxide semiconductor layer 106 is etched so that the island - shaped oxide semiconductor layer 108 remains at least above the gate electrode 102.

[0155] Next, the silicon layer 110 is etched to form an island - shaped silicon layer 112 (see FIGS. 13(C) and 17). At this time, the silicon layer 110 is etched so that the island - shaped silicon layer 112 remains in a region overlapping at least the gate electrode 102. Also, the silicon layer 110 is etched so as to expose at least a part of the oxide semiconductor layer 108.

[0156] Next, contact hole 313 is formed in the gate insulating layer 104 so as to expose the first terminal 321. After that, a conductive film 114 is formed so as to cover the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112 (see FIG. 13(D)). As a result, the conductive film 114 and the first terminal 321 are electrically connected via the contact hole 313.

[0157] Next, the conductive film 114 is etched to form a source electrode layer 116a, a drain electrode layer 116b, a connection electrode 320, and a second terminal 322 (see FIGS. 14(A) and 18). At this time, the silicon layer 112 functions as a channel protection layer for the oxide semiconductor layer 108.

[0158] The second terminal 322 can be configured to be electrically connected to a source wiring (source wiring including the source electrode layer 116a). Also, the connection electrode 320 can be configured to be directly connected to the first terminal 321.

[0159] Through the above steps, the transistor 160 can be fabricated.

[0160] Next, it is preferable to perform a heat treatment at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. For example, a heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes atomic-level rearrangement of the In-Ga-Zn-O-based polycrystalline film that constitutes the oxide semiconductor layer 108. Since the strain that inhibits carrier movement is released by this heat treatment, the heat treatment (including photo annealing) here is effective. The timing of the heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor layer 106. For example, it may be performed after the formation of the pixel electrode formed later.

[0161] Next, a protective insulating layer 340 is formed so as to cover the transistor 160, and the protective insulating layer 34 0 is selectively etched to form a contact hole 325 reaching the drain electrode layer 116b, a contact hole 326 reaching the connection electrode 320, and a contact hole 327 reaching the second terminal 322 (see FIG. 14(B)).

[0162] Next, a transparent conductive layer 310 electrically connected to the drain electrode layer 116b, a transparent conductive layer 328 electrically connected to the connection electrode 320, and a transparent conductive layer electrically connected to the second terminal 322 are formed (see FIGS. 14(C) and 19). The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 serve as electrodes or wirings used for connection to the FPC. More specifically, the transparent conductive layer 328 formed on the connection electrode 320 is used as a connection terminal electrode functioning as an input terminal of the gate wiring, and the transparent conductive layer 329 formed on the second terminal 322 can be used as a connection terminal electrode functioning as an input terminal of the source wiring.

[0163] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 serve as electrodes or wirings used for connection to the FPC. More specifically, the transparent conductive layer 328 formed on the connection electrode 320 is used as a connection terminal electrode functioning as an input terminal of the gate wiring, and the transparent conductive layer 329 formed on the second terminal 322 can be used as a connection terminal electrode functioning as an input terminal of the source wiring. [[ID=?]] The transparent conductive layer 328 formed on the connection electrode 320 is used as a connection terminal electrode functioning as an input terminal of the gate wiring, and the transparent conductive layer 329 formed on the second terminal 322 can be used as a connection terminal electrode functioning as an input terminal of the source wiring. 2 of the terminals 322 on the transparent conductive layer 329 formed as the input terminal of the source wiring functions can be used as a connection terminal electrode.

[0164] In addition, a holding capacitor can be formed by the capacitive wiring 308, the gate insulating layer 104, the protective insulating layer 340, and the transparent conductive layer 310. In this case, the capacitive wiring 308 and the transparent conductive layer 310 serve as electrodes, and the gate insulating layer 104 and the protective insulating layer 340 serve as dielectrics. The transparent conductive layer 310, 328, 329 are indium oxide (In2O3), indium oxide indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium zinc oxide alloy

[0165] The transparent conductive layers 310, 328, and 329 are indium oxide (In2O3), indium oxide indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium zinc oxide alloy It should be noted that there seems to be an error in the original text where "2 of the terminals 322 on the transparent conductive layer 329 formed as the input terminal of the source wiring functions" in line 26 of the English translation is a bit unclear in its structure. You may want to double-check the original Japanese text for accuracy.Indium (In2O3-ZnO) etc. can be formed using a sputtering method, a vacuum evaporation method, or the like. . For example, after forming a transparent conductive film, a resist mask is formed on the transparent conductive film, and the unnecessary portions are removed by etching to form the transparent conductive layers 310, 328, and 329. This can be done.

[0166] Through the above steps, elements such as a bottom-gate type n-channel thin-film transistor and a storage capacitor can be completed. Then, by arranging these elements in a matrix corresponding to individual pixels, an active matrix type display device can be fabricated.

[0167] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0168] (Embodiment 6) In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device including a thin-film transistor. First, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 2 0. FIGS. 20(A1) and (A2) show thin-film transistors 4010, 4011 having an oxide semiconductor layer formed on a first substrate 4001, and a liquid crystal element 4013, which is a top view of the panel sealed with a sealing material 4005 between it and a second substrate 4006, and FIG. 20(B) corresponds to a cross-sectional view taken along M-N in FIGS. 20(A1) and (A2).

[0169] A sealing material 4005 is provided so as to surround a pixel portion 4002 and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0170] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 20(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0171] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 20B, the thin film transistor included in the pixel portion 4002 is a thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4020 and 4011 are formed on the thin film transistors 4010 and 4011. 21 is provided.

[0172] The thin film transistors 4010 and 4011 can be formed using the structure shown in the above embodiment mode. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It is a membrane transistor.

[0173] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. It is formed on 06. The overlapping part of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031 respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. The overlapping part is equivalent to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031 respectively. The liquid crystal layer 4008 is sandwiched therebetween.

[0174] As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) board, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0175] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005.

[0176] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. Yes, when the cholesteric liquid crystal is heated, just before the transition from the cholesteric phase to the isotropic phase appears. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence .

[0177] Note that the liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0178] Also, in the liquid crystal display device shown in this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment, and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. Further, a light-shielding film that functions as a black matrix may be provided.

[0179] Also, in this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a planarizing insulating film . Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film is formed using a sputtering method to form a silicon oxide film or a silicon nitride film . Silicon film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride Aluminum nitride film, aluminum oxide nitride film, or aluminum nitride oxide film, or a single layer or laminated layer. In this embodiment, an example in which the protective film is formed by sputtering is shown, but the method is not particularly limited. The insulating film may be formed by various methods.

[0180] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0181] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the problem of

[0182] After forming the protective film, the semiconductor layer is annealed (at 200°C or higher and 400°C or lower). That's fine.

[0183] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0184] The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group. The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group. The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group. The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

[0185] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing of the semiconductor layer (200°C or higher and 400°C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device.

[0186] The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0187] Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The formed pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. Further, it is preferred that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

[0188] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0189] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4 002 are supplied from the FPC 4018.

[0190] In the present embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 40 30 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010, 40 11.

[0191] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

[0192] Also, in FIG. 20, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0193] The present embodiment can be implemented in appropriate combination with the configurations described in other embodiments.​​ It is as follows.

[0194] (Embodiment 7) In this embodiment, an electronic paper is shown as an example of a semiconductor device including a transistor. .

[0195] FIG. 21 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the semiconductor device can be fabricated in the same manner as the thin film transistors shown in the above Embodiments 1 to 5. The thin film transistor 581 provided on the substrate 580 is a thin film transistor having a bottom gate structure, and the source electrode layer or the drain electrode layer is electrically connected to the first electrode layer 587 through contact holes formed in the insulating layers 583, 584, and 585. Between the first electrode layer 587 and the second electrode layer 588, spherical particles 589 having black regions 590a and white regions 590b and surrounded by a liquid-filled cavity 594 are provided, and a filler 595 such as resin is provided around the spherical particles 589 (see FIG. 21). In FIG. 21, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is provided on the same substrate as the thin film transistor 581. It can be fabricated in the same manner as the thin film transistors shown in the above Embodiments 1 to 5.

[0196] The electronic paper in FIG. 21 is an example of a display device using a twist ball display method. The twist ball display method is a method of arranging spherical particles painted white and black between a first electrode layer and a second electrode layer used as display elements, and controlling the orientation of the spherical particles by generating a potential difference between the first electrode layer and the second electrode layer to perform display. The twist ball display method is an electrode layer that uses spherical particles painted white and black as display elements. It is arranged between the first electrode layer and the second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer. By doing so, the orientation of the spherical particles is controlled to perform display. It is arranged between the first electrode layer and the second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles and perform display. It is a method of controlling the orientation of spherical particles and performing display by generating a potential difference between the first electrode layer and the second electrode layer.

[0197] The thin film transistor 581 provided on the substrate 580 is a thin film transistor having a bottom gate structure, and the source electrode layer or the drain electrode layer is electrically connected to the first electrode layer 587 through contact holes formed in the insulating layers 583, 584, and 585. The thin film transistor provided on the substrate 580 is a thin film transistor with a bottom gate structure, and the source electrode layer or the drain electrode layer is electrically connected to the first electrode layer 587 through contact holes formed in the insulating layers 583, 584, and 585. 84, 585, and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588, there are black regions 590a and white regions 590b, and spherical particles 589 including a cavity 594 filled with liquid around it are provided. And a filler 595 such as resin is provided around the spherical particles 589 (see FIG. 21). In FIG. 21, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. And spherical particles 589 having black regions 590a and white regions 590b and surrounded by a liquid-filled cavity 594 are provided, and a filler 595 such as resin is provided around the spherical particles 589 (see FIG. 21). And a filler 595 such as resin is provided around the spherical particles 589 (see FIG. 21). In FIG. 21, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is provided on the same substrate as the thin film transistor 581. is electrically connected to the common potential line. Using the common connection part shown in the above embodiment, a pair of the second electrode layer 588 provided on the substrate 596 and the common potential line can be electrically connected via conductive particles disposed between the substrates.

[0198] Also, instead of the twist ball, it is also possible to use an electrophoretic element. In that case, a transparent liquid, positively charged white fine particles, and negatively charged black fine particles are encapsulated in a microcapsule having a diameter of about 10 μm to 200 μm. The microcapsules provided between the first electrode layer and the second electrode layer are given an electric field by the first electrode layer and the second electrode layer, and then the white fine particles and the black fine particles move in opposite directions to display white or black. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary backlight is unnecessary, and the power consumption is small, and the display portion can be recognized even in a dim place. Also, even when no power is supplied to the display portion, the image once displayed can be retained. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device having a display device) is separated from the radio wave transmission source, the displayed image can be saved. As described above, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0199] As described above, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0200] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0201] (Embodiment 8) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device including a transistor. As a display element included in the display device, here, a light-emitting element using electroluminescence is shown. The light-emitting element using electroluminescence is classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0202] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0203] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element structure. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination type light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission using inner-shell electron transition of metal ions.

[0204] Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 22. FIG. 22(A) shows a structure formed on a first substrate 4501. The provided thin film transistors 4509, 4510 and the light emitting element 4511 are sealed with a sealing material 4505 between them and the second substrate 450 6, and this is a top view of the panel. FIG. 22(B) is , corresponding to the cross-sectional view at H-I in FIG. 22(A). Here, an organic EL element is used as the light emitting element for explanation.

[0205] A pixel portion 4502, signal line driving circuits 4503a, 450 3b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 are surrounded by a sealing material 4505 . Also, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 45 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506 . In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (enclose) it with a protective film (laminating film, ultraviolet curable resin film, etc.) with little outgassing or a cover material. Also, the pixel portion 4502, signal line driving circuits 4503a, 4 503b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin film transistors, and in FIG. 22(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are exemplified.

[0206] The thin film transistors 4509, 4510 may apply the structure shown in the above embodiment. The thin film transistors 4509, 4510 have a plurality of thin film transistors, and in FIG. 22(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are exemplified. The thin film transistors 4509, 4510 may apply the structure shown in the above embodiment.

[0207] The thin film transistors 4509, 4510 may apply the structure shown in the above embodiment. It is possible. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0208] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the configuration shown in the present embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like.

[0209] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0210] The electroluminescent layer 4512 may be configured with a single layer or a plurality of layers stacked.

[0211] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0212] Also, various signals and potentials applied to the signal line drive circuits 4503a and 4503b, the scan line drive circuits 4504a and 4504b , or the pixel portion 4502 are supplied from the FPCs 4518a and 4518 b.

[0213] In this embodiment, the connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509 and 4510. 517, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509, 4 510.

[0214] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519.

[0215] The second substrate 4506 located in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. Otherwise, it must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0216] In addition, as the filling material 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV A (ethylene vinyl acetate) can be used.

[0217] Further, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed.

[0218] The signal line drive circuits 4503a, 4503b, and the scan line drive circuits 4504a, 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0219] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0220] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0221] (Embodiment 9) The semiconductor device including the transistor described in the above embodiment can be used in various electronic devices (play equipment, etc.). The present invention can be applied to electronic devices such as television sets ( Televisions (also called televisions or television receivers), computer monitors, digital Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones) mobile phones, mobile phone devices), portable game consoles, personal digital assistants, sound reproducing devices, pachinko machines, Examples include large game machines such as prank machines.

[0222] FIG. 23A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0223] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. Operations such as channel and volume can be performed by the operation keys 9609 provided on the remote control unit 9610, and the video displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control unit 9610.

[0224] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive more general television broadcasts, and further, by connecting to a communication network via a wired or wireless connection through the modem, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can also be performed.

[0225] FIG. 23(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in the housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0226] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, etc. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface as it improves the design. For example, the recording medium of the digital photo frame A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0227] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0228] FIG. 24(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 24(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least the semiconductor device It is sufficient that the system is equipped with the above-mentioned equipment, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 24(A) uses a program or data recorded on a recording medium. It has the function of reading the information and displaying it on the display, and sharing information with other portable gaming machines via wireless communication. The functions of the portable gaming machine shown in FIG. 24(A) are not limited to these. It can have a variety of functions.

[0229] Figure 24(B) shows an example of a slot machine 9900 which is a large-sized gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Further, the slot machine 9900 also includes operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above-described one, and any configuration having at least a semiconductor device is acceptable, and other attached facilities can be provided as appropriate.

[0230] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Explanation of Reference Numerals

[0231] 100 Substrate 102 Gate electrode 104 Gate insulating layer 106 Oxide semiconductor layer 108 Oxide semiconductor layer 109a Low-resistance region 109b Low-resistance region 110 Silicon layer 111 Silicon layer 112 Silicon layer 114 Conductive film 115a Metal oxide layer 115b Metal oxide layer 116a Source electrode layer 116b Drain electrode layer 119 Protection insulating layer 120 Transistor 121 Transistor 122 Transistor 123 Transistor 124 Transistor 130 Transistor 140 Transistor 141 Transistor 142 transistors 150 transistors 151 transistors 152 transistors 160 transistors 171 resist masks 172 resist masks 175 resist masks 176 resist masks 308 capacitance wirings 310 transparent conductive layers 313 contact holes 320 connection electrodes 321 first terminals 322 second terminals 325 contact holes 326 contact holes 327 contact holes 328 transparent conductive layers 329 transparent conductive layers 340 protective insulating layers 580 substrates 581 thin film transistors 583 insulating layers 587 first electrode layers 588 second electrode layers 589 spherical particles 594 cavities 595 fillers 596 substrates 4001 first substrates 4002 pixel parts 4003 signal line driving circuits 4004 scanning line driving circuits 4005 sealing materials 4006 second substrates 4008 liquid crystal layers 4010 thin film transistors 4011 thin film transistors 4013 liquid crystal elements 4015 connection terminal electrodes 4016 terminal electrodes 4018 FPC 4019 anisotropic conductive films 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4501 First substrate 4502 Pixel portion 4503a Signal line drive circuit 4503b Signal line drive circuit 4504a Scanning line drive circuit 4504b Scanning line drive circuit 4505 Sealing material 4506 Second substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Second electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 First electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Partition wall 590a Black region 590b White region 9600 Television apparatus 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 Display unit 9883 Display unit 9884 Speaker unit 9885 Operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display part

Claims

1. Having a transistor disposed in a pixel portion, having a first conductive layer having a region that functions as a gate electrode of the transistor, having a first insulating layer provided on the first conductive layer and having a region that functions as a gate insulating film of the transistor, located on the first insulating layer, having indium (In), gallium (Ga), and zinc (Zn), and having a single-layer oxide semiconductor layer, located on the oxide semiconductor layer and having a silicon oxide layer in contact with a first region of the oxide semiconductor layer, having a layer containing silicon on the silicon oxide layer, having a second conductive layer having a region in contact with a first low-resistance region of the oxide semiconductor layer and a region that functions as one of a source electrode or a drain electrode of the transistor, having a third conductive layer having a region in contact with a second low-resistance region of the oxide semiconductor layer and a region that functions as the other of the source electrode or the drain electrode of the transistor, having a planarizing insulating film on the layer containing silicon, having a pixel electrode having a region in contact with the second conductive layer or the third conductive layer on the planarizing insulating film, having an EL layer on the pixel electrode, having a counter electrode on the EL layer, the first region of the oxide semiconductor layer having a channel formation region of the transistor, the oxide semiconductor layer having the first low-resistance region and the second low-resistance region so as to sandwich the channel formation region, the first low-resistance region and the second low-resistance region having a region not in contact with the silicon oxide layer, the first conductive layer being a laminate of a titanium (Ti) film and aluminum (Al) or copper (Cu), the second conductive layer and the third conductive layer having a metal containing an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), the second conductive layer having a region in contact with the upper surface of the layer containing silicon, the third conductive layer having a region in contact with the upper surface of the layer containing silicon, the silicon oxide layer having a region in contact with the side surface of the oxide semiconductor layer, in the channel width direction of the transistor, the layer containing silicon being provided beyond both ends of the oxide semiconductor layer, the layer containing silicon having a region in contact with the first insulating layer, a display device.

2. The display device according to claim 1, wherein the oxide semiconductor layer includes an In-O-based oxide semiconductor.

3. An electronic device including the display device according to claim 1 or 2.

Images