Method for manufacturing a stacked device chip

Abstract

To provide a method for manufacturing a laminated device chip capable of suppressing an obstacle to joining device chips.SOLUTION: A method for manufacturing a laminated device chip comprises a first groove forming step 101, a fixing step 102, a first wafer grinding step 103, a first resin layer forming step 104, a first wafer polishing step 105, a second groove forming step 106, a bonding step 107, a second wafer grinding step 108, a second resin layer forming step 109, and a dividing step 110. The first groove forming step forms a first groove on a first wafer. The fixing step fixes the first wafer to a support. The first wafer grinding step exposes the first groove. The first resin layer forming step forms a first resin layer. The first wafer polishing step exposes the first resin layer. The second groove forming step forms a second groove wider than the first groove on the surface side and narrower than the surface side on the groove bottom side in a second wafer. The bonding step bonds the wafers. The second wafer grinding step exposes the second groove. The second resin layer forming step forms a second resin layer. The dividing step manufactures a laminated device chip.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a laminated device chip manufactured by laminating chips.

Background Art

[0002] With the miniaturization, thinning, and shortening of electronic devices, semiconductor devices are progressing in miniaturization through pattern miniaturization and chip lamination. For example, technologies such as direct bonding, in which chips are laminated and electrodes are directly bonded to each other, have been developed (see, for example, Patent Document 1). In direct bonding, since the device surface (the surface on the functional layer side, the front surface) of a chip having TSV electrodes is directly overlapped with the back surface of the chip to be overlapped, the surface is processed to be flat so as not to sandwich foreign matter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In addition, when resin is filled between adjacent device chips to directly bond device chips having device surfaces of exactly the same area, polishing is performed to planarize the device chips and the resin. However, the elastic resin swells slightly more than the surface (the surface to be polished) of the device chip after polishing and easily protrudes from between the device chips, and may be sandwiched between the overlapping device chips, which may prevent direct bonding.

[0005] An object of the present invention is to provide a method for manufacturing a laminated device chip capable of suppressing obstacles to the bonding between device chips.

Means for Solving the Problems

[0006] In order to solve the above-described problems and achieve the object, a method for manufacturing a stacked device chip according to the present invention uses a wafer in which devices are provided in a plurality of regions on the surface partitioned by a plurality of planned division lines, and manufactures a stacked device chip in which a plurality of device chips are stacked. The method for manufacturing a stacked device chip includes: a first groove forming step of forming a first groove having a depth exceeding the finished thickness of the first device chip from the surface of the first wafer along the plurality of planned division lines of the first wafer; a fixing step of fixing the front surface side of the first wafer to a support; a first wafer grinding step of grinding the first wafer fixed to the support from the back surface side to expose the first groove on the back surface side of the first wafer; a first resin layer forming step of forming a first resin layer in the first groove of the first wafer; a first wafer polishing step of polishing the first wafer fixed to the support and the first resin layer simultaneously to thin the first wafer to a thickness corresponding to the finished thickness of the first device chip and expose the first resin layer provided in the first groove on the back surface side of the first wafer; a second groove forming step of forming a second groove having a depth exceeding the finished thickness of the second device chip from the surface of the second wafer along the plurality of planned division lines of the second wafer having the same configuration as the first wafer, wherein the width of the second groove is wider than the width of the first groove on the front surface side of the second wafer and narrower than the width on the front surface side at the groove bottom side; a bonding step of facing the back surface of the polished first wafer and the front surface of the second wafer and bonding the second wafer to the first wafer so that the first resin layer protruding from the back surface of the first wafer is accommodated in the second groove of the second wafer; a second wafer grinding step of grinding the second wafer bonded to the first wafer from the back surface side to expose the second groove on the back surface side of the second wafer; a second resin layer forming step of forming a second resin layer in the second groove of the second wafer; and a dividing step of cutting the first resin layer and the second resin layer along the first groove and the second groove to manufacture a stacked device chip.

[0007] In the method for manufacturing the stacked device chip, in the second groove forming step, the second groove may be formed by plasma etching using a plasma gas, cutting using a cutting blade, or laser processing using a laser beam.

[0008] In the method for manufacturing the stacked device chip, after the second resin layer forming step and before the dividing step, a second wafer polishing step may be provided in which the second wafer fixed to the first wafer and the second resin layer are polished simultaneously, and the second wafer is thinned to a thickness corresponding to the finished thickness of the second device chip.

Advantages of the Invention

[0009] The present invention has the effect of suppressing obstacles to the bonding between device chips.

Brief Description of the Drawings

[0010]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0011] The embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the constituent elements described below include those that can be easily assumed by those skilled in the art and substantially the same ones. Furthermore, the configurations described below can be combined as appropriate. Also, various omissions, substitutions, or changes in the configuration can be made without departing from the gist of the present invention.

[0012] 〔Embodiment 1〕 A method for manufacturing a stacked device chip according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing an example of a wafer to be processed in the method for manufacturing a stacked device chip according to Embodiment 1. FIG. 2 is a cross-sectional view schematically showing a main part of the wafer shown in FIG. 1. FIG. 3 is a perspective view showing an example of a stacked device chip manufactured by the method for manufacturing a stacked device chip according to Embodiment 1. FIG. 4 is a flowchart showing the flow of the method for manufacturing a stacked device chip according to Embodiment 1.

[0013] (Wafer) The method for manufacturing a stacked device chip according to Embodiment 1 is a method for manufacturing the stacked device chip 10 shown in FIG. 3 using the wafer 1 shown in FIGS. 1 and 2. In Embodiment 1, the wafer 1 is a disk-shaped semiconductor wafer or an optical device wafer having a substrate 2 made of silicon, sapphire, gallium arsenide, or the like. As shown in FIG. 1, the wafer 1 is provided with devices 5 in a plurality of regions on the surface 3 partitioned by a plurality of division planned lines 4 intersecting each other.

[0014] The device 5 is, for example, an integrated circuit such as an IC (Integrated Circuit) or an LSI (Large Scale Integration), or various memories (semiconductor storage devices). Further, as shown in FIG. 2, the wafer 1 includes a through electrode 7 embedded in the substrate 2 and extending from the surface 3 toward the back surface 6 on the back side of the surface 3. The through electrode 7 is made of a conductive metal and is connected to the device 5. Although FIG. 2 shows one through electrode 7 connected to each device 5, in the present invention, a plurality of through electrodes 7 may be connected to each device 5.

[0015] Wafer 1 is divided along the planned division line 4 into individual device chips 9 shown in FIG. 1. The through electrode 7 becomes a so-called TSV (Through-Silicon Via) electrode that penetrates the substrate 2 across the front surface 3 and the back surface 6 when the wafer 1 is divided into individual device chips 9 and connects to the device 5 etc. of other device chips 9. The device chip 9 is composed of the substrate 2 and the device 5. Note that the same parts as those of the wafer 1 of the device chip 9 are denoted by the same reference numerals and the description thereof is omitted.

[0016] (Stacked device chip) As shown in FIG. 3, the stacked device chip 10 is composed of a plurality (two in Embodiment 1) of device chips 9 stacked. Except for the front surface 3 of one device chip 9, the side surfaces of both device chips 9 and the back surface 6 of the other device chip 9 are covered with a resin layer 11 made of resin. Among the two device chips 9 constituting the stacked device chip 10, the upper device chip 9 in FIG. 3 is hereinafter referred to as the first device chip 9-1, and the lower device chip 9 in FIG. 3 is hereinafter referred to as the second device chip 9-2.

[0017] (Manufacturing method of stacked device chip) As shown in FIG. 4, the manufacturing method of the stacked device chip according to Embodiment 1 includes a first groove forming step 101, a fixing step 102, a first wafer grinding step 103, a first resin layer forming step 104, a first wafer polishing step 105, a second groove forming step 106, a bonding step 107, a second wafer grinding step 108, a second resin layer forming step 109, and a dividing step 110.

[0018] (First groove forming step) FIG. 5 is a cross-sectional view schematically showing a main part of the first wafer after the first groove formation step of the method for manufacturing the stacked device chip shown in FIG. 4. The first groove formation step 101 is a step of forming a first groove 13 having a depth 13-1 that exceeds the finished thickness 12-1 (shown in FIG. 3) of the first device chip 9-1 from the surface 3 of the first wafer 1-1 along a plurality of planned division lines 4 of the first wafer 1-1.

[0019] In the first groove formation step 101, the above-described wafer 1 is prepared as the first wafer 1-1, and the cutting device sucks and holds the back surface 6 side of the first wafer 1-1 on the holding surface of the chuck table. In the first groove formation step 101, while the cutting device relatively moves the cutting blade rotated by the spindle and the chuck table along the planned division line 4, the cutting blade is cut into the planned division line 4 from the surface 3 side by the above-described depth 13-1, and as shown in FIG. 5, the first groove 13 is formed in each planned division line 4. Note that the depth 13-1 of the first groove 13 is shallower than the thickness of the first wafer 1-1, and the first groove 13 does not reach the back surface 6 of the first wafer 1-1.

[0020] Note that the first groove 13 is formed with a constant width 13-2 in the thickness direction of the first wafer 1-1, but in the present invention, the width may be gradually narrowed from the surface 3 toward the back surface 6. Also, in the present invention, in the first groove formation step 101, the laser processing device sucks and holds the back surface 6 side of the first wafer 1-1 on the holding surface of the chuck table, and while relatively moving the laser beam irradiation unit and the chuck table along the planned division line 4, irradiates the first wafer 1-1 with a laser beam having an absorbable wavelength from the laser beam irradiation unit from the surface 3 side to the planned division line 4, and the first groove 13 may be formed in each planned division line 4.

[0021] (Fixing step) FIG. 6 is a cross-sectional view schematically showing a main part of the first wafer after the fixing step of the manufacturing method of the laminated device chip shown in FIG. 4. The fixing step 102 is a step of fixing the surface 3 side of the first wafer 1-1 to the plate-shaped support 20. In Embodiment 1, in the fixing step 102, as shown in FIG. 6, the surface 3 side of the first wafer 1-1 is fixed to a support 20 made of a hard material such as an adhesive (not shown) and having the same diameter as or a larger diameter than the first wafer 1-1.

[0022] Note that in Embodiment 1, the surface 3 side of the first wafer 1-1 is fixed to the support 20 made of a hard material in the fixing step 102. However, in the present invention, as the support, a flexible tape including a base material layer made of resin and an adhesive layer made of an adhesive resin or a resin sheet without an adhesive layer may be thermocompression-bonded to fix the surface 3 side of the first wafer 1-1.

[0023] (First Wafer Grinding Step) FIG. 7 is a cross-sectional view schematically showing a main part of the first wafer after the first wafer grinding step of the manufacturing method of the laminated device chip shown in FIG. 4. The first wafer grinding step 103 is a step of grinding the first wafer 1-1 fixed to the support 20 from the back surface 6 side to expose the first groove 13 on the back surface 6 side of the first wafer 1-1.

[0024] In the first wafer grinding step 103, the grinding device sucks and holds the surface 3 side of the first wafer 1-1 to the holding surface of the chuck table via the support 20. In the first wafer grinding step 103, the grinding device rotates the grinding wheel for grinding around the axis by the spindle and rotates the chuck table around the axis, and while supplying grinding fluid from a grinding fluid nozzle (not shown), the grinding stone of the grinding wheel is brought into contact with the back surface 6 of the substrate 2 of the first wafer 1-1 and brought closer to the chuck table at a predetermined feed rate, and the back surface 6 side of the first wafer 1-1 is ground with the grinding stone.

[0025] In Embodiment 1, as shown in FIG. 7, in the first wafer grinding step 103, as shown in FIG. 6, the grinding device grinds the back surface 6 side of the first wafer 1-1 until the thickness of the first wafer 1-1 becomes thinner than the finish thickness 12-1 of the first device chip 9-1 and thicker than the depth 13-1 of the first groove 13. In Embodiment 1, in the first wafer grinding step 103, the grinding device exposes at least the first groove 13 on the back surface 6 of the first wafer 1-1.

[0026] (First resin layer formation step) FIG. 8 is a cross-sectional view schematically showing a main part of the first wafer after the first resin layer formation step of the method for manufacturing a stacked device chip shown in FIG. 4. The first resin layer formation step 104 is a step of forming a resin layer 11 (hereinafter referred to as the first resin layer 11-1) in the first groove 13 of the first wafer 1-1.

[0027] In the first resin layer formation step 104, a softened resin is supplied into the first groove 13 of the first wafer 1-1 by heating or the like, and this resin is coated on the back surface 6 of the first wafer 1-1. As shown in FIG. 8, the first resin layer 11-1 is formed in the first groove 13, and the back surface 6 of the first wafer 1-1 is coated with the first resin layer 11-1.

[0028] (First wafer polishing step) FIG. 9 is a cross-sectional view schematically showing a main part of the first wafer after the first wafer polishing step of the method for manufacturing a stacked device chip shown in FIG. 4. The first wafer polishing step 105 is a step of simultaneously polishing the first wafer 1-1 fixed to the support 20 and the first resin layer 11-1, thinning the first wafer 1-1 to a thickness corresponding to the finish thickness 12-1 of the first device chip 9-1, and exposing the back surface 6 of the first wafer 1-1, the through electrode 7, and the first resin layer 11-1 provided in the first groove 13 on the back surface 6 side of the first wafer 1-1.

[0029] In the first wafer polishing step 105, the polishing apparatus sucks and holds the surface 3 side of the first wafer 1-1 via the support 20 on the holding surface of the chuck table. In the first wafer polishing step 105, the polishing apparatus brings the polishing pad rotated around the axis closer to the chuck table rotated around the axis at a predetermined feed rate, and polishes the first resin layer 11-1 on the back surface 6 of the first wafer 1-1 with the polishing member. Then, the first resin layer 11-1 on the back surface 6 is removed, and the first groove 13 is exposed on the back surface 6 side.

[0030] In Embodiment 1, in the first wafer polishing step 105, as shown in FIG. 9, the polishing and thinning apparatus polishes and thins the back surface 6 of the first wafer 1-1 and the first resin layer 11-1 in the first groove 13 simultaneously until the thickness of the first wafer 1-1 becomes the finished thickness 12-1 of the first device chip 9-1. After the first wafer polishing step 105, as shown in FIG. 9, when the back surface 6 side of the first wafer 1-1 is no longer pressed by the polishing pad, since the first resin layer 11-1 is made of resin, it protrudes slightly more than the back surface 6 due to the restoring force.

[0031] (Second groove forming step) FIG. 10 is a cross-sectional view schematically showing the second groove forming step of the manufacturing method of the stacked device chip shown in FIG. 4. FIG. 11 is a cross-sectional view schematically showing the main part of the second wafer after the second groove forming step of the manufacturing method of the stacked device chip shown in FIG. 4. The second groove forming step 106 forms a second groove 14 with a depth 14-1 exceeding the finished thickness 12-2 (shown in FIG. 3) of the second device chip 9-2 from the surface 3 of the second wafer 1-2 along a plurality of division planned lines 4 of the second wafer 1-2 having the same configuration as the first wafer 1-1. The width of the second groove 14 is wider than the width 13-2 (shown in FIG. 9 etc.) of the first groove 13 on the surface 3 side of the second wafer 1-2 and is a groove narrower than the width 14-2 on the surface 3 side at the groove bottom side.

[0032] In Embodiment 1, in the second groove formation step 106, the above-described wafer 1 is prepared as a second wafer 1-2 having the same configuration as the first wafer 1-1, and the surface 3 side of the second wafer 1-2 is coated with a water-soluble resin to form a protective film 21. In Embodiment 1, in the second groove formation step 106, a laser beam is irradiated onto the surface 3 of the division planned line 4 of the second wafer 1-2 to remove the protective film 21 on the division planned line 4, thereby exposing the surface 3 of the division planned line 4 and maintaining the state in which the device 5 is covered with the protective film 21. At this time, the width of the surface 3 exposed at each division planned line 4 is wider than the width 13-2 of the first groove 13. The water-soluble resin is, for example, polyvinyl alcohol (PVA), polyvinyl pyrrolidone (PVP), or the like in Embodiment 1. The water-soluble resin functions as a shielding film (mask) having resistance to the plasma etching gas 31 shown in FIG. 10.

[0033] In Embodiment 1, in the second groove formation step 106, the plasma etching apparatus 30 sucks and holds the back surface 6 side of the second wafer 1-2 on the holding surface 33 of the chuck table 32. In Embodiment 1, in the second groove formation step 106, the plasma etching apparatus 30 applies a high-frequency voltage for drawing the plasma etching gas 31 into the chuck table, and supplies the plasma etching gas 31 above the holding surface 33 of the chuck table 32.

[0034] In the second groove forming step 106, the substrate 2 is etched with a plasma etching gas 31 from the surface 3 side to the back surface 6 of the division planned line 4 where the protective film 21 has been removed and exposed, and a second groove 14 extending from the surface 3 side to the back surface 6 side is formed along the division planned line 4 in the substrate 2. In Embodiment 1, in the second groove forming step 106, the high-frequency power of a voltage capable of anisotropically etching the substrate 2 of the second wafer 1-2 is applied to the chuck table 32 for a predetermined time while supplying the plasma etching gas 31 so that the width of the second groove 14 gradually narrows from the width 14-2 on the surface 3 side toward the groove bottom. Note that the predetermined time is the time when the depth 14-1 of the second groove 14 is shallower than the thickness of the second wafer 1-2 and exceeds the finished thickness 12-2 of the second device chip 9-2. Further, the second groove 14 may be formed using not only anisotropic etching but also a so-called Bosch process.

[0035] In the second groove forming step 106, as shown in FIG. 11, the protective film 21 is removed from the surface 3 side of the second wafer 1-2 by supplying cleaning water to the surface 3 of the second wafer 1-2 or the like. Thus, in the second groove forming step 106, the second groove 14 having a depth 14-1 exceeding the finished thickness 12-2 of the second device chip 9-2 is formed by plasma processing using the plasma etching gas 31. Further, the second groove 14 is formed as a groove having a width 14-2 on the surface 3 side wider than the width 13-2 of the first groove 13 and a width 14-3 on the groove bottom side narrower than the width 14-2 on the surface 3 side.

[0036] (Bonding step) FIG. 12 is a cross-sectional view schematically showing a main part of the first wafer and the second wafer after the bonding step of the method for manufacturing the laminated device chip shown in FIG. 4. The bonding step 107 is a step of facing the back surface 6 of the polished first wafer 1-1 and the surface 3 of the second wafer 1-2 and bonding the second wafer 1-2 to the first wafer 1-1 so that the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 is accommodated in the second groove 14 of the second wafer 1-2.

[0037] In the bonding step 107, the back surface 6 of the first wafer 1-1 and the front surface 3 of the second wafer 1-2 are faced at positions where the devices 5 overlap each other, the front surface 3 of the second wafer 1-2 is overlapped with the back surface 6 of the first wafer 1-1, the grooves 13 and 14 are overlapped with each other, and the first resin layer 11-1 is accommodated in the second groove 14. In the bonding step 107, as shown in FIG. 12, the back surface 6 of the first wafer 1-1 and the front surface 3 of the second wafer 1-2 are joined to bond the second wafer 1-2 to the first wafer 1-1. In the first embodiment, in the bonding step 107, the through electrode 7 of the first wafer 1-1 is joined (connected) to the device 5 of the second wafer 1-2.

[0038] (Second Wafer Grinding Step) FIG. 13 is a cross-sectional view schematically showing a main part of the first wafer and the second wafer after the second wafer grinding step of the method for manufacturing a laminated device chip shown in FIG. 4. The second wafer grinding step 108 is a step of grinding the second wafer 1-2 bonded to the first wafer 1-1 from the back surface 6 side to expose the second groove 14 on the back surface 6 side of the second wafer 1-2.

[0039] In the second wafer grinding step 108, the grinding device sucks and holds the surface 3 side of the first wafer 1-1 to the holding surface of the chuck table via the support 20. In the second wafer grinding step 108, the grinding device rotates a grinding wheel for grinding around the axis by the spindle and rotates the chuck table around the axis, and while supplying grinding fluid from a grinding fluid nozzle (not shown), the grinding stone of the grinding wheel is brought into contact with the back surface 6 of the substrate 2 of the second wafer 1-2 and approached to the chuck table at a predetermined feed rate, and the back surface 6 side of the second wafer 1-2 is ground with the grinding stone.

[0040] In Embodiment 1, in the second wafer grinding step 108, as shown in FIG. 13, the grinding device grinds the back surface 6 side of the second wafer 1-2 until the thickness of the second wafer 1-2 becomes the finished thickness 12-2 of the second device chip 9-2. For this purpose, in Embodiment 1, in the second wafer grinding step 108, the grinding device exposes the second groove 14 and the through electrode 7 on the back surface 6 of the second wafer 1-2.

[0041] (Second resin layer formation step) FIG. 14 is a cross-sectional view schematically showing the main parts of the first wafer and the second wafer after the second resin layer formation step of the manufacturing method of the laminated device chip shown in FIG. 4. The second resin layer formation step 109 is a step of forming a resin layer 11 (hereinafter referred to as the second resin layer 11-2) in the second groove 14 of the second wafer 1-2.

[0042] In the second resin layer formation step 109, a resin softened by heating or the like is supplied into the second groove 14 of the second wafer 1-2, and this resin is coated on the back surface 6 of the second wafer 1-2. As shown in FIG. 14, the second resin layer 11-2 is formed in the second groove 14, and the back surface 6 of the second wafer 1-2 is coated with the second resin layer 11-2. Then, the resin layer 11 is formed by the resin layers 11-1 and 11-2.

[0043] (Dicing step) FIG. 15 is a cross-sectional view schematically showing the main parts of the first wafer and the second wafer after the dicing step of the manufacturing method of the laminated device chip shown in FIG. 4. The dicing step 110 is a step of cutting the first resin layer 11-1 and the second resin layer 11-2 along the first groove 13 and the second groove 14 to manufacture the laminated device chip 10.

[0044] In the dividing step 110, the cutting device sucks and holds the back surface 6 side of the first wafer 1-1 via the support 20 on the holding surface of the chuck table. In the dividing step 110, the cutting device relatively moves the cutting blade rotated by the spindle and the chuck table along the dividing planned line 4, and cuts the cutting blade into the center in the width direction of the grooves 13 and 14 from the back surface 6 side of the second wafer until it reaches the support 20. In the dividing step 110, as shown in FIG. 15, the cutting device cuts the resin layers 11-1 and 11-2 in the grooves 13 and 14, divides the wafers 1-1 and 1-2 into individual laminated device chips 10, and manufactures the laminated device chips 10.

[0045] Note that the thickness of the cutting blade that cuts the resin layers 11-1 and 11-2 in the grooves 13 and 14 in the dividing step 110 is thinner than the thickness of the cutting blade that forms the first groove 13 in the first groove forming step 101. The manufactured laminated device chip 10 is picked up from the support 20.

[0046] The method for manufacturing a laminated device chip according to Embodiment 1 described above forms the widths 14-2 and 14-3 of the second groove 14 of the second wafer 1-2 bonded to the first wafer 1-1 so that the surface 3 side is wider, so that even if there is a first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1, this first resin layer 11-1 is accommodated in the second groove 14 of the second wafer 1-2. For this reason, the method for manufacturing a laminated device chip according to Embodiment 1 does not prevent the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 from joining the wafers 1-1 and 1-2, that is, the device chips 9-1 and 9-2. As a result, the method for manufacturing a laminated device chip according to Embodiment 1 has the effect of suppressing the hindrance to the joining of the device chips 9-1 and 9-2.

[0047] 〔Embodiment 2〕 The method for manufacturing a laminated device chip according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 16 is a flowchart showing the process of the manufacturing method of the stacked device chip according to Embodiment 2. FIG. 17 is a cross-sectional view schematically showing the main part of the first wafer and the second wafer after the second wafer grinding step of the manufacturing method of the stacked device chip shown in FIG. 16. FIG. 18 is a cross-sectional view schematically showing the main part of the first wafer and the second wafer after the second resin layer forming step of the manufacturing method of the stacked device chip shown in FIG. 16. FIG. 19 is a cross-sectional view schematically showing the main part of the first wafer and the second wafer after the second wafer polishing step of the manufacturing method of the stacked device chip shown in FIG. 16. FIG. 20 is a cross-sectional view schematically showing the main part of the first wafer and the second wafer after the dicing step of the manufacturing method of the stacked device chip shown in FIG. 16. Note that the same reference numerals are given to the same parts as those in Embodiment 1 in FIGS. 16, 17, 18, 19, and 20, and the description thereof is omitted.

[0048] As shown in FIG. 16, the manufacturing method of the stacked device chip according to Embodiment 2 includes a second wafer polishing step 111 of simultaneously polishing the second wafer 1-2 fixed to the first wafer 1-1 and the second resin layer 11-2 after the second resin layer forming step 109 is performed and before the dicing step 110, and thinning the second wafer 1-2 to a thickness corresponding to the finished thickness 12-2 of the second device chip 9-2. Except that the second wafer grinding step 108 and the dicing step 110 are different from those in Embodiment 1, it is the same as Embodiment 1.

[0049] In the second wafer grinding step 108 of the manufacturing method of the stacked device chip according to Embodiment 2, the grinding device sucks and holds the surface 3 side of the first wafer 1-1 through the support 20 on the holding surface of the chuck table. In Embodiment 2, in the second wafer grinding step 108, as shown in FIG. 17, the grinding device grinds the back surface 6 side of the second wafer 1-2 until the thickness of the second wafer 1-2 becomes thicker than the finished thickness 12-2 of the second device chip 9-2 and thinner than the depth 15-1 of the second groove 14. For this purpose, in Embodiment 2, in the second wafer grinding step 108, the grinding device exposes at least the second groove 14 on the back surface 6 of the second wafer 1-2.

[0050] In the second resin layer formation step 109 of the method for manufacturing a laminated device chip according to Embodiment 2, as shown in FIG. 18, similarly to Embodiment 1, a second resin layer 11-2 is formed in the second groove 14, and the back surface 6 of the second wafer 1-2 is covered with the second resin layer 11-2. Then, the resin layer 11 is formed by the resin layers 11-1 and 11-2.

[0051] In the second wafer polishing step 111, the polishing device sucks and holds the surface 3 side of the first wafer 1-1 through the support 20 on the holding surface of the chuck table. In the second wafer polishing step 111, the polishing device brings a polishing pad rotated around the axis closer to the chuck table rotated around the axis at a predetermined feed rate, and polishes the second resin layer 11-2 on the back surface 6 of the second wafer 1-2 with a polishing member. Then, the second resin layer 11-2 on the back surface 6 is removed, and the back surface 6 of the second wafer 1-2, the through electrode 7, and the second groove 14 are exposed on the back surface 6 side.

[0052] In Embodiment 2, in the second wafer polishing step 111, as shown in FIG. 19, the polishing and thinning device simultaneously polishes and thins the back surface 6 of the second wafer 1-2 and the second resin layer 11-2 in the second groove 14 until the thickness of the second wafer 1-2 becomes the finished thickness 12-2 of the second device chip 9-2.

[0053] In Embodiment 2, in the dicing step 110, similarly to Embodiment 1, the dicing device cuts the resin layers 11-1 and 11-2 in the grooves 13 and 14, and dices the wafers 1-1 and 1-2 into individual laminated device chips 10-2 to manufacture the laminated device chip 10. Note that the back surface 6 of the second device chip 9-2 of the laminated device chip 10-2 is exposed without being covered by the resin layer 11.

[0054] In the method for manufacturing a stacked device chip according to Embodiment 2, by forming the widths 14-2 and 14-3 of the second groove 14 in the second wafer 1-2 bonded to the first wafer 1-1 such that the surface 3 side is wider, even if there is a first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1, this first resin layer 11-1 can be accommodated in the second groove 14 of the second wafer 1-2. Therefore, similar to Embodiment 1, the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 does not interfere with the bonding between the wafers 1-1 and 1-2, that is, between the device chips 9-1 and 9-2. As a result, the method for manufacturing a stacked device chip according to Embodiment 2, similar to Embodiment 1, has the effect of being able to suppress interference with the bonding between the device chips 9-1 and 9-2. Also, similar to bonding the first wafer 1-1 and the second wafer 1-2, the surface 3 of a third wafer 1 (equivalent to the wafers 1-1 and 1-2) having a groove formed in the back surface 6 of the second wafer 1-2 in the same manner as the groove 14 of the second wafer 1-2 may be bonded to form a stacked device chip 10 in which the device chips 9 are stacked in three or more layers.

[0055] 〔Modification Example 1〕 The method for manufacturing a stacked device chip according to Modification Example 1 of Embodiment 1 and Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 21 is a perspective view schematically showing the second groove forming step of the method for manufacturing a stacked device chip according to Modification Example 1 of Embodiment 1 and Embodiment 2. In addition, the same reference numerals are given to the same parts as in Embodiment 1, and the description thereof is omitted.

[0056] The manufacturing method of the stacked device chip according to Modification Example 1 is the same as that of Embodiment 1 and Embodiment 2 except that the second groove forming step 106 is different. In Modification Example 1, in the second groove forming step 106, the cutting device 40 sucks and holds the back surface 6 side of the second wafer 1-2 on the holding surface 42 of the chuck table 41, and while relatively moving the cutting blade 44 rotated by the spindle 43 and the chuck table 41 along the division planned line 4, the cutting blade 44 is cut into the division planned line 4 from the surface 3 side to the aforementioned depth 14-1, and as shown in FIG. 21, the second groove 14 is formed in each division planned line 4. Note that the cutting edge of the cutting blade 44 is gradually formed thinner toward the outer edge. Thus, in Modification Example 1, in the second groove forming step 106, the second groove 14 is formed by cutting using the cutting blade 44.

[0057] In the manufacturing method of the stacked device chip according to Modification Example 1, since the widths 14-2 and 14-3 of the second groove 14 of the second wafer 1-2 are formed such that the surface 3 side is wider, the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 can be accommodated in the second groove 14. Similar to Embodiment 1 and the like, it is possible to suppress the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 from interfering with the bonding between the wafers 1-1 and 1-2, that is, between the device chips 9-1 and 9-2, and there is an effect that it is possible to suppress the hindrance to the bonding between the device chips 9-1 and 9-2.

[0058] 〔Modification Example 2〕 The manufacturing method of the stacked device chip according to Modification Example 2 of Embodiment 1 and Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 22 is a perspective view schematically showing the second groove forming step of the manufacturing method of the stacked device chip according to Modification Example 2 of Embodiment 1 and Embodiment 2. Note that the same reference numerals are given to the same parts as in Embodiment 1, and the description thereof is omitted.

[0059] The manufacturing method of the laminated device chip according to Modification 2 is the same as that of Embodiment 1 and Embodiment 2 except that the second groove formation step 106 is different. In Modification 2, in the second groove formation step 106, the laser processing apparatus 50 sucks and holds the back surface 6 side of the second wafer 1-2 on the holding surface 52 of the chuck table 51, and moves the laser beam irradiation unit 53 and the chuck table 51 relatively along the division planned line 4 while irradiating the second wafer 1-2 with a laser beam 54 having an absorbable wavelength from the surface 3 side to the division planned line 4, and forms second grooves 14 in each division planned line 4 as shown in FIG. 22. Thus, in Modification 2, in the second groove formation step 106, the second grooves 14 are formed by laser processing using the laser beam 54.

[0060] In the manufacturing method of the laminated device chip according to Modification 2, since the widths 14-2 and 14-3 of the second grooves 14 of the second wafer 1-2 are formed such that the surface 3 side is wider, the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 can be accommodated in the second grooves 14. Similar to Embodiment 1 and the like, it is possible to suppress the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 from interfering with the bonding of the wafers 1-1 and 1-2, that is, the device chips 9-1 and 9-2, and there is an effect that it is possible to suppress the hindrance to the bonding of the device chips 9-1 and 9-2.

[0061] 〔Modification 3〕 The manufacturing method of the laminated device chip according to Modification 3 of Embodiment 1 and Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 23 is a cross-sectional view schematically showing a main part of the second wafer after the second groove formation step in the manufacturing method of the laminated device chip according to Modification 3 of Embodiment 1 and Embodiment 2. In addition, the same reference numerals are given to the same parts as those in Embodiment 1 in FIG. 23, and the description thereof is omitted.

[0062] The manufacturing method of the stacked device chip according to Modification 3 is the same as that of Embodiment 1 and Embodiment 2 except that the second groove formation step 106 is different. In Modification 3, in the second groove formation step 106, a cutting device having two cutting blades (hereinafter referred to as the first cutting blade and the second cutting blade) sucks and holds the back surface 6 side of the second wafer 1-2 on the holding surface of the chuck table, and while relatively moving the first cutting blade that rotates by a spindle and the chuck table along the division planned line 4, the first cutting blade is cut into the division planned line 4 from the surface 3 side to the aforementioned depth 14-1.

[0063] In Modification 3, in the second groove formation step 106, the cutting device cuts the second cutting blade from the surface 3 side while relatively moving the second cutting blade that rotates by a spindle and the chuck table along the division planned line 4. Note that in Modification 3, the thickness of the cutting edge of the first cutting blade is equal to the width 13-2 and is constant in the radial direction, and the thickness of the cutting edge of the second cutting blade is equal to the width 14-2 and is constant in the radial direction. Thus, in Modification 3, in the second groove formation step 106, a second groove 14 including a narrow groove 14-4 having a width 14-3 with a depth 14-1 and a wide groove 14-5 having a width 14-2 continuous with the surface 3 side of the narrow groove 14-4 is formed by a so-called step cut. The second groove 14 formed in Modification 3 is formed into a groove that is wider than the width 13-2 of the first groove 13 at the width 14-2 on the surface 3 side and narrower than the width 14-2 on the surface 3 side at the width 14-3 on the groove bottom side.

[0064] Since the manufacturing method of the stacked device chip according to Modification 3 forms the widths 14-2 and 14-3 of the second groove 14 of the second wafer 1-2 so that the surface 3 side is wider, the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 can be accommodated in the second groove 14. Similar to Embodiment 1 and the like, it is possible to suppress the first resin layer 11-1 protruding from the back surface 6 of the first wafer 1-1 from interfering with the bonding between the wafers 1-1 and 1-2, that is, between the device chips 9-1 and 9-2, and there is an effect that it is possible to suppress the hindrance to the bonding between the device chips 9-1 and 9-2.

[0065] Note that the present invention is not limited to the above-described embodiments. That is, various modifications can be made and implemented without departing from the gist of the present invention. For example, the first groove formation step 101 may be implemented by plasma etching using the plasma etching apparatus 30 as in the second groove formation step 106. Further, a grinding step of grinding the first resin layer 11-1 on the back surface 6 of the first wafer 1-1 with a grinding wheel attached to a grinding device may be provided between the first resin layer formation step 104 and the first wafer polishing step 105.

Explanation of Reference Numerals

[0066] 1 Wafer 1-1 First Wafer 1-2 Second Wafer 3 Front Surface 4 Scribing Line 5 Device 6 Back Surface 9 Device Chip 9-1 First Device Chip 9-2 Second Device Chip 10,10-2 Stacked Device Chip 11-1 First Resin Layer 11-2 Second Resin Layer 12-1 Finished Thickness 12-2 Finished Thickness 13 First Groove 13-1 Depth 14 Second Groove 14-1 Depth 14-2,14-3 Width 20 Support 31 Plasma Etching Gas (Plasma Gas) 44 Cutting Blade 54 Laser Beam 101 First Groove Formation Step 102 Fixing Step 103 First Wafer Grinding Step 104 First Resin Layer Formation Step 105 First Wafer Polishing Step 106 Second Groove Formation Step 107 Bonding step 108 Second wafer grinding step 109 Second resin layer formation step 110 Dicing step 111 Second wafer polishing step

Claims

1. A method for manufacturing a stacked device chip in which a plurality of device chips are stacked, using a wafer in which devices are provided in a plurality of regions of a surface partitioned by a plurality of planned division lines, comprising: a first groove forming step of forming a first groove having a depth exceeding the finished thickness of a first device chip from the surface of the first wafer along the plurality of planned division lines of the first wafer; a fixing step of fixing the front surface side of the first wafer to a support; a first wafer grinding step of grinding the first wafer fixed to the support from the back surface side to expose the first groove on the back surface side of the first wafer; a first resin layer forming step of forming a first resin layer in the first groove of the first wafer; a first wafer polishing step of polishing the first wafer fixed to the support and the first resin layer simultaneously to thin the first wafer to a thickness corresponding to the finished thickness of the first device chip and expose the first resin layer provided in the first groove on the back surface side of the first wafer; a second groove forming step of forming a second groove having a depth exceeding the finished thickness of a second device chip from the surface of the second wafer along the plurality of planned division lines of the second wafer having the same configuration as the first wafer, wherein the width of the second groove is wider than the width of the first groove on the front surface side of the second wafer and narrower than the width on the front surface side at the groove bottom side; a bonding step of facing the back surface of the polished first wafer and the front surface of the second wafer and bonding the second wafer to the first wafer such that the first resin layer protruding from the back surface of the first wafer is received in the second groove of the second wafer; a second wafer grinding step of grinding the second wafer bonded to the first wafer from the back surface side to expose the second groove on the back surface side of the second wafer; a second resin layer forming step of forming a second resin layer in the second groove of the second wafer; and a dividing step of cutting the first resin layer and the second resin layer along the first groove and the second groove to manufacture a stacked device chip. A method for manufacturing a stacked device chip comprising the above steps.

2. The method for manufacturing a stacked device chip according to claim 1, wherein in the second groove forming step, the second groove is formed by plasma etching using a plasma gas, cutting using a cutting blade, or laser processing using a laser beam.

3. The manufacturing method of the stacked device chip according to claim 1 or claim 2, comprising a second wafer polishing step of simultaneously polishing the second wafer fixed to the first wafer and the second resin layer after the second resin layer forming step and before the dividing step, and thinning the second wafer to a thickness corresponding to the finished thickness of the second device chip.

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