Semiconductor device management system and semiconductor device management method

Abstract

To provide a highly reliable semiconductor device at low cost.SOLUTION: A semiconductor device management system includes: an arithmetic unit that executes predetermined processing; an input unit for inputting data; and an output unit that outputs the processing result. The arithmetic unit includes: an adaptability calculation unit that calculates adaptability for each application of a semiconductor device formed on a semiconductor substrate from three-dimensional position information of crystal defects included in the semiconductor substrate, an impact rate of defects on device specifications, and operating conditions for each application of the semiconductor device; and a determination unit that determines each application of each semiconductor device on the basis of, the adaptability. The determination unit generates data for outputting at least the determined use.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device management system.

Background Art

[0002] In order to achieve carbon neutrality, the implementation of next-generation power semiconductor devices is being promoted in various fields, and it is expected to achieve both low loss and high reliability of power converters. On the other hand, semiconductor substrates used as semiconductor devices contain a wide variety of crystal defects and structural defects, and the influence they have on device reliability varies depending on defect information (defect type, size, position, etc.) and device applications (for automobiles, for trains, etc.). However, regardless of the crystal defects and structural defects contained in the semiconductor substrate, semiconductor devices have been manufactured using a semiconductor manufacturing process defined for a specified application.

[0003] As a method for manufacturing a semiconductor device using the position information of crystal defects in a semiconductor substrate, there is the following prior art. Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2020-4856) discloses a method for manufacturing a semiconductor device including preparing a semiconductor wafer, detecting crystal defects on the surface and inside of the semiconductor wafer, dividing the semiconductor wafer into a normal part and a defective part based on the positions where the crystal defects are detected, forming a plurality of semiconductor elements on the semiconductor wafer, subjecting the semiconductor elements formed in the normal part to an electrical characteristic inspection while excluding the semiconductor elements formed in the defective part from the inspection targets.

[0004] Patent Document 2 (Japanese Patent Application Laid-Open No. 2019-192859) describes a method for manufacturing a semiconductor device having a first silicon carbide substrate and an epitaxial layer formed on the first silicon carbide substrate. This manufacturing method includes a first step of acquiring defect position information of the epitaxial layer, a second step of acquiring micropipe position information of a second silicon carbide substrate cut out from the same crystal as the first silicon carbide substrate, and a third step of comparing the defect position information of the epitaxial layer with the micropipe position information of the second silicon carbide substrate to determine the micropipe positions existing in the epitaxial layer. A manufacturing method of a silicon carbide semiconductor device including these steps is described.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] As described above, regardless of crystal defects and structural defects contained in the semiconductor substrate, semiconductor devices were manufactured by a semiconductor manufacturing process defined for a specified use. Therefore, among the semiconductor devices manufactured on the semiconductor substrate, defective products that do not satisfy the reliability for the specified use may occur, and the manufacturing yield may decrease.

[0007] In the background art described above, the performance classification of the chip including the defect is determined according to the position of the defect contained in the semiconductor substrate. However, information on the use and operating conditions of the semiconductor device to be manufactured is not considered when determining the performance classification.

[0008] An object of the present invention is to provide a highly reliable and low-cost semiconductor device by determining at least one of a manufacturing process and an application based on position information of crystal defects included in a semiconductor substrate as a material and a result classified by application.

Means for Solving the Problems

[0009] A typical example of the invention disclosed in the present application is as follows. That is, a semiconductor device management system includes an arithmetic unit that executes a predetermined process, an input unit to which data is input, and an output unit that outputs a result of the process. The arithmetic unit calculates a degree of fitness for each application of a semiconductor device formed on a semiconductor substrate from three-dimensional position information of crystal defects contained in the semiconductor substrate, an influence rate of the defects on device specifications, and operating conditions for each application of the semiconductor device. The arithmetic unit has a fitness calculation unit, and a determination unit that determines each application for each of the semiconductor devices based on the fitness. The determination unit generates data for outputting at least the determined respective applications.

Effects of the Invention

[0010] According to one aspect of the present invention, it is possible to manufacture a semiconductor device by selecting a semiconductor substrate suitable for different device operating conditions depending on the application, or to select and ship a semiconductor device manufactured at a location within the substrate suitable for the device operating conditions, thereby providing a highly reliable and low-cost semiconductor device. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] FIG. 1 is a diagram showing an overall view of the solution provided by the semiconductor device management system 100 of the present embodiment.

[0013] The semiconductor device management system 100 of this embodiment provides a highly reliable and low-cost semiconductor device by selecting an appropriate semiconductor substrate for each application.

[0014] First, the semiconductor device manufacturer inspects the defects of the semiconductor substrate (step A) and inputs the inspection results and the process condition history into the semiconductor device management system 100 (step B).

[0015] The semiconductor device management system 100 calculates the three-dimensional information of the defects contained in the semiconductor substrate from the input inspection results (step C), and calculates the influence rate of the defects on the device specifications based on the calculated three-dimensional information of the defects, the input process condition history, and the predetermined device operation conditions for each application, and classifies the semiconductor substrates by application (step D). Then, the semiconductor device manufacturer determines the subsequent manufacturing process or application (step E) and ships the manufactured semiconductor device to the semiconductor device user.

[0016] In this way, by manufacturing a semiconductor device using the calculation result of the semiconductor device management system 100, a semiconductor device manufactured with the right material in the right place and meeting the reliability requirements can be supplied at low cost.

[0017] FIG. 2 is a diagram showing the hardware configuration of the semiconductor device management system 100 of this embodiment and the configuration of the devices connected to the semiconductor device management system 100.

[0018] The semiconductor device management system 100 of this embodiment is configured by a computer having a processor (CPU), a memory, a storage unit, a communication interface, an input interface, and an output interface.

[0019] The processor is an arithmetic unit that executes programs stored in the memory and constitutes the arithmetic unit 110. By the processor executing the programs stored in the storage unit 120, the functions of each functional unit of the semiconductor device management system 100 (for example, the defect analysis unit 111, the deterioration rate / remedy rate calculation unit 112, the matching rate calculation unit 113, the application classification unit 114, the listing unit 115, the determination unit 116, etc.) are realized. Note that part of the processing performed by the processor when executing a program may be executed by another arithmetic unit (for example, hardware such as an ASIC or FPGA).

[0020] The memory includes a ROM which is a non-volatile memory element and a RAM which is a volatile memory element. The ROM stores unchangeable programs (for example, BIOS). The RAM is a high-speed and volatile memory element such as a DRAM (Dynamic Random Access Memory), and temporarily stores the programs executed by the processor and the data used when the programs are executed.

[0021] The storage unit is composed of a large-capacity and non-volatile storage device such as a magnetic storage device (HDD) or a flash memory (SSD), and stores the programs executed by the processor (defect analysis program 131, deterioration rate / remedy rate calculation program 132, matching rate calculation program 133, application classification program 134, listing program 135, determination program 136, etc.), and the data used by the processor when executing the programs (for example, substrate information 141, defect inspection results 142, three-dimensional defect information 143, defect influence rate 144, device operating conditions 145, process condition history 146, deterioration rate / remedy rate 147, matching rate 148, classification results according to application 149, defect inactivation rate 150, etc.). That is, the programs are read from the storage unit, loaded into the memory, and executed by the processor to realize each functional unit of the semiconductor device management system 100.

[0022] The communication interface is a network interface device that controls communication with other devices (such as inspection device 200, terminal 210, etc.) according to a predetermined protocol. The semiconductor device management system 100 is connected to the inspection device 200, terminal 210, etc. via a network (such as a LAN).

[0023] The input interface is an interface to which input devices such as a keyboard, touch panel, mouse, etc. are connected and that receives input from an operator. The output interface is an interface to which output devices such as a display device and a printer are connected and that outputs the execution result of a program in a form visible to the operator. Note that the terminal 210 connected to the semiconductor device management system 100 via a network may provide an input device and an output device. In this case, the semiconductor device management system 100 may have the function of a web server, and the terminal 210 may access the semiconductor device management system 100 according to a predetermined protocol (such as http).

[0024] The program executed by the processor is provided to the semiconductor device management system 100 via a removable medium (such as a CD-ROM, flash memory, etc.) or a network and is stored in a non-volatile storage unit that is a non-temporary storage medium. For this reason, the semiconductor device management system 100 preferably has an interface for reading data from a removable medium.

[0025] The semiconductor device management system 100 is a computer system configured physically on one computer or logically or physically on a plurality of computers, and may operate on a virtual computer constructed on a plurality of physical computer resources. For example, the defect analysis unit 111, the deterioration rate / relief rate calculation unit 112, the matching rate calculation unit 113, the application classification unit 114, the listing unit 115, and the determination unit 116 may each operate on a separate physical or logical computer, or a plurality of them may be combined to operate on one physical or logical computer.

[0026] A semiconductor device manufacturer is equipped with an inspection apparatus 200, a terminal 210, and a semiconductor manufacturing apparatus (chamber) 220.

[0027] The inspection apparatus 200 has a processor (CPU), a memory, a storage device, a communication interface, an input interface, an output interface, and a control device, and inspects defects on a semiconductor substrate. The inspection apparatus 200 is connected to the semiconductor device management system 100 via a network, and transmits the inspection result of the semiconductor substrate to the terminal 210 according to an instruction from the terminal 210. Note that the inspection result may be directly transmitted to the semiconductor device management system 100. Further, the inspection apparatus 200 is communicably connected to the semiconductor manufacturing apparatus 220, and may send the process condition history 146 collected from the semiconductor manufacturing apparatus 220 to the semiconductor device management system 100.

[0028] The terminal 210 is composed of a computer having a processor (CPU), a memory, a storage device, a communication interface, an input interface, and an output interface, and receives calculation results (for example, the influence rate on the device specifications of defects, the classification of the semiconductor substrate) output from the semiconductor device management system 100.

[0029] FIG. 3 is a diagram showing the logical configuration of the semiconductor device management system 100 of the present embodiment.

[0030] The semiconductor device management system 100 has an arithmetic unit 110 realized by a processor executing a program, and a storage unit 120 for storing a program 130 and data 140.

[0031] The arithmetic unit 110 realizes a defect analysis unit 111, a deterioration rate / remedy rate calculation unit 112, a matching rate calculation unit 113, an application classification unit 114, a listing unit 115, and a determination unit 116 by executing a program.

[0032] The program 130 stored in the memory unit 120 includes a defect analysis program 131, a deterioration rate / remedy rate calculation program 132, a matching rate calculation program 133, an application classification program 134, a listing program 135, and a determination program 136.

[0033] The defect analysis unit 111 analyzes the three-dimensional defects of the semiconductor substrate from the inspection results of the semiconductor substrate by executing the defect analysis program 131.

[0034] The deterioration rate / remedy rate calculation unit 112 calculates, for each device application, the probability (deterioration rate) that the electrical characteristics of the semiconductor device formed on the semiconductor substrate deviate from the desired conditions, and the probability (remedy rate) that the electrical characteristics become the desired conditions (good product) due to the defect area being inactivated by changes in the manufacturing process after the occurrence of the defect, by executing the deterioration rate / remedy rate calculation program 132.

[0035] The matching rate calculation unit 113 calculates the matching rate for each device application of the semiconductor substrate or chip from the crystal defect information of the input semiconductor substrate (see FIG. 10), the defect influence rate 144 on the device specification (see FIG. 11), and the device operating conditions 145 for each application (see FIG. 12) by executing the matching rate calculation program 133. The matching rate is an index indicating the degree of suitability of a certain semiconductor substrate (or a chip formed on the semiconductor substrate) for a semiconductor device of a certain application, and is represented by a value from 0 to 1, where 0 indicates no suitability at all.

[0036] The application classification unit 114 classifies the semiconductor substrate (or the chip formed on the semiconductor substrate) according to the calculated matching rate 148 by executing the application classification program 134. The listing unit 115 lists the classification results 149 according to the application of the semiconductor substrate (or the chip formed on the semiconductor substrate) by executing the listing program 135. The determination unit 116 determines the semiconductor substrate (or the chip formed on the semiconductor substrate) using the listed results by executing the determination program 136.

[0037] The data 140 stored in the memory unit 120 includes substrate information 141, defect inspection results 142, three-dimensional defect information 143, defect influence rate 144, device operating conditions 145, process condition history 146, deterioration rate / remedy rate 147, matching rate 148, classification result according to use 149, and defect inactivation rate 150.

[0038] The substrate information 141 is information about the semiconductor substrate, including the slot number, lot number, wafer number, imprint ID, information regarding the quality of the substrate, and the like. The slot number is identification information of the slot within the carrier in which the semiconductor substrate is stored. The lot number is identification information of the manufacturing process of the semiconductor substrate. The wafer number is identification information of the semiconductor substrate. The imprint ID is identification information attached to the semiconductor substrate. The information regarding the quality of the substrate includes information such as the diameter, thickness, impurity concentration contained, and information that indexes the goodness or badness of the crystal state of the substrate. The defect inspection result 142 is information about crystal defects contained in the semiconductor substrate, acquired from the inspection apparatus 200. The three-dimensional defect information 143 is information about three-dimensional defects of the semiconductor substrate analyzed by the defect analysis unit 111, and its configuration example will be described later with reference to FIG. 10. The defect impact rate 144 records the impact rate of the defects on the device specifications, and its configuration example will be described later with reference to FIG. 11. The device operating conditions 145 record the operating conditions of the semiconductor device for each application, and its configuration example will be described later with reference to FIG. 12. The process condition history 146 is the process condition during the manufacture of the semiconductor device formed using the semiconductor substrate. The deterioration rate · recovery rate 147 consists of the deterioration rate, which is the probability that the electrical characteristics of the semiconductor device formed on the semiconductor substrate deviate from the desired conditions, and the recovery rate, which is the probability that the defective region is inactivated by the change in the manufacturing process after the occurrence of the defect, resulting in the electrical characteristics being in the desired conditions (good product). The matching rate 148 is the degree of suitability of a certain semiconductor substrate (or a chip formed on the semiconductor substrate) for a semiconductor device for a certain application, and its configuration example will be described later with reference to FIGS. 13 and 14. The classification result 149 by application is the result of classifying the semiconductor substrate (or a chip formed on the semiconductor substrate) based on the calculated matching rate 148. For example, it is the order of suitability for each application, that is, the order of the highest matching rate for each application, and its configuration example will be described later with reference to the screen shown in FIG. 18. The defect inactivation rate 150 is the probability that, for each defect, the defective region is inactivated by the change in the manufacturing process after the occurrence of the defect, resulting in the electrical characteristics being in the desired conditions (good product), and its configuration example will be described later with reference to FIG. 15.

[0039] Figure 4 is a sequence diagram of the processes executed by the semiconductor device management system 100 of this embodiment. In the example shown in Figure 4, the semiconductor device management system 100 selects semiconductor substrates based on the inspection results of crystal defects.

[0040] First, an operator of the semiconductor device manufacturer inputs information of the semiconductor substrate into the terminal 210 (500). The information of the semiconductor substrate input into the terminal 210 is transmitted to the semiconductor device management system 100, received by the communication interface in the semiconductor device management system 100 (501), and stored in the storage unit 120 (502). Note that the input and storage of the information of the semiconductor substrate can be omitted.

[0041] Next, the operator instructs the inspection apparatus 200 to inspect the semiconductor substrate (510). The inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction and outputs the inspection result to the terminal 210 (511). The terminal 210 transmits the input inspection result and the analysis request of the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 by the communication interface (512) and stores it in the storage unit 120 (513). For example, crystal defects existing in the semiconductor substrate are inspected.

[0042] Thereafter, the arithmetic unit 110 (defect analysis unit 111) of the semiconductor device management system 100 executes the defect analysis program 131, analyzes the three-dimensional defects of the semiconductor substrate for which analysis is requested using the inspection result read from the storage unit 120 (514), and stores the three-dimensional defect information 143 in the storage unit 120 (515).

[0043] Next, the arithmetic unit 110 (matching rate calculation unit 113) executes the matching rate calculation program 133, and uses the three-dimensional defect information 143 read from the storage unit 120, the defect impact rate 144 which is a list of the influence rates of the defects on the device specifications, and the device operation conditions 145 for each application to calculate (533) the matching rate 148 for each device application of the semiconductor substrate, and stores the calculation result in the storage unit 120 (534). Details of the matching rate calculation process 533 will be described later with reference to FIG. 9.

[0044] Next, the arithmetic unit 110 (application classification unit 114) executes the application classification program 134, classifies (535) the semiconductor substrate using the matching rate read from the storage unit 120, and stores the classification result in the storage unit 120 (536).

[0045] On the other hand, the operator inputs the application of the manufactured semiconductor device to the terminal 210 and requests the determination of the semiconductor substrate (540). The terminal 210 transmits the classification request for the input application of the semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives (541) the application of the semiconductor device transmitted from the terminal 210 through the communication interface, and stores it in the storage unit 120 (542). Note that the input of the application of the semiconductor device may be before the input of the information of the semiconductor substrate.

[0046] Next, the arithmetic unit 110 (listing unit 115, determination unit 116) executes the listing program 135 and the determination program 136, lists the classification result 149 read from the storage unit 120, determines (543) the semiconductor substrate, and outputs (544) the determination result to the terminal 210 via the communication interface.

[0047] When the terminal 210 receives the determination result, it presents it to the operator in a form recognizable by humans (545).

[0048] As described above, in the form shown in FIG. 4, the semiconductor device management system 100 outputs information for selecting a semiconductor substrate by referring to the three-dimensional defect information 143 obtained from the inspection result 142 of the defects on the semiconductor substrate, the influence rate 144 of the defects on the device specifications, and the device operation conditions 145 that vary depending on the application. Therefore, a semiconductor substrate suitable for the device operation conditions 145 that vary depending on the application can be selected to manufacture a semiconductor device, and a highly reliable and low-cost semiconductor device can be provided.

[0049] FIG. 5 is a sequence diagram of the processes executed by the semiconductor device management system 100 according to Modification 1 of the present embodiment. In Modification 1 shown in FIG. 5, the semiconductor device management system 100 selects semiconductor devices manufactured on a semiconductor substrate based on the inspection results of crystal defects.

[0050] First, an operator of the semiconductor device manufacturer inputs information on the semiconductor substrate to the terminal 210 (500). The information on the semiconductor substrate input to the terminal 210 is transmitted to the semiconductor device management system 100, received by the communication interface in the semiconductor device management system 100 (501), and stored in the storage unit 120 (502). Note that the input and storage of the information on the semiconductor substrate can be omitted.

[0051] Next, the operator instructs the inspection apparatus 200 to inspect the semiconductor substrate (510). The inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (511). The semiconductor manufacturing apparatus 220 manufactures semiconductor devices after the inspection. Also, the terminal 210 transmits the input inspection result and the analysis request for the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 by the communication interface (512) and stores it in the storage unit 120 (513). For example, this inspection inspects crystal defects existing on the semiconductor substrate.

[0052] After that, the arithmetic unit 110 (defect analysis unit 111) of the semiconductor device management system 100 executes a defect analysis program 131, analyzes the three-dimensional defects of the semiconductor substrate for which analysis is requested using the inspection results read from the storage unit 120 (514), and stores three-dimensional defect information 143 in the storage unit 120 (515).

[0053] Next, the arithmetic unit 110 (matching rate calculation unit 113) executes a matching rate calculation program 133, and uses the three-dimensional defect information 143 read from the storage unit 120, the defect influence rate 144 which is a list of the influence rate of defects on the device specifications, and the device operating conditions 145 for each application to calculate the matching rate 148 for each device application of the chip (533), and stores the calculation result in the storage unit 120 (534). Details of the matching rate calculation process 533 will be described later with reference to FIG. 9.

[0054] Next, the arithmetic unit 110 (application classification unit 114) executes an application classification program 134, classifies the semiconductor device using the matching rate 148 read from the storage unit 120 (535), and stores the classification result in the storage unit 120 (536).

[0055] On the other hand, after manufacturing the semiconductor device, the operator inputs the application of the manufactured semiconductor device to the terminal 210 and requests a determination of the semiconductor device (540). The terminal 210 transmits the classification request for the application of the input semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives the application of the semiconductor device transmitted from the terminal 210 through the communication interface (541) and stores it in the storage unit 120 (542). Note that the input of the application of the semiconductor device may be before the input of the information of the semiconductor substrate.

[0056] Next, the arithmetic unit 110 (listing unit 115, determination unit 116) executes a listing program 135 and a determination program 136, lists the classification result 149 read from the storage unit 120, determines the semiconductor device manufactured on the semiconductor substrate (543), and outputs the determination result to the terminal 210 via the communication interface (544).

[0057] When the terminal 210 receives the result of the determination, it presents it to the operator in a form recognizable by humans (545).

[0058] As described above, in the first modification example shown in FIG. 5, the semiconductor device management system 100 refers to the three-dimensional defect information 143 obtained from the inspection result 142 of the semiconductor substrate, the influence rate 144 of the defect on the device specification, and the device operation conditions 145 different depending on the application, and outputs information for selecting the semiconductor device formed on the semiconductor substrate. Therefore, it is possible to select and ship semiconductor devices manufactured at locations within the substrate suitable for the device operation conditions 145 different depending on the application, and provide highly reliable and low-cost semiconductor devices.

[0059] FIG. 6 is a sequence diagram of the processes executed by the semiconductor device management system 100 of the second modification example of the present embodiment. In the second modification example shown in FIG. 6, the semiconductor device management system 100 selects the manufactured semiconductor devices based on the inspection results of crystal defects and process defects that occurred during the manufacturing process of the semiconductor devices.

[0060] First, an operator of a semiconductor device manufacturer inputs information on a semiconductor substrate to the terminal 210 (500). The information on the semiconductor substrate input to the terminal 210 is transmitted to the semiconductor device management system 100, received by the communication interface in the semiconductor device management system 100 (501), and stored in the storage unit 120 (502). Note that the input and storage of information on the semiconductor substrate can be omitted.

[0061] Next, the operator instructs the inspection apparatus 200 to inspect the semiconductor substrate (510). The inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (511). The semiconductor manufacturing apparatus 220 manufactures semiconductor devices after the inspection. Also, the terminal 210 transmits the input inspection result and the analysis request of the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 through the communication interface (512) and stores it in the storage unit 120 (513). For example, this inspection inspects crystal defects present in the semiconductor substrate.

[0062] Thereafter, the arithmetic unit 110 (defect analysis unit 111) of the semiconductor device management system 100 executes the defect analysis program 131 and analyzes the three-dimensional defects of the semiconductor substrate for which analysis is requested using the inspection result read from the storage unit 120 (514), and stores the three-dimensional defect information 143 in the storage unit 120 (515).

[0063] Also, during the manufacturing process of the semiconductor device, the inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction (516) and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (517). The semiconductor manufacturing apparatus 220 adjusts the subsequent processes based on the inspection result and continues the manufacturing process of the semiconductor device. Also, the terminal 210 transmits the input inspection result and the analysis request of the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 through the communication interface (518) and stores it in the storage unit 120 (515). For example, this inspection inspects process defects such as patterning defects that have occurred in the semiconductor substrate.

[0064] Next, the arithmetic unit 110 (deterioration rate / salvage rate calculation unit 112) executes the deterioration rate / salvage rate calculation program 132, and uses the three-dimensional defect information 143 read from the storage unit 120, the process defect information, the defect impact rate 144 which is a list of the impact rate of the defect on the device specifications, and the device operating conditions 145 for each application to calculate (519) the probability that the electrical characteristics of the semiconductor device formed on the semiconductor substrate deviate from the desired conditions (deterioration rate), and the probability that the electrical characteristics become the desired conditions (good product) due to the defect area being inactivated by the change in the manufacturing process after the occurrence of the defect (salvage rate) for each device application, and stores the calculation result in the storage unit 120 (520).

[0065] Some process defects can be salvaged by changes in subsequent processes depending on their type, degree, and location. For chips where the deterioration rate is greater than a predetermined threshold and the salvage rate is greater than a predetermined threshold, the semiconductor device management system 100 instructs the semiconductor manufacturing apparatus 220 to change the subsequent processes so that the manufactured semiconductor device can obtain the desired characteristics (521).

[0066] In the main processes of the manufacturing process, according to the operator's instructions (516), the semiconductor substrate is inspected, the inspection result is output to the semiconductor manufacturing apparatus 220 and the terminal 210 (517), received by the semiconductor device management system 100 through the communication interface (518), stored in the storage unit 120 (515), the deterioration rate and the salvage rate are calculated for each device application (519), the calculation result is stored in the storage unit 120 (520), and based on the calculation result, the semiconductor manufacturing apparatus 220 is instructed to change the subsequent processes (521), and the process is repeated.

[0067] In the last main process, according to the operator's instructions (516), the semiconductor substrate is inspected, the inspection result is output to the semiconductor manufacturing apparatus 220 and the terminal 210 (517), received by the semiconductor device management system 100 through the communication interface (518), and stored in the storage unit 120 (515). Note that the inspection in this last main process can be omitted.

[0068] Next, the arithmetic unit 110 (matching rate calculation unit 113) executes the matching rate calculation program 133, and uses the three-dimensional defect information 143 read from the storage unit 120, the process defect information, and the Impact rate 144 and the device operation conditions 145 for each application to calculate (533) the matching rate 148 for each device application of the chip, and stores the calculation result in the storage unit 120 (534). Details of the matching rate calculation process 533 will be described later with reference to FIG. 9.

[0069] Next, the arithmetic unit 110 (application classification unit 114) executes the application classification program 134, classifies (535) the semiconductor device using the matching rate 148 read from the storage unit 120, and stores the classification result in the storage unit 120 (536).

[0070] On the other hand, after manufacturing the semiconductor device, the operator inputs the application of the manufactured semiconductor device to the terminal 210 and requests the determination of the semiconductor device (540). The terminal 210 transmits the classification request for the application of the input semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives (541) the application of the semiconductor device transmitted from the terminal 210 through the communication interface, and stores it in the storage unit 120 (542). Note that the input of the application of the semiconductor device may be before the input of the information of the semiconductor substrate.

[0071] Next, the arithmetic unit 110 (listing unit 115, determination unit 116) executes the listing program 135 and the determination program 136, lists the classification result 149 read from the storage unit 120, determines (543) the semiconductor device manufactured on the semiconductor substrate, and outputs (544) the determination result to the terminal 210 via the communication interface.

[0072] When the terminal 210 receives the determination result, it presents it to the operator in a form recognizable by humans (545).

[0073] As described above, in Modification Example 2 shown in FIG. 6, the semiconductor device management system 100 refers to the three-dimensional defect information 143 obtained from the inspection result 142 of the defects on the semiconductor substrate, the information on the process defects generated in the manufacturing process of the semiconductor device, the influence rate 144 of the defects on the device specifications, and the device operation conditions 145 that vary depending on the application, calculates the deterioration rate and the salvage rate for each device application, and determines a semiconductor device that can be salvaged by changing the subsequent processes. By changing the subsequent processes according to the determination result, the process defects are inactivated and the manufacturing yield is increased. In addition, the semiconductor device management system 100 refers to the three-dimensional defect information 143, the information on the process defects generated in the manufacturing process of the semiconductor device, the influence rate 144 of the defects on the device specifications, and the device operation conditions 145 that vary depending on the application, and outputs information for selecting the semiconductor devices formed on the semiconductor substrate. Therefore, semiconductor devices manufactured at locations within the substrate that are suitable for the device operation conditions 145 that vary depending on the application can be selected and shipped, and high-reliability and low-cost semiconductor devices can be provided.

[0074] FIG. 7 is a sequence diagram of the processes executed by the semiconductor device management system 100 of Modification Example 3 of the present embodiment. In Modification Example 3 shown in FIG. 7, the semiconductor device management system 100 selects the manufactured semiconductor devices based on the inspection results of crystal defects and the process condition history 146 in the manufacturing of the semiconductor device.

[0075] First, an operator of the semiconductor device manufacturer inputs the information of the semiconductor substrate to the terminal 210 (500). The information of the semiconductor substrate input to the terminal 210 is transmitted to the semiconductor device management system 100, received by the communication interface in the semiconductor device management system 100 (501), and stored in the storage unit 120 (502). Note that the input and storage of the information of the semiconductor substrate can be omitted.

[0076] Next, the operator instructs the inspection apparatus 200 to inspect the semiconductor substrate (510). The inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (511). The semiconductor manufacturing apparatus 220 manufactures semiconductor devices according to the inspection result input by the operator. Also, the terminal 210 transmits the input inspection result and the analysis request for the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 through the communication interface (512) and stores it in the storage unit 120 (513). For example, this inspection inspects crystal defects present in the semiconductor substrate.

[0077] Thereafter, the arithmetic unit 110 (defect analysis unit 111) of the semiconductor device management system 100 executes the defect analysis program 131 and uses the inspection result read from the storage unit 120 to analyze the three-dimensional defects of the semiconductor substrate for which analysis is requested (514), and stores the three-dimensional defect information 143 in the storage unit 120 (515).

[0078] Also, after manufacturing the semiconductor device, the operator inputs the process condition history 146 of the semiconductor device to the terminal 210 and requests classification of the semiconductor device (530). The terminal 210 transmits the required application for the input semiconductor device and the classification request for the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the process condition history 146 transmitted from the terminal 210 through the communication interface (531) and stores it in the storage unit 120 (532).

[0079] Next, the arithmetic unit 110 (matching rate calculation unit 113) executes the matching rate calculation program 133 and uses the three-dimensional defect information 143 read from the storage unit 120, the process condition history 146, the defect impact rate 144 which is a list of the influence rates of the defects on the device specifications, and the device operation conditions 145 for each application to calculate the matching rate 148 for each device application of the chip (533), and stores the calculation result in the storage unit 120 (534). Details of the matching rate calculation process 533 will be described later with reference to FIG. 9.

[0080] Next, the arithmetic unit 110 (application classification unit 114) executes the application classification program 134, classifies the semiconductor device (535) using the matching rate 148 read from the storage unit 120, and stores the classification result in the storage unit 120 (536).

[0081] On the other hand, after manufacturing the semiconductor device, the operator inputs the application of the manufactured semiconductor device into the terminal 210 and requests a determination of the semiconductor device (540). The terminal 210 transmits the classification request for the application of the input semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives the application of the semiconductor device transmitted from the terminal 210 through the communication interface (541) and stores it in the storage unit 120 (542). Note that the input of the application of the semiconductor device may be before the input of the information of the semiconductor substrate.

[0082] Next, the arithmetic unit 110 (listing unit 115, determination unit 116) executes the listing program 135 and the determination program 136, lists the classification result 149 read from the storage unit 120, determines the semiconductor device manufactured on the semiconductor substrate (543), and outputs the determination result to the terminal 210 via the communication interface (544).

[0083] When the terminal 210 receives the determination result, it presents it to the operator in a form recognizable by humans (545).

[0084] As described above, in Modification Example 2 shown in FIG. 7, the semiconductor device management system 100 refers to the three-dimensional defect information 143 obtained from the inspection result 142 of the defects on the semiconductor substrate, the process condition history 146 of the semiconductor device, the defect influence rate 144 on the device specifications, and the device operation conditions 145 that vary depending on the application, and outputs information for selecting the semiconductor devices formed on the semiconductor substrate. There is also a distribution of material quality within the substrate, and the material quality varies depending on the history of the process conditions. In Modification Example 2, by taking into account the information on the material quality that varies depending on the history of the process conditions, semiconductor devices manufactured at locations within the substrate that are suitable for the device operation conditions 145 that vary depending on the application can be selected and shipped, thus providing highly reliable and low-cost semiconductor devices.

[0085] FIG. 8 is a sequence diagram of the processes executed by the semiconductor device management system 100 of Modification Example 4 of the present embodiment. In Modification Example 4 shown in FIG. 8, the semiconductor device management system 100 selects the manufactured semiconductor devices based on the inspection results of crystal defects, the process defects that occurred during the manufacturing process of the semiconductor device, and the process condition history 146 in the manufacturing of the semiconductor device.

[0086] First, an operator of the semiconductor device manufacturer inputs the information of the semiconductor substrate into the terminal 210 (500). The information of the semiconductor substrate input into the terminal 210 is transmitted to the semiconductor device management system 100, received by the communication interface within the semiconductor device management system 100 (501), and stored in the storage unit 120 (502). Note that the input and storage of the information of the semiconductor substrate can be omitted.

[0087] Next, the operator instructs the inspection apparatus 200 to inspect the semiconductor substrate (510). The inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (511). After the inspection, the semiconductor manufacturing apparatus 220 manufactures semiconductor devices. Also, the terminal 210 transmits the input inspection result and the analysis request for the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 through the communication interface (512) and stores it in the storage unit 120 (513). For example, this inspection inspects crystal defects present in the semiconductor substrate.

[0088] Thereafter, the arithmetic unit 110 (defect analysis unit 111) of the semiconductor device management system 100 executes the defect analysis program 131, analyzes the three-dimensional defects of the semiconductor substrate for which analysis is requested using the inspection result read from the storage unit 120 (514), and stores the three-dimensional defect information 143 in the storage unit 120 (515).

[0089] Also, during the manufacturing process of the semiconductor device, the inspection apparatus 200 inspects the semiconductor substrate according to the operator's instruction (516) and outputs the inspection result to the semiconductor manufacturing apparatus 220 and the terminal 210 (517). The semiconductor manufacturing apparatus 220 adjusts the subsequent processes based on the inspection result and continues the manufacturing process of the semiconductor device. Also, the terminal 210 transmits the input inspection result and the analysis request for the semiconductor substrate to the semiconductor device management system 100. The semiconductor device management system 100 receives the inspection result transmitted from the terminal 210 through the communication interface (518) and stores it in the storage unit 120 (515). For example, this inspection inspects process defects such as patterning defects that have occurred in the semiconductor substrate.

[0090] Next, the arithmetic unit 110 (the deterioration rate / salvage rate calculation unit 112) executes the deterioration rate / salvage rate calculation program 132, and uses the three-dimensional defect information 143 read from the storage unit 120, the process defect information, the defect impact rate 144 which is a list of the impact rates of the defects on the device specifications, and the device operation conditions 145 for each application to calculate (519) the probability (deterioration rate) that the electrical characteristics of the semiconductor device formed on the semiconductor substrate deviate from the desired conditions, and the probability (salvage rate) that the electrical characteristics become the desired conditions (good products) due to the inactivation of the defect area by changing the manufacturing process after the occurrence of the defect for each device application, and stores the calculation results in the storage unit 120 (520).

[0091] Depending on the type, degree, and location of the process defect, there are some that can be salvaged by changing the subsequent process. For chips with a deterioration rate greater than a predetermined threshold and a salvage rate greater than a predetermined threshold, the semiconductor device management system 100 instructs the semiconductor manufacturing apparatus 220 to change the subsequent process (521) so that the manufactured semiconductor device can obtain the desired characteristics.

[0092] In the main process of the manufacturing process, according to the operator's instructions (516), the semiconductor substrate is inspected, the inspection results are output to the semiconductor manufacturing apparatus 220 and the terminal 210 (517), received by the semiconductor device management system 100 through the communication interface (518), stored in the storage unit 120 (515), the deterioration rate and the salvage rate are calculated for each device application (519), the calculation results are stored in the storage unit 120 (520), and based on the calculation results, the semiconductor manufacturing apparatus 220 is instructed to change the subsequent process (521), and the process is repeated.

[0093] In the last main process, according to the operator's instructions (516), the semiconductor substrate is inspected, the inspection results are output to the semiconductor manufacturing apparatus 220 and the terminal 210 (517), received by the semiconductor device management system 100 through the communication interface (518), and stored in the storage unit 120 (515). Note that the inspection in this last main process can be omitted.

[0094] Also, after manufacturing the semiconductor device, the operator inputs the process condition history 146 of the semiconductor device into the terminal 210 and requests classification of the semiconductor device (530). The terminal 210 transmits the input classification request of the semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives the process condition history 146 transmitted from the terminal 210 through the communication interface (531) and stores it in the storage unit 120 (532).

[0095] Next, the arithmetic unit 110 (matching rate calculation unit 113) executes the matching rate calculation program 133 and uses the three-dimensional defect information 143 read from the storage unit 120, the process defect information, the defect influence rate 144 which is a list of the influence rates of the defects on the device specifications, the process condition history 146, and the device operation conditions 145 for each application to calculate the matching rate 148 for each device application of the chip (533), and stores the calculation result in the storage unit 120 (534). Details of the matching rate calculation process 533 will be described later with reference to FIG. 9.

[0096] Next, the arithmetic unit 110 (application classification unit 114) executes the application classification program 134, classifies the semiconductor device using the matching rate 148 read from the storage unit 120 (535), and stores the classification result in the storage unit 120 (536).

[0097] On the other hand, after manufacturing the semiconductor device, the operator inputs the application of the manufactured semiconductor device into the terminal 210 and requests determination of the semiconductor device (540). The terminal 210 transmits the input classification request of the application of the semiconductor device to the semiconductor device management system 100. The semiconductor device management system 100 receives the application of the semiconductor device transmitted from the terminal 210 through the communication interface (541) and stores it in the storage unit 120 (542). Note that the input of the application of the semiconductor device may be before the input of the information of the semiconductor substrate.

[0098] Next, the arithmetic unit 110 (listing unit 115, determination unit 116) executes a listing program 135 and a determination program 136 to list the classification results 149 read from the storage unit 120, determine the semiconductor devices manufactured on the semiconductor substrate (543), and output the determination result to the terminal 210 via the communication interface (544).

[0099] When the terminal 210 receives the determination result, it presents it to the operator in a form recognizable by humans (545).

[0100] As described above, in Modification Example 4 shown in FIG. 8, the semiconductor device management system 100 refers to the three-dimensional defect information 143 obtained from the inspection result 142 of the semiconductor substrate, the process defect information generated in the manufacturing process of the semiconductor device, the influence rate 144 of the defect on the device specification, and the device operation conditions 145 that vary depending on the application, calculates the failure probability and the recovery rate for each device application, and determines the semiconductor devices that can be recovered by changing the subsequent processes. By changing the subsequent processes according to the determination result, the process defects are inactivated and the manufacturing yield is increased. In addition, the semiconductor device management system 100 refers to the three-dimensional defect information 143 of the semiconductor substrate, the process defect information generated in the manufacturing process of the semiconductor device, the influence rate 144 of the defect on the device specification, the history 146 of the process conditions, and the device operation conditions 145 that vary depending on the application, and outputs information for selecting the semiconductor devices formed on the semiconductor substrate. In Modification Example 4, by taking into account the information on the material quality that varies depending on the history of the process conditions, semiconductor devices manufactured at locations within the substrate suitable for the device operation conditions 145 that vary depending on the application can be selected and shipped, so that highly reliable and low-cost semiconductor devices can be provided.

[0101] FIG. 9 is a flowchart of the matching rate calculation process 533.

[0102] The matching rate calculation unit 113 (matching rate calculation program 133) of the semiconductor device management system 100 repeatedly executes the arithmetic processing after step S101 for each application of the semiconductor device until the arithmetic processing for all applications is completed.

[0103] First, the matching rate calculation unit 113 acquires the three-dimensional defect information of the semiconductor substrate analyzed by the defect analysis unit 111 from the three-dimensional defect information 143 (S101). The three-dimensional defect information 143 to be acquired may include the position (three-dimensional coordinates) of the defect in the semiconductor substrate, the type of the defect, the shape and size (width, length, area) of the defect, the type of the device manufactured with this semiconductor substrate, the position of the defect in the chip, and the like.

[0104] Next, the matching rate calculation unit 113 acquires the defect influence rate on the specifications for each device specification from the defect influence rate 144 (S102).

[0105] Then, the matching rate calculation unit 113 repeatedly executes the arithmetic processing from step S103 to step S111 for each chip until the arithmetic processing for all chips is completed.

[0106] Next, the matching rate calculation unit 113 determines whether there is a defect in the chip (S103). If there is no defect in the chip, since the characteristic degradation of the chip due to the defect does not occur, the matching rate of the chip is set to 1 (S104). On the other hand, if there is a defect in the chip, the matching rate calculation unit 113 repeatedly executes the arithmetic processing from step S105 to step S108 for each device specification until the arithmetic processing for all device specifications is completed.

[0107] Next, the matching rate calculation unit 113 determines whether the influence rate on the device specification is 1 (S105). If the influence rate on the device specification is 1, the defect has a great influence on the device specification and the application to the device specification is impossible, so the matching rate of the device specification is set to 0 (S106).

[0108] On the other hand, if the influence rate on the device specification is not 1, a matching contribution rate representing the degree of influence on the device specification for each defect is calculated (S107). For example, the matching contribution rate MRi_k_q_m of defect m with respect to device specification q of chip number k in application i can be calculated by the following formula, assuming that the matching contribution rate = 1 - influence rate. MRi_k_q_m = 1 - {influence rate on device specification q × (area of defect ÷ area of chip)}

[0109] After calculating the matching contribution rates of all defects, the matching rate calculation unit 113 calculates the matching contribution rate for each chip (S108). For example, the matching contribution rate MRi_k_q for device specification q of chip number k in application i is a statistical value of the matching contribution rates MRi_k_q_1 to MRi_k_q_M of all defects (defect m = 1 to M) calculated in step S107. As the statistical value, an average value, a median value, a mode value, a weighted average, etc. can be adopted.

[0110] After calculating the matching contribution rates of all device specifications, the matching rate calculation unit 113 determines whether there is a device specification with a matching contribution rate of 0 among the matching contribution rates of all device specifications (S109). If there is even one device specification with a matching contribution rate of 0, the matching rate of the chip is set to 0 (S110). If there is no device specification with a matching contribution rate of 0 among the matching contribution rates of all device specifications, the matching rate for each chip is calculated (S111). For example, the matching rate MRi_k of chip number k in application i is a statistical value of the matching contribution rates MRi_k_1 to MRi_k_Q of all device specifications (specification q = 1 to Q) of chip number k calculated in step S108. As the statistical value, an average value, a median value, a mode value, a weighted average, etc. can be adopted.

[0111] After calculating the matching rates of all chips in all applications, the matching rate calculation unit 113 ends the matching rate calculation process 533.

[0112] The matching rate 148 calculated in the matching rate calculation process 533 is sent to the application classification unit 114, and the application with the maximum (most suitable) matching rate for each chip number is classified as the first application.

[0113] As described above, the matching rate calculation unit 113 receives the three-dimensional defect information 143 (FIG. 10) of the semiconductor substrate, the defect influence rate 144 on the device specification (FIG. 11), and the device operating conditions 145 for each application (FIG. 12), and outputs the matching rate MR for each device application of the semiconductor substrate or chip.

[0114] FIG. 10 is a diagram showing a configuration example of the three-dimensional defect information 143 input to the matching rate calculation unit 113 in tabular form.

[0115] The three-dimensional defect information 143 records information on crystal defects of the semiconductor substrate and includes a slot number, a marking ID, a defect ID, a center coordinate, a defect type, a horizontal width, a vertical width, and an area. The slot number is identification information of a slot in the carrier in which the semiconductor substrate is stored. The marking ID is identification information attached to the semiconductor substrate. The defect ID is identification information of the crystal defect found in the semiconductor substrate. The center coordinate is the coordinate of the center position of the defect, represented by x, y, and z with the center of the surface of the semiconductor substrate as the origin. The defect type is identification information of the type of the defect, and examples include bunching step, stacked defect complex, scratch mark, micropipe, stacked defect, basal plane dislocation, surface particle, etc. The horizontal width and the vertical width are the sizes of the semiconductor substrate in the x and y directions of the defect. The area is the area of the defect.

[0116] FIG. 11 is a diagram showing a configuration example of the defect influence rate 144 input to the matching rate calculation unit 113 in tabular form.

[0117] The defect impact rate 144 records the impact rate indicating the impact of defects on device specifications, and includes the defect type, horizontal width, vertical width, area, device type number, in-chip position, and the impact rate for each device specification. The defect type is identification information for the type of the defect. The horizontal width and vertical width are the sizes of the semiconductor substrate of the defect in the x and y directions. The area is the area of the defect. The device type number is identification information for the type of the semiconductor device, such as a diode, MOS, IGBT, etc. The in-chip position is identification information for the position of the defect in the chip, such as the terminal region, contact region, outside the operating region, etc. The impact rate is determined for each device specification and is a value between 0 and 1. The greater the impact rate, the more the characteristics of the semiconductor device deteriorate (for example, if the impact rate is 1, it becomes a 100% defective product). Usually, the impact rate takes different values depending on the factory.

[0118] FIG. 12 is a diagram showing a configuration example of the device operating conditions 145 input to the matching rate calculation unit 113 in tabular form.

[0119] The device operating conditions 145 record the device specifications and design drawing information for each application, and include the application number, device type number, device specifications, and the positions of the terminal regions of each chip. The specifications of semiconductor devices vary depending on their application destination, i.e., the application. Since the design drawing is determined once the specifications of the semiconductor device are determined, it is advisable to include the design drawing information in the device operating conditions 145. The design drawing information is a coordinate list indicating which regions within the wafer correspond to which locations (operating regions, non-operating regions, etc.) of the chip. Based on the design drawing information, it is possible to determine whether a defect in the semiconductor substrate is within the operating region or the non-operating region of the chip. The application number is identification information for the application of the semiconductor device, such as industrial equipment, automobiles, trains, etc. The device type number is, as described above, identification information for the type of the semiconductor device, such as a diode, MOS, IGBT, etc. The device specifications are the electrical characteristic specifications of the semiconductor device, including rated voltage, rated current, resistance, operating lower temperature, operating upper temperature, on voltage, gate lower voltage, gate upper voltage, threshold voltage, gate-source leakage current, gate resistance, input capacitance, output capacitance, feedback capacitance, etc. The terminal region of each chip is a coordinate list indicating the design drawing information.

[0120] FIG. 13 and FIG. 14 are diagrams showing a configuration example of the matching rate 148 output from the matching rate calculation unit 113 in tabular form.

[0121] The example of the matching rate 148 shown in FIG. 13 is the matching rate for each device application of the semiconductor substrate, and includes the slot number, the imprint ID, and the matching rate for each application. The slot number is information common to the three-dimensional defect information 143 (FIG. 10). The imprint ID is identification information attached to the semiconductor substrate, similar to the three-dimensional defect information 143. The matching rate is, as described above, an index indicating the suitability of the semiconductor substrate of the slot number for each semiconductor device application, and is represented by a value from 0 to 1, where 0 indicates no suitability at all.

[0122] The example of the matching rate 148 shown in FIG. 14 is the matching rate for each device application of the semiconductor chip, and includes the slot number, the lot number, the wafer number, the imprint ID, the chip number, the chip index, and the matching rate for each application. The slot number and the imprint ID are information common to the three-dimensional defect information 143 (FIG. 10). The lot number is identification information of the manufacturing process of the semiconductor substrate. The wafer number is identification information of the semiconductor substrate. The chip number is identification information of the semiconductor chip manufactured on the semiconductor substrate. The chip index is position information in the case where the semiconductor chips cut out from the semiconductor wafer after manufacturing are stored. The matching rate is, as described above, an index indicating the degree of conformity of the semiconductor chip manufactured on the semiconductor substrate of the slot number to each semiconductor device application, and is represented by a value from 0 to 1, where 0 indicates no suitability at all.

[0123] As shown in FIG. 17, the matching rate 148 is displayed on the matching rate display screen in tabular form. [[ID=FIG. 16]]

[0124] As described above, the deterioration rate / remedy rate calculation unit 112 uses the three-dimensional defect information 143, the process defect information, and the influence rate of the defect on the device specifications List of 144(or, the defect inactivation rate list shown in FIG. 15), and the device operation conditions 145 for each application are input, and the deterioration rate and the relief rate are output.

[0125] Whether a chip containing at least one of crystal defects and process defects becomes electrically non-defective depends on the type of the defect, shape information such as the size, device type, location within the chip, and device operation conditions for each application. The Impact rate list records the possibility ( Impact rate 144 ) that the chip becomes electrically defective due to crystal defects and process defects. On the other hand, even for a chip containing crystal defects or process defects in the chip and having a high possibility of being a defective product, depending on the shape information such as the type and size of the defect, device type, location within the chip, defect generation process, and device operation conditions for each application, the defect can be inactivated in subsequent processes. The defect inactivation rate list records the probability that the electrical characteristics become the desired conditions (non-defective products) when the defect region is inactivated by changing the manufacturing process after the defect occurs.

[0126] FIG. 15 is a diagram showing a configuration example of the defect inactivation rate 150 input to the deterioration rate / relief rate calculation unit 112. The defect inactivation rate 150 records, for each defect, the probability that the defect region is inactivated by subsequent processes, and includes defect type, horizontal width, vertical width, area, device type number, position within the chip, application number, category number of the defect generation process, and inactivation rate. The defect type, horizontal width, vertical width, and area are information common to the three-dimensional defect information 143 (FIG. 10). The device type number and the position within the chip are information common to the defect influence rate 144 (FIG. 11). The application number is information common to the device operation conditions 145 (FIG. 12). The category number of the defect generation process is identification information of the type of the process in which the defect occurred, and includes pre-prototype cleaning, alignment mark processing, terminal region ion implantation, contact region ion implantation, backside ion implantation, activation annealing, sacrificial oxidation, gate oxide film formation, protective film formation, and the like. The inactivation rate is the probability that the defect of the defect type is inactivated in subsequent processes.

[0127] FIG. 16 is a diagram showing in tabular form a configuration example of the deterioration rate and the relief rate output from the deterioration rate / relief rate calculation unit 112. The deterioration rate and the relief rate are, respectively, the probability that a chip including at least one of a crystal defect and a process defect becomes an electrically defective product, and the probability that the electrical characteristics of a chip including at least one of a crystal defect and a process defect become desired conditions (good product) due to a change in the manufacturing process after the occurrence of the defect. The deterioration rate and the relief rate are obtained for each chip and for each application, and include a slot number, a lot number, a wafer number, a stamp ID, a chip number, and a chip index. The slot number is information common to the three-dimensional defect information 143 (FIG. 10). The lot number, the wafer number, the stamp ID, the chip number, and the chip index are information common to the matching rate 148 (FIG. 14).

[0128] FIG. 18 is a diagram showing an example of an application classification result display screen for displaying the output result of the application classification unit 114.

[0129] In the semiconductor device management system 100 of the present embodiment, the determination unit 116 collates the classification result 149 of the semiconductor device manufactured on the semiconductor substrate with the input application, and displays the order of the applications to which the chips on the semiconductor substrate are suitable. On the application classification result display screen, a slot number, a lot number, a wafer number, a stamp ID, a chip number, a chip index, and a classification result 149 representing the degree of fitness of the application are displayed. The slot number is information common to the three-dimensional defect information 143 (FIG. 10). The lot number, the wafer number, the stamp ID, the chip number, and the chip index are information common to the matching rate 148 (FIG. 14). In the application column, the order of application fitness, that is, the order from the highest matching rate, is displayed. In the illustrated example, it represents that the fitness of 1 is the highest and the fitness of n is the lowest.

[0130] As described above, according to the semiconductor device management system 100 of the present embodiment, the arithmetic unit 110 calculates the fitness for each device use of the semiconductor substrate from the three-dimensional position information of the crystal defects contained in the semiconductor substrate (three-dimensional defect information 143), the influence rate of the defects on the device specifications (defect influence rate 144), and the operating conditions 145 for each use of the semiconductor device. The fitness calculation unit (matching rate calculation unit 113) and the determination unit 116 that generates data for determining the use for the semiconductor substrate based on the fitness and outputting at least the determined use. Therefore, from the inspection result 142 of the defects of the semiconductor substrate, by referring to the influence rate of the defects on the device specifications (defect influence rate 144) and the device operating conditions 145 that vary depending on the use, information for selecting the semiconductor devices formed on the semiconductor substrate can be output, and semiconductor devices manufactured at locations within the substrate that are suitable for the device operating conditions 145 that vary depending on the use can be selected and shipped, providing high-reliability and low-cost semiconductor devices.

[0131] Also, according to the semiconductor device management system 100 of Modification 1, the arithmetic device calculates the fitness for each use of the semiconductor device from the three-dimensional position information of the crystal defects contained in the semiconductor substrate (three-dimensional defect information 143), the influence rate of the defects on the device specifications (defect influence rate 144), and the operating conditions 145 for each use of the semiconductor device. The fitness calculation unit (matching rate calculation unit 113) and the determination unit 116 that generates data for determining the respective uses for each semiconductor device formed on the semiconductor substrate based on the fitness and outputting at least the determined respective uses. Therefore, the semiconductor device management system 100 can output information for selecting the semiconductor substrate by referring to the influence rate of the defects on the device specifications (defect influence rate 144) and the device operating conditions 145 that vary depending on the use from the inspection result 142 of the defects of the semiconductor substrate, select a semiconductor substrate suitable for the device operating conditions 145 that vary depending on the use, and manufacture semiconductor devices, providing high-reliability and low-cost semiconductor devices.

[0132] Note that the present invention is not limited to the above-described embodiments, and includes various modifications and equivalent configurations within the scope of the appended claims. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and the present invention is not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Further, the configuration of another embodiment may be added to the configuration of one embodiment. Also, with respect to a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations may be made.

[0133] In addition, each of the above-described configurations, functions, processing units, processing means, etc. may be realized in hardware by designing part or all of them, for example, by means of an integrated circuit, or may be realized in software by a processor interpreting and executing a program for realizing each function.

[0134] Information such as programs, tables, files, etc. for realizing each function can be stored in a storage device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, a DVD.

[0135] Also, the control lines and information lines show those considered necessary for explanation, and do not necessarily show all the control lines and information lines necessary for implementation. In practice, it may be considered that almost all configurations are interconnected.

Explanation of Reference Numerals

[0136] 100 Semiconductor device management system 110 Arithmetic unit 111 Defect analysis unit 112 Degradation rate / relief rate calculation unit 113 Matching rate calculation unit 114 Application classification unit 115 Listing unit 116 Determination unit 120 Storage unit 131 Defect analysis program I32 Degradation rate / relief rate calculation program 133 Matching rate calculation program 134 Use classification program 135 Listing program 136 Judgment program 141 Substrate information 142 Defect inspection result 143 Three-dimensional defect information 144 Defect influence rate 145 Device operating conditions 146 Process condition history 147 Degradation rate · Relief rate 148 Matching rate 149 Classification result by use 150 Defect inactivation rate 200 Inspection device 210 Terminal 220 Semiconductor manufacturing device

Claims

1. A semiconductor device management system, comprising: an arithmetic unit that executes a predetermined process, an input unit to which data is input, and an output unit that outputs the result of the process; the arithmetic unit includes a fitness calculation unit that calculates the fitness for each use of the semiconductor device formed on the semiconductor substrate from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the influence rate of the defects on the device specifications, and the operating conditions for each use of the semiconductor device; the arithmetic unit has a determination unit that determines each use for each of the semiconductor devices based on the fitness; the determination unit is a semiconductor device management system that generates data for at least outputting the determined respective uses.

2. The semiconductor device management system according to claim 1, wherein the arithmetic unit includes a use classification unit that classifies the semiconductor devices according to the fitness and registers them in a database; the arithmetic unit includes a listing unit that lists the database; the determination unit determines each use for each of the semiconductor devices according to the classification result by the use classification unit, and selects the semiconductor devices classified as having a high fitness in the determined uses.

3. The semiconductor device management system according to claim 1, wherein the fitness calculation unit calculates the fitness for each use of the semiconductor device formed on the semiconductor substrate from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the three-dimensional position information of the process defects generated during the manufacture of the semiconductor device, the influence rate of the defects on the device specifications, and the operating conditions for each use of the semiconductor device.

4. The semiconductor device management system according to claim 3, wherein the arithmetic unit has a deterioration rate / relief rate calculation unit that calculates the deterioration rate and relief rate of each semiconductor device; the deterioration rate / relief rate calculation unit: calculates, for each use, the deterioration rate, which is the probability that the electrical characteristics of the semiconductor device formed on the semiconductor substrate do not satisfy the desired conditions, from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the three-dimensional position information of the process defects generated during the manufacture of the semiconductor device, the influence rate of the defects on the device specifications, and the operating conditions for each use of the semiconductor device. After the occurrence of the process defect, a salvage rate, which is the probability that the electrical characteristics meet the desired conditions due to the inactivation of the process defect by changes in the manufacturing process, is calculated for each application. A semiconductor device management system that instructs changes in subsequent manufacturing processes for semiconductor devices in which the calculated deterioration rate is greater than a predetermined threshold and the calculated salvage rate is greater than a predetermined threshold.

5. The semiconductor device management system according to claim 1, wherein the fitness calculation unit calculates the fitness for each application of the semiconductor device from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the process condition history during the manufacture of the semiconductor device, the influence rate of the defects on the device specifications, and the operating conditions for each application of the semiconductor device.

6. The semiconductor device management system according to claim 5, wherein the fitness calculation unit calculates the fitness for each application of the semiconductor device from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the three-dimensional position information of the process defects generated during the manufacture of the semiconductor device, the process condition history during the manufacture of the semiconductor device, the influence rate of the defects on the device specifications, and the operating conditions for each application of the semiconductor device.

7. The semiconductor device management system according to claim 6, wherein the arithmetic unit has a deterioration rate / salvage rate calculation unit that calculates the deterioration rate and salvage rate of each semiconductor device, and the deterioration rate / salvage rate calculation unit calculates, for each application, the deterioration rate, which is the probability that the electrical characteristics of the semiconductor device formed on the semiconductor substrate do not meet the desired conditions, from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the three-dimensional position information of the process defects generated during the manufacture of the semiconductor device, the influence rate of the defects on the device specifications, and the operating conditions for each application of the semiconductor device, calculates, for each application, the salvage rate, which is the probability that the electrical characteristics meet the desired conditions due to the inactivation of the process defect by changes in the manufacturing process after the occurrence of the process defect, and instructs changes in subsequent manufacturing processes for semiconductor devices in which the calculated deterioration rate is greater than a predetermined threshold and the calculated salvage rate is greater than a predetermined threshold.

8. The semiconductor device management system according to claim 1, wherein the fitness calculation unit Obtain the defect impact rate for each device specification, Calculate the matching contribution rate for each defect from the obtained impact rate, Calculate the statistical value of the matching contribution rate for each defect, and use it as the matching contribution rate for each semiconductor chip, A semiconductor device management system that calculates the statistical value of the matching contribution rate of all device specifications for each application and each semiconductor chip, and uses it as the fitness for each application and each semiconductor chip.

9. The semiconductor device management system according to claim 1, wherein the fitness calculation unit further calculates the fitness using the defect type and shape of the crystal defect.

10. The semiconductor device management system according to claim 1, which has a defect analysis unit that obtains the inspection result of the semiconductor substrate inspected by the inspection device and analyzes the three-dimensional defects of the semiconductor substrate.

11. A semiconductor device management system, comprising an arithmetic unit that executes a predetermined process, an input unit to which data is input, and an output unit that outputs the result of the process, wherein the arithmetic unit has a fitness calculation unit that calculates the fitness for each application of the semiconductor substrate from the three-dimensional position information of the crystal defects contained in the semiconductor substrate, the impact rate of the defects on the device specifications, and the operating conditions for each application of the semiconductor device, and the arithmetic unit has a determination unit that determines the application for the semiconductor substrate based on the fitness, wherein the determination unit generates data for outputting at least the determined application.

12. The semiconductor device management system according to claim 11, wherein the arithmetic unit has an application classification unit that classifies the semiconductor substrate according to the fitness and registers it in a database, and the arithmetic unit has a listing unit that lists the database, wherein the determination unit determines the application of the semiconductor substrate according to the classification result by the application classification unit, and selects the semiconductor substrate classified as having a high fitness in the determined application.

13. A semiconductor device management method executed by a computer, wherein the computer has an arithmetic unit that executes a predetermined process, an input unit to which data is input, and an output unit that outputs the result of the process, and the semiconductor device management method is as follows: A fitness calculation procedure in which the arithmetic unit calculates the fitness for each use of the semiconductor device from the three-dimensional position information of crystal defects contained in the semiconductor substrate, the influence rate of the defects on the device specifications, and the operating conditions for each use of the semiconductor device A determination procedure in which the arithmetic unit determines each use for each semiconductor device formed on the semiconductor substrate based on the fitness An output procedure in which the arithmetic unit generates data for at least outputting each use determined in the determination procedure A semiconductor device management method having the above.

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