Semiconductor device and electronic apparatus

Abstract

The purpose of the present invention is to provide a low power consumption semiconductor device. This semiconductor device comprises a first transistor, a second transistor, and capacitances. The first transistor has a first gate and a first back gate, and the second transistor has a second gate and a second back gate. The gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function for holding a first potential corresponding to first data when the first transistor is in an off state. The second transistor has a function for passing an output current between the source and drain of the second transistor.

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

Background Art

[0003] Currently, the development of integrated circuits that mimic the structure of the human brain is actively underway. The integrated circuit has the structure of the brain incorporated as an electronic circuit and has circuits corresponding to the "neurons" and "synapses" of the human brain. Therefore, such an integrated circuit may also be referred to as "neuromorphic", "brainomorphic", or "brain-inspired". The integrated circuit has a non-Neumann architecture and is expected to perform parallel processing with extremely low power consumption compared to the Neumann architecture in which power consumption increases as the processing speed increases.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with human-level or even higher-than-human accuracy. In an artificial neural network, the operation of weighted summation of neuron outputs, that is, the multiplication and summation operation, is the main operation.

[0005] Non-Patent Document 1 proposes a multiply-accumulate circuit using non-volatile memory cells. In the multiply-accumulate circuit, in each memory cell, by utilizing the operation in the subthreshold region of a transistor having silicon in the channel formation region, a current corresponding to the multiplication of the data corresponding to the multiplier stored in each memory cell and the input data corresponding to the multiplicand is output. Also, data corresponding to the multiply-accumulate operation is obtained from the sum of the currents output by the memory cells in each column. Since the multiply-accumulate circuit has memory cells inside, it is not necessary to perform data reading and writing from an external memory in multiplication and addition. For this reason, the number of data transfers due to reading, writing, etc. can be reduced, and thus it is expected that the power consumption can be lowered.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] One aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a semiconductor device capable of holding data for a long time. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a novel semiconductor device or the like.

[0008] Note that one aspect of the present invention does not necessarily have to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. These other problems will become apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0009] One aspect of the present invention includes a first transistor, a second transistor, and a capacitor. The first transistor has a first gate and a first back gate. The second transistor has a second gate and a second back gate. The gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of holding a first potential corresponding to first data supplied to the second back gate via the first transistor when the first transistor is in an off state. The capacitor has a function of changing the first potential held at the second back gate to a second potential in response to a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of flowing an output current corresponding to the potential of the second back gate between the source and drain of the second transistor. The output current is a current that flows when the second transistor operates in the subthreshold region. A constant potential is applied to the second gate. It is a semiconductor device.

[0010] Alternatively, one aspect of the present invention has a first transistor, a second transistor, and a capacitor. The first transistor has a first gate and a first back gate. The second transistor has a second gate and a second back gate. The gate insulating layer for the first back gate has ferroelectricity. One electrode of the capacitor is electrically connected to the second gate, and a fixed potential is applied to the other electrode of the capacitor. The first transistor has a function of holding a first potential corresponding to first data applied to the second gate via the first transistor when the first transistor is in an off state. The second transistor has a function of flowing an output current corresponding to the potential of the second gate between the source and drain of the second transistor, and the output current is a current that flows when the second transistor operates in the subthreshold region. It is a semiconductor device.

[0011] Alternatively, one aspect of the present invention has a first transistor, a second transistor, and a capacitor. The first transistor has a first gate and a first back gate. The second transistor has a second gate and a second back gate. The gate insulating layer for the first back gate has ferroelectricity. One electrode of the capacitor is electrically connected to the second back gate, and a fixed potential is applied to the other electrode of the capacitor. The first transistor has a function of holding a first potential corresponding to first data applied to the second back gate via the first transistor when the first transistor is in an off state. The second transistor has a function of flowing an output current corresponding to the potential of the second back gate between the source and drain of the second transistor, and the output current is a current that flows when the second transistor operates in the subthreshold region. It is a semiconductor device.

[0012] Alternatively, in the above aspect, the semiconductor device may have a circuit, and the circuit is electrically connected to the first gate and has a function of generating a signal for controlling on or off of the first transistor.

[0013] Alternatively, in the above aspect, the gate insulating layer for the first back gate may have an oxide containing one or both of hafnium and zirconium.

[0014] Alternatively, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. The first to third transistors each have a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor and one electrode of the first capacitor. The other of the source or drain of the first transistor is electrically connected to the back gate of the second transistor and the other electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. The other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor. It is a semiconductor device.

[0015] Alternatively, in the above aspect, a fixed potential may be applied to the gate of the second transistor.

[0016] Alternatively, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. The first to third transistors each have a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. The other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor. It is a semiconductor device.

[0017] Alternatively, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. The first to third transistors each have a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the first transistor is electrically connected to the back gate of the second transistor and one electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. The other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor. It is a semiconductor device.

[0018] Alternatively, in the above aspect, a fixed potential may be applied to the other electrode of the first capacitor.

[0019] Alternatively, in the above aspect, the semiconductor device has a circuit, the circuit is electrically connected to the gate of the first transistor, and the circuit may have a function of generating a signal for controlling the on or off of the first transistor.

[0020] Alternatively, in the above aspect, the ferroelectric capacitor has a dielectric layer, and the dielectric layer may have an oxide containing one or both of hafnium and zirconium.

[0021] Alternatively, in the above aspect, the first transistor may have a semiconductor layer having a metal oxide in a channel formation region.

[0022] Alternatively, in the above aspect, the metal oxide may contain In, Ga, and Zn.

[0023] Alternatively, in the above aspect, the second transistor may have a semiconductor layer having silicon in a channel formation region.

[0024] An electronic device having a semiconductor device according to an aspect of the present invention and a housing, and performing neural network operations by the semiconductor device is also an aspect of the present invention.

[0025] For other aspects of the present invention, they are described in the embodiments described below and in the drawings.

Effects of the Invention

[0026] According to an aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to an aspect of the present invention, a semiconductor device capable of holding data for a long time can be provided. Alternatively, according to an aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to an aspect of the present invention, a novel semiconductor device or the like can be provided.

[0027] The description of multiple effects does not preclude the existence of other effects. Also, one embodiment of the present invention does not necessarily have all of the illustrated effects. Further, regarding one embodiment of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0028] Figures 1A and 1B are diagrams for explaining a configuration example of a semiconductor device. Figures 2A and 2B are diagrams for explaining a configuration example of a semiconductor device. Figures 3A and 3B are diagrams for explaining a configuration example of a semiconductor device. Figures 4A and 4B are diagrams for explaining a configuration example of a semiconductor device. Figures 5A and 5B are diagrams for explaining a configuration example of a semiconductor device. Figures 6A and 6B are diagrams for explaining a configuration example of a semiconductor device. Figures 7A and 7B are diagrams for explaining a configuration example of a semiconductor device. Figures 8A and 8B are diagrams for explaining an example of an operation method of a semiconductor device. Figures 9A and 9B are diagrams for explaining an example of an operation method of a semiconductor device. Figures 10A and 10B are diagrams for explaining an example of an operation method of a semiconductor device. Figures 11A and 11B are diagrams for explaining an example of an operation method of a semiconductor device. Figures 12A and 12B are diagrams for explaining an example of an operation method of a semiconductor device. Figure 13 is a diagram for explaining a configuration example of a semiconductor device. Figure 14 is a diagram for explaining a configuration example of a semiconductor device. Figure 15 is a diagram for explaining a configuration example of a semiconductor device. Figure 16 is a diagram for explaining a configuration example of an arithmetic circuit. Figures 17A, 17B, and 17C are diagrams for explaining a configuration example of an arithmetic circuit. Figures 18A, 18B, 18C, and 18D are diagrams for explaining a configuration example of an arithmetic circuit. FIG. 19A, FIG. 19B, and FIG. 19C are diagrams for explaining a configuration example of an arithmetic circuit. FIG. 20 is a diagram for explaining a configuration example of an arithmetic circuit. FIG. 21, FIG. 21A, and FIG. 21B are diagrams for explaining a neural network. FIG. 22A is a diagram for explaining a configuration example of a semiconductor device. FIG. 22B and FIG. 22C are diagrams for explaining a configuration example of a transistor. FIG. 23A and FIG. 23B are diagrams for explaining a configuration example of a transistor. FIG. 24 is a diagram for explaining a configuration example of a transistor. FIGS. 25A to 25C are diagrams for explaining a configuration example of a transistor. FIG. 26A is a diagram for explaining the classification of the crystal structure of IGZO. FIG. 26B is a diagram for explaining the XRD spectrum of crystalline IGZO. FIG. 26C is a diagram for explaining the electron backscatter diffraction pattern of crystalline IGZO. FIG. 27 is a diagram for explaining a configuration example of an integrated circuit. FIG. 28A and FIG. 28B are diagrams for explaining application examples of an integrated circuit. FIG. 29A and FIG. 29B are diagrams for explaining application examples of an integrated circuit. FIGS. 30A, 30B, and 30C are diagrams for explaining application examples of an integrated circuit. FIG. 31 is a diagram for explaining an application example of an integrated circuit.

Mode for Carrying Out the Invention

[0029] Hereinafter, embodiments of the present invention will be described. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0030] In this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. For another example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0031] In the drawings, the same reference numerals may be given to the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously, and the repeated description thereof may be omitted.

[0032] In this specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0033] Also, when the same reference numerals are used for a plurality of elements, especially when it is necessary to distinguish them, identification symbols such as "_1", "_2", "_n", "_m,n" may be appended to the reference numerals for description.

[0034] (Embodiment 1) The configuration, operation, etc. of a semiconductor device which is one aspect of the present invention will be described.

[0035] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. It can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. have semiconductor devices.

[0036] FIG. 1A is a diagram for explaining a semiconductor device 10A1 which is one aspect of the present invention.

[0037] The semiconductor device 10A1 includes a reference cell 21(1) and an arithmetic cell 31(1). The reference cell 21(1) includes a transistor 22, a transistor 24, and a capacitor 25. The arithmetic cell 31(1) includes a transistor 32, a transistor 34, and a capacitor 35. The transistors 22, 24, 32, and 34 each have a gate and a back gate.

[0038] In this specification and the like, for example, when a transistor having a function as a switch has a gate and a back gate, it can be assumed that by controlling the potential of the gate, the on / off of the transistor can be controlled. Also, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled.

[0039] The transistors and capacitors included in the reference cell 21(1) and the arithmetic cell 31(1) are connected to at least one of a wiring WSL, a wiring XCL, a wiring WCL, and a wiring for supplying a ground potential as shown in FIG. 1.

[0040] The reference cell 21(1) has a function of causing an arithmetic operation in the arithmetic cell 31(1) to be executed by flowing a set current during data writing and during data reading. Specifically, during data writing, by flowing a reference current, a reference potential is held in the reference cell 21(1), and then, during data reading, a current corresponding to the input data (X) applied to the arithmetic cell 31(1) is caused to flow through the reference cell 21(1), and it has a function of controlling the current flowing through the arithmetic cell 31(1). Note that the reference cell 21(1) may simply be referred to as a cell.

[0041] Next, the connection relationship within the reference cell 21(1) will be described.

[0042] The gate of transistor 22 is electrically connected to wiring WSL. One of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 24 and is also electrically connected to one electrode of capacitor 25 via wiring XCL. The other of the source or drain of transistor 22 is electrically connected to the back gate of transistor 24 and the other electrode of capacitor 25. Transistor 22 can write the reference potential to the holding node (the back gate of transistor 24) in reference cell 21(1) in the on state during data writing and hold the reference potential in reference cell 21(1) by turning off. Note that the node to which the back gate of transistor 24, the other of the source or drain of transistor 22, and the other electrode of capacitor 25 are connected is also called the holding node. The holding node can be set to a potential corresponding to the current flowing through transistor 24.

[0043] Here, by controlling the potential of the back gate of transistor 22, the threshold voltage of transistor 22 can be controlled. Specifically, by increasing the potential of the back gate of transistor 22, the threshold voltage of transistor 22 can be decreased. On the other hand, by decreasing the potential of the back gate of transistor 22, the threshold voltage of transistor 22 can be increased. Therefore, when transistor 22 is in the on state, increasing the potential of the back gate of transistor 22 can increase the on-current of transistor 22, and when transistor 22 is in the off state, decreasing the potential of the back gate of transistor 22 can decrease the off-current of transistor 22.

[0044] The gate of transistor 24 and the other of the source or drain of transistor 24 are connected to a wiring that provides a fixed potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 24.

[0045] When the other electrode is electrically floating, the capacitance 25 changes the potential of the other electrode in response to a change in the potential applied to one electrode.

[0046] During data writing, the arithmetic cell 31(1) has a function of holding a voltage corresponding to the current inside by passing a current corresponding to the weight data (W) held in the arithmetic cell 31(1). Also, during data reading, the arithmetic cell 31(1) has a function of passing a current corresponding to the operation of the weight data and the input data by boosting the voltage held during data writing according to the current flowing through the reference cell 21(1). The weight data may be referred to as the first data, and the input data may be referred to as the second data. Note that the arithmetic cell 31(1) may simply be referred to as a cell. Note that the weight data is, for example, data (weight data) corresponding to weight parameters used in the multiplication and addition operations of an artificial neural network.

[0047] Next, the connection relationship inside the arithmetic cell 31(1) will be described.

[0048] The gate of the transistor 32 is electrically connected to the wiring WSL. One of the source or drain of the transistor 32 is electrically connected to one of the source or drain of the transistor 34 and the wiring WCL. One electrode of the capacitor 35 is electrically connected to the wiring XCL. The other of the source or drain of the transistor 32 is electrically connected to the back gate of the transistor 34 and the other electrode of the capacitor 35. The transistor 32 can write a voltage corresponding to the weight data into the arithmetic cell 31(1) by turning on during data writing, and hold the voltage corresponding to the weight data in the arithmetic cell 31(1) by turning off. Note that the node to which the back gate of the transistor 34, the other of the source or drain of the transistor 32, and the other electrode of the capacitor 35 are connected is also referred to as a holding node.

[0049] Here, by controlling the potential of the back gate of transistor 32, the threshold voltage of transistor 32 can be controlled. Specifically, by increasing the potential of the back gate of transistor 32, the threshold voltage of transistor 32 can be decreased. On the other hand, by decreasing the potential of the back gate of transistor 32, the threshold voltage of transistor 32 can be increased. Therefore, when transistor 32 is in the on state, increasing the potential of the back gate of transistor 32 can increase the on-current of transistor 32, and when transistor 32 is in the off state, decreasing the potential of the back gate of transistor 32 can decrease the off-current of transistor 32.

[0050] The gate of transistor 34 and the other of the source or drain of transistor 34 are connected to a wiring that provides a constant potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 34.

[0051] When the other electrode of capacitor 35 is in an electrically floating state, the potential of the other electrode changes in response to a change in the potential applied to one electrode.

[0052] Next, the transistors included in reference cell 21(1) and arithmetic cell 31(1) will be described.

[0053] Transistors 24 and 34 operate in the subthreshold region unless otherwise specified. The drain current Id of a transistor operating in the subthreshold region can be expressed by Equation (1).

[0054]

Equation

[0055] In Equation (1), I0 is V g =V thWhen the drain current, q is the elementary charge of electricity, V g is the gate voltage, V th is the threshold voltage, η is a coefficient determined by the device structure, etc., k B is the Boltzmann constant, and T is the temperature. As shown in Equation (1), the drain current Id of the transistor operating in the subthreshold region does not depend on the drain voltage. The currents flowing through transistor 24 and transistor 34 are the amounts of current flowing when operating in the subthreshold region. The currents in the subthreshold regions of transistor 24 and transistor 34 can reduce the influence of variations in the drain voltage. Therefore, the accuracy of the data obtained by the calculation can be improved.

[0056] In this specification and the like, the subthreshold region refers to the region where the gate voltage of the transistor is lower than the threshold voltage in the graph showing the gate voltage (Vg)-drain current (Id) characteristics of the transistor. Or the subthreshold region refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Or the subthreshold region refers to the region where the drain current increases exponentially with respect to the increase in the gate voltage. Or the subthreshold region shall include the regions that can be regarded as the regions described above.

[0057] Also, the drain current when the transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage regardless of the drain voltage. In the circuit operation using the subthreshold current, the influence of variations in the drain voltage can be reduced.

[0058] Also, transistors 22 and 32 have a function of holding the potentials of the back gates of transistor 24 and transistor 34 by being turned off. Specifically, they have a function of holding the reference potential applied to the back gate of transistor 24 via transistor 22. Also, they have a function of holding the potential corresponding to the data applied to the back gate of transistor 34 via transistor 32. As an example, transistors 22 and 32 are preferably transistors having a metal oxide in the channel formation region (also referred to as OS transistors). For example, the channel formation regions of transistors 22 and 32 are more preferably oxides containing at least one of indium, gallium, and zinc. Also, instead of the oxide, an oxide containing at least one of indium, element M (element M includes, for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc may be used.

[0059] The current flowing between the source and the drain in the off state of the OS transistor, that is, the leakage current, is extremely small. Therefore, by using the OS transistor as transistor 22 and / or transistor 32, the leakage current of transistor 22 and / or transistor 32 can be suppressed, and thus the power consumption of semiconductor device 10A1 can be reduced. Specifically, since the fluctuations of the potentials held at the back gates of transistor 24 and transistor 34 can be made very small, the refresh operation of the potential can be reduced. Also, by reducing the refresh operation, the power consumption of semiconductor device 10A1 can be reduced. Also, by making the leakage current from the holding node to wiring WCL or wiring XCL extremely small, the cell can hold the potential of the holding node for a long time.

[0060] Also, when the gate voltage of the OS transistor is less than the threshold voltage of the transistor, it can pass an extremely small current as the drain current per 1 μm channel width, such as less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A. Also, when the gate voltage of the OS transistor is equal to the threshold voltage of the transistor, it can pass a drain current per 1 μm channel width, such as 1.0×10 -8 A or less, 1.0×10 -12 A or less, or 1.0×10 -15 A or less. Therefore, the OS transistor can pass subthreshold currents of different magnitudes in the range of gate voltages operating in the subthreshold region. That is, the OS transistor can have a wide range of gate voltages operating in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is V th , in the subthreshold region, circuit operation can be performed using gate voltages in the voltage range of (V th - 1.0V) or higher and V th or lower, or (V th - 0.5V) or higher and V th or lower.

[0061] Since the bandgap of the metal oxide functioning as the oxide semiconductor is 2.5 eV or more, the OS transistor has an extremely small off - current. As an example, at room temperature (25°C) with a voltage of 3.5V between the source and the drain, the off - current per 1 μm channel width can be less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A. Therefore, the OS memory has an extremely small amount of charge leaking from the holding node through the OS transistor.

[0062] Metal oxides applied to OS transistors include zinc oxide, zinc-tin oxide, gallium-tin oxide, indium-gallium oxide, indium-zinc oxide, indium-M-zinc oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), etc. In particular, when a metal oxide using Ga as M is adopted for an OS transistor, it is preferable because a transistor excellent in electrical characteristics such as field-effect mobility can be obtained by adjusting the ratio of elements. Further, the oxide containing indium and zinc may contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0063] For improving the reliability and electrical characteristics of OS transistors, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal part such as CAAC-OS, CAC-OS, nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0064] CAAC-OS has a c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction, resulting in a crystal structure having strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in the region where the plurality of nanocrystals are connected.

[0065] The CAC-OS has a function of allowing carriers, which are electrons (or holes), to flow and a function of not allowing carriers, which are electrons, to flow. By separating the function of allowing electrons to flow and the function of not allowing electrons to flow, both functions can be maximized. That is, by using the CAC-OS in the channel formation region of an OS transistor, both a high on-current and an extremely low off-current can be realized.

[0066] The OS transistor is an accumulation-type transistor with electrons as majority carriers. Therefore, the influence of Drain-Induced Barrier Lowering (DIBL), which is one of the short-channel effects, is small compared to an inversion-type transistor having a pn junction. That is, the OS transistor has higher resistance to the short-channel effect than an Si transistor.

[0067] Also, by using the OS transistor for transistors 24 and 34 as well, it is possible to operate in a wide current range in the subthreshold region, so that the power consumption can be reduced. Also, by using the OS transistor for transistors 24 and 34 as well, it is possible to fabricate them simultaneously with transistors 22 and 32, so that the fabrication process of the arithmetic circuit may be shortened.

[0068] Note that transistors 22, 24, 32, and 34 do not necessarily have to be OS transistors. For example, transistors 22, 24, 32, and 34 can be Si transistors. As the silicon, for example, amorphous silicon (which may be referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single-crystalline silicon, etc. can be used.

[0069] Also, although the transistors 22, 24, 32, and 34 illustrated in FIG. 1 are n-channel transistors, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, some or all of the transistors 22, 24, 32, and 34 may be replaced with p-channel transistors. When some or all of the transistors 22, 24, 32, and 34 are replaced with p-channel transistors, the voltage or the like applied by the wiring may be changed as necessary so that the transistors 22, 24, 32, and 34 operate as desired.

[0070] Note that the examples of changes in the structure and polarity of the transistors are not limited to only the transistors 22, 24, 32, and 34. For example, the structure, polarity, etc. of the transistors described in other parts of the specification or illustrated in other drawings may be changed in the same manner.

[0071] Next, the wirings WSL, XCL, and WCL connected to the reference cell 21(1) and the arithmetic cell 31(1) will be described.

[0072] The wiring WSL is supplied with a signal for controlling the on or off states of the transistors 22 and 32 that function as switches. The wiring WSL functions as a write word line when writing data to the reference cell 21(1) and the arithmetic cell 31(1). Here, by passing a current corresponding to desired data through the wiring XCL or the wiring WCL, data is written to the reference cell 21(1) or the arithmetic cell 31(1). Also, by applying a potential corresponding to desired data to the wiring XCL or the wiring WCL, data is written to the reference cell 21(1) or the arithmetic cell 31(1). The data is written to the reference cell 21(1) by turning on the transistor 22, and written to the arithmetic cell 31(1) by turning on the transistor 32. The transistors 22 and 32 can be turned on by setting the wiring WSL to the H level (high-level potential). Also, the data is held in the reference cell 21(1) by turning off the transistor 22, and the data is held in the arithmetic cell 31(1) by turning off the transistor 32. The transistors 22 and 32 can be turned off by setting the wiring WSL to the L level (low-level potential).

[0073] The wiring WCL has a function of passing a current (weight current or current I Wut ) corresponding to the weight data (also referred to as the first data or the first input data) to the arithmetic cell 31(1), or a function of applying a fixed potential for passing a current according to the potential held in the arithmetic cell 31(1).

[0074] The wiring XCL has a function of passing a current amount (reference current or current I Xut ) corresponding to the reference data, or a current amount (input current or current I X ) corresponding to the input data (also referred to as the second data or the second input data) to the reference cell 21(1) and the arithmetic cell 31(1).

[0075] FIG. 1B is a diagram for explaining a semiconductor device 10B1 which is an aspect of the present invention. In the semiconductor device 10B1, it is assumed that the gate insulating layers for the back gates of the transistors 22 included in the semiconductor device 10A1 and the gate insulating layers for the back gates of the transistors 32 have materials that can have ferroelectricity.

[0076] In the circuit diagrams such as this specification, that the gate insulating layer for the back gate of a transistor has a material that can have ferroelectricity is indicated by applying hatching to the back gate.

[0077] In this specification etc., ferroelectricity indicates the property of maintaining the polarized state even after the application of voltage is stopped after polarizing by applying voltage. Also, paraelectricity indicates the property that the polarized state is not maintained and disappears when the application of voltage is stopped after polarizing by applying voltage.

[0078] Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (where X is a real number greater than 0), materials obtained by adding an element J1 (here, the element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, materials obtained by adding an element J2 (here, the element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like. Also, as materials that can have ferroelectricity, PbTiO X, piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. Further, as a material that can have ferroelectricity, for example, a plurality of materials selected from the materials listed above, or a laminated structure composed of a plurality of materials selected from the materials listed above can be used. By the way, hafnium oxide, zirconium oxide, HfZrO X , and materials obtained by adding element J1 to hafnium oxide, etc. may have their crystal structures (properties) changed not only by film formation conditions but also by various processes, etc. Therefore, in this specification, etc., they are called materials that can have ferroelectricity.

[0079] Among them, as a material that can have ferroelectricity, hafnium oxide, or a material having hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even when processed into a thin film of several nm.

[0080] Further, the film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Also, when using HfZrO X as a material that can have ferroelectricity, it is preferable to form a film using the atomic layer deposition (ALD) method, particularly the thermal ALD method.

[0081] Also, when forming a film of a material that can have ferroelectricity using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbon (also referred to as HC) as a precursor. When either one or both of hydrogen and carbon are contained in the material that can have ferroelectricity, it may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, by using a precursor that does not contain hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that can have ferroelectricity. For example, chlorine-based materials can be mentioned as precursors that do not contain hydrocarbon. When using a material having hafnium oxide and zirconium oxide (HfZrO x ) as the material that can have ferroelectricity, HfCl4 and / or ZrCl4 may be used as the precursor.

[0082] Also, when forming a film of a material that can have ferroelectricity using the thermal ALD method, H2O or O3 can be used as the oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0083] Also, the crystal structure of the material that can have ferroelectricity is not particularly limited. For example, the crystal structure of the material that can have ferroelectricity may be any one or more selected from the cubic system, tetragonal system, orthorhombic system, and monoclinic system. In particular, as the material that can have ferroelectricity, having an orthorhombic crystal structure is preferable because ferroelectricity is exhibited. Or, as the material that can have ferroelectricity, a composite structure having an amorphous structure and a crystal structure may also be used.

[0084] As the material that can have dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0085] In the semiconductor device 10B1, by controlling the potential of the back gate of the transistor 22, the polarization state of the gate insulating layer with respect to the back gate can be controlled. Thereby, the threshold voltage of the transistor 22 can be controlled. Similarly, by controlling the potential of the back gate of the transistor 32, the polarization state of the gate insulating layer with respect to the back gate can be controlled, and thereby the threshold voltage of the transistor 32 can be controlled.

[0086] Also, in the semiconductor device 10B1, even after polarizing the gate insulating layer with respect to the back gate of the transistor 22 or the transistor 32 and then stopping the supply of the potential to the back gate, the gate insulating layer can maintain the polarized state. Therefore, it is not necessary to continuously supply the potential to the back gates of the transistors 22 and 32. Therefore, the semiconductor device 10B1 can be a low-power semiconductor device.

[0087] FIG. 2A is a diagram for explaining a semiconductor device 10A2 which is one aspect of the present invention. In the description of the semiconductor device 10A2 shown hereinafter, the description of the same configurations as those of the semiconductor device 10A1 may be omitted.

[0088] The semiconductor device 10A2 includes a reference cell 21(2) and an arithmetic cell 31(2). The reference cell 21(2) includes a transistor 22, a transistor 24, and a capacitor 25, similarly to the reference cell 21(1). The arithmetic cell 31(2) includes a transistor 32, a transistor 34, and a capacitor 35, similarly to the arithmetic cell 31(1).

[0089] The gate of transistor 22 is electrically connected to wiring WSL. One of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 24 and wiring XCL. The other of the source or drain of transistor 22 is electrically connected to the gate of transistor 24 and one electrode of capacitor 25. Transistor 22 can write the reference potential to the holding node (the gate of transistor 24) in reference cell 21(2) with it being in the on state during data writing, and hold the reference potential in reference cell 21(2) by turning it off. Note that the node to which the gate of transistor 24, the other of the source or drain of transistor 22, and one electrode of capacitor 25 are connected is also referred to as the holding node. The holding node can be set to a potential corresponding to the current flowing through transistor 24.

[0090] The other of the source or drain of transistor 24 and the other electrode of capacitor 25 are connected to a wiring that provides a constant potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 24. Also, the back gate of transistor 24 is electrically connected to wiring XCL.

[0091] Next, the connection relationship within arithmetic cell 31(2) will be described.

[0092] The gate of transistor 32 is electrically connected to wiring WSL. One of the source or drain of transistor 32 is electrically connected to one of the source or drain of transistor 34 and wiring WCL. The other of the source or drain of transistor 32 is electrically connected to the gate of transistor 34 and one electrode of capacitor 35. Transistor 32 can write a voltage corresponding to weight data into arithmetic cell 31(2) by turning on during data writing, and hold the voltage corresponding to weight data in arithmetic cell 31(2) by turning off. Note that the node to which the gate of transistor 34, the other of the source or drain of transistor 32, and one electrode of capacitor 35 are connected is also referred to as a holding node.

[0093] The other of the source or drain of transistor 34 is connected to a wiring that provides a constant potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 34. Also, the back gate of transistor 34 is electrically connected to wiring XCL.

[0094] Next, the transistors included in reference cell 21(2) and arithmetic cell 31(2) will be described.

[0095] Transistors 22 and 32 have a function of holding the potentials of the gates of transistors 24 and 34 by turning off. Specifically, it has a function of holding the reference potential applied to the gate of transistor 24 via transistor 22. Also, it has a function of holding the potential corresponding to the data applied to the gate of transistor 34 via transistor 32.

[0096] As described above, the OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, a leakage current. Therefore, by using the OS transistor as the transistor 22 and / or the transistor 32, the leakage current of the transistor 22 and / or the transistor 32 can be suppressed, and thus the power consumption of the semiconductor device 10A2 can be reduced. Specifically, since the fluctuations in the potentials held at the gates of the transistor 24 and the transistor 34 can be made very small, the refresh operation of the potential can be reduced. Further, by reducing the refresh operation, the power consumption of the semiconductor device 10A2 can be reduced. Also, by making the leakage current from the holding node to the wiring WCL or the wiring XCL extremely small, the cell can hold the potential of the holding node for a long time.

[0097] FIG. 2B is a diagram for explaining a semiconductor device 10B2 which is one aspect of the present invention. In the semiconductor device 10B2, the gate insulating layers for the back gates of the transistor 22 and the transistor 32 included in the semiconductor device 10A2 are assumed to be made of a material having ferroelectricity.

[0098] FIG. 3A is a diagram for explaining a semiconductor device 10A3 which is one aspect of the present invention. In the description of the semiconductor device 10A3 shown hereinafter, the description of the same configurations as those of the semiconductor device 10A1 may be omitted.

[0099] The semiconductor device 10A3 includes a reference cell 21(3) and an arithmetic cell 31(3). The reference cell 21(3) has a transistor 22, a transistor 24, and a capacitor 25, similar to the reference cell 21(1). The arithmetic cell 31(3) has a transistor 32, a transistor 34, and a capacitor 35, similar to the arithmetic cell 31(1). The transistor 22, the transistor 24, the transistor 32, and the transistor 34 each have a gate and a back gate.

[0100] The gate of transistor 22 is electrically connected to wiring WSL. One of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 24 and wiring XCL. The other of the source or drain of transistor 22 is electrically connected to the back gate of transistor 24 and one electrode of capacitor 25. Transistor 22 can write the reference potential to the holding node (the back gate of transistor 24) in reference cell 21(3) in the on state during data writing, and hold the reference potential in reference cell 21(3) by turning off. Note that the node to which the back gate of transistor 24, the other of the source or drain of transistor 22, and one electrode of capacitor 25 are connected is also referred to as the holding node. The holding node can be set to a potential corresponding to the current flowing through transistor 24.

[0101] The other of the source or drain of transistor 24 and the other electrode of capacitor 25 are connected to a wiring that provides a constant potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 24. Also, the gate of transistor 24 is electrically connected to wiring XCL.

[0102] Next, the connection relationship in arithmetic cell 31(3) will be described.

[0103] The gate of transistor 32 is electrically connected to wiring WSL. One of the source or drain of transistor 32 is electrically connected to one of the source or drain of transistor 34 and wiring WCL. The other of the source or drain of transistor 32 is electrically connected to the back gate of transistor 34 and one electrode of capacitor 35. Transistor 32 can write a voltage corresponding to weight data into arithmetic cell 31(3) by being turned on during data writing, and hold the voltage corresponding to weight data in arithmetic cell 31(3) by being turned off. Note that the node to which the back gate of transistor 34, the other of the source or drain of transistor 32, and one electrode of capacitor 35 are connected is also referred to as a holding node.

[0104] The other of the source or drain of transistor 34 is connected to a wiring that provides a fixed potential such as a low power supply potential (e.g., ground potential). The wiring that provides the ground potential functions as a wiring for flowing a current between the source and drain of transistor 34. Also, the gate of transistor 34 is electrically connected to wiring XCL.

[0105] Next, the transistors included in reference cell 21(3) and arithmetic cell 31(3) will be described.

[0106] Transistors 22 and 32 have a function of holding the potentials of the back gates of transistors 24 and 34 by being turned off. Specifically, it has a function of holding the reference potential applied to the back gate of transistor 24 via transistor 22. Also, it has a function of holding the potential corresponding to the data applied to the back gate of transistor 34 via transistor 32.

[0107] As described above, the OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, a leakage current. Therefore, by using the OS transistor as the transistor 22 and / or the transistor 32, the leakage current of the transistor 22 and / or the transistor 32 can be suppressed, and thus the power consumption of the semiconductor device 10A3 can be reduced. Specifically, since the fluctuations in the potentials held at the back gates of the transistor 24 and the transistor 34 can be made very small, the refresh operation of the potential can be reduced. Also, by reducing the refresh operation, the power consumption of the semiconductor device 10A3 can be reduced. Further, by making the leakage current from the holding node to the wiring WCL or the wiring XCL extremely small, the cell can hold the potential of the holding node for a long time.

[0108] FIG. 3B is a diagram for explaining a semiconductor device 10B3 which is one aspect of the present invention. In the semiconductor device 10B3, the gate insulating layers for the back gates of the transistor 22 and the transistor 32 that the semiconductor device 10A3 has are assumed to have a ferroelectric material.

[0109] FIG. 4A is a diagram for explaining a semiconductor device 10C1 which is one aspect of the present invention, FIG. 5A is a diagram for explaining a semiconductor device 10C2 which is one aspect of the present invention, and FIG. 6A is a diagram for explaining a semiconductor device 10C3 which is one aspect of the present invention. In the semiconductor device 10C1, the back gates of the transistor 22 and the transistor 32 that the semiconductor device 10A1 has are assumed to be electrically connected to the circuit HC. Also, in the semiconductor device 10C2, the back gates of the transistor 22 and the transistor 32 that the semiconductor device 10A2 has are assumed to be electrically connected to the circuit HC. In the semiconductor device 10C3, the back gates of the transistor 22 and the transistor 32 that the semiconductor device 10A3 has are assumed to be electrically connected to the circuit HC.

[0110] The circuit HC functions as a holding circuit for holding the potential of the back gate of the transistor 22 and the potential of the back gate of the transistor 32. The circuit HC includes a transistor M1, a transistor M2, a capacitor C1, and a ferroelectric capacitor FEC1. The transistor M1 and the transistor M2 each have a gate and a back gate.

[0111] Each of the transistor M1 and the transistor M2 is preferably an OS transistor. As described above, the OS transistor has an extremely small off-current. Therefore, by using the OS transistor as the transistor M1 and the transistor M2, the potential of the back gate of the transistor 22 and the potential of the back gate of the transistor 32 can be held for a long time.

[0112] The ferroelectric capacitor FEC1 is a capacitor having a material that can have ferroelectricity as a dielectric. In this specification and the like, a capacitor using a material that can have ferroelectricity as a dielectric is referred to as a ferroelectric capacitor.

[0113] In this specification and the like, the circuit symbol of the ferroelectric capacitor (for example, the capacitor FEC1) is shown as adding a diagonal line to the circuit symbol of the capacitor as shown in FIGS. 4A, 5A, and 6A. As another circuit symbol, as shown in FIGS. 4B, 5B, and 6B, a plurality of diagonal lines may be added between two lines that are parallel to each other in the circuit symbol of the capacitor.

[0114] The circuit HC is electrically connected to the reference cell 21 and the arithmetic cell 31. Specifically, the back gates of the transistors 22 and 32 are electrically connected to one of the source or drain of the transistor M1, the back gate of the transistor M1, and one of the source or drain of the transistor M2. The other of the source or drain of the transistor M1 is electrically connected to the wiring VIL. The gate of the transistor M1 is electrically connected to one electrode of the capacitor FEC1. The other of the source or drain of the transistor M2 is electrically connected to the other electrode of the capacitor FEC1 and one electrode of the capacitor C1. The gate of the transistor M2 is electrically connected to the wiring VGL. The other electrode of the capacitor C1 is electrically connected to the wiring VCL.

[0115] In this specification and the like, the electrical connection point between the gate of the transistor M1 and one electrode of the capacitor FEC1 is referred to as the node N1. Also, the electrical connection point between the other electrode of the capacitor FEC1, one electrode of the capacitor C1, and the other of the source or drain of the transistor M2 is referred to as the node N2. Furthermore, the electrical connection point between one of the source or drain of the transistor M1, the back gate of the transistor M1, and one of the source or drain of the transistor M2 is referred to as the node NBG. That is, the potential of the node NBG can be set to the potential applied to the back gates of the transistors 22 and 32.

[0116] Note that since the node N1 is not electrically connected to circuit elements, terminals, wirings, etc. other than the gate of the transistor M1 and one electrode of the capacitor FEC1, no voltage is directly input to the node N1 from a voltage source or the like. Therefore, the node N1 is in a floating state. The initial potential of the node N1 can be determined at the time of manufacturing the semiconductor device (specifically, for example, at the time of forming the circuit HC).

[0117] The wiring VIL functions as a wiring for applying a fixed potential. As the fixed potential, for example, when shifting the threshold voltages of the transistors 22 and 32 to the positive side, it can be a low-level potential, a ground potential, a negative potential, or the like. Also, for example, when shifting the threshold voltages of the transistors 22 and 32 to the negative side, it can be a high-level potential, a positive potential, or the like.

[0118] The wiring VCL functions as a wiring for applying a potential for polarizing a ferroelectric material that may be included in the capacitor FEC1. For example, when the direction of the electric field generated in the material due to the polarization of the material is set to be from one electrode of the capacitor FEC1 to the other electrode, the potential may be a positive potential or the like. Also, for example, when the direction of the electric field generated in the material due to the polarization of the material is set to be from the other electrode of the capacitor FEC1 to one electrode, the potential may be a negative potential or the like. Also, a potential that does not polarize the ferroelectric material that may be included in the capacitor FEC1 may be supplied to the wiring VCL.

[0119] The wiring VGL functions as a wiring for supplying a signal potential for controlling the switching between the on state and the off state of the transistor M2. For example, by setting the potential of the wiring VGL to a high-level potential, the transistor M2 can be turned on, and by setting the potential of the wiring VGL to a low-level potential, the transistor M2 can be turned off.

[0120] Next, a configuration including a plurality of reference cells 21 and arithmetic cells 31 will be described with reference to FIGS. 7A and 7B. FIG. 7A shows an outline of the operation during data writing, and FIG. 7B shows an outline of the operation during data reading.

[0121] In FIGS. 7A and 7B, a reference cell section 20 having a plurality of reference cells 21_1 to 21_m (corresponding to the reference cell 21 in FIG. 1A etc.) and an arithmetic cell section 30 having a plurality of arithmetic cells 31_1,1 to 31_m,n (corresponding to the arithmetic cell 31 in FIG. 1A etc.) are provided. Also, in FIGS. 7A and 7B, a plurality of wirings XCL are illustrated as wirings XCL_1 to XCL_m. Also, in FIGS. 7A and 7B, a plurality of wirings WCL are illustrated as wirings WCL_1 to WCL_n. Note that both m and n are integers of 1 or more.

[0122] In FIGS. 7A and 7B, the cells included in the reference cell section 20 and the arithmetic cell section 30 are arranged in an (n + 1)×m matrix in the row direction and the column direction. The cells included in the reference cell section 20 and the arithmetic cell section 30 may be arranged in a matrix as long as there are two or more cells in the row direction and one or more cells in the column direction.

[0123] In FIGS. 7A and 7B, for the sake of explanation, the reference cell 21 and the arithmetic cell 31 are illustrated in a simplified manner. Terminal C of the reference cell 21 in the reference cell section 20 P corresponds to one electrode of the capacitor 25 in FIG. 1A etc., the back gate of the transistor 24 in FIG. 2A etc., or the gate of the transistor 24 in FIG. 3A etc. Terminal T of the reference cell 21 in the reference cell section 20 W corresponds to one of the source or drain of the transistor 22 in FIGS. 1A, 2A, and 3A etc. and a terminal to which one of the source or drain of the transistor 24 is connected. Terminal C of the arithmetic cell 31 in the arithmetic cell section 30 P corresponds to one electrode of the capacitor 35 in FIG. 1A etc., the back gate of the transistor 34 in FIG. 2A etc., or the gate of the transistor 34 in FIG. 3A etc. Terminal T of the arithmetic cell 31 in the arithmetic cell section 30 X corresponds to a terminal to which one of the source or drain of the transistor 32 and one of the source or drain of the transistor 34 in FIGS. 1A, 2A, and 3A etc. are connected.

[0124] In the operation at the time of data writing shown in FIG. 7A, current I is supplied to the reference cells 21 of each row Xutflows. The current applied to each row is the normalized current I Xut and they are all equal. The current I Xut corresponds to the amount of current (reference current) according to the reference data. Since the arithmetic cells 31 of each row are connected via capacitors, no current flows. In the reference cell 21, it operates so as to hold the voltage corresponding to the flowing current.

[0125] Also, in the operation during data writing shown in FIG. 7A, the current I W1 to I Wn (I W ) flows through each column. The current applied to each column corresponds to the amount of current obtained by multiplying the normalized current I Wut by the weight data w (I W = wI Wut ). The currents I W1 to I Wn may be different for each column.

[0126] In the operation during data reading shown in FIG. 7B, the current I X1 to I Xm (I x ) flows through each row of the reference cells 21. The current I X1 to I Xm applied to each row corresponds to the amount of current obtained by multiplying the normalized current I Xut by the input data x (I X = xI Xut ). The currents I X1 to I Xm may be different for each row. Note that the current I Xut is preferably equal to the current I Wut .

[0127] In the operation during data reading shown in FIG. 7B, the voltage held in the reference cell 21 by the currents I X1 to I Xm is boosted. Due to this boosting, the wirings XCL_1 to XCL_m are also boosted, so that the voltage held by the capacitive coupling of the capacitor 35 in the arithmetic cell 31 is boosted. Then, the potentials of the wirings WCL_1 to WCL_n are set to the voltage Vd. At this time, the current I r flows through the transistor 34.is the product of the current value (I w ) held in the arithmetic cell 31 during data writing and the current value (I x ) passed through the reference cell 21 during data reading, corresponding to (current I r11 to I rmn ). By estimating the sum of the currents I r11 to I rm flowing through each column, data corresponding to the calculation result of the sum of products of the input data and the weight data can be output.

[0128] Note that the sizes (for example, channel length, channel width, transistor configuration, etc.) of the transistors 22 and 24 included in each of the cells of the reference cell section 20 are preferably equal to each other. Also, the sizes of the transistors 32 and 34 included in each of the cells of the arithmetic cell section 30 are preferably equal to each other. Further, the sizes of the transistor 22 and the transistor 32 are preferably equal to each other. Also, the sizes of the transistor 24 and the transistor 34 are preferably equal to each other.

[0129] By making the sizes of the transistors equal to each other, the electrical characteristics of each transistor can be made substantially equal. Therefore, by making the sizes of the transistors 22 included in each of the reference cells 21_1,1 to 21_m,n equal, and making the sizes of the transistors 24 included in each of the reference cells 21_1,1 to 21_m,n equal, each of the reference cells 21_1,1 to 21_m,n can perform substantially the same operation when the conditions are the same for each other. Here, when the conditions are the same, it means that, for example, the input potentials to the source, drain, gate, etc. of the transistor 22, the input potentials to the source, drain, gate, etc. of the transistor 24, the voltages held in each of the reference cells 21_1,1 to 21_m,n, etc. are equal. Also, by making the sizes of the transistors 32 included in each of the arithmetic cells 31_1 to 31_m equal, and making the sizes of the transistors 34 included in each of the arithmetic cells 31_1 to 31_m equal, for example, the arithmetic cells 31_1 to 31_m can make the operation and the result of the operation substantially the same. When the conditions are the same for each other, they can perform substantially the same operation. Here, when the conditions are the same, it means that, for example, the input potentials to the source, drain, gate, etc. of the transistor 32, the input potentials to the source, drain, gate, etc. of the transistor 34, the voltages held in each of the arithmetic cells 31_1 to 31_m, etc. are equal.

[0130] The operations of the reference cell 21(1) and the arithmetic cell 31(1) during data writing will be described with reference to FIG. 8A.

[0131] Set the wiring WSL to the H level and turn on the transistors 22 and 32. Let a current I corresponding to the reference current flow through the wiring XCL. Also, let a current I flow through the wiring WCL. The current I is a current obtained by multiplying the current I normalized by the weight data w (in the figure, I = wI). Xut to flow. W to flow. The current I W is a current obtained by multiplying the current I normalized by the weight data w (in the figure, I Wut = wI w ). Wut corresponds to).

[0132] In the reference cell 21(1), the transistor 22 is turned on. The potential of the holding node to which the back gate of the transistor 24 is electrically connected is such that the threshold voltage of the transistor 24 is V th1 and becomes a potential. As a result, the transistor 24 can pass the current I Xut through between the source and drain of the transistor 24. Specifically, the threshold voltage of the transistor 24 can be set so that the current flowing between the source and drain of the transistor 24 is I Xut In this specification and the like, such an operation may be expressed as "setting (programming) the current flowing between the source and drain of the transistor 24 in the reference cell 21(1) to I Xut ".

[0133] In the arithmetic cell 31(1), the transistor 32 is turned on. The potential of the holding node to which the back gate of the transistor 34 is electrically connected is such that the threshold voltage of the transistor 34 is V th2 and becomes a potential. As a result, the current flowing between the source and drain of the transistor 34 in the arithmetic cell 31(1) is set to I w . Specifically, the threshold voltage of the transistor 34 is set so that the current flowing between the source and drain of the transistor 34 is I w .

[0134] The current I Xut applied to the reference cell 21(1) via the wiring XCL during data writing can be expressed by Equation (2). Here, it is assumed that a ground potential is applied to the gate of the transistor 24 and the other of the source or drain of the transistor 24.

[0135]

Equation

[0136] The current IW can be expressed by Equation (3). Here, it is assumed that a ground potential is applied to the gate of transistor 34 and the other of the source or drain of transistor 34.

[0137]

Number

[0138] As shown in Equation (3), current I w can be expressed as the product of weight data w and normalized current I Wut .

[0139] The operations of reference cell 21(1) and arithmetic cell 31(1) during data reading will be described with reference to FIG. 8B. Note that a period for holding the set current can be provided during the period between data writing and data reading. During the period for holding the set current, transistors 22 and 32 are turned off (OFF). By using transistors 22 and 32 as OS transistors, the potential of the holding node corresponding to the set current can be continuously held.

[0140] In reference cell 21(1), wiring WSL is set to the L level and transistor 22 is turned off (OFF). A current I x corresponding to the input current is passed through wiring XCL. Current I X is a current obtained by multiplying input data x by normalized current I xut (in the figure, I X = xI xut ). The potential of the holding node to which the back gate of transistor 24 is electrically connected varies due to capacitive coupling through capacitor 25 when current I X flows through transistor 24, and thereby the threshold voltage of transistor 24 varies to V th1 + ΔV th . Along with this, the potential of wiring XCL also varies.

[0141] In the arithmetic cell 31(1), the wiring WSL is set to the L level and the transistor 32 is turned off (OFF). Therefore, the holding node of the arithmetic cell 31(1) is in an electrically floating state. Due to the capacitive coupling of the capacitor 35 accompanying the potential fluctuation of the wiring XCL by the operation of the reference cell 21(1), the potential of the holding node of the arithmetic cell 31(1) fluctuates, and the threshold voltage of the transistor 34 becomes V th2 +ΔV th and varies. As a result, a current I r flows between the source and drain of the transistor 34.

[0142] The current I X applied to the reference cell 21(1) via the wiring XCL during data readout can be expressed by Equation (4). Here, it is assumed that a ground potential is applied to the gate of the transistor 24 and the other of the source or drain of the transistor 24.

[0143]

Equation

[0144] In Equation (4), the input data x can be expressed by Equation (5).

[0145]

Equation

[0146] From Equation (4) and Equation (5), the current I X can be expressed as the product of the input data x and the normalized current I Xut .

[0147] During data readout, the wiring WCL is set to the voltage V d so that a current flows through the arithmetic cells 31(1) of each row. Then, as the threshold voltage of the transistor 34 in the arithmetic cell 31(1) changes to V th2 +ΔV th , the current I rcan be represented by Equation (6). Here, it is assumed that a ground potential is applied to the gate of transistor 34 and the other of the source or drain of transistor 34.

[0148] [Number]

[0149] I in Equation (6) from Equation (3) and Equation (5) r can be estimated as a current corresponding to the product of weight data w and input data x. Since the currents flowing through the arithmetic cells 31(1) of each row can be added together, by outputting the current flowing through the wiring WCL to the outside, a signal corresponding to the operation result of the sum-of-products operation processing according to the weight data w and the input data x can be output.

[0150] The operations of the reference cell 2I(2) and the arithmetic cell 3I(2) during data writing will be described with reference to FIG. 9A. In the following description of the operations, it is assumed that when the potential applied to the back gate of transistor 24 is equal to the potential applied to the back gate of transistor 34, the threshold voltage of transistor 24 is equal to the threshold voltage of transistor 34.

[0151] Set the wiring WSL to the H level and turn on transistors 22 and 32. Let a current I Xut corresponding to the reference current flow through the wiring XCL. Also, let a current I W flow through the wiring WCL. As described above, the current I W is a current obtained by multiplying the current I Wut normalized by the weight data w (in the figure, I w = wI Wut ).

[0152] In the reference cell 2I(2), turn on transistor 22. The potential of the holding node to which the gate of transistor 24 is electrically connected becomes V g1 . Also, the potential of the back gate of transistor 24 is such that the threshold voltage of transistor 24 is Vth1 becomes a potential such that. As described above, the transistor 24 has a current I Xut can flow between the source and drain of the transistor 24.

[0153] In the arithmetic cell 31(2), the transistor 32 is turned on. The potential of the holding node to which the gate of the transistor 34 is electrically connected is V g2 becomes. Also, the potential of the back gate of the transistor 34 is such that the threshold voltage of the transistor 34 is V th2 becomes a potential such that. As described above, the current flowing between the source and drain of the transistor 34 in the arithmetic cell 31(2) is I w is set to.

[0154] The current I Xut applied to the reference cell 21(2) via the wiring XCL during data writing can be expressed by Equation (7). Here, it is assumed that a ground potential is applied to the other of the source or drain of the transistor 24.

[0155]

Equation

[0156] The current I W applied to the arithmetic cell 31(2) via the wiring WCL during data writing can be expressed by Equation (8). Here, it is assumed that a ground potential is applied to the other of the source or drain of the transistor 34.

[0157]

Equation

[0158] As shown in Equation (8), the current I w can be expressed as the product of the weight data w and the normalized current I Wut .

[0159] The operations of the reference cell 21(2) and the arithmetic cell 31(2) during data reading will be described with reference to FIG. 9B.

[0160] In the reference cell 21(2), the wiring WSL is set to the L level and the transistor 22 is turned off (OFF). A current I corresponding to the input current flows through the wiring XCL. x As described above, the current I X is the current obtained by multiplying the current I xut normalized by the input data x (in the figure, I X = xI xut ). The potential of the back gate of the transistor 24 varies to a potential such that the threshold voltage of the transistor 24 becomes V X + ΔV th1 as the current I th flows through the transistor 24. Along with this, the potential of the wiring XCL also varies.

[0161] In the arithmetic cell 31(2), the wiring WSL is set to the L level and the transistor 32 is turned off (OFF). As the potential of the wiring XCL varies due to the operation of the reference cell 21(2), the potential of the back gate of the transistor 34 also varies, and the threshold voltage of the transistor 34 varies to V th2 + ΔV th . As a result, a current I r flows between the source and drain of the transistor 34.

[0162] The current I X applied to the reference cell 21(2) via the wiring XCL during data reading can be expressed by Equation (9). Here, it is assumed that the ground potential is applied to the other of the source or drain of the transistor 24.

[0163]

Equation

[0164] In Equation (9), the input data x can be expressed by Equation (10).

[0165]

Number

[0166] From equations (9) and (10), the current I X can be expressed as the product of the input data x and the normalized current I Xut .

[0167] When reading data, the wiring WCL is set to the voltage V so that current flows through the arithmetic cells 31(2) of each row d . And when the threshold voltage of the transistor 34 in the arithmetic cell 31(2) changes to V th2 +ΔV th , the current I flowing through the transistor 34 in the arithmetic cell 31(2) r can be expressed by equation (11). Here, it is assumed that the ground potential is applied to the other of the source or drain of the transistor 34

[0168]

Number

[0169] In equations (8), (10) to (11), I r can be estimated as the current corresponding to the product of the weight data w and the input data x. Since the currents flowing through the arithmetic cells 31(2) of each row can be added together, by outputting the current flowing through the wiring WCL to the outside, a signal corresponding to the operation result of the sum-of-products operation process according to the weight data w and the input data x can be output

[0170] The operations of the reference cell 21(3) and the arithmetic cell 31(3) during data writing will be described with reference to FIG. 10A

[0171] Set the wiring WSL to the H level and turn on the transistors 22 and 32. Let the current I Xut corresponding to the reference current flow through the wiring XCL. Also, let the current I W flow through the wiring WCL. As described above, the current I Wis the current I normalized by the weight data w Wut multiplied by the current (in the figure, I w = wI Wut ).

[0172] In the reference cell 21(3), the transistor 22 is turned on. The potential of the holding node to which the back gate of the transistor 24 is electrically connected becomes a potential such that the threshold voltage of the transistor 24 is V th1 . Also, the potential of the gate of the transistor 24 is V g . Thus, the transistor 24 can pass the current of the current I Xut between the source and drain of the transistor 24. Specifically, the threshold voltage of the transistor 24 can be set so that the current flowing between the source and drain of the transistor 24 is I g when the potential of the gate of the transistor 24 is V Xut .

[0173] In the arithmetic cell 31(3), the transistor 32 is turned on. The potential of the holding node to which the back gate of the transistor 34 is electrically connected becomes a potential such that the threshold voltage of the transistor 24 is V th2 . Also, the potential of the gate of the transistor 34 is V g . Thus, the current flowing between the source and drain of the transistor 34 in the arithmetic cell 31(3) is set to I w . Specifically, the threshold voltage of the transistor 34 is set so that the current flowing between the source and drain of the transistor 34 is I g when the potential of the gate of the transistor 34 is V w .

[0174] The current I Xut applied to the reference cell 21(3) via the wiring XCL during data writing can be expressed by Equation (12). Here, it is assumed that a ground potential is applied to the other of the source or drain of the transistor 24.

[0175]

Number

[0176] The current I applied to the arithmetic cell 31(3) via the wiring WCL during data writing W can be expressed by Equation (13). Here, it is assumed that the ground potential is applied to the other of the source or drain of the transistor 34.

[0177]

Number

[0178] As shown in Equation (13), the current I w is the product of the weight data w and the normalized current I Wut .

[0179] The operations of the reference cell 21(3) and the arithmetic cell 31(3) during data reading will be described with reference to FIG. 10B.

[0180] In the reference cell 21(3), the wiring WSL is set to the L level and the transistor 22 is turned off. A current I x corresponding to the input current flows through the wiring XCL. As described above, the current I X is a current obtained by multiplying the input data x by the normalized current I xut (in the figure, I X = xI xut ). The potential of the gate of the transistor 24 varies to V x + ΔV g as the current I g flows, and the potential of the wiring XCL also varies accordingly.

[0181] In the arithmetic cell 31(3), the wiring WSL is set to the L level and the transistor 32 is turned off. As the potential of the wiring XCL varies due to the operation of the reference cell 21(3), the potential of the gate of the transistor 34 also varies to V g + ΔV gbecomes. When the potential of the gate of transistor 34 changes to V g +ΔV g a current I r flows between the source and drain of transistor 34 in arithmetic cell 31(3).

[0182] The current I X applied to reference cell 21(3) via wiring XCL during data readout can be expressed by Equation (14). Here, it is assumed that the ground potential is applied to the other of the source or drain of transistor 24.

[0183]

Equation

[0184] In Equation (14), the input data x can be expressed by Equation (15).

[0185]

Equation

[0186] From Equation (14) and Equation (15), the current I X can be expressed as the product of the input data x and the normalized current I Xut .

[0187] During data readout, wiring WCL is set to voltage V d so that current flows through the arithmetic cells 31(3) in each row. Then, when the potential of the gate of transistor 34 in arithmetic cell 31(3) changes to V g +ΔV g the current I r flowing through transistor 34 in arithmetic cell 31(3) can be expressed by Equation (16). Here, it is assumed that the ground potential is applied to the other of the source or drain of transistor 34.

[0188]

Equation

[0189] The I in Equation (16) derived from Equations (13) and (15) r can be estimated as the current corresponding to the product of the weight data w and the input data x. Since the currents flowing through the arithmetic cells 31(3) in each row can be added together, by outputting the current flowing through the wiring WCL to the outside, a signal corresponding to the operation result of the sum-of-products operation processing according to the weight data w and the input data x can be output.

[0190] Hereinafter, an operation example of the circuit HC included in the semiconductor device 10C1, the semiconductor device 10C2, and the semiconductor device 10C3 will be described. FIG. 11A is a timing chart showing an operation example of the circuit HC, and shows changes in the potentials of the wiring VCL, the wiring VGL, the wiring VIL, the node N1, the node N2, and the node NBG at times from time T11 to time T16 and in the vicinity thereof. In particular, FIG. 11A shows an operation example of writing a potential to the capacitor FEC1. Also, in FIG. 11A, the high-level potential is denoted as "High" and the low-level potential is denoted as "Low".

[0191] Between time T11 and time T12, potentials in the initial state are applied to each of the wiring VCL, the wiring VGL, and the wiring VIL electrically connected to the circuit HC. Specifically, for example, a potential V FC1 is applied to the wiring VCL, a high-level potential is applied to the wiring VGL, and a potential V IN1 is applied to the wiring VIL. Note that V FC1 can be, for example, a positive potential, a high-level potential, a ground potential, etc., and V IN1 can be, for example, a positive potential, a high-level potential, a ground potential, etc.

[0192] Also, assume that the potential V 11 of the node N1 is lower than the potential V 21 of the node N2. Note that the voltage between the first terminal and the second terminal of the capacitor FEC1 is V 11 -V 12However, it is assumed that no polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1 at this voltage. Also, as long as no polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1 between time T11 and time T12, the potential V 11 of the node N1 21 is not lower than the potential V 21 of the node N2, and may be equal to the potential V 21 or higher than the potential V

[0193] Since a high-level potential from the wiring VGL is applied to the gate of the transistor M2, the transistor M2 is in an on state. Therefore, the connection between the node N2 and the node NBG becomes conductive, and the potential V BG1 of the node NBG 21 becomes almost equal to the potential V

[0194] Between time T12 and time T13, a low-level potential is applied to the wiring VGL. As a result, a low-level potential from the wiring VGL is applied to the gate of the transistor M2, so the transistor M2 is in an off state.

[0195] Also, when the transistor M2 is turned off, the node N2 becomes a floating state.

[0196] Between time T13 and time T14, the potential V FC1 applied by the wiring VCL FC2 changes to the potential V FC2 . The potential V FC1 is lower than V

[0197] and is a potential at which polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1. Since the node N2 is in a floating state, the potential applied by the wiring VCL changes from V FC1 to V FC2By changing to, due to capacitive coupling in capacitor C1, the potential of node N2 changes according to the voltage change. In this operation example, between time T13 and time T14, the potential of node N2 changes from V 21 to V 22 . Note that since the potential V FC2 is lower than V FC1 , the potential V 22 is lower than V 21 .

[0198] Also, since node N1 is also in a floating state, when the potential of node N2 changes from V 21 to V 22 , due to capacitive coupling in capacitor FEC1, the potential of node N1 changes according to the voltage change. However, there is a gate capacitance between the gate and the first terminal of transistor M1 between node N1 and wiring VIL, and there is a gate capacitance between the gate and the second terminal of transistor M1 between node N1 and node NBG. Therefore, the voltage change at node N1 may be smaller than the voltage change V 21 -V 22 at node N2. At this time, the potential of node N1 is assumed to change from V 11 to V 12 .

[0199] At this time, the voltage between the first terminal and the second terminal of capacitor FEC1 is V 12 -V 22 , and it is assumed that polarization occurs in the dielectric that may have ferroelectricity contained in capacitor FEC1. That is, it is assumed that a write operation to capacitor FEC1 is performed at this timing.

[0200] Also, by setting the potential V IN1 given by wiring VIL as a positive potential, a high-level potential, etc., and applying the potential V IN1 from wiring VIL to transistor M1, the potential of node N1 can be boosted through the gate - first terminal of transistor M1. As a result, the voltage V between the first terminal and the second terminal of capacitor FEC112 -V 22 can be increased, and when it is easy to polarize a dielectric that may have ferroelectricity contained in the capacitance FEC1, polarization may occur.

[0201] During the period from time T14 to time T15, the potential V applied by the wiring VCL FC2 is V FC1 changes. That is, the potential applied by the wiring VCL during the period from time T14 to time T15 is assumed to be equal to the potential applied by the wiring VCL at a time before time T13.

[0202] Since the node N2 is in a floating state after time T12, the potential V applied by the wiring VCL FC2 is V FC1 changes, and the potential of the node N2 returns from V 22 to V 21 .

[0203] When the potential of the node N2 changes from V 22 to V 21 , the potential V of the node N1 also changes due to the capacitive coupling of the capacitance FEC1. Note that due to the polarization occurring in the dielectric that may have ferroelectricity contained in the capacitance FEC1 during the operation from time T13 to time T14, the potential of the node N1 does not return to the original potential V 12 , but becomes a potential higher than the potential V 11 and lower than the potential V 12 . In this operation example, during the period from time T14 to time T15, the potential of the node N1 is assumed to change from the potential V 11 to the potential V 12 to the potential V 13 .

[0204] Note that the potential V 13 is lower than the potential V 21 and the potential V IN1 . Here, the gate-source voltage V 13 -V IN1It is assumed to be lower than the threshold voltage of transistor M1, and transistor M1 is turned off.

[0205] Between time T15 and time T16, a high-level potential is applied to wiring VGL. As a result, since the high-level potential from wiring VGL is applied to the gate of transistor M2, transistor M2 is turned on.

[0206] By the above operation, the potential can be written into capacitor FEC1.

[0207] Figure 11B is a timing chart showing an operation example of circuit HC, and shows the changes in the respective potentials of wiring VCL, wiring VGL, wiring VIL, node N1, node N2, and node NBG between time T21 and time T24 and at times in the vicinity thereof. In particular, Figure 11B shows an operation example of writing the potential to the back gates of transistors 22 and 32. Also, in Figure 11B, the high-level potential is denoted as "High" and the low-level potential is denoted as "Low".

[0208] Time T21 is a time after time T16 in the timing chart of Figure 11A. Therefore, between time T21 and time T22, potential V FC1 is applied to wiring VCL, a high-level potential is applied to wiring VGL, and potential V IN1 is applied to wiring VIL. Also, the potential of node N1 is V 13 , the potential of node N2 is V 21 , and node NBG is V BG1 (=V 21 ).

[0209] Between time T22 and time T23, the potential V IN1 applied by wiring VIL changes to potential V IN2 . Note that potential V IN2 is a potential lower than V IN1 . Also, potential V IN2can be, for example, a negative potential, a low-level potential, or the like.

[0210] Since the potential V is supplied to the first terminal of the transistor M1 from the wiring VIL, the gate-source voltage of the transistor M1 is V IN2 - V 13 - V IN2 Here, V 13 - V IN2 is set to a voltage higher than the threshold voltage of the transistor M1.

[0211] By setting V 13 - V IN2 to a voltage higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. Also, since a high-level potential is supplied to the wiring VGL and the transistor M2 is also turned on, the potential from the wiring VIL is supplied to the node N2 via the transistor M1, the node NBG, and the transistor M2.

[0212] Specifically, the potentials of the node N2 and the node NBG decrease from V 21 In this operation example, between time T22 and time T23, the potentials of the node N2 and the node NBG decrease by the voltage ΔV 21 - ΔV BG It is assumed that the potentials of the node N2 and the node NBG decrease by ΔV BG and become V BG2

[0213] Also, as the potential of the node N2 decreases from V 21 to V BG2 the potential V 13 of the node N1 also decreases due to the capacitive coupling of the capacitor FEC1. In this operation example, between time T22 and time T23, the potential of the node N1 is assumed to be V 13 - αΔV BG Here, α is the capacitive coupling coefficient of the capacitor FEC1.

[0214] ​Between time T23 and time T24, the potential V provided by wiring VIL IN2 is V IN1 and changes. That is, the potential provided by wiring VIL between time T23 and time T24 is assumed to be equal to the potential provided by wiring VIL at a time before time T22.

[0215] At this time, since the potential V IN1 from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V 13 -αΔV BG -V IN1 . Note that V 13 -αΔV BG is a potential lower than V 13 , and V 13 is a potential lower than V IN1 . Also, since V 13 -V IN1 is lower than the threshold voltage of transistor M1, V 13 -αΔV BG -V IN1 is also lower than the threshold voltage of transistor M1. As a result, between time T23 and time T24, transistor M1 is in an off state.

[0216] By the above operation, voltage V BG2 can be written to node NBG of circuit HC. In particular, by setting V IN2 to a negative potential, V BG2 can be set to a negative potential, and VBG2 can be written as a negative potential to node NBG of circuit HC. Also, since the gate-source voltage of transistor M1 can be made lower than the threshold voltage to turn off transistor M1, the negative potential V BG2 of node NBG can be held for a long time. As a result, a negative potential V BG2 can be applied to the back gates of transistors 22 and 32 for a long time. Also, depending on the situation, a similar operation may be performed to refresh the negative potential held at node NBG.

[0217] Next, an operation example when rewriting the potential of node NBG after time T24 in the operation example of FIG. 11B will be described.

[0218] [When lowering the potential of node NBG] When it is desired to lower the potential of node NBG, for example, the circuit HC may be operated as shown in the timing chart of FIG. 12A. The timing chart of FIG. 12A shows the changes in the respective potentials of wiring VCL, wiring VGL, wiring VIL, node N1, node N2, and node NBG between time T31 and time T34 and at times in the vicinity thereof. Also, in FIG. 12A, the high-level potential is denoted as "High" and the low-level potential is denoted as "Low".

[0219] Time T31 is a time after time T24 in the timing chart of FIG. 11B. Therefore, between time T31 and time T32, potential V is applied to wiring VCL, a high-level potential is applied to wiring VGL, and potential V is applied to wiring VIL. FC1 is applied, a high-level potential is applied to wiring VGL, and potential V is applied to wiring VIL. IN1 is applied. Also, the potential of node N1 is V 13 -αΔV BG and the potential of node N2 is V BG2 and node NBG is V BG2 at this time.

[0220] Between time T32 and time T33, the potential V applied by wiring VIL changes to potential V IN1 to potential V IN3 . Note that potential V IN3 is a potential lower than V IN2 . Also, potential V IN3 can be, for example, a negative potential lower than V IN2 , a low-level potential, or the like.

[0221] Since potential V IN3 is applied from wiring VIL to the first terminal of transistor M1, the gate-source voltage of transistor M1 becomes V 13 -V IN3 at this time. By the way, V13 -V IN2 is a voltage higher than the threshold voltage of transistor M1, and V IN3 is V IN2 Since it is at a lower potential than, V 13 -V IN3 also becomes a voltage higher than the threshold voltage of transistor M1.

[0222] V 13 -V IN3 Since -V is a voltage higher than the threshold voltage of transistor M1, transistor M1 is in the on state. Also, since a high-level potential is applied to wiring VGL and transistor M2 is also in the on state, the potential from wiring VIL is supplied to node N2 through transistor M1, node NBG, and transistor M2.

[0223] Specifically, the potentials of node N2 and node NBG each decrease from V BG2 In this operation example, between time T32 and time T33, the potentials of node N2 and node NBG each decrease by voltage ΔV BG2 Let's assume it just decreases. Also, the potentials of node N2 and node NBG each decrease by ΔV BGN and become potential V BGN Let's assume it becomes. BG3

[0224] Also, as the potential of node N2 decreases from V BG2 to V BG3 due to the capacitive coupling of capacitor FEC1, the potential V 13 -αΔV BG of node N1 also decreases. In this operation example, between time T32 and time T33, the potential of node N1 is assumed to be V 13 -α(ΔV BG +ΔV BGN ).

[0225] Between time T33 and time T34, the potential V IN3 applied by wiring VIL is V IN1 ​In other words, the potential applied to the wiring VCL from time T33 to time T34 is equal to the potential applied to the wiring VIL at a time before time T32.

[0226] At this time, the first terminal of the transistor M1 receives the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BG +ΔV BGN )-V IN1 In addition, V 13 -α(ΔV BG +ΔV BGN ) is V 13 is lower than V 13 is V IN1 The potential is lower than V 13 -V IN1 is lower than the threshold voltage of transistor M1, so V 13 -α(ΔV BG +ΔV BGN )-V IN1 This causes the transistor M1 to be in an off state between time T33 and time T34.

[0227] By making the circuit HC perform the operation example of FIG. 12B, the voltage written to the node NBG in the operation example of FIG. 11B can be rewritten to a smaller voltage.

[0228] [When increasing the potential of node NBG] To increase the potential of the node NBG, for example, the circuit HC may be operated as shown in the timing chart of Figure 12B. The timing chart of Figure 12B shows changes in the potentials of the wirings VCL, VGL, VIL, node N1, node N2, and node NBG from time T41 to time T45 and at times around those times. In Figure 12B, a high-level potential is represented as "High," and a low-level potential is represented as "Low."

[0229] Time T41 is a time after time T24 in the timing chart of FIG. 11B. Therefore, between time T41 and time T42, a potential V is applied to wiring VCL, a high-level potential is applied to wiring VGL, and a potential V is applied to wiring VIL. Also, the potential of node N1 is V FC1 is applied, a high-level potential is applied to wiring VGL, and a potential V is applied to wiring VIL. Also, the potential of node N1 is V IN1 is applied, and the potential of node N1 is V 13 -αΔV BG and the potential of node N2 is V BG2 and node NBG is at V BG2

[0230] Between time T42 and time T43, the potential V applied by wiring VCL changes to potential V FC1 is changed to potential V FC3 . Note that potential V FC3 is a potential higher than V FC1 .

[0231] When node N2 and node NBG are in a floating state, as the potential applied by wiring VCL changes from V FC1 to V FC3 , due to capacitive coupling in capacitor C1, the potentials of node N2 and node NBG change according to the voltage change. In this operation example, between time T42 and time T43, the potentials of node N2 and node NBG each rise by voltage ΔV BG2 from V BGP . Also, the potentials of node N2 and node NBG each decrease by ΔV BGP and become potential V BG4 .

[0232] Moreover, since node N1 is also in a floating state, as the potential of node N2 changes from V BG2 to V BG4 , due to capacitive coupling in capacitor FEC1, the potential of node N1 changes according to the voltage change. In this operation example, the potential of node N1 changes from V 13 -αΔV BG to V 13 -α(ΔV BG -ΔV​BGP ) is assumed to change.

[0233] During the period from time T42 to time T43, it is assumed that the voltage between node N1 and node N2 does not cause polarization reversal in the dielectric that may have ferroelectricity contained in capacitor FEC1. In other words, the voltage changing from potential V given from wiring VCL FC1 to potential V FC3 is a voltage at which polarization reversal does not occur in the dielectric.

[0234] Since the potential V from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V IN1 - α(ΔV 13 - ΔV BG - ΔV BGP ) - V IN1 . During the period from time T41 to time T42, the gate-source voltage of transistor M1 is V 13 - αΔV BG - V IN1 , so due to the operation from time T42 to time T43 (the change in the potential applied by wiring VCL from V FC1 to V FC3 ), the gate-source voltage of transistor M1 has increased by ΔV BGP .

[0235] Here, assuming that V 13 - α(ΔV BG - ΔV BGP ) - V IN1 is smaller than the threshold voltage of transistor M1, transistor M1 is in the off state.

[0236] Between time T43 and time T44, the potential V applied by wiring VIL IN1 changes to potential V IN4 . Note that potential V IN4 is a potential lower than V IN1 and higher than potential V IN2 . Also, potential V IN4 is, for example, V IN1Lower than and V IN2 Higher negative potential, low-level potential, etc. can be set.

[0237] Since the potential V from the wiring VIL is applied to the first terminal of the transistor M1, IN4 the gate-source voltage of the transistor M1 is V 13 -α(ΔV BG -ΔV BGP )-V IN4 . Here, V 13 -α(ΔV BG -ΔV BGP )-V IN4 is set to a voltage higher than the threshold voltage of the transistor M1.

[0238] V 13 -α(ΔV BG -ΔV BGP )-V IN4 By setting to a voltage higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. Also, since a high-level potential is applied to the wiring VGL and the transistor M2 is also turned on, the potential from the wiring VIL is supplied to the node N2 through the transistor M1, the node NBG, and the transistor M2.

[0239] Specifically, the potentials of the node N2 and the node NBG each decrease from V BG4 . In this operation example, between the time T43 and the time T44, the potentials of the node N2 and the node NBG each decrease by the voltage ΔV BG4 . Also, the potentials of the node N2 and the node NBG each decrease by ΔV BGQ and become the potential V BGQ . BG5

[0240] Also, as the potential of the node N2 decreases from V BG4 to V BG5 , due to the capacitive coupling of the capacitor FEC1, the potential V of the node N1 13 -α(ΔV BGN -ΔVBGP ) also decreases. In this operation example, the potential of the node N1 decreases from time T43 to time T44. 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ) shall be

[0241] Between time T44 and time T45, the potential V IN4 V IN1 In other words, the potential applied to the wiring VIL from time T44 to time T45 is equal to the potential applied to the wiring VIL at a time before time T43.

[0242] At this time, the first terminal of the transistor M1 receives the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ )-V IN1 In addition, V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ) is V 13 is lower than V 13 is V IN1 The potential is lower than V 13 -V IN1 is lower than the threshold voltage of transistor M1, so V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ )-V IN1 This causes the transistor M1 to be in an off state between time T44 and time T45.

[0243] By the above operation, the voltage V BG2 voltage V BG5 In addition, since the transistor M1 is in an off state, the negative potential VBG5 can be held for a long time, so that a negative potential V can be applied to the back gates of the transistors 22 and 32 for a long time. BG5 can be applied.

[0244] By the operations of the timing charts of FIGS. 12A and 12B, the voltage V written in the node NBG of the circuit HC can be rewritten to another potential. BG2 can be rewritten to another potential.

[0245] FIG. 13 is a diagram for explaining the semiconductor device 10D1 having the reference cell 21(1) and the arithmetic cell 31(1), FIG. 14 is a diagram for explaining the semiconductor device 10D2 having the reference cell 21(2) and the arithmetic cell 31(2), and FIG. 15 is a diagram for explaining the semiconductor device 10D3 having the reference cell 21(3) and the arithmetic cell 31(3). The reference cell 21(1) of the semiconductor device 10D1, the reference cell 21(2) of the semiconductor device 10D2, and the reference cell 21(3) of the semiconductor device 10D3 each have a transistor 23 in addition to the transistors 22, 24, and the capacitor 25. Further, the arithmetic cell 31(1) of the semiconductor device 10D1, the arithmetic cell 31(2) of the semiconductor device 10D2, and the arithmetic cell 31(3) of the semiconductor device 10D3 each have a transistor 33 in addition to the transistors 32, 34, and the capacitor 35.

[0246] One of the source or drain of transistor 23 is electrically connected to one of the source or drain of transistor 22 and wiring XCL. The other of the source or drain of transistor 23 is electrically connected to one of the source or drain of transistor 24. One of the source or drain of transistor 33 is electrically connected to one of the source or drain of transistor 32 and wiring WCL. The other of the source or drain of transistor 33 is electrically connected to one of the source or drain of transistor 34. The gates of transistor 23 and transistor 33 are electrically connected to wiring VBL. A fixed potential such as a low power supply potential (e.g., ground potential) can be applied to the back gates of transistor 23 and transistor 33. Note that the potential of the back gate of transistor 23 and the potential of the back gate of transistor 33 may be configured to be variable.

[0247] A bias potential is applied to wiring VBL. Specifically, a potential for operating transistor 23 and transistor 33 in the saturation region is applied to wiring VBL. Thereby, transistor 23 and transistor 33 can have a function as a constant current source, and thus can have a function as a bias transistor. From the above, by applying a bias potential to the gates of transistor 23 and transistor 33, fluctuations in the potential of one of the source or drain of transistor 24 and the potential of one of the source or drain of transistor 34 can be reduced. Thereby, it is possible to suppress fluctuations in the threshold voltage of transistor 24 and the threshold voltage of transistor 34 due to DIBL. As described above, the accuracy of the data obtained by the calculation can be improved.

[0248] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0249] (Embodiment 2) In the present embodiment, an example of an arithmetic unit, which is an apparatus to which a semiconductor device according to one aspect of the present invention can be applied, will be described. The arithmetic unit has a circuit capable of performing a multiply-accumulate operation. The arithmetic unit may be referred to as an arithmetic circuit.

[0250] <Configuration example of arithmetic unit> FIG. 16 shows a configuration example of an arithmetic unit that performs a multiply-accumulate operation on first data and second data. The arithmetic unit MAC1 shown in FIG. 16 is a circuit that performs a multiply-accumulate operation on first data (weight data) corresponding to the potential held in each cell and second data (input data) input thereto, and performs an operation of an activation function using the result of the multiply-accumulate operation. Note that the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0251] The arithmetic unit MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and conversion circuits ITRZ_1 to ITRZ_n.

[0252] The cell array CA includes arithmetic cells 31_1,1 to 31_m,n and reference cells 21_1 to 21_m. Each of the arithmetic cells 31_1,1 to 31_m,n has, for example, a transistor 32, a transistor 34, and a capacitor 35, similar to the arithmetic cell 31 described in the above embodiment. Each of the reference cells 21_1 to 21_m has, for example, a transistor 22, a transistor 24, and a capacitor 25, similar to the reference cell 21 described in the above embodiment. In the following description, "one of the source or drain" described in the first embodiment may be referred to as the "first terminal", and "the other of the source or drain" may be referred to as the "second terminal". Also, in the following description, "one electrode" of the capacitor may be referred to as the "first terminal", and "the other electrode" may be referred to as the "second terminal".

[0253] In FIG. 16, in the arithmetic cell 31_1,1, the connection point of the first terminal of the transistor 32, the back gate of the transistor 34, and the first terminal of the capacitor 35 is defined as the node NN_11. Similarly, in FIG. 16, in the arithmetic cells 31_1,n, 31_m,1, and 31_m,n, the similar connection points are defined as the nodes NN_1n, NN_m1, and NN_mn, respectively. Similarly, in FIG. 16, in the reference cells 21_1 and 21_m, the similar connection points are defined as the nodes NN_ref1 and NNref_m, respectively. Note that the nodes NN_11 to NN_mn and the nodes NNref_1 to NNref_m function as the holding nodes of their respective cells.

[0254] The circuit SWS1 has, as an example, transistors F3_1 to F3_n. The first terminal of the transistor F3_1 is electrically connected to the wiring WCL_1, the second terminal of the transistor F3_1 is electrically connected to the circuit WCS, and the gate of the transistor F3_1 is electrically connected to the wiring SWL1. The first terminal of the transistor F3_n is electrically connected to the wiring WCL_n, the second terminal of the transistor F3_n is electrically connected to the circuit WCS, and the gate of the transistor F3_n is electrically connected to the wiring SWL1.

[0255] As each of the transistors F3_1 to F3_n, for example, a transistor applicable to the transistors included in the cell array CA can be used. In particular, it is preferable to use an OS transistor as each of the transistors F3_1 to F3_n.

[0256] The circuit SWS1 functions as a circuit that makes the circuit WCS and each of the wirings WCL_1 to WCL_n conductive or non-conductive.

[0257] The circuit SWS2 has, as an example, transistors F4_1 to F4_n. The first terminal of transistor F4_1 is electrically connected to wiring WCL_1, the second terminal of transistor F4_1 is electrically connected to the input terminal of conversion circuit ITRZ_1, and the gate of transistor F4_1 is electrically connected to wiring SWL2. The first terminal of transistor F4_n is electrically connected to wiring WCL_n, the second terminal of transistor F4_n is electrically connected to the input terminal of conversion circuit ITRZ_n, and the gate of transistor F4_n is electrically connected to wiring SWL2.

[0258] As each of transistors F4_1 to F4_n, for example, a transistor applicable to the transistors included in cell array CA can be used. In particular, it is preferable to use an OS transistor as each of transistors F4_1 to F4_n.

[0259] The circuit SWS2 has a function of making the state between wiring WCL_1 and conversion circuit ITRZ_1, and between wiring WCL_n and conversion circuit ITRZ_n conductive or non-conductive.

[0260] The circuit WCS has a function of supplying data for storage in each cell included in cell array CA.

[0261] The circuit XCS is electrically connected to wirings XCL_1 to XCL_m. The circuit XCS has a function of passing a current having a current amount corresponding to reference data described later, or a current having a current amount corresponding to second data, through each of reference cells 21_1 and 21_m included in cell array CA.

[0262] The circuit WSD is electrically connected to the wirings WSL_1 to WSL_m. When writing the first data to the arithmetic cells 31_1,1 to 31_m,n, the circuit WSD has a function of selecting a row of the cell array CA that becomes the write destination of the first data by supplying a predetermined signal to the wirings WSL_1 to WSL_m. Specifically, the circuit WSD has a function of generating a signal for controlling the on or off of the transistor 22 and the transistor 32, and applying the signal to the gate of the transistor 22 and the gate of the transistor 32. That is, the wirings WSL_1 to WSL_m function as write word lines.

[0263] Also, as an example, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2. The circuit WSD has a function of making the connection between the circuit WCS and the cell array CA conductive or non-conductive by supplying a predetermined signal to the wiring SWL1, and a function of making the connection between the conversion circuits ITRZ_1 to ITRZ_n and the cell array CA conductive or non-conductive by supplying a predetermined signal to the wiring SWL2.

[0264] Each of the conversion circuits ITRZ_1 to ITRZ_n has, as an example, an input terminal and an output terminal. For example, the output terminal of the conversion circuit ITRZ_1 is electrically connected to the wiring OL_1, and the output terminal of the conversion circuit ITRZ_n is electrically connected to the wiring OL_n.

[0265] Each of the conversion circuits ITRZ_1 to ITRZ_n has a function of converting, when a current is input to the input terminal, into a voltage corresponding to the amount of the current and outputting the voltage from the output terminal. The voltage can be, for example, an analog voltage, a digital voltage, or the like. Also, each of the conversion circuits ITRZ_1 to ITRZ_n may have an arithmetic circuit of a function system. In this case, for example, using the converted voltage, an arithmetic operation of a function may be performed by the arithmetic circuit, and the result of the arithmetic operation may be output to the wirings OL_1 to OL_n.

[0266] In particular, when performing operations on a hierarchical neural network, as the above-mentioned functions, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used.

[0267] <<Circuit WCS, Circuit XCS>> Here, specific examples of circuit WCS and circuit XCS will be described.

[0268] First, circuit WCS will be described. FIG. 17A is a block diagram showing an example of circuit WCS. Note that in FIG. 17A, for showing the electrical connection with the circuits around circuit WCS, circuit SWS1, transistor F3, wiring SWL1, and wiring WCL are also shown. Further, transistor F3 is any one of transistors F3_1 to F3_n included in the arithmetic unit MAC1 in FIG. 16, and wiring WCL is any one of wirings WCL_1 to WCL_n included in the arithmetic unit MAC1 in FIG. 16.

[0269] The circuit WCS shown in FIG. 17A has, as an example, a switch SWW. The first terminal of switch SWW is electrically connected to the second terminal of transistor F3, and the second terminal of switch SWW is electrically connected to wiring VINIL1. Wiring VINIL1 functions as a wiring for applying an initialization potential to wiring WCL, and as the initialization potential, a ground potential (GND), a low-level potential, a high-level potential, etc. can be used. Note that switch SWW is in an on state only when applying an initialization potential to wiring WCL, and is in an off state at other times.

[0270] As switch SWW, for example, an electrical switch such as an analog switch or a transistor can be applied. Note that when applying, for example, a transistor as switch SWW, as the transistor, for example, a transistor applicable to the transistors of cell array CA can be used. Also, other than an electrical switch, a mechanical switch may be applied.

[0271] Also, as an example, the circuit WCS in FIG. 17A has a plurality of current sources CS. Specifically, the circuit WCS has a function of outputting first data of K bits (2 K values) (K is an integer of 1 or more) as a current. In this case, the circuit WCS has 2 K −1 current sources CS. Note that the circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 K-1 current sources CS that output information corresponding to the value of the Kth bit as a current.

[0272] In FIG. 17A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 included in the circuit SWS1. Also, the terminal T2 of one current source CS is electrically connected to the wiring DW_1, and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DW_2, and 2 K-1 each of the terminals T2 of the current sources CS is electrically connected to the wiring DW_K.

[0273] The plurality of current sources CS included in the circuit WCS each have a function of outputting the same constant current I Wut from the terminal T1. The constant current I Wut corresponds to the normalized current I Wut described in Embodiment 1. In practice, in the manufacturing stage of the arithmetic unit MAC1, an error may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is described that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the circuit WCS.

[0274] The wirings DW_1 to DW_K are for the constant current I from the current sources CS that are electrically connectedWut functions as a wiring for transmitting a control signal for outputting. Specifically, for example, when a high-level potential is applied to the wiring DW_1, the current source CS electrically connected to the wiring DW_1 supplies a constant current of I Wut to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW_1, the current source CS electrically connected to the wiring DW_1 does not supply I Wut .

[0275] The current supplied by one current source CS electrically connected to the wiring DW_1 corresponds to the value of the first bit, the current supplied by two current sources CS electrically connected to the wiring DW_2 corresponds to the value of the second bit, and the current supplied by K current sources CS electrically connected to the wiring DW_K corresponds to the value of the Kth bit.

[0276] In FIG. 17A, the circuit WCS in the case where K is an integer of 3 or more is illustrated. However, when K is 1, the circuit WCS in FIG. 17A may be configured without providing the current sources CS electrically connected to the wirings DW_2 to DW_K. When K is 2, the circuit WCS in FIG. 17A may be configured without providing the current sources CS electrically connected to the wirings DW_3 to DW_K.

[0277] Next, a specific configuration example of the current source CS will be described.

[0278] The current source CS1 shown in FIG. 18A is a circuit applicable to the current source CS included in the circuit WCS of FIG. 17A, and the current source CS1 includes a transistor Tr1 and a transistor Tr2.

[0279] The first terminal of transistor Tr1 is electrically connected to wiring VDDL, and the second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr1, the back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is electrically connected to terminal T1, and the gate of transistor Tr2 is electrically connected to terminal T2. Also, terminal T2 is electrically connected to wiring DW.

[0280] Wiring DW is any one of wirings DW_1 to DW_K in FIG. 17A.

[0281] Wiring VDDL functions as a wiring that provides a fixed potential. As the fixed potential, for example, a high-level potential can be used.

[0282] When the fixed potential provided by wiring VDDL is a high-level potential, a high-level potential is input to the first terminal of transistor Tr1. Also, the potential of the second terminal of transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of transistor Tr1 functions as a drain, and the second terminal of transistor Tr1 functions as a source. Also, since the gate of transistor Tr1 and the second terminal of transistor Tr1 are electrically connected, the gate-source voltage of transistor Tr1 becomes 0V. Therefore, when the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) in the current range of the subthreshold region flows between the first terminal and the second terminal of transistor Tr1. As the amount of this current, when transistor Tr1 is an OS transistor, for example, it is preferably 1.0×10 -8 A or less, more preferably 1.0×10 -12 A or less, and even more preferably 1.0×10 -15 A or less. Also, for example, it is more preferable that the current is within a range that increases exponentially with respect to the gate-source voltage. That is, transistor Tr1 functions as a current source for flowing a current in the current range when operating in the subthreshold region. Note that the current is the I described aboveWut or I described later Xut corresponds to.

[0283] Transistor Tr2 functions as a switching element. By the way, when the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage becomes 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, when a high-level potential is input to the gate of transistor Tr2, transistor Tr2 is assumed to be in an on state, and when a low-level potential is input to the gate of transistor Tr2, transistor Tr2 is assumed to be in an off state. Specifically, when transistor Tr2 is in the on state, a current within the current range of the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is in the off state, it is assumed that the current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0284] Note that the circuit applicable to the current source CS included in the circuit WCS in FIG. 17A is not limited to the current source CS1 in FIG. 18A. For example, although the current source CS1 has a configuration in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, the back gate of the transistor Tr2 may be electrically connected to another wiring. Such a configuration example is shown in FIG. 18B. The current source CS2 shown in FIG. 18B has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL. The current source CS2 can apply a predetermined potential to the wiring VTHL by the external circuit or the like when the wiring VTHL is electrically connected to the external circuit or the like, and apply the predetermined potential to the back gate of the transistor Tr2. Thereby, the threshold voltage of the transistor Tr2 can be varied. In particular, by increasing the threshold voltage of the transistor Tr2, the off-current of the transistor Tr2 can be reduced.

[0285] Also, for example, the current source CS1 is configured such that the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected. However, a configuration in which the voltage is held between the back gate and the second terminal of the transistor Tr2 by a capacitor may be employed. Such a configuration example is shown in FIG. 18C. The current source CS3 shown in FIG. 18C includes a transistor Tr3 and a capacitor C6 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 differs from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitor C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected. Further, the current source CS3 is configured such that the second terminal of the transistor Tr3 is electrically connected to the wiring VTL and the gate of the transistor Tr3 is electrically connected to the wiring VWL. The current source CS3 can make the connection between the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the capacitor C6 can hold the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1. That is, by determining the voltage applied from the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

[0286] Also, for example, as a circuit applicable to the current source CS included in the circuit WCS of FIG. 17A, it may be the current source CS4 shown in FIG. 18D. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 18C, the back gate of the transistor Tr2 is electrically connected not to the second terminal of the transistor Tr2 but to the wiring VTHL. That is, similar to the current source CS2 of FIG. 18B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential provided by the wiring VTHL.

[0287] In the current source CS4, when a large current flows between the first terminal and the second terminal of the transistor Tr1, in order to flow the current from the terminal T1 to the outside of the current source CS4, it is necessary to increase the on-current of the transistor Tr2. In this case, the current source CS4 applies a high-level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and increases the on-current of the transistor Tr2, so that a large current flowing between the first terminal and the second terminal of the transistor Tr1 can be flowed from the terminal T1 to the outside of the current source CS4.

[0288] By applying the current sources CS1 to CS4 shown in FIGS. 18A to 18D as the current source CS included in the circuit WCS of FIG. 17A, the circuit WCS can output a current corresponding to the K-bit first data. Also, the amount of the current can be, for example, the current flowing between the first terminal and the second terminal within the range where the transistor 34 operates in the subthreshold region.

[0289] Also, as the circuit WCS of FIG. 17A, the circuit WCS shown in FIG. 17B may be applied. The circuit WCS of FIG. 17B has a configuration in which one current source CS of FIG. 18A is connected to each of the wirings DW_1 to DW_K. Also, when the channel width of the transistor Tr-1_1 is w_1, the channel width of the transistor Tr-1_2 is w_2, and the channel width of the transistor Tr-1_K is w_K, the ratio of each channel width is w_1:w_2:w_K = 1:2:2 K-1It is configured as follows. Since the current flowing between the source and drain of the transistor operating in the subthreshold region is proportional to the channel width, the circuit WCS shown in FIG. 17B can output a current corresponding to the first data of K bits, similar to the circuit WCS in FIG. 17A.

[0290] Note that for the transistor Tr1 (including transistors Tr1_1 to Tr2_K), the transistor Tr2 (including transistors Tr2_1 to Tr2_K), and the transistor Tr3, for example, transistors applicable to the transistors of the cell array CA can be used. In particular, as the transistor Tr1 (including transistors Tr1_1 to Tr2_K), the transistor Tr2 (including transistors Tr2_1 to Tr2_K), and the transistor Tr3, it is preferable to use OS transistors.

[0291] Next, a specific example of the circuit XCS will be described.

[0292] FIG. 17C is a block diagram showing an example of the circuit XCS. Note that in FIG. 17C, for showing the electrical connection with the circuits around the circuit WCS, the wiring XCL is also shown. Also, the wiring XCL is any one of the wirings XCL_1 to XCL_m included in the arithmetic unit MAC1 in FIG. 16.

[0293] The circuit XCS shown in FIG. 17C has, as an example, a switch SWX. The first terminal of the switch SWX is electrically connected to the wiring XCL and a plurality of current sources CS, and the second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring for applying an initialization potential to the wiring XCL, and as the initialization potential, a ground potential (GND), a low-level potential, a high-level potential, etc. can be used. Also, the initialization potential applied by the wiring VINIL2 may be made equal to the potential applied by the wiring VINIL1. Note that the switch SWX is in an on state only when applying an initialization potential to the wiring XCL, and is in an off state at other times.

[0294] As the switch SWX, for example, a switch applicable to the switch SWW can be used.

[0295] Also, the circuit configuration of the circuit XCS in FIG. 17C can be made substantially the same as that of the circuit WCS in FIG. 17A. Specifically, the circuit XCS has a function of outputting reference data as a current and a function of outputting second data of L bits (2 L values) (L is an integer of 1 or more) as a current. In this case, the circuit XCS has 2 L -1 current sources CS. Note that the circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 L-1 current sources CS that output information corresponding to the value of the Lth bit as a current.

[0296] By the way, as the reference data output by the circuit XCS as a current, for example, information in which the value of the first bit is "1" and the values of the bits after the second bit are "0" can be used.

[0297] In FIG. 17C, the terminal T2 of one current source CS is electrically connected to the wiring DX_1, and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DX_2, and 2 L-1 each of the terminals T2 of the current sources CS is electrically connected to the wiring DX_K.

[0298] The plurality of current sources CS included in the circuit XCS each have a function of outputting the same constant current I Xut from the terminal T1. Also, the wirings DX_1 to DX_K function as wirings for transmitting a control signal for outputting I Xut from the electrically connected current sources CS. That is, the circuit XCS has a function of flowing a current corresponding to the L-bit information sent from the wirings DX_1 to DX_K through the wiring XCL.

[0299] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCS, the constant current I output from each of the terminals T1 of the plurality of current sources CS Xut should preferably have an error within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that there is no error in the constant current I output from the terminals T1 of the plurality of current sources CS included in the circuit XCS Xut .

[0300] Also, as the current source CS of the circuit XCS, similar to the current source CS of the circuit WCS, any one of the current sources CS1 to CS4 in FIGS. 18A to 18D can be applied. In this case, the wiring DW shown in FIGS. 18A to 18D may be replaced with the wiring DX. Thereby, the circuit XCS can cause a current in the current range of the subthreshold region to flow through the wiring XCL as reference data or as the second data of the L bits

[0301] Also, as the circuit XCS in FIG. 17C, a circuit configuration similar to the circuit WCS shown in FIG. 17B can be applied. In this case, the circuit WCS shown in FIG. 17B may be replaced with the circuit XCS, the wiring DW_1 may be replaced with the wiring DX_1, the wiring DW_2 may be replaced with the wiring DX_2, the wiring DW_K may be replaced with the wiring DX_K, the switch SWW may be replaced with the switch SWX, and the wiring VINIL1 may be replaced with the wiring VINIL2 for consideration

[0302] <<Conversion circuits ITRZ_1 to ITRZ_n>> Here, a specific example of a circuit applicable to the conversion circuits ITRZ_1 to ITRZ_n included in the arithmetic unit MAC1 in FIG. 16 will be described

[0303] The conversion circuit ITRZ1 shown in FIG. 19A is an example of a circuit applicable to the conversion circuits ITRZ_1 to ITRZ_n in FIG. 16. In FIG. 19A, for showing the electrical connection with the circuits around the conversion circuit ITRZ1, the circuit SWS2, the wiring WCL, the wiring SWL2, and the transistor F4 are also illustrated. Further, the wiring WCL is any one of the wirings WCL_1 to WCL_n included in the arithmetic unit MAC1 in FIG. 16, and the transistor F4 is any one of the transistors F4_1 to F4_n included in the arithmetic unit MAC1 in FIG. 16.

[0304] The conversion circuit ITRZ1 in FIG. 19A is electrically connected to the wiring WCL via the transistor F4. Also, the conversion circuit ITRZ1 is electrically connected to the wiring OL. The conversion circuit ITRZ1 has a function of converting the current flowing from the conversion circuit ITRZ1 to the wiring WCL or the current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. That is, the conversion circuit ITRZ1 has a current-voltage conversion circuit.

[0305] As an example, the conversion circuit ITRZ1 in FIG. 19A has a resistor R5 and an operational amplifier OP1.

[0306] The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

[0307] The wiring VRL functions as a wiring for applying a fixed potential. As the fixed potential, for example, the ground potential (GND), a low-level potential, etc. can be used.

[0308] By configuring the conversion circuit ITRZ1 as shown in Fig. 19A, the current flowing into the conversion circuit ITRZ1 from the wiring WCL via the transistor F4 or the current flowing from the conversion circuit ITRZ1 to the wiring WCL via the transistor F4 can be converted into an analog voltage and output to the wiring OL.

[0309] In particular, by setting the constant potential provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, so that the analog voltage output to the wiring OL can be a voltage referenced to the ground potential (GND).

[0310] Also, although the conversion circuit ITRZ1 in Fig. 19A is configured to output an analog voltage, the circuit configuration applicable to the conversion circuits ITRZ_1 to ITRZ_n in Fig. 16 is not limited to this. For example, the conversion circuit ITRZ1 may be configured to have an analog-to-digital conversion circuit ADC as shown in Fig. 19B. Specifically, in the conversion circuit ITRZ2 of Fig. 19B, the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. By adopting such a configuration, the conversion circuit ITRZ2 in Fig. 19B can output a digital signal to the wiring OL.

[0311] Also, in the conversion circuit ITRZ2, when the digital signal output to the wiring OL is 1-bit (binary), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZ3 shown in FIG. 19C. The conversion circuit ITRZ3 in FIG. 19C has a configuration in which a comparator CMP1 is provided in the conversion circuit ITRZ1 in FIG. 19A. Specifically, in the conversion circuit ITRZ3, the first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, the second input terminal of the comparator CMP1 is electrically connected to the wiring VRL2, and the output terminal of the comparator CMP1 is electrically connected to the wiring OL. The wiring VRL2 functions as a wiring that gives a potential for comparing with the potential of the first terminal of the comparator CMP1. With such a configuration, the conversion circuit ITRZ3 in FIG. 19C can output a low-level potential or a high-level potential (binary digital signal) to the wiring OL according to the magnitude of the voltage converted from the current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage given by the wiring VRL2.

[0312] Also, the conversion circuits ITRZ_1 to ITRZ_n applicable to the arithmetic unit MAC1 in FIG. 16 are not limited to the conversion circuits ITRZ1 to ITRZ3 shown in FIGS. 19A to 19C respectively. For example, when using the arithmetic unit MAC1 for the operation of a hierarchical neural network, it is preferable that the conversion circuits ITRZ1 to ITRZ3 have a functional arithmetic unit. Also, as the functional arithmetic unit, it can be an arithmetic unit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function.

[0313] <Operation Example of Arithmetic Unit> Next, an operation example of the arithmetic unit MAC1 will be described.

[0314] Fig. 20 shows a timing chart of an operation example of the arithmetic unit MAC1. The timing chart of Fig. 20 shows the potential fluctuations of wiring SWL1, wiring SWL2, wiring WSL_i (where i is an integer from 1 to m - 1), wiring WSL_i+1, wiring XCL_i, wiring XCL_i+1, node NN_i,j (where j is an integer from 1 to n - 1), node NN_i+1,j, node NNref_i, and node NNref_i+1 during the period from time T51 to time T63 and in the vicinity thereof. Further, the timing chart of Fig. 20 also shows the respective fluctuations of the current I 34 _i,j flowing between the first terminal and the second terminal of the transistor 34 included in the arithmetic cell 31_i,j, the current I 24 _i flowing between the first terminal and the second terminal of the transistor 24 included in the reference cell 21_i, the current I 34 _i+1,j flowing between the first terminal and the second terminal of the transistor 34 included in the arithmetic cell 31_i+1,j, and the current I 24 _i+1 flowing between the first terminal and the second terminal of the transistor 24 included in the reference cell 21_i+1.

[0315] Note that, as the circuit WCS of the arithmetic unit MAC1, the circuit WCS in Fig. 17A is applied, and as the circuit XCS of the arithmetic unit MAC1, the circuit XCS in Fig. 17C is applied.

[0316] In this operation example, the source potentials of transistors 24 and 34 are set to the ground potential GND. Also, before time T51, as an initial setting, the potentials of nodes NN_i,j, NN_i+1,j, NNref_i, and NNref_i+1 are assumed to be set to the ground potential GND. Specifically, for example, the initialization potential of wiring VINIL1 in FIG. 17A is set to the ground potential GND, and by turning on each of the transistors 32 included in switch SWW, transistor F3, and arithmetic cells 31_i,j and 31_i+1,j, the potentials of nodes NN_i,j and NN_i+1,j can be set to the ground potential GND. Further, for example, the initialization potential of wiring VINIL2 in FIG. 17C is set to the ground potential GND, and by turning on each of the transistors 22 included in switch SWX and arithmetic cells 31_i,j and 31_i+1,j, the potentials of nodes NNref_i,j and NNref_i+1,j can be set to the ground potential GND.

[0317] <<From time T51 to time T52>> During the period from time T51 to time T52, a high-level potential (denoted as High in FIG. 20) is applied to wiring SWL1, and a low-level potential (denoted as Low in FIG. 20) is applied to wiring SWL2. As a result, a high-level potential is applied to the gates of transistors F3_1 to F3_n, causing each of transistors F3_1 to F3_n to be in an on state, and a low-level potential is applied to the gates of transistors F4_1 to F4_n, causing each of transistors F4_1 to F4_n to be in an off state.

[0318] Also, between time T51 and time T52, low-level potentials are applied to wiring WSL_i and wiring WSL_i+1. As a result, low-level potentials are applied to the gates of transistors 32 included in arithmetic cells 31_i,1 to 31_i,n in the i-th row of cell array CA and to the gates of transistors 22 included in reference cell 21_i, causing transistors 32 and transistors 22 to be in an off state. Also, low-level potentials are applied to the gates of transistors 32 included in arithmetic cells 31_i+1,1 to 31_i+1,n in the (i+1)-th row of cell array CA and to the gates of transistors 22 included in reference cell 21_i+1, causing transistors 32 and transistors 22 to be in an off state.

[0319] Also, between time T51 and time T52, ground potential GND is applied to wiring XCL_i and wiring XCL_i+1. Specifically, for example, when the wiring XCL shown in FIG. 17C is each of wiring XCL_i and wiring XCL_i+1, by setting the initialization potential of wiring VINIL2 to ground potential GND and turning switch SWX on, the potentials of wiring XCL_i and wiring XCL_i+1 can be set to ground potential GND.

[0320] Also, between time T51 and time T52, when the wiring WCL shown in FIG. 17A is each of wiring WCL_1 to wiring WCL_K, first data is not input to wiring DW_1 to wiring DW_K. Also, when the wiring XCL shown in FIG. 17C is each of wiring XCL_1 to wiring XCL_K, second data is not input to wiring DX_1 to wiring DX_K. Here, in circuit WCS of FIG. 17A, it is assumed that low-level potentials are input to each of wiring DW_1 to wiring DW_K, and in circuit XCS of FIG. 17C, it is assumed that low-level potentials are input to each of wiring DX_1 to wiring DX_K.

[0321] Also, between time T51 and time T52, no current flows through wiring WCL_j, wiring XCL_i, and wiring XCL_i+1. Therefore, I 34 _i,j, I 24 _i, I 34 _i+1,j, I 24 _i+1 becomes 0.

[0322] <<From time T52 to time T53>> During the period from time T52 to time T53, a high-level potential is applied to wiring WSL_i. As a result, a high-level potential is applied to the gates of the transistors 32 included in the arithmetic cells 31_i,1 to 31_i,n in the i-th row of the cell array CA and to the gates of the transistors 22 included in the reference cell 21_i, and the respective transistors 32 and transistors 22 are turned on. Also, during the period from time T52 to time T53, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i, and the transistors 32 included in the arithmetic cells 31_1,1 to 31_m,n other than the i-th row of the cell array CA and the transistors 22 included in the reference cells 21_1 to 21_m other than the i-th row are assumed to be in an off state.

[0323] Furthermore, a ground potential GND is continuously applied to the wirings XCL_1 to XCL_m since before time T52.

[0324] <<From time T53 to time T54>> During the period from time T53 to time T54, current I 0_ i,j flows from the circuit WCS to the cell array CA via the transistor F3_j as the first data. Specifically, when the wiring WCL shown in FIG. 17A is the wiring WCL_j, signals corresponding to the first data are input to each of the wirings DW_1 to DW_K, and current I 0_ i,j flows to the second terminal of the transistor F3_j from the circuit WCS. That is, the value of the K-bit signal input as the first data is α_i,j (α_i,j is 0 or more and 2 KWhen it is an integer of -1 or less), I0_i,j = α_i,j × I Wut This results in (in the figure, "×" is illustrated as "*").

[0325] Note that when α_i,j is 0, I0_i,j = 0. Strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3_j. However, in this specification, etc., there may be descriptions such as "a current of I0_i,j = 0 flows".

[0326] Between time T53 and time T54, the connection between the first terminal of transistor 32 included in arithmetic cell 31_i,j in the i-th row of cell array CA and wiring WCL_j is in a conductive state, and the connections between the first terminals of transistors 32 included in arithmetic cells 31_1,j to 31_m,j other than the i-th row of cell array CA and wiring WCL_j are in a non-conductive state. Therefore, current I0_i,j flows from wiring WCL_j to arithmetic cell 31_i,j.

[0327] By the way, the transistor 32 included in arithmetic cell 31_i,j is turned on. In transistor 34, the gate-source voltage becomes V g _i,j - GND, and current I0_i,j is set as the current flowing between the first terminal and the second terminal of transistor 34.

[0328] Also, between time T53 and time T54, current I ref0 flows from circuit XCS to wiring XCL_i as reference data. Specifically, when the wiring XCL described in FIG. 17C is wiring XCL_i, a high-level potential is input to wiring DX_1, and low-level potentials are input to each of wirings DX_2 to DX_K, and current I ref0 flows from circuit XCS to wiring XCL_i. That is, I ref0 = I Xut This results in.

[0329] Between time T53 and time T54, since the connection between the first terminal of the transistor 22 included in the reference cell 21_i and the wiring XCL_i is in a conductive state, a current I ref0 flows from the wiring XCL_i to the reference cell 21_i.

[0330] [[ID=⑥]]Similar to the arithmetic cell 31_i,j, the transistor 22 included in the reference cell 21_i is turned on. In the transistor 24, the gate-source voltage becomes V gm _i - GND, and as the current flowing between the first terminal and the second terminal of the transistor 24, a current I ref0 is set.

[0331] <<From time T54 to time T55>> During the period from time T54 to time T55, a low-level potential is applied to the wiring WSL_i. As a result, a low-level potential is applied to the gates of the transistors 32 included in the arithmetic cells 31_i,1 to 31_i,n in the i-th row of the cell array CA and the gate of the transistor 22 included in the reference cell 21_i, and the respective transistors 32 and 22 are turned off.

[0332] When the transistor 32 included in the arithmetic cell 31_i,j is turned off, the capacitor 35 holds V g _i,j - V gm _i, which is the difference between the potential of the gate (node NN_i,j) of the transistor 34 and the potential of the wiring XCL_i. Also, when the transistor 32 included in the reference cell 21_i is turned off, the capacitor 25 holds 0, which is the difference between the potential of the gate (node NNref_i) of the transistor 24 and the potential of the wiring XCL_i.

[0333] <<From time T55 to time T56>> Between time T55 and time T56, GND is applied to wiring XCL_i. Specifically, for example, when the wiring XCL shown in FIG. 17C is the wiring XCL_i, by setting the initialization potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX, the potential of the wiring XCL_i can be set to the ground potential GND.

[0334] Therefore, due to capacitive coupling by the capacitors 35 included in each of the arithmetic cells 31_i,1 to 31_i,n in the i-th row, the potentials of the nodes NN_i,1 to NN_i,n change, and due to capacitive coupling by the capacitor 25 included in the reference cell 21_i, the potential of the node NNref_i changes.

[0335] The amount of change in the potentials of the nodes NN_i,1 to NN_i,n is the potential obtained by multiplying the amount of change in the potential of the wiring XCL_i by the capacitive coupling coefficient determined by the configuration of each of the arithmetic cells 31_i,1 to 31_i,n included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor 35, the gate capacitance of the transistor 34, parasitic capacitance, etc. In each of the arithmetic cells 31_i,1 to 31_i,n, when the capacitive coupling coefficient due to the capacitor 35 is p, the potential of the node NN_i,j of the arithmetic cell 31_i,j decreases by p(V gm _i - GND) from the potential at the time point between time T54 and time T55.

[0336] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to capacitive coupling by the capacitor 25 included in the reference cell 21_i. When the capacitive coupling coefficient due to the capacitor 25 is set to p in the same manner as the capacitor 35, the potential of the node NNref_i of the reference cell 21_i decreases by p(V gm _i - GND) from the potential between time T54 and time T55. In the timing chart of FIG. 20, as an example, p = 1 is used. Therefore, the potential of the node NNref_i between time T55 and time T56 becomes GND.

[0337] As a result, the potential of the node NN_i,j of the arithmetic cell 31_i,j decreases, so the transistor 34 turns off. Similarly, since the potential of the node NNref_i of the reference cell 21_i decreases, the transistor 24 also turns off. Therefore, between time T55 and time T56, I 34 _i,j, I 24 _i each become 0.

[0338] <<From time T56 to time T57>> During the period from time T56 to time T57, a high-level potential is applied to the wiring WSL_i + 1. As a result, a high-level potential is applied to the gates of the transistors 32 included in the arithmetic cells 31_i + 1,1 to 31_i + 1,n in the (i + 1)-th row of the cell array CA and to the gate of the transistor 22 included in the reference cell 21_i + 1, and the respective transistors 32 and 22 turn on. Also, during the period from time T56 to time T57, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i + 1, and it is assumed that the transistors 32 included in the arithmetic cells 31_1,1 to 31_m,n other than the (i + 1)-th row of the cell array CA and the transistors 22 included in the reference cells 21_1 to 21_m other than the (i + 1)-th row are in the off state.

[0339] Furthermore, a ground potential GND has been continuously applied to the wirings XCL_1 to XCL_m since before time T56.

[0340] <<From time T57 to time T58>> Between time T57 and time T58, current I0_i+1,j flows from circuit WCS to cell array CA as the first data via transistor F3_j. Specifically, when the wiring WCL shown in FIG. 17A is wiring WCL_j+1, signals corresponding to the first data are input to each of wirings DW_1 to DW_K, and current I0_i+1,j flows from circuit WCS to the second terminal of transistor F3_j. That is, when the value of the K-bit signal input as the first data is α_i+1,j (α_i+1,j is an integer of 0 or more and 2 K -1 or less), I0_i+1,j = α_i+1,j × I Wut holds (in the figure, "×" is illustrated as "*").

[0341] Note that when α_i+1,j is 0, I0_i+1,j = 0. Strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3_j. However, in this specification and the like, there may be cases where it is described as "current I0_i+1,j = 0 flows" in the same manner as when I0_i,j = 0.

[0342] At this time, the connection between the first terminal of transistor 32 included in arithmetic cell 31_i+1,j in the (i + 1)-th row of cell array CA and wiring WCL_j is in a conductive state, and the connections between the first terminals of transistors 32 included in arithmetic cells 31_1,j to 31_m,j other than the (i + 1)-th row of cell array CA and wiring WCL_j are in a non-conductive state. Therefore, current I0_i+1,j flows from wiring WCL_j to arithmetic cell 31_i+1,j.

[0343] Incidentally, transistor 32 included in arithmetic cell 31_i+1,j is turned on. In transistor 34, the gate-source voltage becomes V g _i+1,j - GND, and current I0_i+1,j is set as the current flowing between the first terminal and the second terminal of transistor 34.

[0344] Also, between time T57 and time T58, current I flows from circuit XCS to wiring XCL_i+1 as reference dataref0 flows. Specifically, in the same manner as between time T53 and time T54, when the wiring XCL shown in FIG. 17C is the wiring XCL_i+1, a high-level potential is input to the wiring DX_1, and low-level potentials are input to each of the wirings DX_2 to DX_K, and a current I ref0 =I Xut flows.

[0345] Between time T57 and time T58, since the connection between the first terminal of the transistor 22 included in the reference cell 21_i+1 and the wiring XCL_i+1 becomes conductive, a current I ref0 flows from the wiring XCL_i+1 to the reference cell 21_i+1.

[0346] Similar to the arithmetic cell 31_i+1,j, the transistor 22 included in the reference cell 21_i+1 is turned on. In the transistor 24, the gate-source voltage becomes V gm _i+1 - GND, and a current I ref0 is set as the current flowing between the first terminal and the second terminal of the transistor 24.

[0347] <<Between time T58 and time T59>> Between time T58 and time T59, a low-level potential is applied to the wiring WSL_i+1. As a result, low-level potentials are applied to the gates of the transistors 32 included in the arithmetic cells 31_i+1,1 to 31_i+1,n in the (i + 1)-th row of the cell array CA and to the gate of the transistor 22 included in the reference cell 21_i+1, and the respective transistors 32 and 22 are turned off.

[0348] When the transistor 32 included in the arithmetic cell 31_i+1,j is turned off, the capacitor 35 has a voltage V which is the difference between the potential of the gate (node NN_i+1,j) of the transistor 34 and the potential of the wiring XCL_i+1 g _i+1,j - V gm_i + 1 is retained. Also, when the transistor 32 included in the reference cell 21_i + 1 is turned off, 0, which is the difference between the potential of the gate (node NNref_i + 1) of the transistor 24 and the potential of the wiring XCL_i + 1, is retained in the capacitor 25. Note that the voltage retained by the capacitor 25 may be a voltage other than 0 (here, for example, V ds is assumed) depending on the transistor characteristics of the transistors 22 and 24 in the operation from time T58 to time T59. In this case, the potential of the node NNref_i + 1 may be considered as the potential obtained by adding V ds to the potential of the wiring XCL_i + 1.

[0349] <<From time T59 to time T60>> During the period from time T59 to time T60, the ground potential GND is applied to the wiring XCL_i + 1. Specifically, for example, when the wiring XCL shown in FIG. 17C is the wiring XCL_i + 1, by setting the initialization potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX, the potential of the wiring XCL_i + 1 can be set to the ground potential GND.

[0350] Therefore, due to the capacitive coupling by the capacitors 35 included in each of the arithmetic cells 31_i + 1,1 to 31_i + 1,n in the (i + 1)-th row, the potentials of the nodes NN_i,1 to NN_i + 1,n change, and due to the capacitive coupling by the capacitor 25 included in the reference cell 21_i + 1, the potential of the node NNref_i + 1 changes.

[0351] The amount of change in the potential of nodes NN_i+1,1 to NN_i+1,n is the potential obtained by multiplying the amount of change in the potential of wiring XCL_i+1 by the capacitance coupling coefficient determined by the configuration of each of the arithmetic cells 31_i+1,1 to 31_i+1,n included in the cell array CA. The capacitance coupling coefficient is calculated based on the capacitance of capacitor 35, the gate capacitance of transistor 34, parasitic capacitance, etc. In each of the arithmetic cells 31_i+1,1 to 31_i+1,n, when the capacitance coupling coefficient due to capacitor 35 is set to p, which is the same as the capacitance coupling coefficient due to capacitor 35 in each of the arithmetic cells 31_i,1 to 31_i,n, the potential of node NN_i+1,j of arithmetic cell 31_i+1,j decreases from the potential at a point in time between time T58 and time T59 by p(V gm _i+1 - GND).

[0352] Similarly, when the potential of wiring XCL_i+1 changes, the potential of node NNref_i+1 also changes due to capacitance coupling by capacitor 25 included in reference cell 21_i+1. When the capacitance coupling coefficient due to capacitor 25 is set to p in the same manner as capacitor 35, the potential of node NNref_i+1 of reference cell 21_i+1 decreases from the potential between time T58 and time T59 by p(V gm _i+1 - GND). In the timing chart of FIG. 20, as an example, p = 1 is assumed. Therefore, the potential of node NNref_i+1 between time T60 and time T61 becomes GND.

[0353] As a result, since the potential of node NN_i+1,j of arithmetic cell 31_i+1,j decreases, transistor 34 turns off. Similarly, since the potential of node NNref_i+1 of reference cell 21_i+1 decreases, transistor 24 also turns off. Therefore, between time T59 and time T60, I 34 _i+1,j and I 24 _i+1 each become 0.

[0354] <<From time T60 to time T61>> Between time T60 and time T61, a low-level potential is applied to wiring SWL1. As a result, a low-level potential is applied to the gates of transistors F3_1 to F3_n, respectively, and transistors F3_1 to F3_n are turned off.

[0355] <<From time T61 to time T62>> Between time T61 and time T62, a high-level potential is applied to wiring SWL2. As a result, a high-level potential is applied to the gates of transistors F4_1 to F4_n, respectively, and transistors F4_1 to F4_n are turned on.

[0356] <<From time T62 to time T63>> Between time T62 and time T63, from circuit XCS, a current x_iI that is x_i times the current I as the second data flows through wiring XCL_i. ref0 which is x_i times I ref0 flows. Specifically, for example, when the wiring XCL shown in FIG. 17C is the wiring XCL_i, a high-level potential or a low-level potential is input to each of wirings DX_1 to DX_K according to the value of x_i, and a current x_iI flows from circuit XCS to wiring XCL_i as a current. ref0 =x_iI Xut flows. In this operation example, x_i corresponds to the value of the second data. At this time, it is assumed that the potential of wiring XCL_i changes from 0 to V gm _i + ΔV_i.

[0357] When the potential of wiring XCL_i changes, the potentials of nodes NN_i,1 to NN_i,n also change due to capacitive coupling by the capacitors 35 included in each of the arithmetic cells 31_i,1 to 31_i,n in the i-th row of the cell array CA. Therefore, the potential of the node NN_i,j of the arithmetic cell 31_i,j becomes V g _i,j + pΔV_i.

[0358] Similarly, when the potential of wiring XCL_i changes, the potential of node NNref_i also changes due to capacitive coupling by capacitor 25 included in reference cell 21_i. Therefore, the potential of node NNref_i of reference cell 21_i is V gm _i + pΔV_i.

[0359] Therefore, the current flowing between the first terminal and the second terminal of transistor 34 included in arithmetic cell 31_i,j is proportional to the product of the first data w_i,j and the second data x_i, as described in Embodiment 1.

[0360] Also, between time T62 and time T63, from circuit XCS, a current of x_i+1I which is x_i+1 times the current I as the second data flows through wiring XCL_i+1. Specifically, for example, when the wiring XCL shown in FIG. 17C is wiring XCL_i+1, a high-level potential or a low-level potential is input to each of wirings DX_1 to DX_K according to the value of x_i+1, and a current of x_i+1I ref0 = x_i+1I ref0 flows through wiring XCL_i+1 from circuit XCS. In this operation example, x_i+1 corresponds to the value of the second data. At this time, it is assumed that the potential of wiring XCL_i+1 changes from 0 to V ref0 _i+1 + ΔV_i+1. Xut When the potential of wiring XCL_i+1 changes, the potentials of nodes NN_i+1,1 to NN_i+1,n also change due to capacitive coupling by capacitors 35 included in each of arithmetic cells 31_i+1,1 to 31_i+1,n in the (i + 1)-th row of cell array CA. Therefore, the potential of node NN_i+1,j of arithmetic cell 31_i+1,j is V gm _i+1,j + pΔV_i+1.

[0361] g

[0362] ​​Similarly, when the potential of wiring XCL_i+1 changes, the potential of node NNref_i+1 also changes due to capacitive coupling by capacitor 25 included in reference cell 21_i+1. Therefore, the potential of node NNref_i+1 of reference cell 21_i+1 is V gm _i+1 + pΔV_i+1.

[0363] Therefore, the current flowing between the first terminal and the second terminal of transistor 34 included in arithmetic cell 31_i+1,j is proportional to the product of the first data w_i+1,j and the second data x_i+1, as described in Embodiment 1.

[0364] Therefore, the current output from conversion circuit ITRZ_j is a current proportional to the sum of products of the first data, the weight coefficients w_i,j and w_i+1,j, and the second data, the values x_i and x_i+1 of the neuron signals.

[0365] For this reason, even in the case of arithmetic unit MAC1 having a cell array CA of three or more rows and two or more columns, as described above, a sum-of-products operation can be performed. In this case, arithmetic unit MAC1 uses one column out of a plurality of columns as a cell that holds I ref0 , and xI ref0 to simultaneously execute sum-of-products operation processing for the number of remaining columns out of the plurality of columns. That is, by increasing the number of columns of the memory cell array, a semiconductor device capable of realizing high-speed sum-of-products operation processing can be provided. Therefore, an arithmetic unit excellent in arithmetic processing ability per unit power can be provided.

[0366] In addition, in this embodiment, the case where the transistors included in the arithmetic unit MAC1 are OS transistors or Si transistors has been described. However, one aspect of the present invention is not limited to this. The transistors included in the arithmetic unit MAC1 may be, for example, transistors in which Ge or the like is included in the channel formation region, transistors in which compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe are included in the channel formation region, transistors in which carbon nanotubes are included in the channel formation region, transistors in which organic semiconductors are included in the channel formation region, and the like.

[0367] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0368] (Embodiment 3) In this embodiment, a hierarchical artificial neural network (hereinafter referred to as a neural network) will be described. Note that the operations of the hierarchical neural network can be performed by using the semiconductor device and the arithmetic unit described in the above embodiment.

[0369] In a neural network, the connection strength of synapses can be changed by providing existing information to the neural network. In this way, the process of determining the connection strength by providing existing information to the neural network may be referred to as "learning".

[0370] In addition, by providing some information to the neural network that has performed "learning" (determined the connection strength), new information can be output based on the connection strength. In this way, in a neural network, the process of outputting new information based on the provided information and the connection strength may be referred to as "inference" or "cognition". The signal input from the neurons in the previous layer to the neurons in the next layer and the connection strength of the synapses connecting these neurons (hereinafter referred to as the weight coefficient) correspond to the weight data described in the above embodiment.

[0371] Examples of neural network models include, for example, the Hopfield type, the hierarchical type, etc. In particular, a neural network with a multi-layer structure is sometimes referred to as a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes referred to as "deep learning".

[0372] <Hierarchical neural network> As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 21A is an example thereof, and the neural network 100 has the first layer to the R-th layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the R-th layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 21A, the (k - 1)-th layer and the k-th layer (where k is an integer of 3 or more and R - 1 or less) are illustrated as intermediate layers, and the illustration of the other intermediate layers is omitted.

[0373] Each layer of the neural network 100 has one or more neurons. In FIG. 21A, the first layer has neurons N1 (1) to neuron N p (1) (where p is an integer of 1 or more), the (k - 1)-th layer has neurons N1 (k-1) to neuron N m (k-1) (where m is an integer of 1 or more), the k-th layer has neurons N1 (k) to neuron N n (k) (where n is an integer of 1 or more), and the R-th layer has neurons N1 (R) to neuron N q (R) (where q is an integer of 1 or more).

[0374] In addition, in FIG. 21A, neurons N1 (1) , neuron Np (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition to this, neuron N of the (k - 1)th layer i (k-1) (where i is an integer from 1 to m), neuron N of the kth layer j (k) (where j is an integer from 1 to n) is also shown, and illustration of other neurons is omitted.

[0375] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input to and output from each neuron will be described. In this description, attention is paid to neuron N of the kth layer j (k) .

[0376] FIG. 21B shows neuron N of the kth layer j (k) and the signal input to neuron N j (k) and the signal output from neuron N j (k) .

[0377] Specifically, the output signals z1 (k-1) to z m (k-1) of each of neurons N1 (k-1) to N m (k-1) of the (k - 1)th layer are output toward neuron N j (k) . And neuron N j (k) outputs z (k-1) to z m (k-1) in response to z1 j (k)Generate z j (k) Output it as an output signal to each neuron in the (k + 1)-th layer (not shown).

[0378] The signal input from the neurons in the previous layer to the neurons in the next layer has its transmission degree determined by the connection strength of the synapses connecting those neurons (hereinafter referred to as the weight coefficient). In the neural network 100, the signal output from the neurons in the previous layer is multiplied by the corresponding weight coefficient and input to the neurons in the next layer. Let i be an integer from 1 to m, and for the neuron N i (k-1) in the (k - 1)-th layer and the neuron N j (k) in the k-th layer, when the weight coefficient of the synapse between them is w i (k-1) j (k) j (k) (k-1) The signal input to the neuron N

[0379]

Equation

[0380] That is, when the signal is transmitted from each of the neurons N1 (k-1) to N m (k-1) in the (k - 1)-th layer to the neuron N j (k) in the k-th layer, the signals z1 (k-1) to z m (k-1) are multiplied by the weight coefficients (w1 (k-1) j (k) to w m (k-1) j (k) ) corresponding to those signals respectively. And for the neuron N j (k) in the k-th layer, w1 (k-1) j (k)·z1 (k-1) up to w m (k-1) j (k) ·z m (k-1) is input. At this time, the sum u of the signals input to the neuron N in the k-th layer j (k) is given by Equation (18). j (k)

[0381]

Equation

[0382] Also, a bias may be given as a bias to the result of the sum of products of the weight coefficients w1 (k-1) j (k) up to w m (k-1) j (k) and the signals z1 of the neuron (k-1) up to z m (k-1) When the bias is b, Equation (18) can be rewritten as the following Equation (19).

[0383]

Equation

[0384] The neuron N j (k) generates an output signal z according to u j (k) Here, the output signal z from the neuron N j (k) is defined by the following Equation (20). j (k) j (k)

[0385]

Equation

[0386] ​​​ The function f(u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, etc. can be used. Note that the activation function may be the same for all neurons, or may be different. In addition, the activation function of neurons may be the same or different for each layer.

[0387] By the way, the signal output by neurons in each layer, the weight coefficient w, or the bias b may be an analog value or a digital value. As a digital value, for example, it may be a binary value or a ternary value. Values with an even larger number of bits may also be used. As an example, in the case of an analog value, a linear ramp function, a sigmoid function, etc. may be used as the activation function. In the case of a binary digital value, for example, a step function that outputs -1 or 1, or 0 or 1, may be used. Also, the signal output by neurons in each layer may be three or more values. In this case, the activation function may be a step function with three values, for example, the output is -1, 0, or 1, or a step function with 0, 1, or 2, etc. Also, for example, as an activation function that outputs five values, a step function that outputs -2, -1, 0, 1, or 2, etc. may be used. By using a digital value for at least one of the signal output by neurons in each layer, the weight coefficient w, or the bias b, the circuit scale can be reduced, the power consumption can be reduced, or the operation speed can be increased, etc. Also, by using an analog value for at least one of the signal output by neurons in each layer, the weight coefficient w, or the bias b, the accuracy of the operation can be improved.

[0388] When an input signal is input to the first layer (input layer) of the neural network 100, the neural network 100 sequentially generates an output signal using equations (17), (18) (or equation (19)), and (20) based on the signal input from the previous layer in each layer from the first layer (input layer) to the last layer (output layer), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.

[0389] When the arithmetic unit MAC1 described in Embodiment 2 is applied as the hidden layer described above, the weight coefficient w s[k-1] (k-1) s_K (k) (where s[k - 1] is an integer from 1 to m and s_K is an integer from 1 to n) is used as the first data, and currents corresponding to the first data are sequentially stored in each cell in the same column, and the output signal z s[k-1] (k-1) from the neuron N s[k-1] (k-1) is used as the second data, and by flowing currents corresponding to the second data from the circuit XCS to the wiring XCL of each row, the current I S input to the conversion circuit ITRZ can be used to obtain the sum of products of the first data and the second data. In addition, by obtaining the value of the activation function using the value of the sum of products, the value of the activation function can be used as a signal for the output signal z s_K (k) of the neuron N s_K (k) in the k-th layer.

[0390] Also, when the arithmetic unit MAC1 described in Embodiment 2 is applied as the output layer described above, the weight coefficient w s[R-1] (R-1) s[R] (R) (where s[R - 1] is an integer greater than or equal to 1 and s[R] is an integer from 1 to q) is used as the first data, and currents corresponding to the first data are sequentially stored in each cell in the same column, and the output signal z s[R-1] (R-1) from the neuron N s[R-1] (R-1)Using the second data, by flowing a current corresponding to the second data from the circuit XCS to the wiring XCL of each row, the current I input to the conversion circuit ITRZ S From this, the sum of products of the first data and the second data can be obtained. In addition, by obtaining the value of the activation function using the value of the sum of products, the value of the activation function is used as a signal for the neuron N s[R] (R) of the R-th layer to obtain the output signal z s[R] (R) can be used.

[0391] Note that the input layer described in this embodiment may function as a buffer circuit that outputs an input signal to the second layer.

[0392] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0393] (Embodiment 4) In this embodiment, a configuration example of the semiconductor device described in the above embodiment and a configuration example of a transistor applicable to the semiconductor device described in the above embodiment will be described.

[0394] <Configuration Example 1 of Semiconductor Device> FIG. 22A shows, as an example, the semiconductor device described in the above embodiment. The semiconductor device includes a transistor 500 and a capacitor 600. FIG. 22B shows a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22C shows a cross-sectional view of the transistor 500 in the channel width direction.

[0395] The transistor 500 can be an OS transistor. The transistor 500 can be applied to, for example, the transistor 22 or the transistor 32 described in the above embodiment. Note that the transistor 500 may be a Si transistor, and as silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used.

[0396] The transistor 500 is provided above an insulator 512 provided, for example, above a substrate (not shown). The capacitor 600 is provided, for example, above the transistor 500. The capacitor 600 can be applied to the capacitor 25 etc. described in the above embodiment.

[0397] An insulator 514 and an insulator 516 are sequentially laminated and provided on the insulator 512. Any one of the insulator 512, the insulator 514, and the insulator 516 is preferably made of a material having barrier properties against oxygen and hydrogen.

[0398] For example, for the insulator 514, it is preferable to use a film having barrier properties such that hydrogen and impurities do not diffuse from the region where the substrate is provided to the region where the transistor 500 is provided.

[0399] As an example of a film having barrier properties against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, by using a film that suppresses the diffusion of hydrogen as the insulator 514, it is possible to suppress the deterioration of the characteristics of semiconductor elements such as the transistor 500. Here, the film that suppresses the diffusion of hydrogen is specifically a film with a small amount of hydrogen desorption.

[0400] Also, as a film having barrier properties against hydrogen, for example, for the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0401] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0402] As the insulator 512 and the insulator 516, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced.

[0403] In this specification and the like, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Further, in this specification and the like, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0404] In addition, conductors (for example, the conductor 503 shown in FIGS. 22B and 22C) constituting the transistor 500 are embedded in the insulator 512, the insulator 514, and the insulator 516.

[0405] A transistor 500 is provided above the insulator 516.

[0406] As shown in FIGS. 22B and 22C, transistor 500 includes insulator 516 on insulator 514, conductor 503 (conductor 503a and conductor 503b) disposed to be embedded in insulator 514 or insulator 516, insulator 522 on insulator 516 and on conductor 503, insulator 524 on insulator 522, oxide 530a on insulator 524, oxide 530b on oxide 530a, conductor 542a on oxide 530b, insulator 571a on conductor 542a, conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping a part of oxide 530b, and insulator 544 disposed on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. Here, as shown in FIGS. 22B and 22C, insulator 552 is in contact with the upper surface of insulator 522, the side surface of insulator 524, the side surfaces of oxide 530a and oxide 530b, the side surfaces and upper surface of conductor 542, the side surfaces of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Also, the upper surface of conductor 560 is disposed to be substantially flush with the upper part of insulator 554, the upper part of insulator 550, the upper part of insulator 552, and the upper surface of insulator 580. Also, insulator 574 is in contact with at least a part of the upper surface of conductor 560, the upper part of insulator 552, the upper part of insulator 550, the upper part of insulator 554, and the upper surface of insulator 580. In this specification etc., conductor 542a and conductor 542b may be collectively referred to as conductor 542, and insulator 571a and insulator 571b may be collectively referred to as insulator 571. Other elements may also be expressed in a similar manner.

[0407] The insulator 580 and the insulator 544 are provided with openings reaching the oxide 530b. Inside the openings, an insulator 552, an insulator 550, an insulator 554, and a conductor 560 are arranged. Also, in the channel length direction of the transistor 500, a conductor 560, an insulator 552, an insulator 550, and an insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0408] The oxide 530 preferably has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By having the oxide 530a under the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0409] Note that in the transistor 500, the oxide 530 is shown as having a configuration in which two layers of the oxide 530a and the oxide 530b are stacked, but the present invention is not limited to this. For example, the transistor 500 can have a configuration with a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, a configuration can be adopted in which each of the oxide 530a and the oxide 530b has a stacked structure.

[0410] The conductor 560 functions as a gate electrode, and the conductor 503 functions as a back gate electrode. Note that the conductor 503 may function as a gate electrode and the conductor 560 may function as a back gate electrode. Also, the insulators 552, 550, and 554 function as gate insulators for the conductor 560, and the insulators 522 and 524 function as gate insulators for the conductor 503. Note that the gate insulator may also be referred to as a gate insulating layer or a gate insulating film. Further, the conductor 542a functions as one of the source or drain, and the conductor 542b functions as the other of the source or drain. Also, at least a part of the region where the oxide 530 overlaps with the conductor 560 functions as a channel formation region.

[0411] Here, an enlarged view of the vicinity of the channel formation region in FIG. 22B is shown in FIG. 23A. By supplying oxygen to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Thus, as shown in FIG. 23A, the oxide 530b has a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich the region 530bc and function as a source region or a drain region. At least a part of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is provided in the region between the conductor 542a and the conductor 542b. The region 530ba is provided to overlap with the conductor 542a, and the region 530bb is provided to overlap with the conductor 542b.

[0412] The region 530bc that functions as a channel formation region has less oxygen deficiency (which may be referred to as V O (oxygen vacancy) in this specification, etc.) or a lower impurity concentration than the regions 530ba and 530bb, and thus is a high-resistance region with a low carrier concentration. Therefore, the region 530bc can be said to be of the i-type (intrinsic) or substantially of the i-type.

[0413] A transistor using a metal oxide may have easily fluctuating electrical characteristics and poor reliability if impurities or oxygen vacancies (V O ) are present in the region where the channel in the metal oxide is formed. Also, hydrogen near an oxygen vacancy (V O ) may form a defect in which hydrogen enters the oxygen vacancy (V O ) (hereinafter sometimes referred to as V O H) and generate electrons serving as carriers. Therefore, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Thus, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible.

[0414] Also, regions 530ba and 530bb that function as a source region or a drain region are regions where the carrier concentration increases and the resistance is reduced because there are many oxygen vacancies (V O ) or the impurity concentrations of hydrogen, nitrogen, metal elements, etc. are high. That is, regions 530ba and 530bb are n-type regions with a high carrier concentration and low resistance compared to region 530bc.

[0415] Here, the carrier concentration of region 530bc that functions as a channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , still more preferably less than 1×10 16 cm -3 , still more preferably less than 1×10 13 cm -3 , still more preferably less than 1×10 12 cm -3 . Note that there is no particular limitation on the lower limit value of the carrier concentration of region 530bc that functions as a channel formation region. For example, 1×10 -9 cm-3 can be set as such.

[0416] Also, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than the carrier concentrations of region 530ba and region 530bb and equal to or higher than the carrier concentration of region 530bc. That is, the region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in the junction region may be equal to or lower than the hydrogen concentrations of region 530ba and region 530bb and equal to or higher than the hydrogen concentration of region 530bc. Also, the oxygen deficiency in the junction region may be equal to or less than the oxygen deficiencies of region 530ba and region 530bb and equal to or more than the oxygen deficiency of region 530bc.

[0417] In FIG. 23A, an example where regions 530ba, 530bb, and 530bc are formed in oxide 530b is shown, but the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0418] Also, in oxide 530, it may be difficult to clearly detect the boundaries of each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region are not limited to stepwise changes from region to region and may also change continuously within each region. That is, the closer the region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, may be.

[0419] For transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for oxides 530 (oxides 530a and 530b) including the channel formation region.

[0420] In addition, as the metal oxide functioning as a semiconductor, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0421] As the oxide 530, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Also, as the oxide 530, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0422] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide 530b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0423] In this way, by disposing the oxide 530a under the oxide 530b, the diffusion of impurities and oxygen from the structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0424] In addition, since the oxide 530a and the oxide 530b have a common element (as the main component) other than oxygen, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Since the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered, the influence on carrier conduction due to interface scattering is small, and a high on-current can be obtained.

[0425] The oxide 530b preferably has crystallinity. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0426] CAAC-OS has a highly crystalline and dense structure and is a metal oxide with few impurities and defects (e.g., oxygen vacancies (V O etc.)). In particular, by heat-treating the metal oxide at a temperature (e.g., 400 °C or higher and 600 °C or lower) such that the metal oxide does not polycrystallize after the formation of the metal oxide, CAAC-OS can be made to have a more highly crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0427] On the other hand, since it is difficult to confirm distinct grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0428] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in the region where the channel in the oxide semiconductor is formed, the electrical characteristics are likely to vary and the reliability may deteriorate. Also, hydrogen near an oxygen vacancy may form a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons serving as carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible. In other words, in the region where the channel in the oxide semiconductor is formed, it is preferable that the carrier concentration is reduced and the region is i-type (intrinsic) or substantially i-type.

[0429] On the other hand, by providing an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiency and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, it may cause a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0430] Therefore, in the oxide semiconductor, the region 530bc that functions as the channel formation region preferably has a reduced carrier concentration and is of the i-type or substantially i-type, while the regions 530ba and 530bb that function as the source region or the drain region preferably have a high carrier concentration and are of the n-type. That is, it is preferable to reduce the oxygen deficiency and V O H in the region 530bc of the oxide semiconductor and prevent an excessive amount of oxygen from being supplied to the regions 530ba and 530bb.

[0431] Therefore, in the present embodiment, while the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to reduce the oxygen deficiency and V O H in the region 530bc. Here, the microwave treatment refers to a treatment using, for example, a device having a power source for generating high-density plasma using microwaves.

[0432] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be made into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high-frequency waves such as RF can also be irradiated to the region 530bc. Due to the action of plasma, microwaves, etc., the V O H in the region 530bc is broken, hydrogen H is removed from the region 530bc, and oxygen deficiency V Ocan be replenished with oxygen. That is, in region 530bc, the reaction "V O H → H + V O " occurs, and the hydrogen concentration in region 530bc can be reduced. Therefore, oxygen vacancies and V O H in region 530bc can be reduced, and the carrier concentration can be decreased.

[0433] Also, when performing microwave treatment in an oxygen-containing atmosphere, the actions of microwaves, or high-frequency waves such as RF, and oxygen plasma are shielded by conductor 542a and conductor 542b and do not reach regions 530ba and 530bb. Furthermore, the action of oxygen plasma can be reduced by insulator 571 and insulator 580 provided to cover oxide 530b and conductor 542. As a result, during microwave treatment, in regions 530ba and 530bb, reduction of V O H and excessive oxygen supply do not occur, so a decrease in carrier concentration can be prevented.

[0434] Also, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes insulator 552 or after forming the insulating film that becomes insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through insulator 552 or insulator 550 in this way, oxygen can be efficiently injected into region 530bc. Also, by arranging insulator 552 so as to be in contact with the side surface of conductor 542 and the surface of region 530bc, injection of more oxygen than necessary into region 530bc can be suppressed, and oxidation of the side surface of conductor 542 can be suppressed. Also, oxidation of the side surface of conductor 542 can be suppressed when forming the insulating film that becomes insulator 550.

[0435] In addition, the oxygen injected into region 530bc exists in various forms such as oxygen atoms, oxygen molecules, oxygen radicals (also referred to as O radicals, atoms, molecules, or ions having unpaired electrons), etc. Note that the oxygen injected into region 530bc is preferably any one or more of the above-mentioned forms, and particularly preferably oxygen radicals. Further, since the film quality of insulator 552 and insulator 550 can be improved, the reliability of transistor 500 is improved.

[0436] In this way, oxygen deficiency and V O H can be selectively removed in region 530bc of the oxide semiconductor, and region 530bc can be made into an i-type or substantially i-type. Further, supply of excessive oxygen to regions 530ba and 530bb that function as a source region or a drain region can be suppressed, and n-type electrical characteristics can be maintained. Thereby, fluctuations in the electrical characteristics of transistor 500 can be suppressed, and variations in the electrical characteristics of transistor 500 within the substrate surface can be reduced.

[0437] By adopting the above configuration, a semiconductor device with little variation in transistor characteristics can be provided. Further, a semiconductor device with good reliability can be provided. Also, a semiconductor device having good electrical characteristics can be provided.

[0438] Further, as shown in FIG. 22C, in a cross-sectional view in the channel width direction of transistor 500, a curved surface may be provided between the side surface and the upper surface of oxide 530b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as round).

[0439] The radius of curvature of the above-mentioned curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half of the length of the region without the above-mentioned curved surface. Specifically, the radius of curvature of the above-mentioned curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 552, the insulator 550, the insulator 554, and the conductor 560 on the oxide 530b can be improved.

[0440] The oxide 530 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0441] Also, the oxide 530b is preferably an oxide having crystallinity such as CAAC-OS. Oxides having crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, so the transistor 500 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0442] Here, at the junction of the oxide 530a and the oxide 530b, the lower end of the conduction band changes smoothly. In other words, it can also be said that the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is preferable to reduce the density of defect levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0443] Specifically, since the oxide 530a and the oxide 530b have a common element other than oxygen as a main component, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 530b is an In-M-Zn oxide, as the oxide 530a, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In-Zn oxide, an indium oxide, etc. may be used.

[0444] Specifically, as the oxide 530a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Also, as the oxide 530b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof may be used. Here, the vicinity of the composition includes a range of ±30% of the desired atomic ratio. Also, as the element M, it is preferable to use gallium.

[0445] Note that when forming a metal oxide film by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide film.

[0446] Also, as shown in FIG. 22B and the like, by providing an insulator 552 formed of aluminum oxide or the like in contact with the upper surface and side surfaces of the oxide 530, indium contained in the oxide 530 may be unevenly distributed at the interface between the oxide 530 and the insulator 552 and in the vicinity thereof. As a result, the vicinity of the surface of the oxide 530 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In-Zn oxide. By increasing the atomic ratio of indium in the vicinity of the surface of the oxide 530, particularly the oxide 530b, the field-effect mobility of the transistor 500 can be improved.

[0447] By configuring the oxide 530a and the oxide 530b as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 500 can obtain a large on-current and high frequency characteristics.

[0448] At least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate).

[0449] In this specification, the barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier property means a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it means a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0450] As the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as the insulators 512, 544, and 576, it is preferable to use silicon nitride or the like having higher hydrogen barrier properties. Further, for example, as the insulators 514, 571, 574, and 581, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 581 to the transistor 500 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 524 or the like to the substrate side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 580 or the like above the transistor 500 through the insulators 574 or the like. In this way, it is preferable to adopt a structure in which the transistor 500 is surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0451] Here, as the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581, it is preferable to use an oxide having an amorphous structure. For example, AlO x (where x is an arbitrary number greater than 0), or MgO y (where y is an arbitrary number greater than 0), etc., it is preferable to use metal oxides. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a transistor 500 and a semiconductor device having good characteristics and high reliability can be fabricated.

[0452] Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 preferably have an amorphous structure, but a region having a polycrystalline structure may be formed partially. Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are laminated. For example, a laminated structure in which a layer having a polycrystalline structure is formed on a layer having an amorphous structure may also be used.

[0453] The film formation of insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 may be performed, for example, using a sputtering method. Since the sputtering method does not require a molecule containing hydrogen as a film formation gas, the hydrogen concentration of insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, etc. may be appropriately used.

[0454] Also, there may be cases where it is preferable to lower the resistivity of insulator 512, insulator 544, and insulator 576. For example, by setting the resistivity of insulator 512, insulator 544, and insulator 576 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, insulator 512, insulator 544, and insulator 576 may be able to mitigate the charge-up of conductor 503, conductor 542, conductor 560, etc. The resistivity of insulator 512, insulator 544, and insulator 576 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0455] Also, insulator 516, insulator 574, insulator 580, and insulator 581 preferably have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as insulator 516, insulator 580, and insulator 581, silicon oxide, silicon oxynitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having pores, etc. may be appropriately used.

[0456] In addition, as an example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarization film, or the like.

[0457] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. Also, a part of the conductor 503 may be embedded in the insulator 514.

[0458] The conductor 503 has a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and the side wall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the upper part of the conductor 503b is substantially the same as the height of the upper part of the conductor 503a and the height of the upper part of the insulator 516.

[0459] Here, for the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0460] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 through the insulator 524 or the like. Also, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, as the conductor 503a, the above conductive material may be a single layer or a laminate. For example, titanium nitride may be used for the conductor 503a.

[0461] In addition, the conductor 503b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 503b.

[0462] Also, the electrical resistivity of the conductor 503 is designed in consideration of the potential applied to the conductor 503, and the film thickness of the conductor 503 is set according to the electrical resistivity. Also, the film thickness of the insulator 516 is made substantially the same as that of the conductor 503. Here, it is preferable to reduce the film thicknesses of the conductor 503 and the insulator 516 within the range allowed by the design of the conductor 503. By reducing the film thickness of the insulator 516, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, so that the diffusion of the impurities into the oxide 530 can be reduced.

[0463] Note that the conductor 503 is preferably provided to be larger than the size of the region that does not overlap with the conductors 542a and 542b of the oxide 530 when viewed from above. In particular, as shown in FIG. 22C, the conductor 503 preferably extends also in a region outside the end portions in the channel width direction of the oxides 530a and 530b. That is, it is preferable that the conductor 503 and the conductor 560 overlap with each other via an insulator outside the side surface of the oxide 530 in the channel width direction. By having such a configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 functioning as a gate electrode and the electric field of the conductor 503 functioning as a back gate electrode. In this specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0464] In addition, in this specification and the like, the transistor with an S-channel structure refers to a structure of a transistor that electrically surrounds a channel formation region by an electric field of one and the other of a pair of gate electrodes. Further, the S-channel structure disclosed in this specification and the like is different from the Fin type structure and the planar type structure. By adopting the S-channel structure, it is possible to enhance the resistance to the short-channel effect, in other words, to make a transistor in which the short-channel effect hardly occurs.

[0465] Also, as shown in FIG. 22C, the conductor 503 is extended to function also as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 503. Further, the conductor 503 does not necessarily have to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 503 is shared by a plurality of transistors.

[0466] Note that, in the transistor 500, the conductor 503 shows a configuration in which the conductor 503a and the conductor 503b are laminated, but the present invention is not limited to this. For example, the conductor 503 may be provided in a single layer or a laminated structure of three or more layers.

[0467] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Further, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0468] The insulator 522 may be made of an insulator containing one or both oxides of aluminum and hafnium, which are insulating materials. As such an insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and suppress the generation of oxygen vacancies in the oxide 530. In addition, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 or the oxide 530.

[0469] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the above insulator. Alternatively, these insulators may be nitrided. Further, the insulator 522 may be used by laminating silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0470] Further, the insulator 522 may be used as a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, in some cases, a substance with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. may be used as the insulator 522.

[0471] For the insulator 524 in contact with the oxide 530, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used.

[0472] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O ). Also, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after the heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0473] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "V O +O→null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with the oxygen vacancies to form V O H.

[0474] Note that the insulator 522 and the insulator 524 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. Also, the insulator 524 may be formed in an island shape by overlapping with the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the upper surface of the insulator 522.

[0475] The conductor 542a and the conductor 542b are provided in contact with the upper surface of the oxide 530b. The conductor 542a and the conductor 542b each function as a source electrode or a drain electrode of the transistor 500.

[0476] As the conductor 542 (the conductor 542a and the conductor 542b), for example, it is preferable to use a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, etc. In one aspect of the present invention, a nitride containing tantalum is particularly preferable. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0477] Note that hydrogen contained in the oxide 530b or the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductor 542a and the conductor 542b, hydrogen contained in the oxide 530b or the like easily diffuses into the conductor 542a or the conductor 542b, and the diffused hydrogen may combine with nitrogen possessed by the conductor 542a or the conductor 542b. That is, hydrogen contained in the oxide 530b or the like may be absorbed by the conductor 542a or the conductor 542b.

[0478] Also, it is preferable that a curved surface is not formed between the side surface and the upper surface of the conductor 542. By making the conductor 542 such that the curved surface is not formed, the cross-sectional area of the conductor 542 in the cross-section in the channel width direction can be increased. Thereby, the conductivity of the conductor 542 can be increased, and the on-current of the transistor 500 can be increased.

[0479] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. The insulator 571 preferably functions as at least a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 571 preferably has a function of suppressing the diffusion of oxygen more than the insulator 580. As the insulator 571, for example, a nitride containing silicon such as silicon nitride may be used. Further, the insulator 571 preferably has a function of capturing impurities such as hydrogen. In that case, as the insulator 571, an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide, may be used. In particular, using aluminum oxide having an amorphous structure or aluminum oxide of an amorphous structure as the insulator 571 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 500 having good characteristics and a highly reliable semiconductor device can be manufactured.

[0480] The insulator 544 is provided so as to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 544 preferably contains silicon nitride or an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide. Further, for example, as the insulator 544, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.

[0481] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be wrapped with an insulator having barrier properties against oxygen. That is, it is possible to prevent oxygen contained in the insulator 524 and the insulator 580 from diffusing into the conductor 542. Thereby, it is possible to suppress the direct oxidation of the conductor 542 by oxygen contained in the insulator 524 and the insulator 580, an increase in resistivity, and a reduction in on-current.

[0482] The insulator 552 functions as part of the gate insulator. As the insulator 552, it is preferable to use a barrier insulating film against oxygen. As the insulator 552, an insulator that can be used for the above-described insulator 574 may be used. As the insulator 552, an insulator containing one or both of aluminum and hafnium oxides may be used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. In the present embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 becomes an insulator having at least oxygen and aluminum.

[0483] As shown in FIG. 22C, the insulator 552 is provided in contact with the upper surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the upper surface of the insulator 522. That is, the region overlapping the conductor 560 of the oxide 530a, the oxide 530b, and the insulator 524 is covered with the insulator 552 in the cross section in the channel width direction. Thereby, when heat treatment or the like is performed, the desorption of oxygen by the oxides 530a and 530b can be blocked by the insulator 552 having barrier properties against oxygen. Therefore, the formation of oxygen vacancies (Vo) in the oxides 530a and 530b can be reduced. Thereby, the oxygen vacancies (Vo) and V formed in the region 530bc O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved and the reliability can be enhanced.

[0484] Conversely, even if the insulators 580 and 550 etc. contain an excessive amount of oxygen, it is possible to suppress the excessive supply of the oxygen to the oxides 530a and 530b. Therefore, it is possible to suppress the excessive oxidation of the regions 530ba and 530bb via the region 530bc and cause a decrease in the on-current or a decrease in the field-effect mobility of the transistor 500.

[0485] Also, as shown in FIG. 22B, the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580, respectively. Therefore, oxidation of the side surface of the conductor 542 can be reduced, and formation of an oxide film on the side surface can be suppressed. Thereby, it is possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0486] Also, the insulator 552 needs to be provided in an opening formed in the insulator 580 or the like together with the insulator 554, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 552 is thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and is preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 552 may have a region having a film thickness as described above at least in part. Also, the film thickness of the insulator 552 is preferably thinner than the film thickness of the insulator 550. In this case, the insulator 552 may have a region having a film thickness thinner than that of the insulator 550 at least in part.

[0487] In order to form the insulator 552 with a thin film thickness as described above, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD (Thermal ALD) method in which the reaction of a precursor and a reactant is performed only by thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like. In the PEALD method, in some cases, it is preferable because film formation at a lower temperature is possible by using plasma.

[0488] The ALD method utilizes the self-limiting property of atoms and can deposit atoms one by one, enabling extremely thin film formation, film formation on structures with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of openings formed in the insulator 580 or the like, and a thin film with the above-described film thickness can be formed.

[0489] Note that some of the precursors used in the ALD method contain carbon or the like. For this reason, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film formation methods. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0490] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. As the insulator 550, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide having pores, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 550 is an insulator having at least oxygen and silicon.

[0491] Similar to the insulator 524, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 550 only needs to have a region with the above-described film thickness in at least a part thereof.

[0492] In FIGS. 22B and 22C etc., the configuration in which the insulator 550 is a single layer is shown, but the present invention is not limited to this, and it may have a laminated structure of two or more layers. For example, as shown in FIG. 23B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0493] As shown in FIG. 23B, when the insulator 550 has a two-layer laminated structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. By adopting such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 550a to the conductor 560. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. In addition, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be provided using a material that can be used for the above-described insulator 550, and the insulator 550b may be an insulator containing one or both of aluminum oxide and hafnium oxide. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. In the present embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b becomes an insulator having at least oxygen and hafnium. Further, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 550b only needs to have a region with the film thickness as described above in at least a part thereof.

[0494] In addition, when using silicon oxide, silicon oxynitride, etc. for the insulator 550a, the insulator 550b may be made of an insulating material that is a high-k material with a high relative permittivity. By forming the gate insulator into a laminated structure of the insulator 550a and the insulator 550b, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator. Thus, the breakdown voltage of the insulator 550 can be increased.

[0495] The insulator 554 functions as part of the gate insulator. As the insulator 554, it is preferable to use a barrier insulating film against hydrogen. Thereby, it is possible to prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. As the insulator 554, an insulator that can be used for the above-described insulator 576 may be used. For example, silicon nitride formed by the PEALD method may be used as the insulator 554. In this case, the insulator 554 becomes an insulator having at least nitrogen and silicon.

[0496] Also, the insulator 554 may further have a barrier property against oxygen. Thereby, it is possible to suppress the diffusion of oxygen contained in the insulator 550 into the conductor 560.

[0497] In addition, the insulator 554 needs to be provided in the opening formed in the insulator 580 or the like together with the insulator 552, the insulator 550, and the conductor 560. When miniaturizing the transistor 500, it is preferable that the film thickness of the insulator 554 is thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and is preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 554 may have a region with a film thickness as described above at least in part. Also, it is preferable that the film thickness of the insulator 554 is thinner than the film thickness of the insulator 550. In this case, the insulator 554 may have a region with a film thickness thinner than that of the insulator 550 at least in part.

[0498] The conductor 560 functions as a gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed on the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 560b. Also, as shown in FIGS. 22B and 22C, the height position of the upper part of the conductor 560 substantially coincides with the height position of the upper part of the insulator 550. Note that in FIGS. 22B and 22C, the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b, but the conductor 560 can have a single-layer structure or a stacked structure of three or more layers other than the two-layer structure.

[0499] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0500] In addition, since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550 and the decrease in the conductivity. As the conductive material having the function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0501] In addition, since the conductor 560 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, as the conductor 560b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b can have a laminated structure of titanium, or titanium nitride and the above conductive material.

[0502] In the transistor 500, the conductor 560 is self-alignedly formed so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be surely arranged in the region between the conductor 542a and the conductor 542b without aligning the conductor 560.

[0503] Also, as shown in FIG. 22C, in the channel width direction of the transistor 500, when the bottom surface of the insulator 522 is used as a reference, the height of the bottom surface of the conductor 560 in the region where the conductor 560 and the oxide 530b do not overlap is preferably lower than the height of the bottom surface of the oxide 530b. By configuring the conductor 560 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 560 and the height of the bottom surface of the oxide 530b in the region where the oxide 530a and the oxide 530b and the conductor 560 do not overlap when the bottom surface of the insulator 522 is used as a reference is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other.

[0504] The insulator 580 is provided on the insulator 544, and an opening is formed in the region where the insulator 550 and the conductor 560 are provided. Further, the upper surface of the insulator 580 may be planarized.

[0505] The insulator 580 that functions as an interlayer film preferably has a low dielectric constant. By using a material having a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 580 is preferably provided using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because a region containing oxygen that desorbs by heating can be easily formed.

[0506] The insulator 580 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 580. For example, the insulator 580 may be appropriately formed using an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0507] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 580, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an insulator having an amorphous structure, for example, an insulator such as aluminum oxide may be used. In this case, the insulator 574 is an insulator having at least oxygen and aluminum. By providing the insulator 574 having a function of capturing impurities such as hydrogen in contact with the insulator 580 within the region sandwiched between the insulator 512 and the insulator 581, impurities such as hydrogen contained in the insulator 580 and the like can be captured, and the amount of hydrogen in the region can be set to a constant value. In particular, it is preferable to use aluminum oxide having an amorphous structure as the insulator 574 because hydrogen can be captured or fixed more effectively in some cases. Thereby, a transistor 500 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0508] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 580. The insulator 576 is disposed on the insulator 574. As the insulator 576, it is preferable to use a silicon-containing nitride such as silicon nitride or silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 576. By forming the insulator 576 by a sputtering method, a silicon nitride film having a high density can be formed. Further, as the insulator 576, silicon nitride formed by a PEALD method or a CVD method may be laminated on silicon nitride formed by a sputtering method.

[0509] Also, one of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540a that functions as a plug, and the other of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540b. In this specification and the like, the conductor 540a and the conductor 540b are collectively referred to as the conductor 540.

[0510] Conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Also, in this specification and the like, a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0511] As the material of each plug and wiring, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated manner. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0512] The conductor 540a is provided, as an example, in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 22B, and further in the insulators 582 and 586 shown in FIG. 22A, and the conductor 540a is provided inside the openings. Also, the conductor 540b is provided, as an example, in a region that overlaps with the conductor 542b. Specifically, in the region that overlaps with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 22B, and further in the insulators 582 and 586 shown in FIG. 22A, and the conductor 540b is provided inside the openings. Note that the insulators 582 and 586 will be described later.

[0513] Furthermore, as shown in FIG. 22B, an insulator 541a may be provided between the side surface of the opening in the region that overlaps with the conductor 542a and the conductor 540a as an insulator having a barrier property against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening in the region that overlaps with the conductor 542b and the conductor 540b as an insulator having a barrier property against impurities. Note that in this specification and the like, the insulators 541a and 541b will be collectively referred to as the insulator 541.

[0514] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductors 540a and 540b. Also, the conductors 540a and 540b may have a laminated structure.

[0515] When the conductor 540 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor disposed in the vicinity of the insulator 574, the insulator 576, the insulator 581, the insulator 580, the insulator 544, and the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. Further, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 576 from mixing into the oxide 530 through the conductor 540a and the conductor 540b.

[0516] As the insulator 541a and the insulator 541b, a barrier insulating film that can be used for the insulator 544 or the like may be used. For example, as the insulator 541a and the insulator 541b, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulator 541a and the insulator 541b are provided in contact with the insulator 574, the insulator 576, and the insulator 571, it is possible to suppress impurities such as water and hydrogen contained in the insulator 580 or the like from mixing into the oxide 530 through the conductor 540a and the conductor 540b. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b.

[0517] When the insulator 541a and the insulator 541b have a laminated structure as shown in Fig. 22B, the first insulator in contact with the inner wall of the opening of the insulator 580 or the like and the second insulator inside thereof are preferably used in combination with a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0518] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. With such a configuration, oxidation of the conductor 540 can be suppressed, and further, the mixing of hydrogen into the conductor 540 can be reduced.

[0519] Note that, in the transistor 500, a configuration in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are laminated is shown, but the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a laminated structure of three or more layers. Also, in the transistor 500, a configuration in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are laminated is shown, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a laminated structure of three or more layers.

[0520] Also, as shown in FIG. 22A, conductors 610, 612, etc. that function as wiring may be arranged in contact with the upper part of the conductor 540a and the upper part of the conductor 540b. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductors 610 and 612. Also, the conductor can be formed as a laminated structure. Specifically, for example, the conductor may be a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0521] Note that the structure of the transistor included in a semiconductor device of one aspect of the present invention is not limited to the transistor 500 shown in FIGS. 22A to 22C. The structure of the transistor included in the semiconductor device of one aspect of the present invention may be changed according to the situation.

[0522] For example, the transistor 500 shown in FIGS. 22A to 22C may have the configuration shown in FIG. 24. The transistor in FIG. 24 is different from the transistor 500 shown in FIGS. 22A to 22C in that it has oxides 543a and 543b. In this specification, etc., the oxides 543a and 543b are collectively referred to as the oxide 543. Also, the configuration of the cross-section in the channel width direction of the transistor in FIG. 24 can be the same as the cross-section of the transistor 500 shown in FIG. 22C.

[0523] Oxide 543a is provided between oxide 530b and conductor 542a, and oxide 543b is provided between oxide 530b and conductor 542b. Here, it is preferable that oxide 543a contacts the upper surface of oxide 530b and the lower surface of conductor 542a. Also, it is preferable that oxide 543b contacts the upper surface of oxide 530b and the lower surface of conductor 542b.

[0524] Oxide 543 preferably has a function of suppressing oxygen permeation. By disposing oxide 543 having a function of suppressing oxygen permeation between conductor 542 functioning as a source electrode or a drain electrode and oxide 530b, the electrical resistance between conductor 542 and oxide 530b is reduced, which is preferable. With such a configuration, the electrical characteristics, field-effect mobility, and reliability of transistor 500 may be improved.

[0525] Also, a metal oxide having element M may be used as oxide 543. In particular, as element M, aluminum, gallium, yttrium, or tin may be used. Also, it is preferable that the concentration of element M in oxide 543 is higher than that in oxide 530b. Also, gallium oxide may be used as oxide 543. Also, a metal oxide such as In-M-Zn oxide may be used as oxide 543. Specifically, in the metal oxide used for the oxide, it is preferable that the atomic ratio of element M to In is larger than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Also, the film thickness of oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. Also, it is preferable that oxide 543 has crystallinity. When oxide 543 has crystallinity, the release of oxygen in oxide 530 can be preferably suppressed. For example, if oxide 543 has a crystal structure such as a hexagonal crystal, the release of oxygen in oxide 530 may be suppressed.

[0526] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0527] It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0528] Also, the same material as the insulator 512 can be used for the insulator 586. By applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, etc. can be used as the insulator 586.

[0529] Subsequently, the capacitor 600, and the wirings and plugs around it included in the semiconductor device shown in FIG. 22A will be described. Note that above the transistor 500 shown in FIG. 22A, a capacitor 600, wirings, and / or plugs are provided.

[0530] As an example, the capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0531] A conductor 610 is provided on one of the conductor 540a or the conductor 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of the pair of electrodes of the capacitor 600.

[0532] Also, a conductor 612 is provided on the other of the conductor 540a or the conductor 540b and the insulator 586. The conductor 612 functions as a plug, wiring, terminal, etc. that electrically connects the transistor 500 to the circuit elements, wirings, etc. arranged above.

[0533] Note that the conductor 612 and the conductor 610 may be formed simultaneously.

[0534] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0535] In FIG. 22A, the conductor 612 and the conductor 610 are shown in a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, a conductor having barrier properties, a conductor having high conductivity, and a conductor having high adhesion to the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0536] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitor 600.

[0537] As the insulator 630, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, etc. can be used. Further, the insulator 630 can be provided as a laminate or a single layer using the above-described materials.

[0538] Further, for example, the insulator 630 may use a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this configuration, the capacitor 600 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric breakdown voltage and suppress the dielectric breakdown of the capacitor 600 by having an insulator with high dielectric strength.

[0539] Note that examples of insulators made of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0540] Alternatively, the insulator 630 may use, for example, a single layer or a laminate of an insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). Further, as the insulator 630, a compound containing hafnium and zirconium may be used. As semiconductor devices become more miniaturized and highly integrated, problems such as leakage current in transistors, capacitor elements, etc. may occur due to the thinning of the gate insulator and the dielectric used in capacitor elements. By using a high-k material as the insulator that functions as the gate insulator and the dielectric used in capacitor elements, it becomes possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitor element while maintaining the physical film thickness.

[0541] A conductor 620 is provided so as to overlap the conductor 610 with the insulator 630 therebetween. The conductor 610 functions as one of the pair of electrodes of the capacitor 600.

[0542] Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that can achieve both heat resistance and conductivity, and it is particularly preferable to use tungsten. Also, when forming simultaneously with other structures such as the conductor, Cu (copper), Al (aluminum), etc., which are low resistance metal materials, can be used. Further, for example, the conductor 620 can use the materials applicable to the conductor 610. Also, the conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.

[0543] An insulator 640 is provided on the conductor 620 and the insulator 630. As the insulator 640, for example, it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse into the region where the transistor 500 is provided. Therefore, the same material as the insulator 514 can be used.

[0544] An insulator 650 is provided on the insulator 640. The insulator 650 can be provided using the same material as the insulator 512. Also, the insulator 650 may function as a planarization film that covers the uneven shape below it. Therefore, as the insulator 650, for example, the material applicable to the insulator 514 can be used.

[0545] Incidentally, the capacitor 600 shown in FIG. 22A is of a planar type, but the shape of the capacitor element is not limited to this. The capacitor 600 may be, for example, of a cylinder type instead of a planar type.

[0546] Also, a wiring layer may be provided above the capacitor 600. For example, in FIG. 22A, insulators 411, 412, 413, and 414 are sequentially provided above the insulator 650. Also, a configuration is shown in which a conductor 416 that functions as a plug or wiring is provided in the insulators 411, 412, and 413. Also, as an example, the conductor 416 can be provided in a region that overlaps with the conductor 660 described later.

[0547] In addition, openings are provided in regions of the insulators 630, 640, and 650 that overlap with the conductor 612, and a conductor 660 is provided so as to fill the openings. The conductor 660 functions as a plug and a wiring that is electrically connected to the conductor 416 included in the wiring layer described above.

[0548] For the insulators 411 and 414, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similar to the insulator 514 and the like. Therefore, as the insulators 411 and 414, for example, materials applicable to the insulator 514 and the like can be used.

[0549] For the insulators 412 and 413, it is preferable to use an insulator having a relatively low dielectric constant in order to reduce the parasitic capacitance generated between wirings, similar to the insulator 512.

[0550] <Configuration Example of Transistor> Next, a configuration will be described in which a dielectric that may have ferroelectricity is provided inside and around a transistor 500 in which a metal oxide is included in a channel formation region.

[0551] FIG. 25A shows an example of the configuration of a transistor in which a dielectric that may have ferroelectricity is provided in the configuration of the transistor 500 such as FIGS. 22A and 22B.

[0552] The transistor shown in FIG. 25A has a configuration in which an insulator 522 that functions as a gate insulator for the conductor 503 is replaced with an insulator 520. As an example, the insulator 520 can use a dielectric that may have ferroelectricity.

[0553] Note that examples of materials that may have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X(Let X be a real number greater than 0), materials obtained by adding element J1 (where element J1 here is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, materials obtained by adding element J2 (where element J2 here is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like. Also, as materials that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as PbTiO X , barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. Also, as materials that can have ferroelectricity, for example, they can be mixtures or compounds selected from the materials listed above. Or, as materials that can have ferroelectricity, they can be a laminated structure composed of a plurality of materials selected from the materials listed above. By the way, hafnium oxide, zirconium oxide, HfZrO X , and materials obtained by adding element J1 to hafnium oxide, etc. may have their crystal structures (properties) changed not only by film formation conditions but also by various processes, etc. Therefore, in this specification, etc., not only materials that exhibit ferroelectricity are called ferroelectrics, but materials that can have ferroelectricity are called.

[0554] Among them, as materials that can have ferroelectricity, hafnium oxide, or materials having hafnium oxide and zirconium oxide are preferable because they can have ferroelectricity even when processed into thin films of several nm. Here, the film thickness of the insulator 520 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By using the formed ferroelectric layer, a ferroelectric capacitor can be combined with the miniaturized transistor 500 to form a semiconductor device.

[0555] Also, in FIG. 25A, the insulator 520 is shown as a single layer, but the insulator 520 may be an insulating film of two or more layers including a dielectric that may have ferroelectricity. A specific example of the transistor is shown in FIG. 25B. In FIG. 25B, for example, the insulator 520 has an insulator 520a and an insulator 520b. The insulator 520a is provided on the upper surfaces of the insulator 516 and the conductor 503, respectively, and the insulator 520b is provided on the upper surface of the insulator 520a.

[0556] As the insulator 520a, for example, a dielectric that may have ferroelectricity can be used. As the insulator 520b, for example, silicon oxide or the like can be used. Also, for example, conversely, silicon oxide may be used for the insulator 520a and a dielectric that may have ferroelectricity may be used for the insulator 520b.

[0557] As shown in FIG. 25B, by providing the insulator 520 as two layers, with a dielectric that may have ferroelectricity provided in one layer and silicon oxide provided in the other layer, current leakage flowing between the conductor 503 functioning as a gate electrode and the oxide 530 can be suppressed.

[0558] Also, FIG. 25C shows a configuration example of a transistor in which the insulator 520 is three layers. In FIG. 25C, the insulator 520 has, for example, an insulator 520a, an insulator 520b, and an insulator 520c. The insulator 520c is provided on the upper surfaces of the insulator 516 and the conductor 503, respectively, the insulator 520a is provided on the upper surface of the insulator 520c, and the insulator 520b is provided on the upper surface of the insulator 520a.

[0559] As the insulator 520a, for example, a dielectric that may have ferroelectricity can be used. As the insulator 520b and the insulator 520c, for example, silicon oxide or the like can be used.

[0560] The transistor configurations shown in FIGS. 25A to 25C can be applied, for example, to the transistors 22 and 32 shown in FIG. 1B described in the above embodiment.

[0561] By applying the present structure described in this embodiment to a semiconductor device using a transistor having an oxide semiconductor, fluctuations in the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0562] Further, in a semiconductor device using a transistor having an oxide semiconductor, by achieving a stacked structure, miniaturization, high integration, etc., the area of the circuit constituting the semiconductor device can be reduced. In particular, as a capacitive element included in the semiconductor device, by using a ferroelectric capacitor, the value of the capacitance of the capacitive element can be increased, so that miniaturization of the capacitive element can be achieved. For this reason, the area of the circuit including the capacitive element can be reduced. Also, as described in this embodiment, by stacking transistors and capacitive elements, the circuit scale can be increased while suppressing an increase in the circuit area of the semiconductor device.

[0563] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0564] (Embodiment 5) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0565] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to those, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0566] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 26A. FIG. 26A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically an IGZO (metal oxide containing In, Ga, and Zn).

[0567] As shown in FIG. 26A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) are included in "Crystalline". Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, single crystal and poly crystal are included in "Crystal".

[0568] Note that the structure within the thick frame shown in FIG. 26A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0569] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 26B. In FIG. 26B, the horizontal axis is 2θ [deg.], and the vertical axis is Intensity [a.u.]. Note that the GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 26B may be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 26B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 26B is 500 nm.

[0570] As shown in FIG. 26B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in FIG. 26B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0571] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 26C. FIG. 26C is a diffraction pattern observed by NBED in which an electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 26C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0572] As shown in FIG. 26C, a plurality of spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0573] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 26A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0574] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0575] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0576] Note that each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0577] Also, in an In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The said layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0578] When a structural analysis is performed on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in the vicinity thereof. Note that the position (2θ value) of the peak indicating c-axis orientation may vary depending on the type, composition, etc. of the metal elements constituting CAAC-OS.

[0579] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0580] When observing the crystal region from the specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be an irregular hexagon. Also, in the above-mentioned strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, even in the vicinity of the strain, no distinct grain boundaries can be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the strain of the lattice arrangement. This is presumably because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, the bond distance between atoms changes due to the substitution of metal atoms, etc.

[0581] A crystal structure in which distinct grain boundaries are confirmed is called a so-called polycrystal. Grain boundaries can act as recombination centers, and there is a high possibility that carriers are captured, causing a decrease in the on-current of the transistor, a decrease in the field-effect mobility, etc. Therefore, CAAC-OS in which no distinct grain boundaries are confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. To form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0582] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities and the generation of defects, etc., it can also be said that CAAC-OS is an oxide semiconductor with few impurities, defects (such as oxygen deficiencies), etc. Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when using CAAC-OS for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0583] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and an amorphous oxide semiconductor. For example, when performing structural analysis on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Further, when performing electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0584] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film compared with nc-OS and CAAC-OS.

[0585] <<Constitution of Oxide Semiconductor>> Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0586] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0587] Furthermore, CAC-OS becomes a mosaic state by separating the material into a first region and a second region, and the first region has a structure distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0588] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are respectively denoted as [In], [Ga], and [Zn]. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0589] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, or the like. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, or the like. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0590] Note that there may be cases where a clear boundary cannot be observed between the above-mentioned first region and the second region.

[0591] For example, in CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0592] When CAC-OS is used in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, so that a switching function (On / Off function) can be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be realized.

[0593] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0594] <Transistor having an oxide semiconductor> Subsequently, the case where the above-mentioned oxide semiconductor is used in a transistor will be described.

[0595] By using the above-mentioned oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0596] For the transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, and further preferably 1×10 10 cm -3 or less, and is 1×10 -9 cm -3 or more. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0597] In addition, since an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0598] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0599] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0600] <Impurities> Here, the effects of various impurities in the oxide semiconductor will be described.

[0601] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Hereinafter, preferably 2×10 17 atoms / cm 3 or less.

[0602] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 or less.

[0603] In addition, when nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18atoms / cm 3 Hereinafter, more preferably 5×10 17 atoms / cm 3 or less.

[0604] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen that binds to metal atoms to form water, oxygen deficiency may be formed. When hydrogen enters the oxygen deficiency, carriers, electrons, may be generated. Also, a part of hydrogen may bind to oxygen that binds to metal atoms to generate carriers, electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less, preferably 1×10 19 atoms / cm 3 less, more preferably 5×10 18 atoms / cm 3 less, still more preferably 1×10 18 atoms / cm 3 or less.

[0605] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0606] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0607] (Embodiment 6) In this embodiment, a configuration of an integrated circuit including each configuration of the semiconductor device and the arithmetic device MAC1 described in the above embodiment will be described with reference to FIG. 27.

[0608] FIG. 27 is an example of a semiconductor chip 391 incorporating an integrated circuit 390. The semiconductor chip 391 shown in FIG. 27 has leads 392 and an integrated circuit 390. The integrated circuit 390 has various circuits including the semiconductor device and the arithmetic unit MAC1 shown in the above embodiment provided on a single die. The integrated circuit 390 has a stacked structure and is roughly classified into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). Since the OS transistor layer 395 can be stacked on the Si transistor layer 393, it is easy to miniaturize the semiconductor chip 391.

[0609] In FIG. 27, a QFP (Quad Flat Package) is applied to the package of the semiconductor chip 391, but the package form is not limited to this. As other configuration examples, DIP (Dual In-line Package), PGA (Pin Grid Array) which are insertion mounting types, SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), DTP (Dual Tape carrier Package) which is a contact mounting type, QTP (Quad Tape-carrier Package), etc. can be appropriately used.

[0610] The semiconductor device having Si transistors and the arithmetic unit MAC1 can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the above semiconductor device can be formed by the same manufacturing process. Therefore, even if the number of elements constituting the semiconductor chip shown in FIG. 27 increases, it is not necessary to increase the manufacturing process, and the above semiconductor device can be incorporated at low cost.

[0611] According to one aspect of the present invention described above, a novel semiconductor device and an electronic device can be provided. Or, according to one aspect of the present invention, a semiconductor device and an electronic device with low power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device and an electronic device capable of suppressing heat generation can be provided.

[0612] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0613] (Embodiment 7) In this embodiment, an electronic device, a moving body, and an arithmetic system to which the integrated circuit 390 (or the semiconductor chip 391 incorporating the integrated circuit 390) described in the above embodiment can be applied will be described with reference to FIGS. 28 to 31.

[0614] FIG. 28A shows an external view of an automobile as an example of a moving body. FIG. 28B is a simplified diagram of data exchange inside the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter-wave radar, and a laser radar.

[0615] In the automobile 590, the above integrated circuit 390 can be used for the cameras 591 and the like. The automobile 590 processes a plurality of images obtained by the cameras 591 in a plurality of imaging directions 592 with the integrated circuit 390 described in the above embodiment, and collectively analyzes the plurality of images by a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and performing automatic driving. It can also be used in a system for road guidance, danger prediction, and the like.

[0616] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of an image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (widening the dynamic range), restoring an image of a lensless image sensor, positioning, character recognition, and reducing specular reflections can be performed.

[0617] Note that in the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. The computer according to one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0618] FIG. 29A is an external view showing an example of a portable electronic device. FIG. 29B is a diagram simplifying data exchange in the portable electronic device. The portable electronic device 595 includes a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0619] In the portable electronic device 595, the integrated circuit 390 can be provided on the printed wiring board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of data obtained from the speaker 597, the camera 598, the microphone 599, etc. using the integrated circuit 390 described in the above embodiment.

[0620] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of an image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (widening the dynamic range), restoring an image of a lensless image sensor, positioning, character recognition, and reducing specular reflections can be performed.

[0621] The portable game machine 1100 shown in FIG. 30A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, etc. The housings 1101, 1102, and 1103 can be removed. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. An integrated circuit 390 shown in the previous embodiment can be incorporated into chips and the like provided on the substrates of the housings 1102 and 1103.

[0622] FIG. 30B shows a USB connection type stick-shaped electronic device 1120. The electronic device 1120 includes a housing 1121, a cap 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the substrate 1124. An integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 and the like on the substrate 1124.

[0623] FIG. 30C shows a humanoid robot 1130. The robot 1130 includes sensors 2101 to 2106 and a control circuit 2110. For example, an integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0624] Instead of being built into an electronic device, the integrated circuit 390 described in the above embodiment can also be used in a server that communicates with the electronic device. In this case, an arithmetic system is configured by the electronic device and the server. FIG. 31 shows a configuration example of the system 3000.

[0625] The system 3000 is composed of an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via the Internet line 3003.

[0626] The server 3002 has a plurality of racks 3004. A plurality of substrates 3005 are provided on the plurality of racks, and the integrated circuit 390 described in the above embodiment can be mounted on the substrate 3005. Thereby, a neural network is configured in the server 3002. Then, the server 3002 can perform neural network operations using the data input from the electronic device 3001 via the Internet line 3003. The result of the operation by the server 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. Thereby, the operation load on the electronic device 3001 can be reduced.

[0627] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0628] (Supplementary Note Regarding the Descriptions in this Specification, etc.) Regarding the above embodiments and the descriptions of each configuration in the embodiments, the following supplementary notes are provided.

[0629] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form an aspect of the present invention. Also, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

[0630] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with the content described in another content (even a part of the content) described in that embodiment and / or the content described in one or more other embodiments (even a part of the content).

[0631] Note that the content described in the embodiments refers to the content described using various figures or the text described in the specification in each embodiment.

[0632] Note that the figure (which may be a part) described in a certain embodiment can be combined with another part of that figure, another figure (which may be a part) described in that embodiment, and / or the figure (which may be a part) described in one or more other embodiments to form even more figures.

[0633] Also, in this specification and the like, in the block diagram, the components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components by function, and there may be a case where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0634] Also, in the drawings, the size, layer thickness, or area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0635] Also, the positional relationship of the components illustrated in the drawings and the like is relative. Therefore, when explaining the components with reference to the drawings, terms such as "above" and "below" indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description in this specification and can be appropriately rephrased according to the situation.

[0636] In this specification and the like, when explaining the connection relationship of a transistor, the notation "one of the source or the drain" (or the first electrode, or the first terminal) and the other of the sourc...

Claims

1. A semiconductor device having a first transistor, a second transistor, and a capacitor, wherein the first transistor has a first gate and a first back gate; the second transistor has a second gate and a second back gate; a gate insulating layer for the first back gate has ferroelectricity; when the first transistor is in an off state, the first transistor has a function of holding a first potential corresponding to first data applied to the second back gate via the first transistor; the capacitor has a function of changing the first potential held in the second back gate to a second potential in accordance with a change in potential corresponding to second data applied to one electrode of the capacitor; the second transistor has a function of flowing an output current corresponding to the potential of the second back gate between a source and a drain of the second transistor; the output current is a current that flows when the second transistor operates in a subthreshold region; and a constant potential is applied to the second gate.

2. A semiconductor device having a first transistor, a second transistor, and a capacitor, wherein the first transistor has a first gate and a first back gate; the second transistor has a second gate and a second back gate; a gate insulating layer for the first back gate has ferroelectricity; one electrode of the capacitor is electrically connected to the second gate; a constant potential is applied to the other electrode of the capacitor; when the first transistor is in an off state, the first transistor has a function of holding a first potential corresponding to first data applied to the second gate via the first transistor; the second transistor has a function of flowing an output current corresponding to the potential of the second gate between a source and a drain of the second transistor; and the output current is a current that flows when the second transistor operates in a subthreshold region.

3. A semiconductor device having a first transistor, a second transistor, and a capacitor, wherein the first transistor has a first gate and a first back gate; the second transistor has a second gate and a second back gate; a gate insulating layer for the first back gate has ferroelectricity; one electrode of the capacitor is electrically connected to the second back gate; a constant potential is applied to the other electrode of the capacitor; When the first transistor is in the off state, it has a function of holding a first potential corresponding to first data applied to the second back gate via the first transistor. The second transistor has a function of flowing an output current corresponding to the potential of the second back gate between the source and drain of the second transistor. The output current is a current that flows when the second transistor operates in the subthreshold region. A semiconductor device.

4. In any one of Claims 1 to 3, The semiconductor device has a circuit, The circuit is electrically connected to the first gate, The circuit has a function of generating a signal for controlling on or off of the first transistor. A semiconductor device.

5. In any one of Claims 1 to 4, The gate insulating layer for the first back gate has an oxide containing one or both of hafnium and zirconium. A semiconductor device.

6. It has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. The first to third transistors each have a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor and one electrode of the first capacitor. The other of the source or drain of the first transistor is electrically connected to the back gate of the second transistor and the other electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. The other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor. A semiconductor device.

7. In Claim 6, A constant potential is applied to the gate of the second transistor. A semiconductor device.

8. It has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. Each of the first to third transistors has a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. A semiconductor device, wherein the other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor.

9. A semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor. Each of the first to third transistors has a gate and a back gate. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the first transistor is electrically connected to the back gate of the second transistor and one electrode of the first capacitor. The back gate of the first transistor is electrically connected to one of the source or drain of the third transistor, the back gate of the third transistor, and one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to one electrode of the ferroelectric capacitor. A semiconductor device, wherein the other of the source or drain of the fourth transistor is electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor.

10. In Claim 8 or 9, A semiconductor device, wherein a fixed potential is applied to the other electrode of the first capacitor.

11. In any one of Claims 6 to 10, The semiconductor device has a circuit. The circuit is electrically connected to the gate of the first transistor. The circuit is a semiconductor device having a function of generating a signal for controlling on or off of the first transistor.

12. In any one of Claims 6 to 11, the ferroelectric capacitor has a dielectric layer, the dielectric layer has an oxide containing one or both of hafnium and zirconium, a semiconductor device.

13. In any one of Claims 1 to 12, the first transistor has a semiconductor layer having a metal oxide in a channel formation region, a semiconductor device.

14. In Claim 13, the metal oxide contains In, Ga, and Zn, a semiconductor device.

15. In Claim 13, the metal oxide is indium oxide, a semiconductor device.

16. In any one of Claims 1 to 15, the second transistor has a semiconductor layer having silicon in a channel formation region, a semiconductor device.

17. An electronic device having a semiconductor device according to any one of Claims 1 to 16 and a housing, wherein the semiconductor device performs operations of a neural network. Electronic device.

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