Light-emitting device

Abstract

To provide a semiconductor device which enables the achievement of a high-speed operation, or has a large strength against a stress.SOLUTION: A semiconductor device comprises: a first gate electrode; a first insulation film over the first gate electrode; a semiconductor film having a channel formation region and a pair of impurity regions located on both sides of the channel formation region, and arranged so that the channel formation region overlaps with the first gate electrode through the first insulation film; a second insulation film covering side and top portions of the semiconductor film in the channel formation region; a second gate electrode overlying the side and top portions of the semiconductor film in the channel formation region through the second insulation film; and a source electrode and a drain electrode which are put in contact with the side and top portions of the semiconductor film in the pair of impurity regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device utilizing semiconductor characteristics .

Background Art

[0002] For semiconductor display devices used in portable electronic devices and the like, it is required to narrow (bezel) the area other than the pixel portion. The system-on-panel in which part or all of the driving circuit is fabricated on the same substrate as the pixel portion is one of the effective means for realizing bezel narrowing. The following Patent Document 1 discloses a system-on-panel type display device in which a display portion and a peripheral circuit portion are formed on the same substrate.

[0003]

Prior Art Document

Patent Document

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in an active matrix type semiconductor display device, the number of pixels tends to increase in order to display higher definition and higher resolution images. Therefore, the scanning line driving circuit and the signal line driving circuit Drive circuits such as lines are required to drive at high speed. In particular, the signal line drive circuit needs to supply an image signal to all the pixels in the line while each pixel in the line is selected. Therefore, its drive frequency is much higher than that of the scanning line drive circuit. While each pixel in the line is selected, it is necessary to supply an image signal to all the pixels in the line. Therefore, its drive frequency is much higher than that of the scanning line drive circuit.

[0006] In addition, by using a flexible material such as plastic as the substrate of the semiconductor device (flexible material), the range of usage forms of the semiconductor device can be expanded. However, when using a flexible substrate, a higher strength against stress is required for the semiconductor element compared to the case of using a substrate with poor flexibility such as a glass substrate. By using a flexible material such as plastic as the substrate of the semiconductor device (flexible material), the range of usage forms of the semiconductor device can be expanded. However, when using a flexible substrate, a higher strength against stress is required for the semiconductor element compared to the case of using a substrate with poor flexibility such as a glass substrate. When using a flexible substrate, a higher strength against stress is required for the semiconductor element compared to the case of using a substrate with poor flexibility such as a glass substrate. Therefore, a higher strength against stress is required for the semiconductor element compared to the case of using a substrate with poor flexibility such as a glass substrate.

[0007] Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Under the technical background as described above, in one aspect of the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Or, in one aspect of the present invention, one of the problems is to provide a semiconductor device having high strength against stress. Or, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become clear from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0008] A semiconductor device according to one aspect of the present invention includes a semiconductor film having a channel formation region and a pair of impurity regions sandwiching the channel formation region therebetween, and in the channel formation region A semiconductor film having a channel formation region and a pair of impurity regions sandwiching the channel formation region therebetween, and in the channel formation region An insulating film that covers the side and upper portions of the semiconductor film, and a gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. And has.

[0009] A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. And has.

[0010] A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A semiconductor device according to one aspect of the present invention includes a first gate electrode, a first insulating film on the first gate electrode, a channel formation region, and a pair of impurity regions positioned with the channel formation region interposed therebetween, and a semiconductor film having the channel formation region overlapping the first gate electrode with the first insulating film interposed therebetween, a second insulating film that covers the side and upper portions of the semiconductor film in the channel formation region, a second gate electrode that overlaps the side and upper portions of the semiconductor film in the channel formation region with the second insulating film interposed therebetween, and source and drain electrodes that are respectively in contact with the side and upper portions of the semiconductor film in the pair of impurity regions. A source electrode and a drain electrode, each in contact with a side portion and an upper portion of the semiconductor film in the pair of impurity regions. have.

Advantages of the Invention

[0011] According to one aspect of the present invention, a semiconductor device capable of realizing high-speed operation can be provided. According to one aspect of the present invention, a semiconductor device having high strength against stress can be provided. Further, a novel semiconductor device, display device, light-emitting device, etc. can be provided. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0012]

Figure 1

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0014] Note that one aspect of the present invention includes all semiconductor devices using transistors, such as integrated circuits, RF tags, and semiconductor display devices. Note that integrated circuits include microprocessors , image processing circuits, DSPs (Digital Signal Processors), and LSIs (Large Scale Integrated Circuits) including microcontrollers , and FPGAs (Field Programmable Gate Arrays) y) or programmable logic circuits such as CPLD (Complex PLD) (PLD: Programmable Logic Device) are included in its scope. Also, semiconductor display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements (OLED) provided in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc., and semiconductor display devices having transistors in their drive circuits are included in its scope. (Field Emission Display), etc., and semiconductor display devices having transistors in their drive circuits are included in its scope. Note that in this specification, a semiconductor display device refers to a panel in which display elements such as liquid crystal elements and light-emitting elements are formed in each pixel,

[0015] and a module in a state where an IC including a controller is mounted on the panel, and is included in its scope. Further, a semiconductor display device according to an aspect of the present invention includes, in its scope, an element substrate corresponding to a form before the display element is completed in the process of manufacturing the semiconductor display device, and the element substrate includes a transistor, electrodes such as a pixel electrode or a common electrode used for the display element, and a capacitor element in a plurality of each pixel. In addition, a semiconductor display device according to an aspect of the present invention may include a touch panel, which is a position input device that can detect a position pointed by a finger or a stylus and generate a signal including the position information, as a component. In addition, in this specification, "connection" means electrical connection, and when the circuit configuration is such that current, voltage, or potential can be supplied or transmitted, it is considered connected.

[0016] In addition, a semiconductor display device according to an aspect of the present invention may include a touch panel, which is a position input device that can detect a position pointed by a finger or a stylus and generate a signal including the position information, as a component. In addition, in this specification, "connection" means electrical connection, and when the circuit configuration is such that current, voltage, or potential can be supplied or transmitted, it is considered connected.

[0017] Also, in this specification, "connection" means electrical connection, and when the circuit configuration is such that current, voltage, or potential can be supplied or transmitted, it is considered connected. Therefore, a configuration in which one circuit is connected to another is equivalent to a configuration in which they are directly connected. It does not necessarily refer to a structure capable of supplying or transmitting current, voltage, or potential. As shown in the figure, they are indirectly connected through elements such as wiring, resistors, diodes, and transistors. Also, a configuration in which certain elements are connected to other elements does not mean that the elements are directly connected to each other. It does not necessarily refer to a structure in which a current, voltage, or potential can be supplied, Or, it can be transmitted through elements such as wiring, resistors, diodes, and transistors. This also includes configurations that are indirectly connected via other circuits. Even when elements are connected to each other, in reality, for example, part of the wiring functions as an electrode. In some cases, a single conductive film may have the functions of multiple components. In the specification, connection means that one conductive film has the functions of multiple components. If so, include it in that category.

[0018] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The source electrode of a transistor is a region or a semiconductor film connected to the source electrode. The drain is a drain region that is a part of the semiconductor film, or a region connected to the semiconductor film. The term "gate" refers to a gate electrode.

[0019] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics given to each terminal. The name changes depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. is called a drain. In a p-channel transistor, the terminal to which a low potential is applied is called a drain, and the terminal to which a high potential is applied is called a source. In this specification, for convenience assuming that the source and the drain are fixed, the connection relationship of the transistor may be described However, in reality, the names of the source and the drain are interchanged according to the above potential relationship .

[0020] <Example Configuration 1 of Transistor> FIG. 1 shows, as an example, the configuration of a transistor 10 included in a semiconductor device according to one aspect of the present invention . FIG. 1(A) shows a plan view of the transistor 10. In FIG. 1(A), various insulating films are omitted for clarity of the layout of the transistor 10 . Further, FIG. 1(B) shows a circuit diagram symbol of the transistor 10 shown in FIG. 1(A). Also, a cross-sectional view taken along the broken line A1 - A2 in the plan view shown in FIG. 1(A) is shown in FIG. 1(C), and a cross-sectional view taken along the broken line B1 - B 2 is shown in FIG. 1(D). ) The cross-sectional view taken along the broken line A1 - A2 in the plan view shown in FIG. 1(A) is shown in FIG. 1(C), and the cross-sectional view taken along the broken line B1 - B 2 is shown in FIG. 1(D).

[0021] The transistor 10 shown in FIGS. 1(A), 1(C), and 1(D) has a semiconductor film 12 on a substrate 11 having an insulating surface . The semiconductor film 12 has a channel formation region 12a, and impurity regions 12b and 12c positioned with the channel formation region 12a sandwiched therebetween . Further, the transistor 10 has a function as a gate insulating film and also has an insulating film 13 that covers side portions and an upper portion of the semiconductor film 12 in the channel formation region 12a . Furthermore, the transistor 10 has a function as a gate electrode (FG) shown in the circuit diagram symbol of FIG. 1(B) and also has a semiconductor film in the channel formation region 12a with the insulating film 13 sandwiched therebetween It has a conductive film 17 that overlaps the side and upper portions of 12. Also, the transistor 10 functions as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 1(B ). Further, it has a conductive film 14 and a conductive film 15 respectively connected to the side and upper portions of the semiconductor film 12 in the impurity region 12b and the impurity region 12c. Note that at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is provided on at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12.

[0022] Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is in contact with at least a part (or all) of the semiconductor film 12.

[0023] Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is electrically connected to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is electrically connected to a part (or all) of the semiconductor film 12.

[0024] Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed in proximity to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is

[0025] Or, at least a part (or all) of the conductive film 14 (and / or the conductive film 15) is ​ Part (or all) of it is disposed adjacent to part (or all) of the semiconductor film 12.

[0026] Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed beside at least part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed beside part (or all) of the semiconductor film 12.

[0027] Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed obliquely above at least part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed obliquely above part (or all) of the semiconductor film 12.

[0028] Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed above at least part (or all) of the surface, side surface, upper surface, and / or lower surface of the semiconductor film 12. Or, at least part (or all) of the conductive film 14 (and / or the conductive film 15) is disposed above part (or all) of the semiconductor film 12.

[0029] Also, in FIGS. 1(A), 1(C), and 1(D), a case is illustrated where an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, and the conductive film 17, and the conductive film 14 and the conductive film 15 are provided on the insulating film 16. And, in FIGS. 1(A), 1(C), and 1(D), at the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film The case where 15 is connected to the impurity regions 12b and 12c is illustrated.

[0030] As shown in FIG. 1, in the transistor 10 according to one aspect of the present invention, in the channel formation region 1 2a, carriers flow in a wide range including the side and upper portions of the semiconductor film 12 and the conductive film 17, so that the carriers flow in a wide range including the side and upper portions of the channel formation region 12a. Therefore, while suppressing the occupied area on the substrate in the channel formation region 12a of the semiconductor film 12 to be small, the amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 10 increases and the field-effect mobility is enhanced. In particular, when the length (channel width) in the channel width direction of the semiconductor film 12 in the channel formation region 12a is W and the film thickness of the semiconductor film 12 in the channel formation region 12a is T, when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which carriers flow becomes wider. Therefore, the on-current of the transistor 10 can be made larger, and the field-effect mobility can also be further enhanced. In this specification, the aspect ratio refers to the ratio (T / W) of the film thickness (T) of the semiconductor film to the length of the short side of the bottom surface of the semiconductor film (channel width W). can be made larger, and the field-effect mobility can also be further enhanced. Note that, unlike the case of a transistor using a bulk semiconductor substrate, in the case of the transistor 10 using a thin-film semiconductor film 12, the aspect ratio is desirably such that a sufficient degree of crystallinity can be ensured in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a sufficient degree of crystallinity of the semiconductor film 12, specifically, the film thickness T is 5 nm or more and 150 nm or less.

[0031] Note that, unlike the case of a transistor using a bulk semiconductor substrate, in the case of the transistor 10 using a thin-film semiconductor film 12, the aspect ratio is desirably such that a sufficient degree of crystallinity can be ensured in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a sufficient degree of crystallinity of the semiconductor film 12, specifically, the film thickness T is 5 nm or more and 150 nm or less. It is desirable that the thickness is less than 20 nm, and more desirable that the thickness is between 20 nm and 100 nm. Assuming that the film thickness T is within the above range, the resolution of the exposure device when using a glass substrate is Considering that the degree of the crystal grain is about several μm, the specific aspect ratio is between 0.05 and 10. It is desirable that the ratio be 0.1 or more and 5 or less, and more desirable that the ratio be 0.1 or more and 5 or less. It is more desirable that the ratio be 1 or more and 5 or less.

[0032] The channel length direction is the direction in which the carrier flows between the impurity region 12b and the impurity region 12c. The channel width direction is perpendicular to the channel length direction. means the direction of.

[0033] As shown in FIG. 1, in a transistor 10 according to an embodiment of the present invention, an impurity region 1 The conductive film 14 and the conductive film 15 are formed on the sides and the top of the semiconductor film 12 in the impurity regions 12b and 12c. Therefore, the conductive film 14 and the conductive film 15 are connected to the semiconductor film 12. The conductive film 14 and the conductive film 15 are connected to the impurity region 12 in comparison with the case where the conductive film 14 and the conductive film 15 are connected to the impurity region 12 only. This allows the area where the impurity region 12b and the impurity region 12c are in contact with each other to be increased. Therefore, the contact between the conductive film 14 and the conductive film 15 and the impurity region 12b and the impurity region 12c is The resistance can be kept small, and as a result, the on-current of the transistor 10 can be increased.

[0034] <Transistor configuration example 2> Next, FIG. 2 shows a transistor 10 included in a semiconductor device according to one embodiment of the present invention, which is shown in FIG. FIG. 2A shows a plan view of a transistor 10. In FIG. 2A, various insulating films are omitted to clarify the layout of the transistor 10. It is abbreviated. Also, FIG. 2(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 2(A). Also, FIG. 2(C) shows a cross-sectional view taken along the broken line A1 - A2 of the plan view shown in FIG. 2(A). And FIG. 2(D) shows a cross-sectional view taken along the broken line B1 - B2.

[0035] The transistor 10 shown in FIGS. 2(A), 2(C), and 2(D) has an insulating surface On the substrate 11, it has a conductive film 20 having the function of a gate electrode (BG) shown in the circuit diagram symbol of FIG. 2(B). Also, the transistor 10 has the function of a gate insulating film and has an insulating film 21 covering the conductive film 20. Also, the transistor 10 has a semiconductor film 12 sandwiching the insulating film 21 and overlapping the conductive film 20. The semiconductor film 12 has a channel formation region 12a, an impurity region 12b and an impurity region 12c located with the channel formation region 12a sandwiched therebetween. Also, the transistor 10 has the function of a gate insulating film and has an insulating film 13 covering the side and upper portions of the semiconductor film 12 in the channel formation region 12a. Also, the transistor 10 has the function of a gate electrode (FG) shown in the circuit diagram symbol of FIG. 2(B) and has a conductive film 17 sandwiching the insulating film 13 and overlapping the side and upper portions of the semiconductor film 12 in the channel formation region 12a. The conductive film 17 is connected to the conductive film 20 at the openings 22 and 23 of the insulating film 13 and the insulating film 21. Also, the transistor 10 has the function of a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 2(B) and has conductive films 14 and conductive films 15 respectively connected to the side and upper portions of the semiconductor film 12 in the impurity region 12b and the impurity region 12c. ​​​​​​​

[0036] Also, in FIGS. 2(A), 2(C), and 2(D), an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, and the conductive film 17, and the conductive films 14 and 15 are provided on the insulating film 16. This is an example of such a case. And in FIGS. 2(A), 2(C), and 2(D), in the openings 18 and 19 provided in the insulating film 16, this is an example of the case where the conductive films 14 and 15 are connected to the impurity regions 12b and 12c.

[0037] Also, in FIGS. 2(A), 2(C), and 2(D), this is an example of the case where the openings 22 and 23 are provided at positions facing each other with the semiconductor film 12 interposed therebetween.

[0038] As shown in FIG. 2, in the transistor 10 according to one aspect of the present invention, the carrier flows in a wide range including the side portions and the upper portion of the semiconductor film 12 in the channel formation region 1 2a, where the side portions and the upper portion of the semiconductor film 12 overlap with the conductive film 17. Therefore, while suppressing the occupation area on the substrate in the channel formation region 12a of the semiconductor film 12 to be small, the amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 10 becomes large and the field-effect mobility is enhanced. In particular, when the length (channel width) in the channel width direction of the semiconductor film 12 in the channel formation region 12a is W and the film thickness of the semiconductor film 12 in the channel formation region 12a is T, when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which the carrier flows becomes wider. Therefore, the on-current of the transistor 10 can be made larger and the field-effect mobility can also be enhanced more.

[0039] And, as described above, in the case of the transistor 10 using the semiconductor film 12 of the thin film, the aspect ratio is desirably high enough to ensure a high degree of crystallinity in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12, specifically, the film thickness T is desirably 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. Assuming that the value of the film thickness T is within the above range, considering that the resolution of the exposure apparatus when using a glass substrate is about several μm, the specific aspect ratio is desirably 0.05 or more and 10 or less, and more desirably 0.1 or more and 5 or less. Furthermore, it is more desirable that the aspect ratio is 1 or more and 5 or less.

[0040] Also, as shown in FIG. 2, in the transistor 10 according to one aspect of the present invention, on the side and upper portions of the semiconductor film 12 in the impurity regions 1 2b and the impurity region 12c, the conductive film 14 and the conductive film 15 are respectively connected. Therefore, compared with the case where the conductive film 14 and the conductive film 15 are connected only to the upper portion of the semiconductor film 12, it is possible to ensure a larger area of contact between the conductive film 14 and the conductive film 15 and the impurity regions 12 b and the impurity region 12c, respectively. Thus, the contact resistance between the conductive film 14 and the conductive film 15 and the impurity regions 12b and the impurity region 12c can be suppressed to be small, and as a result, the on-current of the transistor 10 can be increased.

[0041] Also, in the transistor 10 shown in FIG. 2, the conductive film 17 that functions as the gate electrode (FG) On the side of the region near the surface of the semiconductor film 12 (back channel region) far from it, a conductive film 20 that functions as a gate electrode (BG) is provided. In addition, the conductive film 20 is connected to the conductive film 1 7. With the above configuration, in the transistor 10 shown in FIG. 2, the back channel region is prevented from generating fixed charges, and the off-current can be reduced. Also, in the transistor 10 shown in FIG. 2, since the conductive film 20 is connected to the conductive film 17, compared to the transistor 10 shown in FIG. 1, the region where carriers move spans a wider

[0042] range, so the on-current can be made larger. Also, in the transistor 10 shown in FIG. 2, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Therefore, since the upper and lower parts of the semiconductor film 12 are supported by the

[0043] conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1.

[0044] 〈Example Configuration 3 of Transistor〉 Note that in the transistors 10 shown in FIGS. 1 and 2, the conductive films 14 and 15 that function as source electrodes or drain electrodes are provided on the insulating film 16, and in the openings of the insulating film 16, the conductive films 14 and 15 are connected to the impurity regions 12b and 12c, respectively, as an example. The transistor 1 0 according to one aspect of the present invention may have the insulating film 16 provided on the conductive films 14 and 15.

[0044] The transistor 10 shown in FIG. 3 is different in configuration from the transistor 10 shown in FIG. 1 in that an insulating film 16 is provided on the conductive film 14 and the conductive film 15. FIG. 3(A) shows a plan view of the transistor 10. In FIG. 3(A), various insulating films are omitted for clarity of the layout of the transistor 10. FIG. 3(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 3(A). Also, FIG. 3(C) shows a cross-sectional view taken along the dashed line A1 - A2 of the plan view shown in FIG. 3(A), and FIG. 3(D) shows a cross-sectional view taken along the dashed line B1 - B2. The transistor 10 shown in FIGS. 3(A), 3(C), and 3(D) has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 3(B), and further has a conductive film 14 and a conductive film 15 connected to the side and the upper part of the semiconductor film 12 in the impurity region 12b and the impurity region 12c, respectively. In FIGS. 3(A), 3(C), and 3(D), an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, the conductive film 17, the conductive film 14, and the conductive film 15.

[0045] The transistor 10 shown in FIGS. 3(A), 3(C), and 3(D) has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 3(B), and further has a conductive film 14 and a conductive film 15 connected to the side and the upper part of the semiconductor film 12 in the impurity region 12b and the impurity region 12c, respectively. In FIGS. 3(A), 3(C), and 3(D), an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, the conductive film 17, the conductive film 14, and the conductive film 15. The transistor 10 shown in FIG. 4 is different in configuration from the transistor 10 shown in FIG. 2 in that an insulating film 16 is provided on the conductive film 14 and the conductive film 15. FIG. 4(A) shows a plan view of the transistor 10. In FIG. 4(A), various insulating films are omitted for clarity of the layout of the transistor 10. FIG. 4(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 4(A). Also, FIG. 4(C) shows a cross-sectional view taken along the dashed line A1 - A2 of the plan view shown in FIG. 4(A), and FIG. 4(D) shows a cross-sectional view taken along the dashed line B1 - B2.

[0046] The transistor 10 shown in FIG. 4 is different in configuration from the transistor 10 shown in FIG. 2 in that an insulating film 16 is provided on the conductive film 14 and the conductive film 15. FIG. 4(A) shows a plan view of the transistor 10. In FIG. 4(A), various insulating films are omitted for clarity of the layout of the transistor 10. FIG. 4(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 4(A). Also, FIG. 4(C) shows a cross-sectional view taken along the dashed line A1 - A2 of the plan view shown in FIG. 4(A), and FIG. 4(D) shows a cross-sectional view taken along the dashed line B1 - B2. The transistor 10 shown in FIGS. 4(A), 4(C), and 4(D) has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 4(B), and further has a conductive film 14 and a conductive film 15 connected to the side and the upper part of the semiconductor film 12 in the impurity region 12b and the impurity region 12c, respectively. ​

[0047] The transistors 10 shown in FIGS. 4(A), 4(C), and 4(D) are circuits of FIG. 4(B) It has a function as a source electrode (S) or a drain electrode (D) shown by a circuit symbol, and respectively, on the side and upper part of the semiconductor film 12 in the impurity region 12b and the impurity region 12c It has a conductive film 14 and a conductive film 15 connected thereto. And in FIGS. 4(A), 4(C), and 4(D), an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, the conductive film 17, the conductive film 14, and the conductive film 1 5.

[0048] The transistor 10 shown in FIGS. 3 and 4 is also the same as the transistor 10 shown in FIGS. 1 and 2 The side and upper part of the semiconductor film 12 in the channel formation region 12a overlap with the conductive film 17 As a result, carriers flow in a wide range including the side and upper part of the channel formation region 12a. Therefore, while suppressing the occupied area on the substrate in the channel formation region 12a of the semiconductor film 12 to be small The amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 10 increases and the field-effect mobility is enhanced. In particular, when the length (channel width) in the channel width direction of the semiconductor film 12 in the channel formation region 12a is W and the film thickness of the semiconductor film 12 in the channel formation region 12a is T The on-current of the transistor 10 can be made larger and the field-effect mobility can also be further enhanced when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high because the range in which carriers flow becomes wider. is W, and the film thickness of the semiconductor film 12 in the channel formation region 12a is T When the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which carriers flow becomes wider Therefore, the on-current of the transistor 10 can be made larger, and the field-effect mobility can also be further enhanced. When the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which carriers flow becomes wider Therefore, the on-current of the transistor 10 can be made larger, and the field-effect mobility can also be further enhanced.

[0049] And as described above, in the case of the transistor 10 using the thin-film semiconductor film 12, the aspect The aspect ratio is high enough to ensure a high degree of crystallinity in the semiconductor film 12. This is desirable. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12 specifically, it is desirable that the film thickness T is 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. Assuming that the value of the film thickness T is within the above range, considering that the resolution of the exposure apparatus when using a glass substrate is about several μm, the specific aspect ratio is desirably 0.05 or more and 10 or less, and more desirably 0.1 or more and 5 or less It is more desirable that the aspect ratio is 1 or more and 5 or less.

[0050] Also, the transistor 10 shown in FIGS. 3 and 4 is the same as the transistor 10 shown in FIGS. 1 and 2. Similarly, the conductive films 14 and 15 are connected to the side and upper portions of the semiconductor film 12 in the impurity regions 12b and 12c, respectively. Therefore, compared with the case where the conductive films 14 and 15 are connected only to the upper portion of the semiconductor film 12, the areas where the conductive films 14 and 15 are in contact with the impurity regions 12b and 12c can be ensured to be larger. Thus, the contact resistance between the conductive films 14 and 15 and the impurity regions 12b and 12c can be reduced, and as a result, the on-current of the transistor 10 can be increased.

[0051] Also, the transistor 10 shown in FIG. 4 is provided with a conductive film 20 that functions as a gate electrode (BG) on the back channel region side. In addition, the conductive film 20 is connected to the conductive film 17. This is the case. With the above configuration, in the transistor 10 shown in FIG. 4, the generation of fixed charges in the back channel region can be prevented, and the off-current can be reduced. Also, in the transistor 10 shown in FIG. 4, since the conductive film 20 is connected to the conductive film 17, the region where carriers move spans a wider range compared to the transistor 10 shown in FIG. 1, so the on-current can be increased. Also, in the transistor 10 shown in FIG. 4, since the conductive film 20 is connected to the conductive film 17, the region where carriers move spans a wider range compared to the transistor 10 shown in FIG. 1, so the on-current can be increased. Also, in the transistor 10 shown in FIG. 4, since the conductive film 20 is connected to the conductive film 17, the region where carriers move spans a wider range compared to the transistor 10 shown in FIG. 1, so the on-current can be increased. Also, in the transistor 10 shown in FIG. 4, since the conductive film 20 is connected to the conductive film 17, the region where carriers move spans a wider range compared to the transistor 10 shown in FIG. 1, so the on-current can be increased. Also, in the transistor 10 shown in FIG. 4, since the conductive film 20 is connected to the conductive film 17, the region where carriers move spans a wider range compared to the transistor 10 shown in FIG. 1, so the on-current can be increased.

[0052] Also, in the transistor 10 shown in FIG. 4, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Thus, since the top and bottom of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1. Also, in the transistor 10 shown in FIG. 4, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Thus, since the top and bottom of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1. Also, in the transistor 10 shown in FIG. 4, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Thus, since the top and bottom of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1. Also, in the transistor 10 shown in FIG. 4, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Thus, since the top and bottom of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1. Also, in the transistor 10 shown in FIG. 4, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap. Thus, since the top and bottom of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress compared to the transistor 10 shown in FIG. 1.

[0053] <Example Configuration 4 of Transistor> Note that, in the transistors 10 shown in FIGS. 2 and 4, the case where the conductive film 17 is connected to the conductive film 20 is illustrated. The transistor 10 according to one aspect of the present invention may have the conductive film 17 and the conductive film 20 electrically separated. Note that, in the transistors 10 shown in FIGS. 2 and 4, the case where the conductive film 17 is connected to the conductive film 20 is illustrated. The transistor 10 according to one aspect of the present invention may have the conductive film 17 and the conductive film 20 electrically separated. Note that, in the transistors 10 shown in FIGS. 2 and 4, the case where the conductive film 17 is connected to the conductive film 20 is illustrated. The transistor 10 according to one aspect of the present invention may have the conductive film 17 and the conductive film 20 electrically separated.

[0054] The transistor 10 shown in FIG. 5 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 and the conductive film 20 are electrically separated. FIG. 5(A) shows a plan view of the transistor 10. Note that, in FIG. 5(A), various insulating films are omitted to clarify the layout of the transistor 10. Also, FIG. 5(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 5(A). Also, in the plan view shown in FIG. 5(A), along the dashed line A1 - A2 The transistor 10 shown in FIG. 5 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 and the conductive film 20 are electrically separated. FIG. 5(A) shows a plan view of the transistor 10. Note that, in FIG. 5(A), various insulating films are omitted to clarify the layout of the transistor 10. Also, FIG. 5(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 5(A). Also, in the plan view shown in FIG. 5(A), along the dashed line A1 - A2 The transistor 10 shown in FIG. 5 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 and the conductive film 20 are electrically separated. FIG. 5(A) shows a plan view of the transistor 10. Note that, in FIG. 5(A), various insulating films are omitted to clarify the layout of the transistor 10. Also, FIG. 5(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 5(A). Also, in the plan view shown in FIG. 5(A), along the dashed line A1 - A2 The transistor 10 shown in FIG. 5 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 and the conductive film 20 are electrically separated. FIG. 5(A) shows a plan view of the transistor 10. Note that, in FIG. 5(A), various insulating films are omitted to clarify the layout of the transistor 10. Also, FIG. 5(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 5(A). Also, in the plan view shown in FIG. 5(A), along the dashed line A1 - A2 The transistor 10 shown in FIG. 5 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 and the conductive film 20 are electrically separated. FIG. 5(A) shows a plan view of the transistor 10. Note that, in FIG. 5(A), various insulating films are omitted to clarify the layout of the transistor 10. Also, FIG. 5(B) shows the circuit diagram symbol of the transistor 10 shown in FIG. 5(A). Also, in the plan view shown in FIG. 5(A), along the dashed line A1 - A2 The cross-sectional view is shown in FIG. 5(C), and the cross-sectional view taken along the dashed line B1 - B2 is shown in FIG. 5(D).

[0055] The transistor 10 shown in FIGS. 5(A), 5(C), and 5(D) has a conductive film 20 that functions as a gate electrode (BG) shown by the circuit diagram symbol in FIG. 5(B). Also, the transistor 10 has a function as a gate electrode (FG) shown by the circuit diagram symbol in FIG. 5(B), and further has a conductive film 17 that overlaps the side and upper portions of the semiconductor film 12 in the channel formation region 12a with the insulating film 13 interposed therebetween. And, as shown in FIGS. 5(A), 5(C), and 5 (D), the conductive film 17 and the conductive film 20 are electrically separated. The transistor 10 shown in FIG. 5 is also the same as the transistor 10 shown in FIGS. 2 and 4. By the side and upper portions of the semiconductor film 12 in the channel formation region 12a overlapping with the conductive film 17, carriers flow in a wide range including the side and upper portions of the channel formation region 12a. Therefore, while suppressing the reduction of the occupied area on the substrate in the channel formation region 12a of the semiconductor film 12, the amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 1

[0056] 0 increases and the field-effect mobility is enhanced. In particular, when the aspect ratio corresponding to the ratio of the film thickness T of the semiconductor film 12 in the channel formation region 12a to the channel width W (channel width) is high, since the range in which carriers flow becomes wider, the on-current of the transistor 1 0 can be made larger, and the field-effect mobility can also be further enhanced. 0 increases and the field-effect mobility is enhanced. In particular, when the aspect ratio corresponding to the ratio of the film thickness T of the semiconductor film 12 in the channel formation region 12a to the channel width W (channel width) is high, since the range in which carriers flow becomes wider, the on-current of the transistor 1 0 can be made larger, and the field-effect mobility can also be further enhanced. Let the length (channel width) in the channel width direction of the semiconductor film 12 in the channel formation region 12a be W, and the film thickness of the semiconductor film 12 in the channel formation region 12a be T. Then, when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, since the range in which carriers flow becomes wider, the on-current of the transistor 1 0 can be made larger, and the field-effect mobility can also be further enhanced. 0 can be made larger, and the field-effect mobility can also be further enhanced. When the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, since the range in which carriers flow becomes wider, the on-current of the transistor 1 0 can be made larger, and the field-effect mobility can also be further enhanced.

[0057] And, as described above, in the case of the transistor 10 using the semiconductor film 12 of the thin film, the aspect ratio is at a level that can ensure a high degree of crystallinity in the semiconductor film 12 which is desirable. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12 , specifically, it is desirable that the film thickness T is 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. Assuming that the value of the film thickness T is within the above range, considering that the resolution of the exposure apparatus when using a glass substrate is about several μm, specifically, the aspect ratio is desirably 0.05 or more and 10 or less, and more desirably 0.1 or more and 5 or less . Furthermore, it is more desirable that the aspect ratio is 1 or more and 5 or less .

[0058] Also, the transistor 10 shown in FIG. 5 is the same as the transistors 10 shown in FIGS. 2 and 4, and a conductive film 14 and a conductive film 15 are respectively connected to the side portions and the upper portion of the semiconductor film 12 in the impurity regions 12b and 12c. Therefore, compared with the case where the conductive films 14 and 15 are connected only to the upper portion of the semiconductor film 12, it is possible to ensure a larger area where the conductive films 14 and 15 are respectively in contact with the impurity regions 12b and 12c. Thus, the contact resistance between the conductive films 14 and 15 and the impurity regions 12b and 12c can be suppressed to be small, and as a result, the on-current of the transistor 10 can be increased.

[0059] Also, the transistor 10 shown in FIG. 5 has a gate electrode (BG) on the back channel region side, and A conductive film 20 is provided to function. Therefore, in the transistor 10 shown in FIG. 5, By supplying a predetermined potential to the conductive film 20, the generation of fixed charges in the back channel region is prevented, and the off-current can be reduced. Also, in the transistor 10 shown in FIG. 5, the threshold voltage of the transistor 10 can be controlled to a desired value by the potential supplied to the conductive film 17.

[0060] Also, in the transistor 10 shown in FIG. 5, a conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and a conductive film 17 is provided above the semiconductor film 12 so as to overlap. Therefore, since the top and bottom of the semiconductor film 12 are supported by the conductive films 17 and 20, the transistor 10 can be said to have higher strength against stress compared to the transistor 10 shown in FIG. 1.

[0061] Note that in FIG. 5, similar to the transistor 10 shown in FIG. 2, conductive films 14 and 15 that function as source electrodes or drain electrodes are provided on the insulating film 16, and at the opening of the insulating film 16, the conductive films 14 and 15 are connected to the impurity regions 12b and 12c, respectively, to illustrate the configuration of the transistor 10. However, in one aspect of the present invention, in the transistor 10 shown in FIG. 5, similar to the transistor 10 shown in FIG. 4, an insulating film 16 may be provided on the conductive films 14 and 15.

[0062] <Example Configuration 5 of Transistor> Next, a conductive film electrically connected to the conductive film 20 is provided in the same layer as the conductive film 17. The configuration of the transistor 10 is shown as an example in FIG. 6. In FIG. 6(A), the plan view of the transistor 10 is shown. In FIG. 6(A), for the sake of clarity of the layout of the transistor 10 various insulating films are omitted. Further, in FIG. 6(B), the circuit diagram symbol of the transistor 1 0 shown in FIG. 6(A) is shown. Also, the cross-sectional view of the plane view shown in FIG. 6(A) along the broken line A1 - A2 is shown in FIG. 6(C), and the cross-sectional view along the broken line B1 - B2 is shown in FIG. 6(D).

[0063] The transistor 10 shown in FIGS. 6(A), 6(C), and 6(D) has a conductive film 20 having a function as a gate electrode (BG) shown in the circuit diagram symbol of FIG. 6(B) on a substrate 11 having an insulating surface. Further, the transistor 10 has an insulating film 21 having a function as a gate insulating film and covering the conductive film 20. Also, the transistor 10 has a semiconductor film 12 that overlaps the conductive film 20 with the insulating film 2 1 interposed therebetween. The semiconductor film 12 has a channel formation region 12a, and impurity regions 12b and 12c that are positioned with the channel formation region 12a interposed therebetween. Further, the transistor 10 has an insulating film 13 that has a function as a gate insulating film and covers the side portions and the upper portion of the semiconductor film 12 in the channel formation region 12a. Also, the transistor 10 has a conductive film 17 having a function as a gate electrode (FG) shown in the circuit diagram symbol of FIG. 6(B) and overlapping the side portions and the upper portion of the semiconductor film 12 in the channel formation region 12a with the insulating film 13 interposed therebetween. Also, the transistor 10 has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 6(B) and covers the side portions and the upper portion of the semiconductor film 12 in the channel formation region 12a. Further, the transistor 10 has a conductive film 17 that has a function as a gate electrode (FG) shown in the circuit diagram symbol of FIG. 6(B) and overlaps the side portions and the upper portion of the semiconductor film 12 in the channel formation region 12a with the insulating film 13 interposed therebetween. Also, the transistor 10 has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 6(B) and overlaps the side portions and the upper portion of the semiconductor film 12 in the channel formation region 12a with the insulating film 13 interposed therebetween. Also, the transistor 10 has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 6(B) and has a function as a source electrode (S) or a drain electrode (D) shown in the circuit diagram symbol of FIG. 6(B), and overlaps the semiconductor film in the impurity regions 12b and 12c. A conductive film 14 and a conductive film 15 are respectively connected to the side and upper part of 12, and a conductive film 24 is connected to the conductive film 17. It has a conductive film 24 continued from the conductive film 17.

[0064] Also, in FIGS. 6(A), 6(C), and 6(D), an insulating film 16 is provided on the semiconductor film 12, the insulating film 13, and the conductive film 17, and the conductive film 14, the conductive film 15, and the conductive film 24 are provided on the insulating film 16. This is an example. And in the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film 15 are connected to the impurity regions 12b and 12c, and in the opening 25 provided in the insulating film 16, the conductive film 24 is connected to the conductive film 17. This is an example. An insulating film 16 is provided on the semiconductor film 12, the insulating film 13, and the conductive film 17, and the conductive film 14, the conductive film 15, and the conductive film 24 are provided on the insulating film 16. And in the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film 15 are connected to the impurity regions 12b and 12c, and in the opening 25 provided in the insulating film 16, the conductive film 24 is connected to the conductive film 17. In the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film 15 are connected to the impurity regions 12b and 12c, and in the opening 25 provided in the insulating film 16, the conductive film 24 is connected to the conductive film 17. In the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film 15 are connected to the impurity regions 12b and 12c, and in the opening 25 provided in the insulating film 16, the conductive film 24 is connected to the conductive film 17. In the openings 18 and 19 provided in the insulating film 16, the conductive film 14 and the conductive film 15 are connected to the impurity regions 12b and 12c, and in the opening 25 provided in the insulating film 16, the conductive film 24 is connected to the conductive film 17.

[0065] Also, in FIGS. 6(A), 6(C), and 6(D), the openings 28 and 29 are provided at positions facing each other with the semiconductor film 12 interposed therebetween. This is an example.

[0066] Also, in FIGS. 6(A), 6(C), and 6(D), in the same layer as the conductive film 17, specifically, on the insulating film 13, there are a conductive film 26 and a conductive film 27. The conductive film 26 and the conductive film 27 are continued to the conductive film 20 in the openings 28 and 29 of the insulating film 13 and the insulating film 21. On the insulating film 13, there are a conductive film 26 and a conductive film 27. In the openings 28 and 29 of the insulating film 13 and the insulating film 21, the conductive film 26 and the conductive film 27 are continued to the conductive film 20. They are continued to the conductive film 20.

[0067] As shown in FIG. 6, in the transistor 10 according to one aspect of the present invention, in the channel formation region 12a, the side and upper parts of the semiconductor film 12 overlap with the conductive film 17, so that carriers flow in a wide range including the side and upper parts of the channel formation region 12a. Therefore, while suppressing the occupied area on the substrate in the channel formation region 12a of the semiconductor film 12 to be small, the transistor In the channel formation region 12a, the side and upper parts of the semiconductor film 12 overlap with the conductive film 17, so that carriers flow in a wide range including the side and upper parts of the channel formation region 12a. In the channel formation region 12a, the side and upper parts of the semiconductor film 12 overlap with the conductive film 17, so that carriers flow in a wide range including the side and upper parts of the channel formation region 12a. In the channel formation region 12a of the semiconductor film 12, while suppressing the occupied area on the substrate to be small, the transistor The amount of carrier movement in the resistor 10 increases, and as a result, the on-current of the transistor 10 increases and the field-effect mobility is enhanced. In particular, in the channel formation region 12a if the length (channel width) in the channel width direction of the semiconductor film 12 is W and the film thickness of the semiconductor film 12 in the channel formation region 12a is T, when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which carriers flow becomes wider, so the on-current of the transistor 10 can be made larger and the field-effect mobility can also be enhanced more. And, as described above, in the case of the transistor 10 using the thin-film semiconductor film 12, the aspect

[0068] ratio is desirably high enough to ensure a high degree of crystallinity in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12, specifically, the film thickness T is desirably 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 100 nm or less. Assuming that the value of the film thickness T is within the above range and considering that the resolution of the exposure apparatus when using a glass substrate is about several μm, specifically, the aspect ratio is desirably 0.05 or more and 10 or less, and more desirably 0.1 or more and 5 or less. Further, it is more desirable that the aspect ratio is 1 or more and 5 or less.

[0069] Also, as shown in FIG. 6, in the transistor 10 according to one aspect of the present invention, on the side and upper portions of the semiconductor film 12 in the impurity region 1 2b and the impurity region 12c, conductive films 14 and conductive The films 15 are each connected. Therefore, compared with the case where the conductive film 14 and the conductive film 15 are connected only to the upper part of the semiconductor film 12 , it is possible to ensure a larger area where the conductive film 14 and the conductive film 15 are in contact with the impurity regions 12 b and the impurity region 12c, respectively. Thus, the contact resistance between the conductive film 14 and the conductive film 15 and the impurity regions 12b and 12c can be suppressed to be small, and as a result, the on-current of the transistor 10 can be increased.

[0070] Also, in the transistor 10 shown in FIG. 6, a conductive film 20 that functions as a gate electrode (BG) is provided on the back channel region side. Therefore, in the transistor 10 shown in FIG. 6 , by supplying a predetermined electric potential to the conductive film 20 via the conductive film 26 or the conductive film 27 connected to the conductive film 20, generation of fixed charges in the back channel region can be prevented, and the off-current can be made small . Also, in the transistor 10 shown in FIG. 6, the threshold voltage of the transistor 10 can be controlled to a desired value by the electric potential supplied to the conductive film 17.

[0071] Also, in the transistor 10 shown in FIG. 6, the conductive film 20 is provided below the semiconductor film 12 so as to overlap at least the channel formation region 12a, and the conductive film 17 is provided above the semiconductor film 12 so as to overlap the channel formation region 12a. Therefore, since the upper and lower parts of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress than the transistor 10 shown in FIG. 1.

[0072] <Example Configuration 6 of Transistor> Note that in the transistor 10 shown in FIG. 2, the semiconductor film 12 is sandwiched therebetween and is provided at positions facing each other In the formed openings 22 and 23, the conductive film 17 is connected to the conductive film 20 is illustrated. The transistor 10 according to one aspect of the present invention may have the conductive film 17 connected to the conductive film 20 at an opening existing on one side of the semiconductor film 12

[0073] The transistor 10 shown in FIG. 7 is different in configuration from the transistor 10 shown in FIG. 2 in that the conductive film 17 is connected to the conductive film 20 at the opening 22 existing on one side of the semiconductor film 12 FIG. 7(A) shows a plan view of the transistor 10. In FIG. 7(A), various insulating films are omitted to clarify the layout of the transistor 10. Further FIG. 7(B) shows a circuit diagram symbol of the transistor 10 shown in FIG. 7(A). Also, a cross-sectional view taken along the broken line A1 - A2 in the plan view shown in FIG. 7(A) is shown in FIG. 7(C), and a cross-sectional view taken along the broken line B1 - B2 is shown in FIG. 7(D)

[0074] Specifically, in the transistor 10 shown in FIGS. 7(A), 7(C), and 7(D), at the opening 22 of the insulating film 13 and the insulating film 21, the conductive film 17 having a function as a gate electrode (FG) shown in the circuit diagram symbol of FIG. 7(B) is connected to the conductive film 20 having a function as a gate electrode (BG) shown in the circuit diagram symbol of FIG. 7(B)

[0075] Note that in FIG. 7, similar to the transistor 10 shown in FIG. 2, the conductive films 14 and 15 functioning as a source electrode or a drain electrode are provided on the insulating film 16, and at the opening of the insulating film 16 the configuration of the transistor 10 in which the conductive films 14 and 15 are respectively connected to the impurity regions 12b and 12c is illustrated. However, in the present invention ​​​​​​​​​In one aspect of the disclosure, in the transistor 10 shown in FIG. 7, similar to the transistor 10 shown in FIG. 4, Similarly, an insulating film 16 may be provided on the conductive film 14 and the conductive film 15.

[0076] Similar to the transistor 10 shown in FIGS. 1 and 2, in the transistor 10 shown in FIG. 7, carriers flow in a wide range including the side and upper portions of the semiconductor film 12 in the channel formation region 12a and the conductive film 17 overlap. Therefore, while suppressing the occupied area on the substrate in the channel formation region 12a of the semiconductor film 12 to a small value, the amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 10 increases and the field-effect mobility is enhanced. In particular, when the length (channel width) in the channel width direction of the semiconductor film 12 in the channel formation region 12a is W and the film thickness of the semiconductor film 12 in the channel formation region 12a is T, when the aspect ratio corresponding to the ratio of the film thickness T to the channel width W is high, the range in which carriers flow becomes wider. Therefore, the on-current of the transistor 10 can be made larger and the field-effect mobility can also be enhanced more. And, as described above, in the case of the transistor 10 using the thin-film semiconductor film 12, it is desirable that the aspect ratio is at a height that can ensure a high degree of crystallinity in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12, specifically, it is desirable that the film thickness T is 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. Assuming that the value of the film thickness T is within the above range, the range in which carriers flow becomes wider. Therefore, the on-current of the transistor 10 can be made larger and the field-effect mobility can also be enhanced more. And, as described above, in the case of the transistor 10 using the thin-film semiconductor film 12, it is desirable that the aspect ratio is at a height that can ensure a high degree of crystallinity in the semiconductor film 12.

[0077] And, as described above, in the case of the transistor 10 using the thin-film semiconductor film 12, the aspect ratio is at a height that can ensure a high degree of crystallinity in the semiconductor film 12. When the semiconductor film 12 contains silicon, or when the semiconductor film 12 contains silicon and germanium, considering ensuring a high degree of crystallinity of the semiconductor film 12, specifically, it is desirable that the film thickness T is 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. Assuming that the value of the film thickness T is within the above range, it is desirable that the film thickness T is 5 nm or more and 150 nm or less, and more desirably 20 nm or more and 1 00 nm or less. And, assuming that the value of the film thickness T is within the above range, Considering that the resolution of the exposure apparatus when using a glass substrate is about several micrometers, Specifically, the aspect ratio is desirably 0.05 or more and 10 or less, and more desirably 0.1 or more and 5 or less. Furthermore, it is more desirable that the aspect ratio is 1 or more and 5 or less.

[0078] Also, the transistor 10 shown in FIG. 7 is the same as the transistor 10 shown in FIGS. 1 and 2. On the side and upper portions of the semiconductor film 12 in the impurity region 12b and the impurity region 12c, the conductive films 14 and the conductive film 15 are respectively connected. Therefore, compared with the case where the conductive films 14 and 15 are connected only to the upper portion of the semiconductor film 12, the areas where the conductive films 14 and 15 are in contact with the impurity region 12b and the impurity region 12c can be ensured to be larger. Thus, the contact resistance between the conductive films 14 and 15 and the impurity region 12b and the impurity region 12 c can be suppressed to be small, and as a result, the on-current of the transistor 10 can be increased.

[0079] Also, the transistor 10 shown in FIG. 7 is the same as the transistor 10 shown in FIG. 2, and a conductive film 20 that functions as a gate electrode (BG) is provided on the back-channel region side. Note that and the conductive film 20 is connected to the conductive film 17. With the above configuration, in the transistor 10 shown in FIG. 7, the generation of fixed charges in the back-channel region can be prevented, and the off-current can be reduced. In addition, in the transistor 10 shown in FIG. 7, since the conductive film 20 is connected to the conductive film 17, compared with the transistor 10 shown in FIG. 1, the region where carriers move spans a wider range, so the on-current can be made larger.

[0080] ​​​​Also, in the transistor 10 shown in FIG. 7, at least overlapping the channel formation region 12a, a conductive film 20 is provided below the semiconductor film 12, and a conductive film 17 is provided above the semiconductor film 12 so as to overlap the channel formation region 12a. Therefore, since the upper and lower portions of the semiconductor film 12 are supported by the conductive film 17 and the conductive film 20, it can be said that the transistor 10 has higher strength against stress than the transistor 10 shown in FIG. 1. Between the transistor 10 and the substrate 11 shown in FIGS. 1 to 7, various semiconductor elements may be provided. In this case, the transistor 10 may be provided on an insulating film covering the semiconductor element.

[0081]

[0082] Also, in the transistor 10 shown in FIGS. 1 to 7, the state where the conductive films 14 and 15 are connected to the impurity regions 12b and 12c does not only mean the state where the conductive films 14 and 15 are in direct contact with the impurity regions 12b and 12c. For example, a state where an insulating film such as a natural oxide film having a film thickness small enough to ensure electrical connection is provided between the conductive films 14 and 15 and the impurity regions 12b and 12c is also included in the connected state.

[0083] Also, in the transistor 10 shown in FIGS. 1 to 7, in addition to the channel formation region 12a, the impurity regions 12b and 12c, the semiconductor film 12 may have a lightly doped drain (LDD) region containing an impurity for imparting one conductivity type to the semiconductor at a lower concentration than the impurity regions 12b and 12c. The LDD region is ​​​​​​​​​​​​​Between the region 12a and the impurity region 12b, or between the impurity region 12c and the channel formation region 1 can be provided.

[0084] In addition, in the transistor 10 shown in FIGS. 1 to 7, a cross-sectional view in the channel length direction, that is, the cross-sectional view along the broken line A1 - A2, illustrates a case where the boundary between the channel formation region 12a and the impurity regions 12b and 12c overlaps with the end of the conductive film 17. However, in one aspect of the present invention, the boundary between the channel formation region 12a and the impurity region 12b, or the boundary between the channel formation region 12a and the impurity region 12c may be positioned so as to overlap with the conductive film 17. In this case, a part of the impurity region 12b or a part of the impurity region 12c overlaps with the conductive film 17 with the insulating film 13 interposed therebetween. Alternatively, in one aspect of the present invention, the end of the conductive film 17 may be positioned so as to overlap with the channel formation region 12a. In this case, a part of the channel formation region 12a does not overlap with the conductive film 17 with the insulating film 13 interposed therebetween. Also, when the LDD region is provided in the semiconductor film 12, a part of the LDD region may overlap with the conductive film 17 with the insulating film 13 interposed therebetween. formation region 12a may overlap with the conductive film 17 with the insulating film 13 interposed therebetween. Also, when the LDD region is provided in the semiconductor film 12, a part of the LDD region may overlap with the conductive film 17 with the insulating film 13 interposed therebetween.

[0085] <Example Configuration 7 of Transistor> Next, a plan view of a plurality of transistors 10 when the transistors 10 shown in FIG. 2 are connected in series is shown as an example in FIG. 8.

[0086] In this specification, the state where transistors are connected in series means, for example, a state where only one of the source and drain of the first transistor is connected to only one of the source and drain of the second transistor. Also, the state where transistors are connected in parallel ​​​​​​​The state in which one of the source and drain of the first transistor is connected to one of the source and drain of the second transistor, and the other of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor is meant. Specifically, in FIG. 8, three transistors 10 shown by transistors 10a to 10c are shown to be connected in series. However, in FIG. 8, various insulating films are omitted in order to clarify the layout of the transistors 10. Transistors 10a to 10c share a semiconductor film 12. And, .

[0087] Transistor 10a has a conductive film 30 and a conductive film 31 that function as a source electrode or a drain electrode. Transistor 10b has a conductive film 31 and a conductive film 32 that function as a source electrode or a drain electrode. Transistor 10c has a conductive film 32 and a conductive film 33 that function as a source electrode or a drain electrode. Each of the conductive films 30 to 33 corresponds to either one of the conductive film 14 and the conductive film 15 that the transistor 10 shown in FIG. 2 has. And, the conductive film 17a that functions as the gate electrode of the transistor 10a is connected to the conductive film 20 that functions as the gate electrode (BG) through the opening 18a and the opening 19a. Also, the conductive film 17b that functions as the gate electrode of the transistor 10b is connected to the conductive film 20 that functions as the gate electrode (BG) through the opening 18b and the opening 19b. Also, the conductive film 17c that functions as the gate electrode of the transistor 10c is an opening 。

[0088] 。 。 。 。 。 。 。

[0089] 。 。 。 。 。 It is connected to a conductive film 20 that functions as a gate electrode (BG) through a portion 18c and an opening 19c. It is continued.

[0090] Fig. 9 shows a perspective view of the transistors 10a to 10c shown in Fig. 8. However, in Fig. 9, in order to clarify the shapes of the transistors 10a to 10c, among the insulating films that function as gate insulating films, the portions respectively existing between the conductive films 17a to 17c and the semiconductor film 1 2 are shown as insulating films 13a to 13c, and various insulating films other than the insulating films 13a to 13c are omitted. Also, in Fig. 9, the conductive films 30 to 33 are omitted.

[0091] In addition, in Figs. 8 and 9, the case where the conductive films 17a to 17c respectively included in the transistors 10a to 10c connected in series are all connected to the conductive film 20 is illustrated, but the conductive films 17a to 17c may be respectively connected to a plurality of conductive films 20 that are electrically separated from each other.

[0092] <Fabrication method> Next, taking a transistor 10N having the same structure as the transistor 10 shown in Fig. 2 and being an n-channel type, and a transistor 10P having the same structure as the transistor 10 shown in Fig. 2 and being a p-channel type as examples, the specific fabrication method of the transistor 10 will be described with reference to Figs. 10 to 13. In Figs. 10 to 13, the cross-sectional view in the channel length direction of the region where the transistor 10P is formed is shown within the range of the broken line C1 - C2, and the cross-sectional view in the channel length direction of the region where the transistor 10N is formed is shown by the broken line ​​​​​​The cross-sectional view in the channel width direction is shown within the range of dashed line C5-C6. show.

[0093] First, as shown in FIG. 10(A), an insulating film 301 is formed on a heat-resistant substrate 300. Then, a conductive film 302 and a conductive film 303 which function as a gate electrode (BG) are formed on the insulating film 301. Form on top.

[0094] The substrate 300 is preferably a substrate having heat resistance sufficient to withstand the subsequent manufacturing steps. For example, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, etc. may be used.

[0095] The insulating film 301 is formed by removing the alkali metals and alkaline earth metals contained in the substrate 300 from the insulating film 301. The diffusion of the semiconductor film 306 and the semiconductor film 307 into the transistor 10P and The insulating film 30 has a function of preventing the insulating film 30 from adversely affecting the electrical characteristics of the transistor 10N. 1 is a silicon oxide, silicon nitride, silicon oxynitride, nitride, etc., which are produced by using a CVD method, a sputtering method, etc. The insulating film is formed using an insulating material such as silicon dioxide.

[0096] The conductive films 302 and 303 may be made of aluminum, titanium, chromium, cobalt, or nickel. Copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum and titanium When a film made of a conductive material containing one or more kinds of tungsten is used, one or more layers are laminated. For example, a copper film may be stacked on a tungsten nitride film as the conductive film 302 and the conductive film 303. A conductive film having a layered structure or a single layer of tungsten film can be used. The film 302 and the conductive film 303 are made of tungsten films with a thickness of 200 nm. .

[0097] Next, as shown in FIG. 10(B), an insulating film 304 is formed on the conductive film 302 and the conductive film 303, and after that, a semiconductor film 305 is formed on the insulating film 304.

[0098] The insulating film 304 is formed using a method such as plasma CVD or sputtering, as a single layer or a laminated film containing silicon nitride, silicon oxide, silicon oxynitride or silicon nitride oxide. When laminating, for example, it is preferable to have a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the substrate 300 side.

[0099] It is desirable to form the semiconductor film 305 without exposing it to the atmosphere after forming the insulating film 304. The film thickness of the semiconductor film 305 is preferably 5 nm or more and 150 nm or less, more preferably 20 nm or more and 100 nm or less. Note that the semiconductor film 305 may be an amorphous semiconductor or a polycrystalline semiconductor. Also, not only silicon but also silicon germanium can be used as the semiconductor. When using silicon germanium, the concentration of germanium is preferably about 0.01 atomic% or more and 4.5 atomic% or less.

[0100] The semiconductor film 305 may be crystallized by various techniques. Various crystallization methods include a laser crystallization method using laser light and a crystallization method using a catalyst element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method can be combined and used. Also, when using a substrate with excellent heat resistance such as quartz as the substrate 300, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalyst element, or a crystallization method combining a high-temperature annealing at about 950°C can be used.

[0101] ​​​​​ Note that channel doping may be performed by adding an impurity element that imparts a p-type or an impurity element that imparts an n-type to the semiconductor film 305 at a low concentration. As the impurity element that imparts a p-type, boron (B), aluminum (Al), gallium (Ga), etc. can be used. As the impurity element that imparts an n-type, phosphorus (P), arsenic (As), etc. can be used. For example, when boron (B) is used as the impurity element, the boron is 1×10 atom s / cm 16 atom s / cm 3 or more and 5×10 17 atoms / cm 3 or less, and channel doping is performed so that it is contained in the semiconductor film 305.

[0102] Next, as shown in FIG. 11(A), the shape of the semiconductor film 305 is processed by etching or the like, and island-shaped semiconductor films 306 and 307 are formed on the insulating film 304. The semiconductor film 306 overlaps the conductive film 302 with the insulating film 304 interposed therebetween, and the semiconductor film 307 overlaps the conductive film 303 with the insulating film 304 interposed therebetween.

[0103] Next, as shown in FIG. 11(B), an insulating film 308 is formed so as to cover the semiconductor films 306 and 307. The insulating film 308 can be formed by using a plasma CVD method or a sputtering method, and a film containing silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide is formed as a single layer or by laminating. When laminating, for example, it is preferable to have a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the substrate 300 side.

[0104] The insulating film 308 is subjected to high-density plasma treatment to form the semiconductor films 306 and 30 ​​​It may be formed by oxidizing or nitriding the surface of 7. High-density plasma treatment is, for example, H e, Ar, Kr, Xe and other noble gases and oxygen, nitrogen oxides, ammonia, nitrogen, hydrogen and other mixed gases. In this case, by exciting the plasma by introducing microwaves, a high-density plasma can be generated at a low electron temperature. With such a high-density plasma generated oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals ), the surface of the semiconductor film is oxidized or nitrided, so that an insulating film with a thickness of 1n m or more and 20 nm or less, typically 5 nm or more and 10 nm or less, is formed in contact with the semiconductor film. This insulating film with a thickness of 5 nm or more and 10 nm or less is used as the insulating film 308.

[0105] Since the oxidation or nitridation of the semiconductor film by the above-mentioned high-density plasma treatment proceeds by a solid-phase reaction, the interface state density between the gate insulating film and the semiconductor film can be made extremely low. Also, by directly oxidizing or nitriding the semiconductor film by high-density plasma treatment, the thickness variation of the formed insulating film can be suppressed. Further, when the semiconductor film has crystallinity, by oxidizing the surface of the semiconductor film by a solid-phase reaction using high-density plasma treatment, the oxidation that proceeds rapidly only at the crystal grain boundaries can be suppressed, and a gate insulating film with good uniformity and a low interface state density can be formed. A transistor formed by including the insulating film formed by high-density plasma treatment in part or all of the gate insulating film can suppress the variation in characteristics.

[0106] Next, as shown in Fig. 12(A), after forming a conductive film on the insulating film 308, the conductive film ​​​​​​​​By processing (patterning) into a predetermined shape, an island-shaped semiconductor film 306 and a semiconductor film 30 A conductive film 309 and a conductive film 310 are formed above 7. The conductive film 309 and the conductive film 3 Thus, a film made of a conductive material containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten may be laminated and used in one or more layers. For the formation of the conductive film 309 and the conductive film 3 10, a CVD method, a sputtering method, or the like can be used.

[0107] Next, as shown in FIG. 12(B), a resist 311 is formed so as to cover the semiconductor film 306. Using the resist 311 and the conductive film 310 as masks, an impurity element (typically P or As) for imparting an n-type is added to the semiconductor film 307. The addition of the above impurity element is, for example, When the concentration of impurities contained in the semiconductor film 307 is 1×10 atoms / cm 19 or more and 1×1 3 0 atoms / cm 20 or less, it can be performed by an ion implantation method with an acceleration voltage of 60 keV or more and 100 keV 3 or less. By the addition of the above impurities, a pair of impurity regions 312 are formed in the semiconductor film 307.

[0108] Next, as shown in FIG. 13(A), a resist 313 is formed so as to cover the semiconductor film 307. Using the resist 313 and the conductive film 309 as masks, an impurity element (typically B) for imparting a p-type is added to the semiconductor film 306. The addition of the above impurity element is, for example, when the concentration of impurities contained in the semiconductor film 30 6 is 1×10 atoms / cm 19 or more and 1×10 3 atoms / cm 20 or more, 1×10 mS / cm 3 As follows, the acceleration voltage can be set to 20 keV or more and 40 keV or less, and ions can be implanted. By adding the above impurities, a pair of impurity regions 314 are formed in the semiconductor film 306. As follows, the acceleration voltage can be set to 20 keV or more and 40 keV or less, and ions can be implanted. By adding the above impurities, a pair of impurity regions 314 are formed in the semiconductor film 306. are formed.

[0109] Next, as shown in Fig. 13(B), an insulating film 320 is formed to cover the substrate 300, and then an opening is formed in the insulating film 320. Thereafter, a conductive film 321 that contacts the impurity region 312 at the opening and a conductive film 322 that contacts the impurity region 314 at the opening are formed. Next, as shown in Fig. 13(B), an insulating film 320 is formed to cover the substrate 300, and then an opening is formed in the insulating film 320. Thereafter, a conductive film 321 that contacts the impurity region 312 at the opening and a conductive film 322 that contacts the impurity region 314 at the opening are formed. are formed.

[0110] The insulating film 320 is formed by a single layer or a stack of films containing silicon films, silicon oxide films, silicon oxynitride films, silicon nitride oxide films, or organic materials such as organic resins by a plasma CVD method, a sputtering method, or the like. In this embodiment, a silicon oxide film with a thickness of 100 nm is formed by a plasma CVD method. The insulating film 320 is formed by a single layer or a stack of films containing silicon films, silicon oxide films, silicon oxynitride films, silicon nitride oxide films, or organic materials such as organic resins by a plasma CVD method, a sputtering method, or the like. In this embodiment, a silicon oxide film with a thickness of 100 nm is formed by a plasma CVD method. method. method.

[0111] As the conductive films 321 and 322, a film made of a conductive material containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten is used by laminating one layer or two or more layers. As the conductive films 321 and 322, a film made of a conductive material containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten is used by laminating one layer or two or more layers. is good. is good.

[0112] Next, activation by heat treatment of the impurity region may be performed. For example, the above activation can be carried out by performing heat treatment at 550 °C for 4 hours in a nitrogen atmosphere. Next, activation by heat treatment of the impurity region may be performed. For example, the above activation can be carried out by performing heat treatment at 550 °C for 4 hours in a nitrogen atmosphere.

[0113] Also, after forming a silicon nitride film containing hydrogen to a thickness of 100 nm, heat treatment is performed at 410 °C for 1 hour in a nitrogen atmosphere to hydrogenate the semiconductor film 306 and the semiconductor film 307. is performed. It may be processed. Or, in an atmosphere containing hydrogen, at 300 °C or higher and 450 °C or lower perform a heat treatment for 1 hour or more and 12 hours or less to hydrogenate the semiconductor film 306 and the semiconductor film 307 The heat treatment may be performed. For the heat treatment, thermal annealing, laser annealing method or RTA method or the like can be used. By the heat treatment, not only hydrogenation but also activation of impurity elements added to the semiconductor film can be performed. Also, as another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. By this hydrogenation process, dangling bonds can be terminated by thermally excited hydrogen. By the above-described series of processes, a p-channel transistor 10P and an n-channel transistor 10N are formed. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. In this case, as the plastic substrate, polyethylene terephthalate (PET) is representative

[0114] By the above-described series of processes, a p-channel transistor 10P and an n-channel transistor 10N are formed.

[0115] Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned. Note that the transistor 10P and the transistor 10N manufactured using the above method may be transferred onto a separately prepared flexible substrate such as plastic. To transfer the semiconductor element to another substrate, various methods can be used. For example, a method of providing a metal oxide film between the substrate and the semiconductor element, weakening the metal oxide film by crystallization to peel off the semiconductor element and transfer it, a method of providing an amorphous silicon film containing hydrogen between the substrate and the semiconductor element, and removing the amorphous silicon film by irradiation with a laser beam or etching to peel off and transfer the substrate and the semiconductor element, a method of mechanically removing the substrate on which the semiconductor element is formed or removing it by etching with a solution or gas to cut off the semiconductor element from the substrate and transfer it, etc. can be mentioned.

[0116] In this case, as the plastic substrate, polyethylene terephthalate (PET) is representative​ polyesters, polyethersulfone (PES), polyethylene naphthalate (PEN ), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene sty rene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc. are mentioned.

[0117] <Configuration Example of Semiconductor Display Device> Next, a configuration example of a semiconductor display device corresponding to one form of the semiconductor device of the present invention will be described. do.

[0118] In the semiconductor display device 70 shown in Fig. 14(A), the pixel portion 71 includes a plurality of pixels 55 and a pixel 5 5 for each row, wiring GL1 to wiring GLy (y is a natural number of 2 or more) shown by wiring GL, and wiring SL1 to wiring S Lx (x is a natural number of 2 or more) shown by wiring SL for supplying an image signal to the selected pixel 55. The supply of the signal to wiring GL is controlled by the scan line drive circuit 72. The supply of the image signal to wiring SL is controlled by the signal line drive circuit 73. The plurality of pixels 55 are each connected to at least one of wiring GL and at least one of wiring SL.

[0119] Note that the type and number of wiring provided in the pixel portion 71 can be determined according to the configuration, number, and arrangement of the pixels 55. Specifically, in the case of the pixel portion 71 shown in Fig. 14(A), the pixels 55 of x columns × y rows are arranged in a matrix, and wiring SL1 to wiring SLx, wiring GL1 to wiring GLy are provided. Even when the wiring GLy is disposed within the pixel portion 71, this is illustrated as an example.

[0120] In addition, in FIG. 14(A), the case where the scanning line driving circuit 72 and the signal line driving circuit 73 are formed on the same substrate as the pixel portion 71 is illustrated. However, part or all of the signal line driving circuit 73 may be formed on a substrate different from the pixel portion 71. The transistor 10 shown in FIGS. 1 to 7 can be used for the scanning line driving circuit 72, the signal line driving circuit 73, or the pixel portion 71. ... ... ... ...

[0121] Also, FIG. 14(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a pixel electrode, a common electrode, and a liquid crystal layer containing a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. ... ... ... ...

[0122] The transistor 56 controls whether to apply the potential of the wiring SL to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60. ...

[0123] Hereinafter, the specific connection configuration of the transistor 56 and the liquid crystal element 60 will be described. In FIG. 14(B), the gate of the transistor 56 is connected to any one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to any one of the wirings SL1 to SLx, and the other of the source and drain of the transistor 56 is connected to the pixel electrode of the liquid crystal element 60. ... ... ... ...

[0124] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance is controlled by the potential of the image signal applied to the In each of the plurality of pixels 55 included in the pixel section 71, the liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, and an image is displayed on the pixel section 71. is displayed.

[0125] In FIG. 14B, a pixel 55 has a switch that controls the supply of an image signal to the pixel 55. However, the case where one transistor 56 is used as a switch is shown. A plurality of transistors may be used in pixel 55, each of which functions in the same way.

[0126] The transistor 10 shown in FIGS. 1 to 7 can have a large on-state current. 1 to 7 is used as the transistor 56, the pixel 5 Since the image signal can be supplied to the pixel 55 at high speed, the image quality of the pixel 55 can be improved. 2 and 4 to 7 can reduce the off-state current. Therefore, the transistor 10 shown in FIGS. 2 and 4 to 7 can be used as the transistor 56. By using the transistor 56 as a gate, it is possible to prevent leakage of electric charge through the transistor 56. The potential of the image signal applied to the crystal element 60 and the capacitance element 57 can be more reliably maintained. As a result, the transmittance of the liquid crystal element 60 changes due to the leakage of electric charges within one frame period. This prevents the image from changing, thereby improving the quality of the displayed image.

[0127] Next, FIG. 14(C) shows another example of the pixel 55. The pixel 55 includes a transistor 95 that controls the supply of an image signal to the pixel 55, a light-emitting element 98, a transistor 96 that controls the current value supplied to the light-emitting element 98 according to the image signal, and a capacitor element 97 for holding the potential of the image signal. The light-emitting element 98 includes, within its scope, elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or multiple layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting substance among these layers. Furthermore, when the potential difference between the cathode and the anode becomes equal to or greater than the threshold voltage of the light-emitting element 98, electroluminescence is obtained by the current supplied. Electroluminescence includes luminescence (fluorescence) when returning from the singlet excited state to the ground state and luminescence (phosphorescence) when returning from the triplet excited state to the ground state. One of the anode and the cathode of the light-emitting element 98 has its potential controlled according to the image signal supplied to the pixel 55. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode.

[0128] The light-emitting element 98 includes, within its scope, elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or multiple layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting substance among these layers. Furthermore, when the potential difference between the cathode and the anode becomes equal to or greater than the threshold voltage of the light-emitting element 98, electroluminescence is obtained by the current supplied. Electroluminescence includes luminescence (fluorescence) when returning from the singlet excited state to the ground state and luminescence (phosphorescence) when returning from the triplet excited state to the ground state. One of the anode and the cathode of the light-emitting element 98 has its potential controlled according to the image signal supplied to the pixel 55. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. The light-emitting element 98 includes, within its scope, elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or multiple layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting substance among these layers.

[0129] Furthermore, when the potential difference between the cathode and the anode becomes equal to or greater than the threshold voltage of the light-emitting element 98, electroluminescence is obtained by the current supplied. Electroluminescence includes luminescence (fluorescence) when returning from the singlet excited state to the ground state and luminescence (phosphorescence) when returning from the triplet excited state to the ground state. One of the anode and the cathode of the light-emitting element 98 has its potential controlled according to the image signal supplied to the pixel 55. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. The light-emitting element 98 includes, within its scope, elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or multiple layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting substance among these layers.

[0130] One of the anode and the cathode of the light-emitting element 98 has its potential controlled according to the image signal supplied to the pixel 55. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. is determined by the potential difference. Therefore, the light-emitting element 98 can display gradations by controlling its luminance according to the potential of the image signal. Then, in each of the plurality of pixels 55 included in the pixel portion, the gradation of the light-emitting element 98 is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. By being controlled, gradations can be displayed. And in each of the plurality of pixels 55 that the pixel portion has, since the gradation of the light-emitting element 98 is adjusted according to the image signal having the image information, an image is displayed on the pixel portion 71.

[0131] Next, the connection configuration of the transistor 95, the transistor 96, the capacitor element 97, and the light-emitting element 98 included in the pixel 55 will be described.

[0132] One of the source or drain of the transistor 95 is connected to the wiring SL, and the other of the source or drain is connected to the gate of the transistor 96. The gate of the transistor 95 is connected to the wiring GL. One of the source or drain of the transistor 96 is connected to the power supply line VL, and the other of the source or drain is connected to the light-emitting element 98. Specifically, the other of the source or drain of the transistor 96 is connected to either the anode or the cathode of the light-emitting element 98. A predetermined potential is applied to the other of the anode and the cathode of the light-emitting element 98.

[0133] (The transistor 10 shown in FIGS. 1 to 7 can increase the on-current. Therefore, by using the transistor 10 shown in FIGS. 1 to 7 as the transistor 95, the supply of the image signal to the pixel 55 can be performed at high speed, so that the image quality of the pixel 55 can be improved. Also, the transistor 10 shown in FIGS. 2, 4 to 7 can decrease the off-current. Therefore, by using the transistor 10 shown in FIGS. 2, 4 to 7 as the transistor 95, the supply of the image signal to the pixel 55 can be performed at high speed, so that the image quality of the pixel 55 can be improved. Also, the transistor 10 shown in FIGS. 2, 4 to 7 can decrease the off-current. Therefore, by using the transistor 10 shown in FIGS. 2, 4 to 7 as the transistor 95, ​​​​​​​​​​By being used in this way, it is possible to prevent charge from leaking through the transistor 95, and the potential of the image signal applied to the capacitance element 97 can be more reliably held. As a result, it is possible to prevent the luminance of the light-emitting element 98 from changing due to charge leakage within one frame period, and thereby improve the quality of the displayed image.

[0134] For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or have various elements. As an example of the display element, the display device, the light-emitting element, or the light-emitting device, there are an EL (electroluminescence) element (including an organic and an inorganic EL element, an organic EL element, an inorganic EL element), an LED (such as a white LED, a red LED, a green LED, a blue LED ), a transistor (a transistor that emits light according to current), an electron-emitting element, a liquid crystal element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a MEMS (micro-electro-mechanical system), a digital micro mirror device (DMD), a DMS (digital micro shutter), an IMO D (interference modulation) element, an electro-wetting element, a piezoelectric ceramic display, a carbon nanotube, etc., which have a display medium whose contrast, luminance, reflectance, transmittance, etc. change due to an electromagnetic action. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there is a field emission display (FED) or an SED ​​​​​There are, for example, surface-conduction electron-emitter displays (SEDs). As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), and the like. As an example of a display device using electronic ink or an electrophoretic element, there is electronic paper, and the like.

[0135] <Pixel Configuration> Next, taking a light-emitting device, which is one of the semiconductor display devices 70 shown in FIG. 14(A), as an example, a configuration example of the pixel 55 will be described. FIG. 15 shows a top view of the pixel 55 shown in FIG. 14(C) as an example. In FIG. 15, various insulating films and the light-emitting element 98 are omitted in order to clarify the layout of the pixel 55.

[0136] The pixel 55 shown in FIG. 15 includes a transistor 95, a transistor 96, and a capacitor element 97. In FIG. 15, the transistors 95 and 96 having the same structure as the transistor 10 shown in FIG. 1 are exemplified when used in the light-emitting device. However, in one aspect of the present invention, any of the transistors 10 shown in FIGS. 1 to 7 can be used in the light-emitting device.

[0137] The transistor 95 includes a conductive film 501 having a function as a gate electrode, a semiconductor film 502, and a conductive film 503 connected to the semiconductor film 502 and having a function as a source electrode or a drain electrode. The conductive film 501 has a function as the wiring GL shown in FIG. 14(C). ​​​​​​​​​​​​It is done. Further, the conductive film 503 functions as a wiring SL shown in FIG. 14(C).

[0138] The capacitor element 97 includes a semiconductor film 502, a conductive film 504, and an insulating film (not shown) provided between the semiconductor film 502 and the conductive film 504. The conductive film 504 is connected to a conductive film 505 disposed in the same layer as the conductive film 503. It has. The conductive film 504 is connected to a conductive film 505 arranged in the same layer as the conductive film 503. It is connected.

[0139] The transistor 96 includes a conductive film 506 having a function as a gate electrode, a semiconductor film 507, and conductive films 508 and 509 connected to the semiconductor film 507 and having a function as a source electrode or a drain electrode. Further, the conductive film 509 is connected to the pixel electrode of the light emitting element 98 shown in FIG. 14(C). The conductive film 506 is connected to the semiconductor film 502 via a conductive film 510. The conductive film 508 is connected to a conductive film 511, and the conductive film 511 functions as a wiring VL shown in FIG. 14(C). And a semiconductor film 507, and a conductive film 508 and a conductive film 509 connected to the semiconductor film 507 and having a function as a source electrode or a drain electrode. Further, the conductive film 509 is connected to the pixel electrode of the light emitting element 98 shown in FIG. 14(C). The conductive film 506 is connected to the semiconductor film 502 via a conductive film 510. The conductive film 508 is connected to a conductive film 511, and the conductive film 511 functions as a wiring VL shown in FIG. 14(C). It has. Also, the conductive film 509 is connected to the pixel electrode of the light emitting element 98 shown in FIG. 14(C). The conductive film 506 is connected to the semiconductor film 502 via the conductive film 510. The conductive film 508 is connected to the conductive film 511, and the conductive film 511 functions as the wiring VL shown in FIG. 14(C). It is connected. The conductive film 506 is connected to the semiconductor film 502 via the conductive film 510. The conductive film 508 is connected to the conductive film 511, and the conductive film 511 functions as the wiring VL shown in FIG. 14(C). 02 is connected. The conductive film 508 is connected to a conductive film 511, and the conductive film 511 functions as a wiring VL shown in FIG. 14(C). It has.

[0140] Note that electrodes that become anodes or cathodes can use metals, alloys, electrically conductive compounds, and mixtures thereof. Specifically, indium tin oxide (ITO: Indium Tin Oxide), indium tin oxide containing silicon or silicon oxide, indium zinc oxide (Indium Zinc Oxide), indium oxide containing tungsten and zinc oxide, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), titanium (Ti), and elements belonging to Group 1 or Group 2 of the periodic table of elements, that is, lithium (Li) and cesium (C TO: Indium Tin Oxide), indium tin oxide containing silicon or silicon oxide Dium tin oxide, indium zinc oxide (Indium Zinc Oxide) It is. Indium oxide containing tungsten and zinc oxide, gold (Au), platinum (Pt) Nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron ( Fe), cobalt (Co), copper (Cu), palladium (Pd), titanium (Ti), and other Elements belonging to Group 1 or Group 2 of the periodic table of elements, that is, lithium (Li) and cesium (C Alkali metals such as (s), and alkaline earth metals such as calcium (Ca) and strontium (Sr), magnesium (Mg) and alloys containing these (MgAg, AlLi), rare earth metals such as europium (Eu) and ytterbium (Yb) and alloys containing these, and others such as graphene can be used. By appropriately selecting the above materials and setting the film thickness to an optimal value, it is possible to create a top emission structure, a bottom emission structure, or a dual emission structure.

[0141] In addition, in one aspect of the present invention, a color filter method for displaying a full-color image is adopted by combining a light-emitting element that emits monochromatic light such as white and a color filter. Alternatively, a method of displaying a full-color image using a plurality of light-emitting elements that emit light of different hues can also be adopted. This method is called a painting method because the EL layer provided between a pair of electrodes of the light-emitting element is painted for each corresponding color.

[0142] In the case of the painting method, the painting of the EL layer is usually performed by vapor deposition using a mask such as a metal mask. Therefore, the pixel size depends on the painting accuracy of the EL layer by vapor deposition. On the other hand, in the case of the color filter method, unlike the painting method, it is not necessary to paint the EL layer. Therefore, it is easier to reduce the pixel size than in the case of the painting method, and a high-definition pixel portion can be realized.

[0143] In the case of the top emission structure, the light emitted from the light-emitting element is transmitted through wiring, transistors, Since it is not blocked by various elements such as a Ta and a capacitive element, a bottom emission structure can improve the light extraction efficiency from the pixel as compared with . Therefore, even when the current value supplied to the light emitting element is kept low, a high luminance can be obtained in the top emission structure, which is advantageous for extending the life of the light emitting element.

[0144] In addition, in one aspect of the present invention, the light emitting device may have a microcavity (micro optical resonator) structure that resonates light emitted from the EL layer within the light emitting element. The microcavity structure can improve the extraction efficiency of light of a specific wavelength from the light emitting element, so that the luminance and color purity of the pixel portion can be improved.

[0145] <Cross-sectional structure of the light emitting device> FIG. 16 shows, as an example, a cross-sectional structure of a pixel portion of a light emitting device corresponding to one form of the semiconductor device of the present invention.

[0146] Specifically, the light emitting device shown in FIG. 16 has a transistor 42 on a substrate 400. In FIG. 16, a case where a transistor 42 having the same structure as the transistor 10 shown in FIG. 2 is used in the light emitting device is illustrated. However, in one aspect of the present invention, any of the transistors 10 shown in FIGS. 1 to 7 can be used in the light emitting device.

[0147] An insulating film 420 is provided on the transistor 42, and a conductive film 42 4 is provided on the insulating film 420. The conductive film 424 is connected to a conductive film 404 that functions as a source electrode or a drain electrode of the transistor 42 at an opening provided in the insulating film 420.

[0148] ​​​​​​​​​An insulating film 425 is provided on the insulating film 420 and the conductive film 424. The insulating film 425 has an opening at a position overlapping with the conductive film 424. Also, on the insulating film 425, an insulating film 426 is provided at a position different from the opening of the insulating film 425. Then, on the insulating film 425 and the insulating film 426, an EL layer 427 and a conductive film 428 are provided so as to be laminated in order. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The insulating film 425 has an opening at a position overlapping with the conductive film 424. Also, on the insulating film 425, an insulating film 426 is provided at a position different from the opening of the insulating film 425. Then, on the insulating film 425 and the insulating film 426, an EL layer 427 and a conductive film 428 are provided so as to be laminated in order. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The insulating film 425 has an opening at a position overlapping with the conductive film 424. Also, on the insulating film 425, an insulating film 426 is provided at a position different from the opening of the insulating film 425. Then, on the insulating film 425 and the insulating film 426, an EL layer 427 and a conductive film 428 are provided so as to be laminated in order. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The insulating film 425 has an opening at a position overlapping with the conductive film 424. Also, on the insulating film 425, an insulating film 426 is provided at a position different from the opening of the insulating film 425. Then, on the insulating film 425 and the insulating film 426, an EL layer 427 and a conductive film 428 are provided so as to be laminated in order. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode. The overlapping portion where the conductive film 424 and the conductive film 428 sandwich the EL layer 427 functions as a light-emitting element 43. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode.

[0149] The light-emitting device further includes a substrate 430 facing the substrate 400 with the light-emitting element 43 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element 43, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in a region overlapping with the light-emitting element 43. In the opening overlapping with the light-emitting element 43, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430. The light-emitting device further includes a substrate 430 facing the substrate 400 with the light-emitting element 43 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element 43, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in a region overlapping with the light-emitting element 43. In the opening overlapping with the light-emitting element 43, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430. The light-emitting device further includes a substrate 430 facing the substrate 400 with the light-emitting element 43 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element 43, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in a region overlapping with the light-emitting element 43. In the opening overlapping with the light-emitting element 43, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430. The light-emitting device further includes a substrate 430 facing the substrate 400 with the light-emitting element 43 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element 43, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in a region overlapping with the light-emitting element 43. In the opening overlapping with the light-emitting element 43, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430. The light-emitting device further includes a substrate 430 facing the substrate 400 with the light-emitting element 43 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element 43, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in a region overlapping with the light-emitting element 43. In the opening overlapping with the light-emitting element 43, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430.

[0150] <Example Configuration of Sequential Circuit> Next, an example configuration of a sequential circuit using the transistor 10 shown in FIGS. 1 to 7 will be described. Next, an example configuration of a sequential circuit using the transistor 10 shown in FIGS. 1 to 7 will be described.

[0151] FIG. 17(A) schematically shows the positions of various wirings connected to the sequential circuit 80. Also, FIG. 17(B) shows an example of the circuit configuration of the sequential circuit 80. The sequential circuit 80 shown in FIG. 17(B) includes p-channel transistors 81 to 85 and n-channel transistors 86 to 90. The transistors 81 to 90 FIG. 17(A) schematically shows the positions of various wirings connected to the sequential circuit 80. Also, FIG. 17(B) shows an example of the circuit configuration of the sequential circuit 80. The sequential circuit 80 shown in FIG. 17(B) includes p-channel transistors 81 to 85 and n-channel transistors 86 to 90. The transistors 81 to 90 FIG. 17(A) schematically shows the positions of various wirings connected to the sequential circuit 80. Also, FIG. 17(B) shows an example of the circuit configuration of the sequential circuit 80. The sequential circuit 80 shown in FIG. 17(B) includes p-channel transistors 81 to 85 and n-channel transistors 86 to 90. The transistors 81 to 90 FIG. 17(A) schematically shows the positions of various wirings connected to the sequential circuit 80. Also, FIG. 17(B) shows an example of the circuit configuration of the sequential circuit 80. The sequential circuit 80 shown in FIG. 17(B) includes p-channel transistors 81 to 85 and n-channel transistors 86 to 90. The transistors 81 to 90 The structure of the transistor 10 shown in FIGS. 1 to 7 can be applied thereto.

[0152] In the sequential circuit 80, the transistors 81, 82, 86, and transistor 87 constitute a clocked inverter whose signal output presence or absence is controlled according to the signals supplied to the wirings c1 and c2.

[0153] Specifically, for transistor 81, the gate is connected to wiring c2, and one of the source and drain is connected to wiring 74, and the other of the source and drain is connected to one of the source and drain of transistor 82. For transistor 82, the gate is connected to wiring in, and the other of the source and drain is connected to the gates of transistors 85 and 90. For transistor 87, the gate is connected to wiring c1, and one of the source and drain is connected to wiring 75, and the other of the source and drain is connected to one of the source and drain of transistor 86. For transistor 86, the gate is connected to wiring in, and the other of the source and drain is connected to the gates of transistors 85 and 90. .

[0154] Also, in the sequential circuit 80, the transistors 83, 84, 88 , and transistor 89 constitute a clocked inverter whose signal output presence or absence is controlled according to the signals supplied to the wirings c1 and c2.

[0155] Specifically, for transistor 83, the gate is connected to wiring c1, and one of the source and drain is connected to wiring 76, and the other of the source and drain is connected to the source and drain is connected to one side of the rain. The transistor 84 has its gate connected to the wiring out, and the other sides of the source and drain are connected to the gates of the transistors 85 and 90 respectively. The transistor 89 has its gate connected to the wiring c2, and one of the source and drain is connected to the wiring 77, and the other sides of the source and drain are connected to one of the source and drain of the transistor 88. The transistor 88 has its gate connected to the wiring out, and the other sides of the source and drain are connected to the gates of the transistors 85 and 90.

[0156] Also, in the sequential circuit 80, the transistors 85 and 90 form an inverter.

[0157] Specifically, for the transistor 85, one of the source and drain is connected to the wiring 78, and the other side of the source and drain is connected to the wiring out. For the transistor 90, one of the source and drain is connected to the wiring 79, and the other side of the source and drain is connected to the wiring out.

[0158] Also, a low-level potential VSS is applied to the wirings 75, 77, and 79, and a high-level potential VDD is applied to the wirings 74, 76, and 78.

[0159] The transistor 10 shown in FIGS. 1 to 7 can increase the on-current. Therefore, by using the transistor 10 shown in FIGS. 1 to 7 for any of the transistors 81 to 90 in the sequential circuit 80, the sequential circuit 80 can be operated at high speed. Also, the transistor 10 shown in FIGS. 2, 4 to 7 can reduce the off-current. ​​​​​Therefore, by using the transistor 10 shown in FIGS. 2, 4 to 7 for any one of the transistors 81 to 90 of the sequential circuit 80, the leakage current flowing between the wirings 75, 77, and 79 and the wirings 74, 76, and 78 can be significantly suppressed, and the power consumption of the sequential circuit 80 can be reduced. 81 to any one of the transistors 90, the leakage current flowing between the wiring 75, the wiring 77, and the wiring 7 9 and the wirings 74, 76, and 78 can be suppressed to a small value, and the power consumption of the sequential circuit 80 can be reduced.

[0160] <Example Configuration of Drive Circuit> Next, the configuration of the signal line drive circuit using the sequential circuit 80 shown in FIG. 17 is shown as an example in FIG. 18 in a block diagram. In the block diagram, the components are classified by function and shown as independent blocks, but in actual components, it is difficult to completely separate them by function, and one component may be related to multiple functions.

[0161] In the signal line drive circuit shown in FIG. 18, a shift register is configured using a plurality of sequential circuits 80. And in the plurality of sequential circuits 80, the start pulse signal SSP or the signal of the wiring out connected to the previous sequential circuit 80 is input to the wiring in. One of the wirings c1 and the wiring c2 receives the clock signal SCK, and the other of the wirings c1 and the wiring c2 receives the clock signal SCKb in which the logical value of the clock signal SCK is inverted.

[0162] The signal input to the wiring in of the plurality of sequential circuits 80 and the signal input to the wiring out are respectively input to a pair of input terminals of the plurality of NAND40. The signals output from the output terminals of the plurality of NAND40 are respectively input to one of the pair of input terminals of the plurality of NOR41. Also, to the other of the pair of input terminals of the plurality of NOR41 are respectively input. one of the pair of input terminals of the plurality of NOR41, ​​The signals output from the output terminals of the plurality of NANDs 40 are input via a buffer 44. The signals output from the output terminals of the plurality of NORs 41 are input via a buffer 45. The signals are then input to first terminals of the plurality of transmission gates 47. The signal output from the output terminal of the NOR 41 is input to a plurality of inverters 46. The signal is input to a second terminal of the transmission gate 47 .

[0163] The transmission gate 47 receives signals from the first and second terminals. The image signal VIDEO input to the input terminal is supplied to the line SL.

[0164] Next, an example of the configuration of a scanning line driving circuit using the sequential circuit 80 shown in FIG. 17 is shown in FIG. and shown in the block diagram.

[0165] In the scanning line driving circuit shown in FIG. 19, a shift register is configured using a plurality of sequential circuits 80. In the plurality of sequential circuits 80, a start pulse signal GSP or a A signal from the wiring out connected to the sequential circuit 80 is input to the wiring in. A clock signal GCK is input to one end of the line c2, and the other ends of the lines c1 and c2 are A clock signal GCKb, which is the inverted logical value of the clock signal GCK, is input.

[0166] The signals input to the wirings in and out of the plurality of sequential circuits 80 are input in a plurality of ways. The NAND gates 48 are connected to a pair of input terminals. The signal output from the output terminal of the NOR49 is input to one of the pair of input terminals of the NOR49. The other of the pair of input terminals of the multiple NORs 49 is The signals PWC are each input. Specifically, in FIG. 19, the signal output from one of the output terminals of a NAND 48 is input to one of the pair of input terminals of six NORs 49, respectively. This is exemplified by the case where the signals are respectively input. And the case where signals PWC1 to PWC6 are respectively input to the other of the pair of input terminals of the six NORs 49 is exemplified. The signals output from the output terminals of the plurality of NORs 49 are respectively input to a plurality of wirings GL via a buffer 50. Note that the transistor 10 shown in FIGS. 1 to 7 can be used not only for the sequential circuit 80 but also for various circuits constituting the signal line driving circuit shown in FIG. 18 or various circuits constituting the scanning line driving circuit shown in FIG. 19. The transistor 10 shown in FIGS. 1 to 7 can increase the on-current. Therefore, by using the transistor 10 shown in FIGS. 1 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the signal line driving circuit or the scanning line driving circuit can be operated at high speed. Also, the transistor 10 shown in FIGS. 2, 4 to 7 can decrease the off-current. Therefore, by using the transistor 10 shown in FIGS. 2, 4 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the power consumption of the signal line driving circuit or the scanning line driving circuit can be reduced.

[0167] <Appearance of the light-emitting device> FIG. 20 is a perspective view showing an example of the appearance of a light-emitting device corresponding to one form of the semiconductor device of the present invention. The light-emitting device shown in FIG. 20 includes a panel 1601, a controller, a power supply circuit, an image circuit, etc. By using the transistor 10 shown in FIGS. 1 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the signal line driving circuit or the scanning line driving circuit can be operated at high speed. Also, by using the transistor 10 shown in FIGS. 2, 4 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the power consumption of the signal line driving circuit or the scanning line driving circuit can be reduced. The transistor 10 shown in FIGS. 2, 4 to 7 can decrease the off-current. Therefore, by using the transistor 10 shown in FIGS. 2, 4 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the power consumption of the signal line driving circuit or the scanning line driving circuit can be reduced. By using the transistor 10 shown in FIGS. 2, 4 to 7 for various circuits constituting the signal line driving circuit or the scanning line driving circuit, the power consumption of the signal line driving circuit or the scanning line driving circuit can be reduced.

[0168] <Appearance of the light-emitting device> FIG. 20 is a perspective view showing an example of the appearance of a light-emitting device corresponding to one form of the semiconductor device of the present invention. The light-emitting device shown in FIG. 20 includes a panel 1601, a controller, a power supply circuit, an image A circuit board 1602 provided with a processing circuit, an image memory, a CPU, etc., and a connection part 1603 It has. The panel 1601 includes a pixel part 1604 provided with a plurality of pixels, and a plurality of pixels A drive circuit 1605 that selects each row, and supplies an image signal Sig to the pixels in the selected row And a drive circuit 1606 that controls the supply.

[0169] From the circuit board 1602, various signals and the potential of the power supply are input to the panel 1601 via the connection part 1603. As the connection part 1603, an FPC (Flexible Printe d Circuit) etc. can be used. Also, when using a COF tape For the connection part 1603, a part of the circuit in the circuit board 1602, or a drive circuit that the panel 1601 has A part of 1605 or drive circuit 1606 is formed on a separately prepared chip, and COF (Chip On Film) method can be used to connect the chip to the COF tape It's okay.

[0170] <Configuration example of electronic device> The semiconductor device according to one aspect of the present invention is a display device, a notebook personal computer, a recording An image playback device equipped with a medium (typically a device having a display that can play a recording medium such as a DVD: Digital Versatile Disc and display its image) can be used. In addition, electronic devices that can use the semiconductor device according to one aspect of the present invention include mobile phones, portable game machines, portable information terminals, e-books, video cameras, digital Cameras such as still cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (car audio, digital audio players ), etc. layers, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 21. Examples include cash deposit and withdrawal machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG. 21. shown.

[0171] FIG. 21(A) is a display device, having a housing 5001, a display unit 5002, a support base 5003, etc. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other various circuits. Note that the display device includes all display devices for information display, such as for personal computers, TV broadcast reception, and advertisement display. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other various circuits. Note that the display device includes all display devices for information display, such as for personal computers, TV broadcast reception, and advertisement display. for advertisement display, etc. are included.

[0172] FIG. 21(B) is a portable information terminal, having a housing 5101, a display unit 5102, operation keys 5103, etc. The semiconductor device according to one aspect of the present invention can be used for the display unit 5102 or other various circuits. The semiconductor device according to one aspect of the present invention can be used for the display unit 5102 or other various circuits. circuits.

[0173] FIG. 21(C) is a display device, having a housing 5701 with a curved surface, a display unit 5702, etc. The semiconductor device according to one aspect of the present invention can be used for the display unit 5702 or other various circuits. By using a flexible substrate for the semiconductor device according to one aspect of the present invention, the semiconductor device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided. The semiconductor device according to one aspect of the present invention can be used for the display unit 5702 or other various circuits. By using a flexible substrate for the semiconductor device according to one aspect of the present invention, the semiconductor device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided. can be used, and a flexible, lightweight, and user-friendly display device can be provided. A display unit 5702 supported by a housing 5701 having a curved surface can be used, and a flexible, lightweight, and user-friendly display device can be provided.

[0174] FIG. 21(D) is a portable game machine, having a housing 5301, a housing 5302, display units 5303, display units 5304, a microphone 5305, a speaker 5306, operation keys 5307, a stylus 5308, etc. The semiconductor device according to one aspect of the present invention can be used for the display units 5303, display It can be used for the section 5304 or other various circuits. Note that as shown in FIG. 21(D), the portable game machine has two display sections 5303 and 5304, but the number of display sections the portable game machine has is not limited to this.

[0175] FIG. 21(E) is an electronic book, which has a housing 5601, a display section 5602, etc. The semiconductor device according to one aspect of the present invention can be used for the display section 5602 or other various circuits. By using a flexible substrate, the display section can be made flexible, so that a flexible, lightweight, and easy-to-use electronic book can be provided.

[0176] FIG. 21(F) is a mobile phone, and a display section 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection section 5906, and operation buttons 5905 are provided on a housing 5901. The semiconductor device according to one aspect of the present invention can be used for the display section 5902 or other various circuits. Further, when the semiconductor device according to one aspect of the present invention is formed on a flexible substrate, the semiconductor device can be applied to the display section 5902 having a curved surface as shown in FIG. 21(F).

Explanation of Reference Numerals

[0177] 1 Configuration Example 2 Configuration Example 3 Configuration Example 4 Configuration Example 5 Configuration Example 6 Configuration Example 7 Configuration Example 10 Transistor 10a Transistor 10b Transistor 10c Transistor 10N Transistor 10P Transistor 11 Substrate 12 Semiconductor film 12a Channel formation region 12b Impurity region 12c Impurity region 13 Insulating film 13a Insulating film 13c Insulating film 14 Conductive film 15 Conductive film 16 Insulating film 17 Conductive film 17a Conductive film 17b Conductive film 17c Conductive film 18 Opening 18a Opening 18b Opening 18c Opening 19 Opening 19a Opening 19b Opening 19c Opening 20 Conductive film 21 Insulating film 22 Opening 23 Opening 24 Conductive film 25 Opening 26 Conductive film 27 Conductive film 28 Opening 29 Opening 30 Conductive film 31 Conductive film 32 Conductive film 33 Conductive film 40 NAND 42 Transistor 43 Light-emitting element 44 Buffer 45 Buffer 46 Inverter 47 Transmission gate 48 NAND 50 Buffer 55 Pixel 56 Transistor 57 Capacitive element 60 Liquid crystal element 70 Semiconductor display device 71 Pixel section 72 Scanning line drive circuit 73 Signal line drive circuit 74 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 80 Sequential circuit 81 Transistor 82 Transistor 83 Transistor[[ID=29]] 84 Transistor 85 Transistor 86 Transistor 87 Transistor 88 Transistor 89 Transistor 90 Transistor 95 Transistor 96 Transistor 97 Capacitor element 98 Light-emitting element 300 Substrate 301 Insulating film 302 Conductive film 303 Conductive film 304 Insulating film 305 Semiconductor film 306 Semiconductor film 307 Semiconductor film 308 Insulating film 309 Conductive film 310 Conductive film 311 Resist 312 Impurity region 313 Resist 314 Impurity region 320 Insulating film 321 Conductive film 322 Conductive film 400 Substrate 404 Conductive film 420 Insulating film 424 Conductive film 425 Insulating film 426 Insulating film 427 EL layer 428 Conductive film 430 Substrate 431 Masking film 432 Coloring layer 501 Conductive film 502 Semiconductor film 503 Conductive film 504 Conductive film 505 Conductive film 506 Conductive film 507 Semiconductor film 508 Conductive film 509 Conductive film 510 Conductive film 511 Conductive film 1601 Panel 1602 Circuit board 1603 Connection part 1604 Pixel part 1605 Driving circuit 1606 Driving circuit 5001 Housing 5002 Display part 5003 Support stand 5101 Housing 5102 Display part 5103 Operation key 5301 Housing 5302 Housing 5303 Display part 5304 Display part 5305 Microphone 5306 Speaker 5307 Operation key 5308 Stylus 5601 Housing 5602 Display part 5701 Housing 5702 Display part 5901 Housing 5902 Display part 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mic

Claims

1. A pixel includes a first transistor, a second transistor, a light-emitting element, a capacitor, a wiring to which an image signal is input, a scanning line, and a power supply line, wherein one of a source and a drain of the first transistor is always in conduction with the wiring, the other of the source and the drain of the first transistor is always in conduction with a gate of the second transistor, a gate of the first transistor is always in conduction with the scanning line, one of a source and a drain of the second transistor is always in conduction with the power supply line, the other of the source and the drain of the second transistor is always in conduction with a pixel electrode of the light-emitting element, the capacitor has a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element, and the light-emitting device, a first semiconductor film having a channel formation region of the first transistor and having a function as a first electrode of the capacitor, a second semiconductor film having a channel formation region of the second transistor, a first conductive film having a function as a gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film, a second conductive film having a function as the wiring, a third conductive film having a function as a second electrode of the capacitor, a fourth conductive film and a fifth conductive film having a function as the power supply line, and having the second conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the fifth conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the third conductive film has no overlap with the first conductive film, the third conductive film has no overlap with the fourth conductive film, a light-emitting device.

2. A pixel includes a first transistor, a second transistor, a light-emitting element, a capacitor, a wiring to which an image signal is input, a scanning line, and a power supply line, wherein one of a source and a drain of the first transistor is always in conduction with the wiring, the other of the source and the drain of the first transistor is always in conduction with a gate of the second transistor, a gate of the first transistor is always in conduction with the scanning line, one of a source and a drain of the second transistor is always in conduction with the power supply line, The other of the source or drain of the second transistor is always in conduction with the pixel electrode of the light-emitting element. The capacitor element is a light-emitting device having a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element. A first semiconductor film having a channel formation region of the first transistor and having a function as a first electrode of the capacitor element. A second semiconductor film having a channel formation region of the second transistor. A first conductive film having a function as a gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film. A second conductive film having a function as the wiring. A third conductive film having a function as a second electrode of the capacitor element. A fourth conductive film and a fifth conductive film having a function as the power supply line. It has. The second conductive film has a region intersecting the first conductive film and a region intersecting the fourth conductive film. The fifth conductive film has a region intersecting the first conductive film and a region intersecting the fourth conductive film. The third conductive film has no overlap with the first conductive film. The third conductive film has no overlap with the fourth conductive film. The third conductive film has no overlap with the second conductive film. Light-emitting device.

3. A pixel includes a first transistor, a second transistor, a light-emitting element, a capacitor element, a wiring to which an image signal is input, a scanning line, and a power supply line. One of the source or drain of the first transistor is always in conduction with the wiring. The other of the source or drain of the first transistor is always in conduction with the gate of the second transistor. The gate of the first transistor is always in conduction with the scanning line. One of the source or drain of the second transistor is always in conduction with the power supply line. The other of the source or drain of the second transistor is always in conduction with the pixel electrode of the light-emitting element. The capacitor element is a light-emitting device having a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element. A first semiconductor film having a channel formation region of the first transistor and having a function as a first electrode of the capacitor element. A second semiconductor film having a channel formation region of the second transistor. A first conductive film having a function as a gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film; A second conductive film having a function as the wiring; A third conductive film having a function as a second electrode of the capacitive element; A fourth conductive film and a fifth conductive film having a function as the power supply line; comprising; The second conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film; The fifth conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film; The third conductive film does not overlap with the first conductive film; The third conductive film does not overlap with the fourth conductive film; A first region of the first semiconductor film that overlaps with the third conductive film has, in a plan view, a region disposed between a channel formation region of the first transistor and a channel formation region of the second transistor; A light-emitting device. [

4. ] A pixel includes a first transistor, a second transistor, a light-emitting element, a capacitive element, a wiring to which an image signal is input, a scanning line, and a power supply line, One of a source or a drain of the first transistor is always in conduction with the wiring, The other of the source or the drain of the first transistor is always in conduction with the gate of the second transistor, The gate of the first transistor is always in conduction with the scanning line, One of the source or the drain of the second transistor is always in conduction with the power supply line, The other of the source or the drain of the second transistor is always in conduction with the pixel electrode of the light-emitting element, The capacitive element is a light-emitting device having a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element, A first semiconductor film having a channel formation region of the first transistor and having a function as a first electrode of the capacitive element; A second semiconductor film having a channel formation region of the second transistor; A first conductive film having a function as a gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film; A second conductive film having a function as the wiring; A third conductive film having a function as a second electrode of the capacitive element; A fourth conductive film and a fifth conductive film having a function as the power supply line, having, the second conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the fifth conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the third conductive film does not overlap with the first conductive film, the third conductive film does not overlap with the fourth conductive film, a first region of the first semiconductor film that overlaps with the third conductive film has, in a plan view, a region disposed between the second conductive film and the fifth conductive film, a light-emitting device.

5. A pixel has a first transistor, a second transistor, a light-emitting element, a capacitor element, a wiring to which an image signal is input, a scanning line, and a power supply line, one of the source or drain of the first transistor is always in conduction with the wiring, the other of the source or drain of the first transistor is always in conduction with the gate of the second transistor, the gate of the first transistor is always in conduction with the scanning line, one of the source or drain of the second transistor is always in conduction with the power supply line, the other of the source or drain of the second transistor is always in conduction with the pixel electrode of the light-emitting element, the capacitor element is a light-emitting device having a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element, a first semiconductor film having a channel formation region of the first transistor and having a function as a first electrode of the capacitor element, a second semiconductor film having a channel formation region of the second transistor, a first conductive film having a function as the gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film, a second conductive film having a function as the wiring, a third conductive film having a function as a second electrode of the capacitor element, a fourth conductive film and a fifth conductive film having a function as the power supply line, having, the second conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the fifth conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film, the third conductive film does not overlap with the first conductive film, The third conductive film has no overlap with the fourth conductive film, The third conductive film has no overlap with the second conductive film, Among the first semiconductor films, a first region overlapping with the third conductive film has, in plan view, a region disposed between the channel formation region of the first transistor and the channel formation region of the second transistor. Light-emitting device.

6. A pixel includes a first transistor, a second transistor, a light-emitting element, a capacitor element, a wiring to which an image signal is input, a scanning line, and a power supply line. One of the source or drain of the first transistor is always in conduction with the wiring. The other of the source or drain of the first transistor is always in conduction with the gate of the second transistor. The gate of the first transistor is always in conduction with the scanning line. One of the source or drain of the second transistor is always in conduction with the power supply line. The other of the source or drain of the second transistor is always in conduction with the pixel electrode of the light-emitting element. The capacitor element is a light-emitting device having a function of holding a voltage between the gate of the second transistor and the pixel electrode of the light-emitting element. A first semiconductor film having the channel formation region of the first transistor and having a function as a first electrode of the capacitor element. A second semiconductor film having the channel formation region of the second transistor. A first conductive film having a function as the gate of the first transistor, having a function as the scanning line, and having a region disposed above the first semiconductor film. A second conductive film having a function as the wiring. A third conductive film having a function as a second electrode of the capacitor element. A fourth conductive film and a fifth conductive film having a function as the power supply line. And has The second conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film. The fifth conductive film has a region intersecting with the first conductive film and a region intersecting with the fourth conductive film. The third conductive film has no overlap with the first conductive film. The third conductive film has no overlap with the fourth conductive film. The third conductive film has no overlap with the second conductive film. A first region of the first semiconductor film that overlaps with the third conductive film has, in a plan view, a region disposed between the second conductive film and the fifth conductive film. Light-emitting device.

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