Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device according to an embodiment includes: a frame body having a wall surface; an insulating substrate surrounded by the frame body, the insulating substrate having a first metal layer and a second metal layer on a surface thereof, the second metal layer being located between the first metal layer and the wall surface; a semiconductor chip including an electrode and provided on the first metal layer; and a bonding wire having a first bond portion connected to the electrode, a second bond portion connected to the second metal layer, and an intermediate portion between the first bond portion and the second bond portion. A second angle formed between a second direction in which the second bond portion extends and the wall surface is smaller than a first angle formed between a first direction in which the intermediate portion extends and the wall surface.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] In a power semiconductor module, for example, a power semiconductor chip is mounted on a metal base with an insulating substrate interposed therebetween. The power semiconductor chip is, for example, a Metal Oxide Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or a diode.

[0003] In order to realize miniaturization of equipment on which a power semiconductor module is mounted, miniaturization of the power semiconductor module is desired.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of achieving miniaturization.

Means for Solving the Problems

[0006] A semiconductor device according to one aspect of the present invention includes a frame having a wall surface, an insulating substrate surrounded by the frame, the insulating substrate having a first metal layer and a second metal layer on its surface, the second metal layer being located between the first metal layer and the wall surface, a semiconductor chip provided on the first metal layer, a first bonding portion connected to the electrode, a second bonding portion connected to the second metal layer, and a bonding wire having an intermediate portion between the first bonding portion and the second bonding portion, wherein a second angle formed between a second direction in which the second bonding portion extends and the wall surface is smaller than a first angle formed between a first direction in which the intermediate portion extends and the wall surface. <, the first angle is 60 degrees or more and 90 degrees or less, the difference between the first angle and the second angle is 20 degrees or more and 45 degrees or less, the first bond portion extends in the first direction, and the length of the second bond portion in the second direction is longer than the length of the first bond portion in the first direction> 。

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] In this specification, for the same or similar members, the same reference numerals may be given, and redundant descriptions may be omitted.

[0009] In this specification, in order to indicate the positional relationship of components etc., the upper direction of the drawing may be described as "upper" and the lower direction of the drawing may be described as "lower". In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0010] The semiconductor device according to the embodiment includes a frame body having a wall surface, and an insulating substrate surrounded by the frame body, the insulating substrate having a first metal layer and a second metal layer on its surface, the second metal layer being located between the first metal layer and the wall surface, an insulating substrate, a semiconductor chip provided on the first metal layer, a first bonding portion connected to the electrode, a second bonding portion connected to the second metal layer, and a bonding wire having an intermediate portion between the first bonding portion and the second bonding portion. And the second angle formed by the second direction in which the second bonding portion extends and the wall surface is smaller than the first angle formed by the first direction in which the intermediate portion extends and the wall surface.

[0011] FIG. 1 is a schematic top view of a semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment. FIG. 2 is a cross-section taken along the line AA' of FIG. 1.

[0012] The semiconductor device of the embodiment is the power semiconductor module 100. As shown in FIG. 1, in the power semiconductor module 100 of the embodiment, two MOSFETs are connected in series. The power semiconductor module of the embodiment is a so-called "2 in 1" type module that can form a half-bridge circuit with one module. For example, a three-phase inverter circuit can be configured by using three power semiconductor modules of the embodiment.

[0013] The power semiconductor module 100 of the embodiment includes a resin case 10 (frame), a lid 12, a first main terminal 14, a second main terminal 16, an AC output terminal 18, a first gate terminal 21, a second gate terminal 22, a metal base 24, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a fourth metal layer 34, a fifth metal layer 35, a back metal layer 36, a first MOSFET 38 (semiconductor chip), a second MOSFET 40, a first bonding wire 41 (bonding wire), a second bonding wire 42, a third bonding wire 43, a fourth bonding wire 44, a fifth bonding wire 45, a sixth bonding wire 46, and a sealing resin 50.

[0014] The resin case 10 has a wall surface 10a. The first MOSFET 38 includes a gate electrode pad 38a (electrode), a source electrode 38b, a semiconductor layer 38c, and a drain electrode 38d. The first bonding wire 41 includes a first bond portion 41a, a second bond portion 41b, and a loop portion 41c. The loop portion 41c is an example of an intermediate portion.

[0015] FIG. 1 is a top view of the power semiconductor module 100 with the lid 12 and the sealing resin 50 removed.

[0016] The metal base 24 is, for example, copper. For example, when the power semiconductor module 100 is mounted on a product, a heat sink (not shown) is connected to the back surface of the metal base 24.

[0017] The insulating substrate 30 is provided on the metal base 24. The insulating substrate 30 is surrounded by the resin case 10. The insulating substrate 30 is provided between the metal base 24 and the first MOSFET 38, and between the metal base 24 and the second MOSFET 40. The insulating substrate 30 has a function of electrically separating the metal base 24 from the first MOSFET 38 and the second MOSFET 40.

[0018] The insulating substrate 30 is, for example, ceramic. The insulating substrate 30 is, for example, aluminum oxide, aluminum nitride, or silicon nitride.

[0019] On the surface of the insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a fourth metal layer 34, and a fifth metal layer 35 are provided. The first metal layer 31, the second metal layer 32, the third metal layer 33, the fourth metal layer 34, and the fifth metal layer 35 are, for example, copper.

[0020] The second metal layer 32 is located between the first metal layer 31 and the wall surface 10a of the resin case 10. The fourth metal layer 34 is located between the third metal layer 33 and the wall surface 10a of the resin case 10.

[0021] On the back surface of the insulating substrate 30, a back surface metal layer 36 is provided. The back surface metal layer 36 is, for example, copper. The back surface metal layer 36 is joined to the metal base 24 using, for example, a solder layer or a metal nanoparticle layer (not shown).

[0022] The resin case 10 is provided around the metal base 24 and the insulating substrate 30. A part of the resin case 10 is provided on the metal base 24. The resin case 10 is an example of a frame body. The resin case 10 has a function of protecting the first MOSFET 38, the second MOSFET 40, and the insulating substrate 30. The resin case 10 has a wall surface 10a.

[0023] A lid 12 is provided on the resin case 10. The lid 12 sandwiches the first MOSFET 38 and the second MOSFET 40 between itself and the insulating substrate 30. The lid 12 has a function of protecting the first MOSFET 38, the second MOSFET 40, and the insulating substrate 30.

[0024] The first bonding wire 41, the second bonding wire 42, the third bonding wire 43, the fourth bonding wire 44, the fifth bonding wire 45, and the sixth bonding wire 46 electrically connect between the members of the power semiconductor module 100. The materials of the first bonding wire 41, the second bonding wire 42, the third bonding wire 43, the fourth bonding wire 44, the fifth bonding wire 45, and the sixth bonding wire 46 are, for example, aluminum, copper, or gold.

[0025] The first MOSFET 38 is provided on the insulating substrate 30. The first MOSFET 38 has a gate electrode pad 38a, a source electrode 38b, a semiconductor layer 38c, and a drain electrode 38d. The gate electrode pad 38a is an example of an electrode.

[0026] The first MOSFET 38 is formed using, for example, silicon carbide. The semiconductor layer 38c is, for example, a silicon carbide layer.

[0027] The first MOSFET 38 is provided on the first metal layer 31. The drain electrode 38d is fixed on the first metal layer 31 using, for example, a solder layer or a metal nanoparticle layer (not shown). The drain electrode 38d is joined to the first metal layer 31. The drain electrode 38d is electrically connected to the first metal layer 31.

[0028] The source electrode 38b is electrically connected to the fifth metal layer 35. The source electrode 38b is electrically connected to the fifth metal layer 35 using the third bonding wire 43.

[0029] The gate electrode pad 38a is electrically connected to the second metal layer 32. The gate electrode pad 38a is electrically connected to the second metal layer 32 using the first bonding wire 41.

[0030] The second MOSFET 40 is provided on the insulating substrate 30. The second MOSFET 40 is provided on the third metal layer 33.

[0031] The encapsulation resin 50 is filled in the resin case 10. The encapsulation resin 50 is surrounded by the resin case 10. The encapsulation resin 50 covers the first MOSFET 38, the second MOSFET 40, and the insulating substrate 30.

[0032] The encapsulation resin 50 has a function of protecting the first MOSFET 38, the second MOSFET 40, and the insulating substrate 30. It also has a function of insulating the first MOSFET 38, the second MOSFET 40, and the insulating substrate 30.

[0033] The encapsulation resin 50 contains resin. The encapsulation resin 50 is, for example, a silicone gel. Other resins such as epoxy resin and polyimide resin can also be applied to the encapsulation resin 50.

[0034] The first main terminal 14 is electrically connected to the fifth metal layer 35. A negative voltage, for example, is applied to the first main terminal 14 from the outside. The first main terminal 14 is, for example, made of copper.

[0035] The second main terminal 16 is electrically connected to the third metal layer 33. A positive voltage, for example, is applied to the second main terminal 16 from the outside. The second main terminal 16 is, for example, made of copper.

[0036] The AC output terminal 18 is electrically connected to the first metal layer 31. One end of the AC output terminal 18 is fixed to the first metal layer 31, for example. The AC output terminal 18 outputs the output current of the half - bridge circuit.

[0037] The first gate terminal 21 is electrically connected to the gate electrode pad 38a of the first MOSFET 38. The first gate terminal 21 has a function of applying a gate voltage signal for controlling the first MOSFET 38 to the gate electrode pad 38a.

[0038] The second gate terminal 22 is electrically connected to the gate electrode pad of the second MOSFET 40. The second gate terminal 22 has a function of applying a gate voltage signal for controlling the second MOSFET 40 to the gate electrode pad.

[0039] FIG. 3 is an enlarged schematic top view of the semiconductor device according to the embodiment. FIG. 3 is an enlarged view of the region X surrounded by the dashed line in FIG. 1. FIG. 3 is a top view in a state where the lid 12 and the sealing resin 50 are removed.

[0040] FIG. 4 is an enlarged schematic cross-sectional view of the semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view including the region along the bonding wire in FIG. 3.

[0041] The first bonding wire 41 has a first bond portion 41a, a second bond portion 41b, and a loop portion 41c.

[0042] The first bond portion 41a is connected to the gate electrode pad 38a of the first MOSFET 38. The second bond portion 41b is connected to the second metal layer 32. The loop portion 41c is located between the first bond portion 41a and the second bond portion 41b.

[0043] When forming the first bonding wire 41, the first bond portion 41a is formed prior to the second bond portion 41b.

[0044] The loop portion 41c extends in the first direction. The angle formed by the first direction and the wall surface 10a of the resin case 10 is the first angle (θ1 in FIG. 3). The first angle θ1 is, for example, 60 degrees or more and 90 degrees or less.

[0045] The second bonding portion 41b extends in a second direction. The second direction is different from the first direction. The angle formed by the second direction and the wall surface 10a of the resin case 10 is the second angle (θ2 in FIG. 3). The second angle is, for example, 0 degrees or more and 80 degrees or less.

[0046] The second angle θ2 is smaller than the first angle θ1. The difference between the first angle θ1 and the second angle θ2 is, for example, 10 degrees or more and 90 degrees or less. Preferably, the difference between the first angle θ1 and the second angle θ2 is, for example, 20 degrees or more and 45 degrees or less.

[0047] Next, an example of a method for manufacturing a semiconductor device according to an embodiment will be described. Hereinafter, in particular, the formation of bonding wires will be described.

[0048] The method for manufacturing a semiconductor device according to the embodiment includes preparing an insulating substrate surrounded by a frame having a wall surface, the insulating substrate having a first metal layer and a second metal layer on the surface, the second metal layer being located between the first metal layer and the wall surface, placing a semiconductor chip including electrodes on the first metal layer, forming a first bonding portion of a bonding wire on the electrodes, forming an intermediate portion of the bonding wire extending in a first direction, and forming a second bonding portion of the bonding wire on the second metal layer, the second angle formed by the extending second direction and the wall surface being smaller than the first angle formed by the first direction and the wall surface.

[0049] FIG. 5 is a schematic diagram of a wedge bonding apparatus used in the method for manufacturing a semiconductor device according to the embodiment. FIG. 5 is an enlarged view of the tip of the bonding head of the wedge bonding apparatus.

[0050] The bonding head 60 of the wedge bonding apparatus according to the embodiment includes a wedge tool 61, a cutter blade 62, and a wire guide 63.

[0051] The bonding head 60 can move up, down, left, and right. Further, the bonding head 60 can rotate within a horizontal plane.

[0052] The wedge tool 61 has a groove (not shown) at its tip for holding the wire 70. By applying ultrasonic vibration while pressing the wire 70 against the connection part with the wedge tool 61, the wire 70 and the connection part are joined.

[0053] The cutter blade 62 has a function of cutting the wire 70. The cutter blade 62 can move independently in the vertical direction with respect to the wedge tool 61 and the wire guide 63.

[0054] The wire guide 63 has a function of feeding the wire 70 to the wedge tool 61.

[0055] Figures 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are schematic diagrams showing a method of manufacturing a semiconductor device according to an embodiment. Figures 6 to 15 correspond to the cross-section shown in Figure 4. Figures 6 to 15 are diagrams showing a method of forming the first bonding wire 41 shown in Figure 4.

[0056] First, an insulating substrate 30 surrounded by a resin case 10 having a wall surface 10a is prepared (Figure 6). The resin case 10 is an example of a frame body.

[0057] A first metal layer 31 and a second metal layer 32 are provided on the surface of the insulating substrate 30. The second metal layer 32 is located between the first metal layer 31 and the wall surface 10a.

[0058] Next, a first MOSFET 38 is placed on the first metal layer 31 (Figure 7). The first MOSFET 38 is an example of a semiconductor chip.

[0059] The first MOSFET 38 is joined to the first metal layer 31. The first MOSFET 38 includes a gate electrode pad 38a, a source electrode 38b, a semiconductor layer 38c, and a drain electrode 38d. The gate electrode pad 38a is an example of an electrode.

[0060] Next, a first bonding wire 41 is formed using a wedge bonding device.

[0061] First, the wire 70 is pressed against the surface of the gate electrode pad 38a by the wedge tool 61 to form the first bond portion 41a (FIG. 8).

[0062] Next, the bonding head 60 is moved laterally to form the loop portion 41c (FIG. 9). The loop portion 41c is an example of an intermediate portion. The bonding head 60 moves in the first direction shown in FIG. 3. The loop portion 41c extends in the first direction shown in FIG. 3.

[0063] Next, when the bonding head 60 reaches the planned region for forming the second bond portion 41b, the bonding head 60 is rotated in the horizontal plane on the surface of the second metal layer 32 (FIG. 10). The rotation angle is, for example, 10 degrees or more and 90 degrees or less. The rotation angle is preferably, for example, 20 degrees or more and 45 degrees or less.

[0064] Next, the wire 70 is pressed against the surface of the second metal layer 32 by the wedge tool 61 to form the second bond portion 41b (FIG. 11). Due to the rotation of the bonding head 60, the second bond portion 41b extends in the second direction shown in FIG. 3.

[0065] Next, the wire 70 is half-cut using the cutter blade 62 (FIG. 12).

[0066] Next, the cutter blade 62 is separated from the wire 70 (FIG. 13).

[0067] Next, while feeding out the wire 70 from the wire guide 63, the bonding head 60 is moved laterally (FIG. 14). The bonding head 60 is moved in the direction of the wall surface 10a. The bonding head 60 moves in the second direction shown in FIG. 3. The wire 70 fed out from the wire guide 63 becomes the first bond portion when forming the next wire bond.

[0068] Next, with the wire 70 clamped by the wire guide 63, the bonding head 60 is moved obliquely upward to pull the wire 70 to completely cut it (FIG. 15). When cutting the wire 70, the bonding head 60 moves in the direction of the wall surface 10a. At this time, the bonding head 60 moves in the second direction shown in FIG. 3.

[0069] By the above method, the first bonding wire 41 is formed.

[0070] Next, the operation and effect of the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment will be described.

[0071] FIGS. 16(a) and 16(b) are explanatory diagrams of the operation and effect of the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment. FIG. 16(a) is an enlarged schematic top view of a semiconductor device of a comparative example. FIG. 16(b) is an enlarged schematic top view of a semiconductor device according to the embodiment. FIGS. 16(a) and 16(b) are diagrams corresponding to FIG. 3.

[0072] The bonding wire 49 of the semiconductor device of the comparative example has a first bond portion 49a, a second bond portion 49b, and a loop portion 49c. The bonding wire 49 of the comparative example is different from the first bonding wire 41 of the embodiment in that the second bond portion 49b extends in the first direction in the same manner as the loop portion 49c.

[0073] In the bonding wire 49 of the comparative example, the distance dx in the first direction from the end of the second bond portion 49b to the wall surface 10a is smaller than the distance dy in the second direction from the end of the second bond portion 49b of the first bonding wire 41 of the embodiment to the wall surface 10a.

[0074] FIG. 17 is an explanatory diagram of the problems of the semiconductor device of the comparative example. FIG. 17 is a diagram showing a method of forming the bonding wire 49 of the semiconductor device of the comparative example.

[0075] FIG. 17 is a diagram corresponding to FIG. 15 of the method for manufacturing a semiconductor device according to the embodiment. When cutting the wire 70, the bonding head 60 moves in a first direction toward the wall surface 10a. At this time, if the distance dx in the first direction from the end of the second bond portion 49b to the wall surface 10a is small, the bonding head 60 collides with the wall surface 10a. Therefore, it becomes difficult to continue the formation of wire bonding.

[0076] In the embodiment, the second bond portion 41b extends in a second direction different from the first direction. The second angle θ2 formed between the second direction and the wall surface 10a of the resin case 10 is smaller than the first angle θ1 formed between the first direction and the wall surface 10a of the resin case 10.

[0077] Therefore, as shown in FIGS. 16(a) and 16(b), the distance dy in the second direction from the end of the second bond portion 41b to the wall surface 10a when cutting the wire 70 in the embodiment is larger than the distance dx in the first direction from the end of the second bond portion 49b to the wall surface 10a in the comparative example. Thus, in the embodiment, the bonding head 60 is suppressed from colliding with the wall surface 10a.

[0078] In the embodiment, since the bonding head 60 is suppressed from colliding with the wall surface 10a, the distance in the first direction from the second bond portion 41b of the first bonding wire 41 to the wall surface 10a can be made smaller than in the comparative example. Therefore, miniaturization of the power semiconductor module 100 can be realized.

[0079] From the viewpoint of reducing the distance in the first direction from the second bond portion 41b to the wall surface 10a and realizing miniaturization of the power semiconductor module 100, the difference between the first angle θ1 and the second angle θ2 is preferably 10 degrees or more, more preferably 20 degrees or more, and still more preferably 30 degrees or more.

[0080] The electrode to which the first bond portion 41a of the first bonding wire 41 is connected is preferably the gate electrode pad 38a of the MOSFET or IGBT as in the embodiment. Compared with the source electrode 38b and the drain electrode 38d, a large current does not flow through the gate electrode pad 38a. Therefore, the size of the metal layer to which the second bond portion 41b is connected becomes smaller. For example, the width in the direction perpendicular to the wall surface 10a of the metal layer becomes smaller. Therefore, the distance from the second bond portion 41b of the first bonding wire 41 to the wall surface 10a is likely to be shortened, and the semiconductor device and the method of manufacturing the semiconductor device of the embodiment function effectively.

[0081] In the embodiment, the case where a MOSFET or an IGBT is used as the semiconductor chip has been described as an example, but the semiconductor chip is not limited to these. For example, other transistors and diodes such as SBD (Schottky Barrier Diode) and PIN diode can also be applied. Also, a combination of a transistor and a diode can be applied.

[0082] In the embodiment, the "2 in 1" type module has been described as an example, but for example, a "4 in 1" type or a "6 in 1" type module may be used.

[0083] In the embodiment, the case where the number of semiconductor chips is two has been described as an example, but the number of semiconductor chips may be one or three or more.

[0084] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with the components of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0085] 10 Resin case (frame) 10a Wall surface 30 Insulation substrate 31 First metal layer 32 Second metal layer 38 First MOSFET (semiconductor chip) 38a Gate electrode pad (electrode) 41 First bonding wire (bonding wire) 41a First bond part 41b Second bond part 41c Loop part (intermediate part) 60 Bonding head θ1 First angle θ2 Second angle

Claims

1. A frame body having a wall surface, an insulating substrate surrounded by the frame body, having a first metal layer and a second metal layer on its surface, and the second metal layer being located between the first metal layer and the wall surface, a semiconductor chip including electrodes and provided on the first metal layer, a first bonding portion connected to the electrodes, a second bonding portion connected to the second metal layer, and a bonding wire having an intermediate portion between the first bonding portion and the second bonding portion, comprising, the second angle formed between the second direction in which the second bonding portion extends and the wall surface is smaller than the first angle formed between the first direction in which the intermediate portion extends and the wall surface, the first angle is 60 degrees or more and 90 degrees or less, the difference between the first angle and the second angle is 20 degrees or more and 45 degrees or less, the first bonding portion extends in the first direction, a semiconductor device in which the length of the second bonding portion in the second direction is longer than the length of the first bonding portion in the first direction.

2. The semiconductor device according to claim 1, wherein the semiconductor chip is a MOSFET or an IGBT, and the electrode is a gate electrode pad.

3. The semiconductor device according to claim 1 or claim 2, wherein when the bonding wire is formed, the first bonding portion is formed earlier than the second bonding portion.

4. Preparing an insulating substrate surrounded by a frame body having a wall surface, having a first metal layer and a second metal layer on its surface, and the second metal layer being located between the first metal layer and the wall surface, placing a semiconductor chip including electrodes on the first metal layer, forming a first bonding portion of a bonding wire on the electrodes, forming an intermediate portion of the bonding wire extending in a first direction, forming a second bonding portion of the bonding wire, the second angle formed between the second direction in which it extends and the wall surface being smaller than the first angle formed between the first direction in which it extends and the wall surface, on the second metal layer, the first angle is 60 degrees or more and 90 degrees or less, the difference between the first angle and the second angle is 20 degrees or more and 45 degrees or less, the first bonding portion extends in the first direction, a method of manufacturing a semiconductor device in which the length of the second bonding portion in the second direction is longer than the length of the first bonding portion in the first direction.

5. The bonding wire is formed using a wedge bonding device, When forming the intermediate portion, move the bonding head of the wedge bonding device in the first direction, The method of manufacturing a semiconductor device according to claim 4, wherein after forming the second bond portion, the bonding head is moved in the second direction.

6. The method of manufacturing a semiconductor device according to claim 5, wherein before forming the second bond portion, the bonding head is rotated in a plane parallel to the surface of the second metal layer.

7. The method of manufacturing a semiconductor device according to any one of claims 4 to 6, wherein the semiconductor chip is a MOSFET or an IGBT, and the electrode is a gate electrode pad.

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