Semiconductor Chip and Semiconductor Device

Abstract

To provide a highly reliable semiconductor chip.SOLUTION: A semiconductor chip includes: a semiconductor substrate having a plate upper surface and having a first region and a second region which are arranged in a first direction parallel to the substrate upper surface; first wiring provided on the substrate upper surface in the first region; second wiring provided below the substrate upper surface in the second region and having an upper surface being below a lower surface of the first wiring; and a first insulating film provided on the second wiring so as to be separated from the first wiring.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor chip and a semiconductor device.

Background Art

[0002] A pressure-contact type semiconductor device realizes an improvement in power density by double-sided heat dissipation and high reliability under high voltage and large current. The pressure-contact type semiconductor device has a structure in which a plurality of semiconductor chips are sandwiched between upper and lower electrode blocks. By applying an external pressing force to the upper and lower electrode blocks, internal electrical contact is maintained.

[0003] There is a demand for a highly reliable semiconductor device including a semiconductor chip and a pressure-contact type semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a highly reliable semiconductor chip and a semiconductor device.

Means for Solving the Problems

[0006] The semiconductor chip according to the embodiment includes a semiconductor substrate having an upper surface of the substrate and a first region and a second region provided side by side in a first direction parallel to the upper surface of the substrate, a first wiring provided on the upper surface of the substrate in the first region, a second wiring provided under the upper surface of the substrate in the second region and having an upper surface lower than the lower surface of the first wiring, and a first insulating film provided on the second wiring and spaced apart from the first wiring. A third insulating film provided across under the first wiring and under the second wiring It is provided with.

Brief Description of the Drawings

[0007]

Figure 1

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Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

[0009] In this specification, in order to indicate the positional relationship of components and the like, the upward direction of the drawing is described as "up" and the downward direction of the drawing is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms indicating the relationship with the direction of gravity.

[0010] (Embodiment) The semiconductor chip of the embodiment has a semiconductor substrate having an upper surface of the substrate, and a first region and a second region provided side by side in a first direction parallel to the upper surface of the substrate, a first wiring provided on the upper surface of the substrate in the first region, a second wiring provided under the upper surface of the substrate in the second region, the upper surface of which is lower than the lower surface of the first wiring, and a first insulating film provided on the second wiring and spaced apart from the first wiring.

[0011] The semiconductor device of the embodiment includes a first electrode, a first buffer portion provided on the first electrode, a semiconductor chip provided on the first buffer portion, a second buffer portion provided on the first buffer portion, and a second electrode provided on the second buffer portion.

[0012] FIG. 1 is a schematic front view of the semiconductor device 200 of the embodiment.

[0013] The semiconductor device 200 of the embodiment is a pressure-contact type semiconductor device.

[0014] The semiconductor chip 100 of the embodiment is preferably used, for example, in the semiconductor device 200. However, the semiconductor chip 100 is also preferably used in semiconductor devices other than the semiconductor device 200.

[0015] The semiconductor device 200 includes a first electrode 110, a first buffer portion 130, a semiconductor chip 100, a second buffer portion 150, and a second electrode 160.

[0016] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The X direction is an example of the first direction. The Y direction is an example of the second direction.

[0017] The first electrode 110 is an electrode containing a metal such as Cu (copper), for example. The first electrode 110 is a plate-like member, for example. The first electrode 110 is a member having a columnar shape, for example. The first electrode 110 has a first surface 114 and a second surface 116 facing the first surface 114. For example, the first surface 114 and the second surface 116 are provided in a plane perpendicular to the Z axis.

[0018] The first buffer portion 130 is provided on the second surface 116. The first buffer portion 130 is provided to relieve the thermal stress received by the semiconductor chip 100 when the first electrode 110 and the second electrode 160 are pressed against each other in the vertical direction. The first buffer portion 130 contains a conductive metal such as Mo (molybdenum), for example.

[0019] The semiconductor chip 100 is provided on the first buffer portion 130. For example, the semiconductor chip 100 is provided in the same number as the number of the convex portions 162 described later. The semiconductor chip 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor chip 100 is not limited to the IGBT, and may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a diode. For example, in a plane perpendicular to the Z axis or in a plane parallel to the second surface 116, the shape of the semiconductor chip 100 is rectangular. However, the shape of the semiconductor chip 100 in the plane perpendicular to the Z axis is not limited to a rectangle.

[0020] The second electrode 160 has the convex portions 162 and the plate portion 164. The second electrode 160 is an electrode containing a metal such as Cu (copper), for example. The plate portion 164 has the third surface 166 and the fourth surface 168 facing the third surface 166. The third surface 166 faces the second surface 116. Further, the plate portion 164 has a plurality of convex portions 162. The plurality of convex portions 162 are provided between each of the plurality of semiconductor chips 100 and the third surface 166. And the plurality of convex portions 162 are connected to the third surface 166.

[0021] Note that the number of the convex portions 162 is not limited to that shown in FIG. 1.

[0022] For example, when the shape of the semiconductor chip 100 is rectangular, the top surface 162a of the convex portion 162 in a plane perpendicular to the Z axis or in a plane parallel to the second surface 116 has the same rectangular shape as the shape of the semiconductor chip 100.

[0023] The second buffer portion 150 is provided between each semiconductor chip 100 and each convex portion 162. The second buffer portion 150 is provided to relieve the thermal stress received by the semiconductor chip 100 when the first electrode 110 and the second electrode 160 are pressed against each other during the use of the semiconductor device 200. The second buffer portion 150 contains a conductive metal such as Mo (molybdenum). For example, the shape and size of each second buffer portion 150 in the plane perpendicular to the Z-axis are the same as the shape and size of each semiconductor chip 100 in the plane perpendicular to the Z-axis.

[0024] In addition, in FIG. 1, the shape and size of the first buffer portion 130 in the plane perpendicular to the Z-axis are the same as the shape and size of the second surface 116 of the first electrode 110 in the plane perpendicular to the Z-axis. Also, the shape and size of the second buffer portion 150 in the plane perpendicular to the Z-axis are the same as the shape and size of the top surface 162a of the convex portion 162 in the plane perpendicular to the Z-axis. However, the shapes of the first buffer portion 130 and the second buffer portion 150 are not limited to this.

[0025] During the use of the semiconductor device 200, the first electrode 110 and the second electrode 160 are pressed against each other from the vertical direction. Note that the first electrode 110 and the second electrode 160 may be pressed against each other using an electrode block (not shown). Also, a resin support (not shown) may be provided around the semiconductor chip 100, the second buffer portion 150, and the convex portion 162. Further, a ceramic insulating member (not shown) may be provided around the semiconductor device 200.

[0026] FIG. 2 is a schematic top view of the semiconductor chip 100 of the embodiment. The plurality of emitter wirings 90 are provided spaced apart from each other in the X direction. The plurality of emitter wirings 90 are connected to, for example, the emitter electrode of an IGBT. Also, a gate pad 94 is provided. The gate pad 94 is connected to, for example, the gate electrode of an IGBT. Also, regions 10a, 10b, 10c, and 10d are shown.

[0027] FIG. 3 is a schematic cross-sectional view of the semiconductor chip 100 of the embodiment. FIG. 3(a) is a schematic cross-sectional view of the semiconductor chip 100 of the embodiment taken along the A-A' cross-section shown in FIG. 2. FIG. 3(b) is a schematic cross-sectional view of the semiconductor chip 100 of the embodiment taken along the B-B' cross-section shown in FIG. 2.

[0028] The semiconductor chip 100 of the embodiment will be described with reference to FIGS. 2 and 3.

[0029] The semiconductor substrate 2 is, for example, an Si (silicon) substrate having n - -type impurities. Here, the n-type impurity is, for example, P (phosphorus). However, the semiconductor substrate 2 may be an SiC (silicon carbide) substrate, a GaAs (gallium arsenide) substrate, or a GaN (gallium nitride) substrate. The semiconductor substrate 2 has a substrate upper surface 2a. Note that, for example, a drain electrode (not shown) is provided under the semiconductor substrate 2.

[0030] The semiconductor substrate 2 has regions (an example of a first region) 10a, regions (an example of a second region) 10b, and a region 10c arranged in the X direction in a plane parallel to the substrate upper surface 2a. The semiconductor substrate 2 also has regions 10a and 10d (an example of a third region) arranged in the Y direction in a plane parallel to the substrate upper surface 2a.

[0031] The diffusion layer 4 is provided on the substrate upper surface 2a side within the semiconductor substrate 2. The diffusion layer 4 contains, for example, p-type impurities. Here, when the semiconductor substrate 2 is an Si substrate, the p-type impurity is, for example, B (boron). The diffusion layer 4 is provided to alleviate the electric field concentration at the end of the trench 20 described later.

[0032] The trench 20a is provided in the region 10a. The trench 20a reaches the diffusion layer 4 from the substrate upper surface 2a.

[0033] The electrode 6a is provided within the trench 20a. The electrode 6a contains, for example, polysilicon containing a conductive type impurity. The electrode 6a functions as, for example, the emitter electrode of an IGBT.

[0034] Trench 20b is provided in region 10c. Trench 20b reaches the diffusion layer 4 from the upper surface 2a of the substrate.

[0035] Electrode 6b is provided in trench 20b. Electrode 6b includes, for example, polysilicon containing a conductivity type impurity. Electrode 6b functions as, for example, the emitter electrode of the IGBT.

[0036] Trench 20c is provided in region 10a. Trench 20c reaches the diffusion layer 4 from the upper surface 2a of the substrate.

[0037] Electrode 6c is provided in trench 20c. Electrode 6c includes, for example, polysilicon containing a conductivity type impurity. Electrode 6c functions as, for example, the emitter electrode of the IGBT.

[0038] Trench 20d is provided in region 10a. Trench 20d is provided between trench 20a and trench 20b. Trench 20d reaches the diffusion layer 4 from the upper surface 2a of the substrate.

[0039] Trench 20e is provided in region 10c. Trench 20e is provided between trench 20b and trench 20d. Trench 20e reaches the diffusion layer 4 from the upper surface 2a of the substrate.

[0040] Emitter wiring (an example of the first wiring) 90a is provided on the upper surface 2a of the substrate in region 10a. Emitter wiring 90a has, for example, a first portion 92a containing Al (aluminum) and a second portion 94a provided on the first portion 92a and containing Al. Emitter wiring 90a has a side surface 96a, a side surface 96d, an upper surface 98a, and a lower surface 99a. The upper surface 98a of emitter wiring 90a is pressed by the second buffer portion 150 (FIG. 1).

[0041] The emitter wiring 90c is provided on the upper surface 2a of the substrate in the region 10c. The emitter wiring 90c has, for example, a first portion 92c containing Al (aluminum), and a second portion 94c provided on the first portion 92c and containing Al. The emitter wiring 90c has a side surface 96c, an upper surface 98c, and a lower surface 99c. The upper surface 98c of the emitter wiring 90c is pressed against by the second buffer portion 150 (FIG. 1).

[0042] The guard ring electrode 78 is provided on the upper surface 2a of the substrate in the region 10d. The guard ring electrode 78 contains, for example, Al.

[0043] The gate wiring (an example of the second wiring) 80b is provided under the upper surface 2a of the substrate in the region 10b. The gate wiring 80b contains, for example, Al. The gate wiring 80b has an upper surface 82b.

[0044] The gate wiring 80e (an example of the third wiring) is provided under the upper surface 2a of the substrate in the region 10d. The gate wiring 80e is provided between the emitter wiring 90a and the guard ring electrode 78 when the semiconductor chip 100 is viewed from above. The gate wiring 80e contains, for example, Al. The gate wiring 80e has an upper surface 82e.

[0045] The upper surface 82b of the gate wiring 80b is provided below the upper surface 2a of the substrate. The lower surfaces 99a of the emitter wiring 90a and 99c of the emitter wiring 90c are provided above the upper surface 2a of the substrate. And the upper surface 82b of the gate wiring is provided below the lower surfaces 99a of the emitter wiring 90a and 99c of the emitter wiring 90c.

[0046] The upper surface 82e of the gate wiring 80e is provided below the upper surface 2a of the substrate. And the upper surface 82e of the gate wiring is provided below the lower surfaces 99a of the emitter wiring 90a and 99c of the emitter wiring 90c.

[0047] The gate wiring 80b and the gate wiring 80e are connected to the gate electrode of the IGBT.

[0048] The gate wiring 80b and the gate wiring 80e are electrically connected to the gate pad 94 (FIG. 2).

[0049] The gate wiring 80b and the gate wiring 80e are electrically connected to each other.

[0050] The first insulating film 30b is provided over the gate wiring 80b in the region 10b. The first insulating film 30b is provided spaced apart from the emitter wiring 90a and the emitter wiring 90c. The first insulating film 30b includes, for example, polyimide. However, the first insulating film 30b may include other insulating materials.

[0051] The second insulating film 30e is provided over the gate wiring 80e and the guard ring electrode 78 in the region 10d. The second insulating film 30e is provided spaced apart from the emitter wiring 90a. The second insulating film 30e includes, for example, polyimide. However, the second insulating film 30e may include other insulating materials.

[0052] The passivation film 70b (an example of the fourth insulating film) is provided between the gate wiring 80b and the first insulating film 30b. The passivation film 70b includes, for example, SiO X (silicon oxide) or SiN (silicon nitride).

[0053] The passivation film 70e is provided between the gate wiring 80e and the guard ring electrode 78 and the second insulating film 30e. The passivation film 70e includes, for example, SiO X (silicon oxide) or SiN (silicon nitride).

[0054] The polysilicon 12b is provided across within the trench 20d, between the emitter wiring 90a and the upper surface 2a of the substrate, within the diffusion layer 4 under the gate wiring 80b, within the trench 20e, and between the emitter wiring 90c and the upper surface 2a of the substrate. The polysilicon 12b includes, for example, a conductivity type impurity. For example, the gate wiring 80b is connected to the polysilicon 12b.

[0055] Polysilicon 12e is provided between the emitter wiring 90a and the upper surface 2a of the substrate, within the diffusion layer 4 under the gate wiring 80e, and across between the guard ring electrode 78 and the diffusion layer 4. The polysilicon 12e contains, for example, a conductivity type impurity.

[0056] The contact plug 76a is provided between the emitter wiring 90a and the electrode 6a. The contact plug 76a connects the emitter wiring 90a and the electrode 6a. The contact plug 76a contains, for example, W (tungsten).

[0057] The contact plug 76c is provided between the emitter wiring 90c and the electrode 6b. The contact plug 76c connects the emitter wiring 90c and the electrode 6b. The contact plug 76a contains, for example, W.

[0058] The contact plug 76d is provided between the emitter wiring 90a and the electrode 6c. The contact plug 76d connects the emitter wiring 90a and the electrode 6c. The contact plug 76d contains, for example, W.

[0059] The contact plug 76e is provided between the guard ring electrode 78 and the diffusion layer 4. The contact plug 76d connects the guard ring electrode 78 and the diffusion layer 4. The contact plug 76e contains, for example, W.

[0060] The contact plug 76f is provided between the emitter wiring 90a and the diffusion layer 4. The contact plug 76f connects the emitter wiring 90a and the diffusion layer 4. The contact plug 76f contains, for example, W.

[0061] The oxide film 74 is provided between the electrode 6a and the polysilicon 12b and the semiconductor substrate 2 and the diffusion layer 4. Also, the oxide film 74 is provided between the electrode 6c and the polysilicon 12e and the diffusion layer 4. Also, the oxide film 74 is provided between the guard ring electrode 78 and the semiconductor substrate 2. The oxide film 74 contains, for example, silicon oxide.

[0062] The interlayer film 72 is provided between the electrode 6a, the oxide film 74 and the polysilicon 12b and the emitter wiring 90a, between the first insulating film 30b, the passivation film 70b and the gate wiring 80b and the polysilicon 12b, and between the electrode 6b, the oxide film 74 and the polysilicon 12b and the emitter wiring 90c. Further, the interlayer film 72 is provided between the oxide film 74 and the polysilicon 12e and the emitter wiring 90a, between the second insulating film 30e, the passivation film 70e and the gate wiring 80e and the polysilicon 12e, between the guard ring electrode 78 and the polysilicon 12e, and between the guard ring electrode 78 and the oxide film 74. The interlayer film 72 contains, for example, silicon oxide.

[0063] FIG. 4 is a schematic cross-sectional view of a main part of the emitter wiring 90a. An oxide film 97a containing Al is provided between the first portion 92a and the second portion 94a. Such an oxide film 97a is, for example, a natural oxide film of Al formed by natural oxidation of the first portion 92a. Similarly, for the emitter wiring 90c, an oxide film containing Al is provided between the first portion 92c and the second portion 94c. Even if a natural oxide film containing Al is provided, the first portion 92a and the second portion 94a are electrically connected. Also, even if a natural oxide film containing Al is provided, the first portion 92c and the second portion 94c are electrically connected.

[0064] FIGS. 5 to 10 are schematic cross-sectional views showing the manufacturing process of the semiconductor chip of the embodiment.

[0065] First, a diffusion layer 4 containing, for example, a p-type impurity is formed on the semiconductor substrate 2 by, for example, ion implantation. Next, a photoresist P is appropriately formed on the upper surface 2a of the substrate (FIG. 5).

[0066] Next, using the photoresist P as a mask, grooves 88a, 88b, 88c, 88d, 88e, 88f and 88g are formed by, for example, RIE (Reactive Ion Etching) (FIG. 6).

[0067] Next, for example, by LPCVD (Low Pressure Chemical Vapor Deposition), an oxide film 74 is formed in grooves 88a, 88b, 88c, 88d, 88e, 88f, and 88g. Next, on the oxide film 6, polysilicon 12b, 12e containing conductive type impurities, electrode 6a, and electrode 6c are formed by, for example, CVD (Fig. 7).

[0068] Next, for example, by photolithography and etching, holes penetrating the oxide film 74 and the interlayer film 72 are formed. Next, a contact plug 76 containing W is formed in such holes by, for example, CVD.

[0069] Next, for example, by sputtering, a first portion 92a of the emitter wiring 90a, a first portion 92c of the emitter wiring 90c, the gate wiring 80b, and the gate wiring 80e are formed. Next, a passivation film 70 is formed on the first portion 92a of the emitter wiring 90a, the first portion 92c of the emitter wiring 90c, the gate wiring 80b, and the gate wiring 80e by, for example, CVD (Fig. 8).

[0070] Next, for example, by photolithography and RIE, a part of the passivation film 70 is removed (Fig. 9).

[0071] Next, a first insulating film 30b and a second insulating film 30e are formed on the passivation film 70. Next, for example, by sputtering, a second portion 94a is formed on the first portion 92a of the emitter wiring 90a. Also, a second portion 94c is formed on the first portion 92c of the emitter wiring 90c. Thus, the semiconductor chip 100 of the embodiment is obtained.

[0072] Next, the operation and effect of the semiconductor chip of the embodiment will be described.

[0073] Fig. 10 is a schematic cross-sectional view of a semiconductor chip 1000 which is a comparative form of the embodiment. In the semiconductor chip 1000, the gate wiring 80b and the gate wiring 80e are provided on the upper surface 2a of the substrate.

[0074] Due to the self-heating of the semiconductor chip 1000, there was a risk that the emitter wirings 90a and 90c would extend in the X direction, break through the first insulating film 30b and the passivation film 70, and come into contact with the gate wiring 80b.

[0075] In particular, when the semiconductor chip 1000 is used in the semiconductor device 200 which is a pressure-contact type semiconductor device, the upper surfaces 98a of the emitter wiring 90a and the upper surfaces 98c of the emitter wiring 90c are pressure-contacted by the second buffer portion 150. Therefore, in particular, there was a risk that the emitter wiring 90a and the emitter wiring 90c would extend in the X direction.

[0076] Similarly, there was a risk that the emitter wiring 90a would extend in the Y direction and come into contact with the gate wiring 80e.

[0077] Therefore, the semiconductor chip 100 of the embodiment includes a semiconductor substrate 2 having a substrate upper surface 2a and having a region 10a and a region 10b in a plane parallel to the substrate upper surface 2a, an emitter wiring 90a provided on the substrate upper surface 2a of the region 10a, and a gate wiring 80b provided under the substrate upper surface 2a of the region 10b and having an upper surface 82b lower than a lower surface 99a.

[0078] Thereby, even if the emitter wiring 90a and the emitter wiring 90c extend in the X direction, it becomes difficult for contact with the gate wiring 80b to occur. Thus, it is possible to provide a highly reliable semiconductor chip and semiconductor device.

[0079] The semiconductor chip 100 of the embodiment further includes a first insulating film 30b provided on the gate wiring 80b and spaced apart from the emitter wiring 90a and the emitter wiring 90c.

[0080] Thereby, the emitter wiring 90a and the emitter wiring 90c that have extended in the X direction ride on the first insulating film 30b. Therefore, it becomes even more difficult for contact between the emitter wiring 90a and the emitter wiring 90c and the gate wiring 80b to occur. Thus, it is possible to provide an even more highly reliable semiconductor chip and semiconductor device.

[0081] In addition, since it is difficult for the emitter wiring 90 and the gate wiring 80 to come into contact with each other, the distance between the emitter wiring 90 and the gate wiring 80 can be shortened. Therefore, the active area of the semiconductor chip 100 can be made wider.

[0082] When an insulating film is provided on the side surface 96a and the upper surface 98a of the emitter wiring 90a, elongation in the X direction may be induced. By not providing an insulating film on the side surface 96a and the upper surface 98a of the emitter wiring 90a, this can be avoided.

[0083] According to the semiconductor chip and the semiconductor device of the embodiment, it is possible to provide a highly reliable semiconductor chip and semiconductor device.

[0084] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0085] 2: Semiconductor substrate 2a: Upper surface of the substrate 10a: Region (first region) 10b: Region (second region) 10d: Region (third region) 30b: First insulating film 30e: Second insulating film 70b: Passivation film (fourth insulating film) 72: Third insulating film 74: Oxide film 80b: Gate wiring (second wiring) 80e: Gate wiring (third wiring) 82b: Upper surface (upper surface of the second wiring) 82e: Upper surface (upper surface of the third wiring) 90a: Emitter wiring (first wiring) 92a: First part 94a: Second part 96a: Side surface (side surface of the first wiring) 96d: Side surface (side surface of the first wiring) 97: Oxide film 98a: Upper surface (upper surface of the first wiring) 99a: Lower surface (lower surface of the first wiring) 100: Semiconductor chip 110: First electrode 130: First buffer portion 150: Second buffer portion 160: Second electrode 200: Semiconductor device

Claims

1. A semiconductor substrate having a substrate upper surface, and having a first region and a second region provided side by side in a first direction parallel to the substrate upper surface; In the first region, a first wiring provided on the substrate upper surface; In the second region, a second wiring provided under the substrate upper surface, the upper surface of which is lower than the lower surface of the first wiring; A first insulating film provided on the second wiring and spaced apart from the first wiring; A third insulating film provided over the lower part of the first wiring and the lower part of the second wiring; A semiconductor chip comprising the above.

2. A semiconductor substrate having a substrate upper surface, and having a first region and a second region provided side by side in a first direction parallel to the substrate upper surface; In the first region, a first wiring provided on the substrate upper surface; In the second region, a second wiring provided under the substrate upper surface, the upper surface of which is lower than the lower surface of the first wiring; A first insulating film provided on the second wiring and spaced apart from the first wiring; A fourth insulating film provided between the first insulating film and the second wiring and containing an insulating material different from that of the first insulating film; A semiconductor chip comprising the above.

3. No insulating film is provided on the side surface and the upper surface of the first wiring. The semiconductor chip according to Claim 1 or Claim 2.

4. The semiconductor substrate further has a third region provided side by side with the first region in a second direction parallel to the substrate upper surface and intersecting the first direction, The semiconductor chip, In the third region, a third wiring provided under the substrate upper surface, the upper surface of which is lower than the lower surface of the first wiring; A second insulating film provided on the third wiring and spaced apart from the first wiring; The semiconductor chip according to any one of Claims 1 to 3, further comprising the above.

5. A control wiring located under the third insulating film and electrically connected to the second wiring; The semiconductor chip according to Claim 1, further comprising the above.

6. A semiconductor substrate having a substrate upper surface, and having a first region and a second region provided side by side in a first direction parallel to the substrate upper surface; In the first region, a first wiring provided on the substrate upper surface; In the second region, a second wiring provided under the substrate upper surface, the upper surface of which is lower than the lower surface of the first wiring; A first insulating film provided on the second wiring and spaced apart from the first wiring; A third electrode electrically connected to the first wiring and located under the substrate upper surface; A semiconductor chip comprising the above. [

7. ] A first oxide film provided between the third electrode and the semiconductor substrate, further comprising: the third electrode is located within a trench of the semiconductor substrate, the semiconductor chip according to claim 6. [

8. ] the first wiring includes a first portion containing Al, a second portion provided on the first portion and containing Al, and a second oxide film provided between the first portion and the second portion and containing Al oxide, the semiconductor chip according to any one of claims 1 to 7. [

9. ] a first electrode, a first buffer portion provided on the first electrode, the semiconductor chip according to any one of claims 1 to 8 provided on the first buffer portion, a second buffer portion provided on the semiconductor chip, a second electrode provided on the second buffer portion, a semiconductor device comprising.

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