Semiconductor device and semiconductor circuit

Abstract

To provide a semiconductor device capable of reducing turn-on loss including an RC-IGBT having an IGBT and a diode.SOLUTION: A semiconductor device according to an embodiment includes: a transistor region including a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, and a third gate electrode provided in the third trench; a diode region including a fifth trench and a conductive layer provided in the fifth trench; a boundary region including a fourth trench and a fourth gate electrode provided in the fourth trench and provided between the transistor region and the diode region; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor circuit.

Background Art

[0002] As an example of a semiconductor device for power, there is an Insulated Gate Bipolar Transistor (IGBT). In the IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on a collector electrode. Then, a gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region with a gate insulating film interposed therebetween. Further, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, a Reverse-Conducting IGBT (RC-IGBT) in which an IGBT and a freewheeling diode are formed on the same semiconductor chip has been widely developed and commercialized. The RC-IGBT is used, for example, as a switching element in an inverter circuit. The freewheeling diode has a function of flowing a current in the direction opposite to the on-current of the IGBT. Forming the IGBT and the freewheeling diode on the same semiconductor chip has many advantages such as reducing the chip size by sharing the termination region and dispersing the heat generation locations.

[0004] In the RC-IGBT, in many designs, a boundary region that does not include the IGBT and the diode is provided between the transistor region including the IGBT and the diode region including the diode. By providing the boundary region, it is possible to suppress the interference between the operation of the IGBT and the operation of the diode and the deterioration of the element characteristics of the RC-IGBT.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor circuit that include an RC-IGBT having an IGBT and a diode and enable reduction of turn-on loss. [Means for Solving the Problems]

[0007] The semiconductor device of the embodiment includes a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, a fifth semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the third semiconductor region, a first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a first gate electrode provided in the first trench, a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region, a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a second gate electrode provided in the second trench, a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region, a third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a third gate electrode provided in the third trench, a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region, a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region, and provided on the second surface side with respect to the semiconductor layer,A transistor region including a second electrode in contact with the first semiconductor region, the semiconductor layer, the second semiconductor region, a sixth semiconductor region of a second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the second surface, and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region, a seventh semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the first surface, an eighth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the seventh semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the seventh semiconductor region, a fifth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region, a conductive layer provided in the fifth trench, an insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region, a first electrode in contact with the eighth semiconductor region, and a second electrode in contact with the sixth semiconductor region; a diode region including the semiconductor layer, the second semiconductor region, a ninth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the first surface, a tenth semiconductor region of a second conductivity type provided in the semiconductor layer, provided between the ninth semiconductor region and the first surface, an eleventh semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the ninth semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the ninth semiconductor region, provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region, A plurality of a fourth trench, a fourth gate electrode provided in the fourth trench, a fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region, a first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region, and a second electrode, including a boundary region provided between the transistor region and the diode region, a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode e, in a direction from the first surface to the second surface of the plurality of fourth trenches, the second electrode is in contact with the first semiconductor region or the second semiconductor region 。

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] In this specification, when there is notation such as n + type, n-type, n - type, it means that the n-type impurity concentration decreases in the order of n + type, n-type, n - type. Also, when there is notation such as p + type, p-type, p - type, it means that the p-type impurity concentration decreases in the order of p + type, p-type, p - type.

[0011] In this specification, the n-type impurity concentration does not indicate the actual n-type impurity concentration, but the effective n-type impurity concentration after compensation. Similarly, the p-type impurity concentration does not indicate the actual p-type impurity concentration, but the effective p-type impurity concentration after compensation. For example, when the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is taken as the n-type impurity concentration. The same applies to the p-type impurity concentration.

[0012] In this specification, the distribution and absolute value of the impurity concentration in the semiconductor region can be measured, for example, using Secondary Ion Mass Spectrometry (SIMS). Also, the relative magnitude relationship of the impurity concentrations in two semiconductor regions can be determined, for example, using Scanning Capacitance Microscopy (SCM). Further, the distribution and absolute value of the impurity concentration can be measured, for example, using Spreading Resistance Analysis (SRA). In SCM and SRA, the relative magnitude relationship and absolute value of the carrier concentration in the semiconductor region are obtained. By assuming the activation rate of the impurity, it is possible to obtain the relative magnitude relationship between the impurity concentrations in two semiconductor regions, the distribution of the impurity concentration, and the absolute value of the impurity concentration from the measurement results of SCM and SRA.

[0013] In this specification, for the sake of convenience in operation description, in a semiconductor device, the transistor portion driven using the first gate electrode may be expressed as "the transistor having the first gate electrode". Similarly, the transistor portion driven using the second gate electrode may be expressed as "the transistor having the second gate electrode", the transistor portion driven using the third gate electrode may be expressed as "the transistor having the third gate electrode", and the transistor portion driven using the fourth gate electrode may be expressed as "the transistor having the fourth gate electrode".

[0014] (First Embodiment) The semiconductor device of the first embodiment includes a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, a fifth semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the third semiconductor region, a first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a first gate electrode provided in the first trench, a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region, a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a second gate electrode provided in the second trench, a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region, a third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a third gate electrode provided in the third trench, a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region, a first electrode provided on the first surface side with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region, a second electrode provided on the second surface side with respect to the semiconductor layer and in contact with the first semiconductor region, a transistor region including, a semiconductor layer, a second semiconductor region, provided in the semiconductor layer and provided between the second semiconductor region and the second surface, having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region,A sixth semiconductor region of a second conductivity type, a seventh semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, an eighth semiconductor region of a first conductivity type provided in the semiconductor layer and between the seventh semiconductor region and the first surface and having a higher first conductivity type impurity concentration than that of the seventh semiconductor region, a fifth trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region, a conductive layer provided in the fifth trench, an insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region, a first electrode in contact with the eighth semiconductor region, a second electrode in contact with the sixth semiconductor region, a diode region including the above; a semiconductor layer; a second semiconductor region; a ninth semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; a tenth semiconductor region of a second conductivity type provided in the semiconductor layer and between the ninth semiconductor region and the first surface; an eleventh semiconductor region of a first conductivity type provided in the semiconductor layer and between the ninth semiconductor region and the first surface and having a higher first conductivity type impurity concentration than that of the ninth semiconductor region; a fourth trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region; a fourth gate electrode provided in the fourth trench; a fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region; a first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region; a second electrode; a boundary region provided between the transistor region and the diode region; a first electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode.

[0015] The semiconductor circuit according to the first embodiment includes a control circuit that drives the semiconductor device.

[0016] The semiconductor device of the first embodiment is an RC-IGBT 100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT 100 has a trench gate type IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

[0017] The control circuit of the first embodiment is a gate driver circuit 150. The semiconductor circuit of the first embodiment includes a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which the RC-IGBT 100 and the gate driver circuit 150 are mounted.

[0018] FIG. 1 is a schematic diagram of the semiconductor circuit of the first embodiment.

[0019] FIG. 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. FIG. 2 is a cross-section taken along line AA' in FIG. 1.

[0020] FIG. 3 is a schematic top view of a part of the semiconductor device of the first embodiment. FIG. 3 is a top view on the first surface F1. FIG. 2 is a cross-section taken along line AA' in FIG. 3.

[0021] FIG. 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. FIG. 4 is a cross-section taken along line BB' in FIG. 3.

[0022] FIG. 5 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. FIG. 5 is a cross-section taken along line CC' in FIG. 3.

[0023] The semiconductor circuit of the first embodiment includes an RC-IGBT 100 and a gate driver circuit 150. The RC-IGBT 100 has a transistor region 101, a diode region 102, and a boundary region 103. The boundary region 103 is provided between the transistor region 101 and the diode region 102.

[0024] The RC-IGBT 100 is an example of a semiconductor device. The gate driver circuit 150 is an example of a control circuit.

[0025] The transistor region 101 operates as an IGBT. The diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0026] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a fourth gate insulating film 44, a diode insulating film 45 (insulating film), a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, a fourth gate electrode 54, a diode conductive layer 55 (conductive layer), a first interlayer insulating layer 61, a second interlayer insulating layer 62, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0027] In the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a fourth gate trench 24 (fourth trench), a diode trench 25 (fifth trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a cell base region 28 (third semiconductor region), a cell emitter region 29 (fourth semiconductor region), a cell contact region 30 (fifth semiconductor region), a cathode region 31 (sixth semiconductor region), an anode region 32 (seventh semiconductor region), a diode contact region 33 (eighth semiconductor region), a boundary base region 34 (ninth semiconductor region), a boundary emitter region 35 (tenth semiconductor region), and a boundary contact region 36 (eleventh semiconductor region) are provided.

[0028] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0029] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. Also, a direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. Also, in this specification, "depth" is defined as the distance in the direction toward the second surface F2 with reference to the first surface F1.

[0030] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, and a first interlayer insulating layer 61.

[0031] In the semiconductor layer 10 of the transistor region 101, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a cell base region 28 (third semiconductor region), a cell emitter region 29 (fourth semiconductor region), and a cell contact region 30 (fifth semiconductor region) are provided.

[0032] The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a part of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0033] In the transistor region 101, the upper electrode 12 functions as an emitter electrode of an IGBT. The upper electrode 12 is, for example, a metal.

[0034] The upper electrode 12 is in contact with the cell emitter region 29. The upper electrode 12 is electrically connected to the cell emitter region 29.

[0035] The upper electrode 12 is in contact with the cell contact region 30. The upper electrode 12 is electrically connected to the cell contact region 30. The upper electrode 12 is electrically connected to the cell base region 28 via the cell contact region 30.

[0036] The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. At least a part of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0037] In the transistor region 101, the lower electrode 14 functions as the collector electrode of the IGBT. The lower electrode 14 is, for example, made of metal.

[0038] In the transistor region 101, the lower electrode 14 is in contact with the collector region 26. In the transistor region 101, the lower electrode 14 is electrically connected to the collector region 26.

[0039] The collector region 26 is a p + -type semiconductor region. The collector region 26 is in contact with the second surface F2. The collector region 26 is electrically connected to the lower electrode 14. The collector region 26 is in contact with the lower electrode 14. The collector region 26 serves as a source of holes when the IGBT is in the on state.

[0040] The drift region 27 is an n - -type semiconductor region. The drift region 27 is provided between the collector region 26 and the first surface F1.

[0041] The drift region 27 serves as a path for the on-current when the IGBT is in the on state. The drift region 27 depletes when the IGBT is in the off state and has the function of maintaining the breakdown voltage of the IGBT.

[0042] The cell base region 28 is a p-type semiconductor region. The cell base region 28 is provided between the drift region 27 and the first surface F1. The cell base region 28 sandwiches the drift region 27 between it and the collector region 26.

[0043] The depth of the cell base region 28 is, for example, 5 μm or less. In the regions of the cell base region 28 facing the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53, an n-type inversion layer is formed when the IGBT is in the on state. The cell base region 28 functions as the channel region of the transistor.

[0044] The cell emitter region 29 is an n + -type semiconductor region. The cell emitter region 29 is provided between the cell base region 28 and the first surface F1.

[0045] The cell emitter region 29 is in contact with the first gate insulating film 41, the second gate insulating film 42, and the third gate insulating film 43.

[0046] The n-type impurity concentration of the cell emitter region 29 is higher than that of the drift region 27.

[0047] The cell emitter region 29 is in contact with the upper electrode 12. The cell emitter region 29 is electrically connected to the upper electrode 12. The cell emitter region 29 serves as a source of electrons when the transistors having the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 are in the on state.

[0048] The cell contact region 30 is a p + -type semiconductor region. The cell contact region 30 is provided between the cell base region 28 and the first surface F1. The cell contact region 30 is in contact with the upper electrode 12. The cell contact region 30 is electrically connected to the upper electrode 12.

[0049] The p-type impurity concentration of the cell contact region 30 is higher than that of the cell base region 28.

[0050] The first gate trench 21 is provided on the side of the first surface F1 of the semiconductor layer 10. The first gate trench 21 is a groove provided in the semiconductor layer 10. The first gate trench 21 is part of the semiconductor layer 10.

[0051] As shown in FIG. 3, the first gate trench 21 extends in a first direction parallel to the first surface F1 on the first surface F1. The first gate trench 21 has a stripe shape. A plurality of first gate trenches 21 are repeatedly arranged in a second direction orthogonal to the first direction.

[0052] The first gate trench 21 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The first gate trench 21 penetrates the cell base region 28 and reaches the drift region 27. The depth of the first gate trench 21 is, for example, 8 μm or less.

[0053] The first gate electrode 51 is provided in the first gate trench 21. The first gate electrode 51 is, for example, a semiconductor or a metal. The first gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing an n-type impurity or a p-type impurity. The first gate electrode 51 is electrically connected to the first gate electrode pad 104.

[0054] The first gate insulating film 41 is provided between the first gate electrode 51 and the semiconductor layer 10. The first gate insulating film 41 is provided between the first gate electrode 51 and the drift region 27, between the first gate electrode 51 and the cell base region 28, and between the first gate electrode 51 and the cell emitter region 29. The first gate insulating film 41 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The first gate insulating film 41 is, for example, silicon oxide.

[0055] The second gate trench 22 is provided on the side of the first surface F1 of the semiconductor layer 10. The second gate trench 22 is a groove provided in the semiconductor layer 10. The second gate trench 22 is part of the semiconductor layer 10.

[0056] As shown in FIG. 3, the second gate trench 22 extends in a first direction parallel to the first surface F1 on the first surface F1. The second gate trench 22 has a stripe shape. A plurality of second gate trenches 22 are repeatedly arranged in a second direction orthogonal to the first direction.

[0057] The second gate trench 22 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The second gate trench 22 penetrates the cell base region 28 and reaches the drift region 27. The depth of the second gate trench 22 is, for example, 8 μm or less.

[0058] The second gate electrode 52 is provided in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 52 is electrically connected to the second gate electrode pad 105.

[0059] The second gate insulating film 42 is provided between the second gate electrode 52 and the semiconductor layer 10. The second gate insulating film 42 is provided between the second gate electrode 52 and the drift region 27, between the second gate electrode 52 and the cell base region 28, and between the second gate electrode 52 and the cell emitter region 29. The second gate insulating film 42 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The second gate insulating film 42 is, for example, silicon oxide.

[0060] The third gate trench 23 is provided on the side of the first surface F1 of the semiconductor layer 10. The third gate trench 23 is a groove provided in the semiconductor layer 10. The third gate trench 23 is a part of the semiconductor layer 10.

[0061] As shown in FIG. 3, the third gate trench 23 extends in a first direction parallel to the first surface F1 on the first surface F1. The third gate trench 23 has a stripe shape. A plurality of third gate trenches 23 are repeatedly arranged in a second direction orthogonal to the first direction.

[0062] In the transistor region 101, the number of the third gate trenches 23 is, for example, larger than the number of the first gate trenches 21.

[0063] The third gate trench 23 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The third gate trench 23 penetrates the cell base region 28 and reaches the drift region 27. The depth of the third gate trench 23 is, for example, 8 μm or less.

[0064] The third gate electrode 53 is provided in the third gate trench 23. The third gate electrode 53 is, for example, a semiconductor or a metal. The third gate electrode 53 is, for example, amorphous silicon or polycrystalline silicon containing an n-type impurity or a p-type impurity. The third gate electrode 53 is electrically connected to the third gate electrode pad 106.

[0065] The third gate insulating film 43 is provided between the third gate electrode 53 and the semiconductor layer 10. The third gate insulating film 43 is provided between the third gate electrode 53 and the drift region 27, between the third gate electrode 53 and the cell base region 28, and between the third gate electrode 53 and the cell emitter region 29. The third gate insulating film 43 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The third gate insulating film 43 is, for example, silicon oxide.

[0066] The first interlayer insulating layer 61 is provided between the first gate electrode 51 and the upper electrode 12. The first interlayer insulating layer 61 electrically separates the first gate electrode 51 and the upper electrode 12. The first interlayer insulating layer 61 is provided between the second gate electrode 52 and the upper electrode 12. The first interlayer insulating layer 61 electrically separates the second gate electrode 52 and the upper electrode 12. The first interlayer insulating layer 61 is provided between the third gate electrode 53 and the upper electrode 12. The first interlayer insulating layer 61 electrically separates the third gate electrode 53 and the upper electrode 12. The first interlayer insulating layer 61 is, for example, silicon oxide.

[0067] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a diode insulating film 45 (insulating film), a diode conductive layer 55 (conductive layer), and a second interlayer insulating layer 62.

[0068] In the semiconductor layer 10 of the diode region 102, a cathode region 31 (sixth semiconductor region), a drift region 27 (second semiconductor region), an anode region 32 (seventh semiconductor region), and a diode contact region 33 (eighth semiconductor region) are provided.

[0069] In the diode region 102, the upper electrode 12 functions as the anode electrode of the diode. The upper electrode 12 is in contact with the diode contact region 33. The upper electrode 12 is electrically connected to the diode contact region 33. The upper electrode 12 is electrically connected to the anode region 32 via the diode contact region 33. Alternatively, the upper electrode 12 may be in direct contact with the anode region 32. In this case, for example, the anode region 32 and the anode region 32 have a Schottky junction.

[0070] In the diode region 102, the lower electrode 14 functions as the cathode electrode of the diode. The lower electrode 14 is in contact with the collector region 26.

[0071] The cathode region 31 is n +It is an n-type semiconductor region. The cathode region 31 is in contact with the second surface F2. The cathode region 31 serves as a source of electrons when the diode is in the on state. The cathode region 31 is in contact with the lower electrode 14.

[0072] The drift region 27 is an n - -type semiconductor region. The drift region 27 is provided between the cathode region 31 and the first surface F1. The n-type impurity concentration of the drift region 27 is lower than that of the cathode region 31.

[0073] The drift region 27 serves as a path for the on-current when the diode is in the on state.

[0074] The anode region 32 is a p-type semiconductor region. The anode region 32 is provided between the drift region 27 and the first surface F1. The anode region 32 sandwiches the drift region 27 between it and the cathode region 31.

[0075] The anode region 32 serves as a source of holes when the diode is in the on state.

[0076] The p-type impurity concentration of the anode region 32 is lower than, for example, that of the cell base region 28. The p-type impurity concentration of the anode region 32 is lower than, for example, that of the boundary base region 34. The depth of the anode region 32 is the same as, for example, the depths of the cell base region 28 and the boundary base region 34.

[0077] The diode contact region 33 is a p + -type semiconductor region. The diode contact region 33 is provided between the anode region 32 and the first surface F1.

[0078] The diode contact region 33 is in contact with the upper electrode 12. The diode contact region 33 is electrically connected to the upper electrode 12.

[0079] The p-type impurity concentration of the diode contact region 33 is higher than that of the anode region 32.

[0080] The diode trench 25 is provided in contact with the anode region 32 on the side of the first surface F1 of the semiconductor layer 10. The diode trench 25 is a groove provided in the semiconductor layer 10. The diode trench 25 is part of the semiconductor layer 10.

[0081] As shown in FIG. 3, the diode trench 25 extends in a first direction parallel to the first surface F1 on the first surface F1. The diode trench 25 has a stripe shape. A plurality of diode trenches 25 are repeatedly arranged in a second direction orthogonal to the first direction.

[0082] The diode trench 25 is in contact with the drift region 27 and the anode region 32. The diode trench 25 penetrates the anode region 32 and reaches the drift region 27. The depth of the diode trench 25 is, for example, 8 μm or less.

[0083] The diode conductive layer 55 is provided in the diode trench 25. The diode conductive layer 55 is, for example, a semiconductor or a metal. The diode conductive layer 55 is, for example, amorphous silicon or polycrystalline silicon containing an n-type impurity or a p-type impurity. The diode conductive layer 55 is electrically connected to the upper electrode 12, for example.

[0084] Note that it is also possible to set the diode conductive layer 55 in a floating state without fixing it to a specific potential. It is also possible to connect the diode conductive layer 55 to an electrode other than the upper electrode 12 and apply a voltage different from that of the upper electrode 12 to the diode conductive layer 55.

[0085] The diode insulating film 45 is provided between the diode conductive layer 55 and the semiconductor layer 10. The diode insulating film 45 is provided between the diode conductive layer 55 and the drift region 27 and between the diode conductive layer 55 and the anode region 32. The diode insulating film 45 is in contact with the drift region 27 and the anode region 32. The diode insulating film 45 is, for example, silicon oxide.

[0086] The second interlayer insulating layer 62 is provided between the diode conductive layer 55 and the upper electrode 12. For example, the diode conductive layer 55 and the upper electrode 12 are electrically connected using an opening provided in the second interlayer insulating layer 62.

[0087] The boundary region 103 includes the semiconductor layer 10, the upper electrode 12 (first electrode), the lower electrode 14 (second electrode), the fourth gate insulating film 44, the fourth gate electrode 54, and the first interlayer insulating layer 61.

[0088] In the semiconductor layer 10 of the boundary region 103, a fourth gate trench 24 (fourth trench), a drift region 27 (second semiconductor region), a boundary base region 34 (ninth semiconductor region), a boundary emitter region 35 (tenth semiconductor region), and a boundary contact region 36 (eleventh semiconductor region) are provided.

[0089] In the boundary region 103, the upper electrode 12 functions as the emitter electrode of the IGBT. The upper electrode 12 is in contact with the boundary emitter region 35. The upper electrode 12 is electrically connected to the boundary emitter region 35. The upper electrode 12 is electrically connected to the boundary base region 34 via the boundary emitter region 35.

[0090] In the boundary region 103, the lower electrode 14 is in contact with the drift region 27. The drift region 27 is an n - -type semiconductor region.

[0091] The drift region 27 serves as a path for the on-current when the IGBT is in the on state. The drift region 27 depletes when the IGBT is in the off state and has a function of maintaining the breakdown voltage of the IGBT.

[0092] The boundary base region 34 is a p-type semiconductor region. The boundary base region 34 is provided between the drift region 27 and the first surface F1. The boundary base region 34 sandwiches the drift region 27 between it and the second surface F2.

[0093] The depth of the boundary base region 34 is, for example, 5 μm or less. In the region of the boundary base region 34 facing the fourth gate electrode 54, an n-type inversion layer is formed when the IGBT is in the on state. The boundary base region 34 functions as the channel region of the transistor.

[0094] The p-type impurity concentration of the boundary base region 34 is, for example, lower than the p-type impurity concentration of the cell base region 28. The p-type impurity concentration of the boundary base region 34 is, for example, the same as the p-type impurity concentration of the anode region 32. The depth of the boundary base region 34 is, for example, the same as the depths of the cell base region 28 and the anode region 32.

[0095] The boundary emitter region 35 is an n + -type semiconductor region. The boundary emitter region 35 is provided between the boundary base region 34 and the first surface F1.

[0096] The boundary emitter region 35 is in contact with the fourth gate insulating film 44. The n-type impurity concentration of the boundary emitter region 35 is higher than the n-type impurity concentration of the drift region 27.

[0097] The boundary emitter region 35 is in contact with the upper electrode 12. The boundary emitter region 35 is electrically connected to the upper electrode 12. The boundary emitter region 35 serves as a source of electrons when the transistor having the fourth gate electrode 54 is in the on state.

[0098] The boundary contact region 36 is a p + -type semiconductor region. The boundary contact region 36 is provided between the boundary base region 34 and the first surface F1. The boundary contact region 36 is in contact with the upper electrode 12. The boundary base region 34 is electrically connected to the upper electrode 12.

[0099] The p-type impurity concentration of the boundary contact region 36 is higher than the p-type impurity concentration of the boundary base region 34.

[0100] For example, as shown in FIG. 3, the occupied area ratio of the boundary contact region 36 on the first surface F1 of the boundary region 103 is smaller than the occupied area ratio of the cell contact region 30 on the first surface F1 of the transistor region 101. For example, the occupied area ratio of the boundary contact region 36 on the first surface F1 of the boundary region 103 is equal to or less than one-half of the occupied area ratio of the cell contact region 30 on the first surface F1 of the transistor region 101.

[0101] The fourth gate trench 24 is provided on the side of the first surface F1 of the semiconductor layer 10. The fourth gate trench 24 is a trench provided in the semiconductor layer 10. The fourth gate trench 24 is part of the semiconductor layer 10.

[0102] As shown in FIG. 3, the fourth gate trench 24 extends in a first direction parallel to the first surface F1 on the first surface F1. The fourth gate trench 24 has a stripe shape. A plurality of fourth gate trenches 24 are repeatedly arranged in a second direction orthogonal to the first direction.

[0103] The fourth gate trench 24 is in contact with the drift region 27, the boundary base region 34, and the boundary emitter region 35. The fourth gate trench 24 penetrates the boundary base region 34 and reaches the drift region 27. The depth of the fourth gate trench 24 is, for example, 8 μm or less.

[0104] The fourth gate electrode 54 is provided in the fourth gate trench 24. The fourth gate electrode 54 is, for example, a semiconductor or a metal. The fourth gate electrode 54 is, for example, amorphous silicon or polycrystalline silicon containing an n-type impurity or a p-type impurity. The fourth gate electrode 54 is electrically connected to the third gate electrode pad 106.

[0105] For example, as shown in FIG. 3, the occupied area ratio of the fourth gate electrode 54 in a cross section parallel to the first surface F1 of the boundary region 103 is larger than the occupied area ratio of the third gate electrode 53 in the above cross section of the transistor region 101. FIG. 3 shows a case where the cross section parallel to the first surface F1 coincides with the first surface F1.

[0106] For example, the density of the fourth gate trench 24 occupying the boundary region 103 is larger than the density of the third trench occupying the transistor region 101. For example, the density of the transistor having the fourth gate electrode 54 occupying the boundary region 103 is larger than the density of the transistor having the third gate electrode 53 occupying the transistor region 101.

[0107] The fourth gate insulating film 44 is provided between the fourth gate electrode 54 and the semiconductor layer 10. The fourth gate insulating film 44 is provided between the fourth gate electrode 54 and the drift region 27, between the fourth gate electrode 54 and the boundary base region 34, and between the fourth gate electrode 54 and the boundary emitter region 35. The fourth gate insulating film 44 is in contact with the drift region 27, the boundary base region 34, and the boundary emitter region 35. The fourth gate insulating film 44 is, for example, silicon oxide.

[0108] The first interlayer insulating layer 61 is provided between the fourth gate electrode 54 and the upper electrode 12. The first interlayer insulating layer 61 electrically separates between the fourth gate electrode 54 and the upper electrode 12.

[0109] The first gate electrode pad 104 is provided on the side of the first surface F1 of the semiconductor layer 10. The first gate electrode pad 104 is electrically connected to the first gate electrode 51. The first gate electrode pad 104 and the first gate electrode 51 are connected by, for example, a metal wiring (not shown).

[0110] A first gate voltage (Vg1) is applied to the first gate electrode pad 104. For example, a first turn-on voltage (Von1) and a first turn-off voltage (Voff1) are applied to the first gate electrode pad 104.

[0111] The second gate electrode pad 105 is provided on the side of the first surface F1 of the semiconductor layer 10. The second gate electrode pad 105 is electrically connected to the second gate electrode 52. The second gate electrode pad 105 and the second gate electrode 52 are connected by, for example, a metal wiring (not shown).

[0112] A second gate voltage (Vg2) is applied to the second gate electrode pad 105. For example, a second turn-on voltage (Von2) and a second turn-off voltage (Voff2) are applied to the second gate electrode pad 105.

[0113] The third gate electrode pad 106 is provided on the side of the first surface F1 of the semiconductor layer 10. The third gate electrode pad 106 is electrically connected to the third gate electrode 53 and the fourth gate electrode 54. The third gate electrode pad 106 and the third gate electrode 53 and the fourth gate electrode 54 are connected by, for example, a metal wiring (not shown).

[0114] A third gate voltage (Vg3) is applied to the third gate electrode pad 106. For example, a third turn-on voltage (Von3) and a third turn-off voltage (Voff3) are applied to the third gate electrode pad 106.

[0115] The gate driver circuit 150 is provided, for example, on the same circuit board as the RC-IGBT 100 or on a different circuit board. The gate driver circuit 150 has a function of driving the RC-IGBT 100.

[0116] The gate driver circuit 150 has a function of applying a desired first gate voltage (Vg1), a desired second gate voltage (Vg2), and a desired third gate voltage (Vg3) to the first gate electrode pad 104, the second gate electrode pad 105, and the third gate electrode pad 106 at a desired timing.

[0117] The gate driver circuit 150 applies a first turn-on voltage (Von1) to the first gate electrode pad 104, a second turn-on voltage (Von2) to the second gate electrode pad 105, a third turn-on voltage (Von3) to the third gate electrode pad 106, a first turn-on voltage (Von1) to the first gate electrode pad 104, a second turn-on voltage (Von2) to the second gate electrode pad 105, and a third turn-on voltage (Von3) to the third gate electrode pad 106. After that, a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106. After applying the third turn-off voltage (Voff3) to the third gate electrode pad 106, a second turn-off voltage (Voff2) is applied to the second gate electrode pad 105. After applying the second turn-off voltage (Voff2) to the second gate electrode pad 105, a first turn-off voltage (Voff1) is applied to the first gate electrode pad 104.

[0118] Next, a method for driving the RC-IGBT 100, particularly a method for driving the IGBTs in the transistor region 101 and the boundary region 103, will be described.

[0119] FIG. 6 is an explanatory diagram of a method for driving a semiconductor device according to the first embodiment. FIG. 6 is a timing chart of a first gate voltage (Vg1) applied to the first gate electrode pad 104, a second gate voltage (Vg2) applied to the second gate electrode pad 105, and a third gate voltage (Vg3) applied to the third gate electrode pad 106.

[0120] In the off state of the IGBT, for example, an emitter voltage is applied to the upper electrode 12. The emitter voltage is, for example, 0V. A collector voltage is applied to the lower electrode 14. The collector voltage is, for example, 200V or more and 6500V or less.

[0121] In the off state of the IGBT, a first turn-off voltage (Voff1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-off voltage (Voff1). Accordingly, the first turn-off voltage (Voff1) is also applied to the first gate electrode 51.

[0122] The first turn-off voltage (Voff1) is a voltage less than the threshold voltage at which the transistor having the first gate electrode 51 does not turn on, and is, for example, 0 V or a negative voltage.

[0123] In the off state, an n-type inversion layer is not formed in the cell base region 28 that faces the first gate electrode 51 and is in contact with the first gate insulating film 41.

[0124] In the off state of the IGBT, a second turn-off voltage (Voff2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-off voltage (Voff2). Accordingly, the second turn-off voltage (Voff2) is also applied to the second gate electrode 52.

[0125] The second turn-off voltage (Voff2) is a voltage less than the threshold voltage at which the transistor having the second gate electrode 52 does not turn on, and is, for example, 0 V or a negative voltage.

[0126] In the off state, an n-type inversion layer is not formed in the cell base region 28 that faces the second gate electrode 52 and is in contact with the second gate insulating film 42.

[0127] In the off state of the IGBT, a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-off voltage (Voff3). Accordingly, the third turn-off voltage (Voff3) is also applied to the third gate electrode 53.

[0128] The third turn-off voltage (Voff3) is a voltage less than the threshold voltage at which the transistor having the third gate electrode 53 does not turn on, and is, for example, 0V.

[0129] In the off state, an n-type inversion layer is not formed in the cell base region 28 that faces the third gate electrode 53 and is in contact with the third gate insulating film 43.

[0130] The third gate electrode pad 106 is also electrically connected to the fourth gate electrode 54 in the boundary region 103. Therefore, in the off state of the IGBT, the third turn-off voltage (Voff3) is also applied to the fourth gate electrode 54.

[0131] The third turn-off voltage (Voff3) is a voltage less than the threshold voltage at which the transistor having the fourth gate electrode 54 does not turn on.

[0132] In the off state, an n-type inversion layer is not formed in the boundary base region 34 that faces the fourth gate electrode 54 and is in contact with the fourth gate insulating film 44.

[0133] At time t1, a first turn-on voltage (Von1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-on voltage (Von1). The first turn-on voltage (Von1) is also applied to the first gate electrode 51.

[0134] The first turn-on voltage (Von1) is a positive voltage that exceeds the threshold voltage of the transistor having the first gate electrode 51. The first turn-on voltage (Von1) is, for example, 15V. By applying the first turn-on voltage (Von1) to the first gate electrode 51, the transistor having the first gate electrode 51 turns on after time t1.

[0135] In the on state, an n-type inversion layer is formed in the cell base region 28 that faces the first gate electrode 51 and is in contact with the first gate insulating film 41.

[0136] At time t1, a second turn-on voltage (Von2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-on voltage (Von2). The second turn-on voltage (Von2) is also applied to the second gate electrode 52.

[0137] The second turn-on voltage (Von2) is a positive voltage that exceeds the threshold voltage of the transistor having the second gate electrode 52. The second turn-on voltage (Von2) is, for example, 15V. By applying the second turn-on voltage (Von2) to the second gate electrode 52, the transistor having the second gate electrode 52 becomes on after time t1.

[0138] In the on state, an n-type inversion layer is formed in the cell base region 28 that faces the second gate electrode 52 and is in contact with the second gate insulating film 42.

[0139] At time t1, a third turn-on voltage (Von3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-on voltage (Von3). The third turn-on voltage (Von3) is also applied to the third gate electrode 53.

[0140] The third turn-on voltage (Von3) is a positive voltage that exceeds the threshold voltage of the transistor having the third gate electrode 53. The third turn-on voltage (Von3) is, for example, 15V. By applying the third turn-on voltage (Von3) to the third gate electrode 53, the transistor having the third gate electrode 53 becomes on after time t1.

[0141] In the on state, an n-type inversion layer is formed in the cell base region 28 that faces the third gate electrode 53 and is in contact with the third gate insulating film 43.

[0142] At time t1, the third turn-on voltage (Von3) is also applied to the fourth gate electrode 54 in the boundary region 103.

[0143] The third turn-on voltage (Von3) is a positive voltage exceeding the threshold voltage of the transistor having the fourth gate electrode 54. By applying the third turn-on voltage (Von3) to the fourth gate electrode 54, the transistor having the fourth gate electrode 54 in the boundary region 103 turns on after time t1.

[0144] In the on state, an n-type inversion layer is formed in the boundary base region 34 facing the fourth gate electrode 54 and in contact with the fourth gate insulating film 44.

[0145] After time t1, the IGBTs in the transistor region 101 and the boundary region 103 turn on.

[0146] At time t2, a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-off voltage (Voff3). The third turn-off voltage (Voff3) is also applied to the third gate electrode 53 and the fourth gate electrode 54.

[0147] By applying the third turn-off voltage (Voff3) to the third gate electrode 53, the transistor having the third gate electrode 53 turns off after time t2. By applying the third turn-off voltage (Voff3) to the fourth gate electrode 54, the transistor having the fourth gate electrode 54 in the boundary region 103 turns off after time t2.

[0148] At time t3, a second turn-off voltage (Voff2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-off voltage (Voff2). The second turn-off voltage (Voff2) is also applied to the second gate electrode 52.

[0149] By applying the second turn-off voltage (Voff2) to the second gate electrode 52, the transistor having the second gate electrode 52 turns off after time t3.

[0150] For example, when the second turn-off voltage (Voff2) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the second gate insulating film 42. The second turn-off voltage (Voff2) is, for example, not less than -15V and less than 0V.

[0151] FIG. 7 is an explanatory diagram of a first modification of a driving method of the semiconductor device according to the first embodiment. As shown in FIG. 7, at time t3, the second turn-off voltage (Voff2) may be applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the second turn-off voltage (Voff2). The second turn-off voltage (Voff2) is also applied to the third gate electrode 53 and the fourth gate electrode 54. Then, when the second turn-off voltage (Voff2) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the third gate insulating film 43 and the fourth gate insulating film 44. The second turn-off voltage (Voff2) is, for example, not less than -15V and less than 0V.

[0152] At time t4, the first turn-off voltage (Voff1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-off voltage (Voff1). The first turn-off voltage (Voff1) is also applied to the first gate electrode 51.

[0153] By applying the first turn-off voltage (Voff1) to the first gate electrode 51, the transistor having the first gate electrode 51 is turned off after time t4.

[0154] For example, when the first turn-off voltage (Voff1) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the first gate insulating film 41. The first turn-off voltage (Voff1) is, for example, not less than -15V and less than 0V.

[0155] FIG. 8 is an explanatory diagram of a second modification of the driving method of the semiconductor device according to the first embodiment. As shown in FIG. 8, at time t4, a first turn-off voltage (Voff1) may be applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the first turn-off voltage (Voff1). The first turn-off voltage (Voff1) is also applied to the third gate electrode 53 and the fourth gate electrode 54. When the first turn-off voltage (Voff1) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the third gate insulating film 43 and the fourth gate insulating film 44. The first turn-off voltage (Voff1) is, for example, -15V or more and less than 0V.

[0156] After time t4, all of the transistor having the first gate electrode 51, the transistor having the second gate electrode 52, the transistor having the third gate electrode 53, and the transistor having the fourth gate electrode 54 are in the off state.

[0157] Next, the operations and effects of the semiconductor device and the semiconductor circuit according to the first embodiment will be described.

[0158] The RC-IGBT 100 according to the first embodiment includes, in the transistor region 101, a transistor having a first gate electrode 51, a transistor having a second gate electrode 52, and a transistor having a third gate electrode 53. And each transistor can be driven independently. With this configuration, the turn-on loss and the turn-off loss of the RC-IGBT 100 can be reduced.

[0159] Furthermore, the RC-IGBT 100 includes, in the boundary region 103, a transistor having a fourth gate electrode 54. The transistor having the fourth gate electrode 54 is driven simultaneously with the transistor having the third gate electrode 53. With this configuration, the turn-on loss of the RC-IGBT 100 can be further reduced. This will be described in detail below.

[0160] At time t1, the transistors having the first gate electrode 51, the transistors having the second gate electrode 52, and the transistors having the third gate electrode 53 all enter the on operation and become in the on state. In the transistor region 101, electrons are injected from the cell emitter region 29 into the drift region 27. Correspondingly, holes are injected from the collector region 26 into the drift region 27, so that the transistors having the first gate electrode 51, the transistors having the second gate electrode 52, and the transistors having the third gate electrode 53 all become in the on state.

[0161] For example, compared with the case where the transistors having the third gate electrode 53 are not provided, the amount of electrons injected from the cell emitter region 29 into the drift region 27 increases, and correspondingly, the amount of holes injected from the collector region 26 into the drift region 27 also increases. Therefore, the turn-on time of the RC-IGBT 100 can be shortened. Thus, the turn-on loss of the RC-IGBT 100 is reduced.

[0162] At time t2, the transistors having the third gate electrode 53 enter the off operation and become in the off state. The injection of electrons into the drift region 27 by the transistors having the third gate electrode 53 stops. After time t2, the transistors having the third gate electrode 53 will function as dummy gates that do not contribute to the injection of electrons.

[0163] Since the injection of electrons into the drift region 27 by the transistors having the third gate electrode 53 stops, the carrier density on the cell emitter region 29 side of the drift region 27 decreases. Therefore, the saturation current of the RC-IGBT 100 can be suppressed. Thus, for example, the short-circuit withstand of the RC-IGBT 100 is improved.

[0164] At time t3, the transistors having the second gate electrode 52 enter the off operation and become in the off state. Thereafter, at time t4, the transistors having the first gate electrode 51 enter the off operation and become in the off state. After time t4, the IGBTs in the transistor region 101 become in the off state.

[0165] After time t3, by turning off the transistor having the second gate electrode 52, the carrier density on the cell emitter region 29 side of the drift region 27 is reduced. Therefore, when turning off the transistor having the first gate electrode 51, the amount of carriers to be discharged is reduced.

[0166] Therefore, the turn-off time of the RC-IGBT 100 can be shortened. Thus, the turn-off loss of the RC-IGBT 100 is reduced.

[0167] In particular, when the second turn-off voltage (Voff2) applied to the second gate electrode 52 is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the second gate insulating film 42. Therefore, the discharge of holes from the drift region 27 to the upper electrode 12 is promoted until time t4, and when turning off the transistor having the first gate electrode 51, the amount of carriers to be discharged is further reduced. Thus, the turn-off loss of the RC-IGBT 100 is further reduced.

[0168] FIG. 9 is a schematic cross-sectional view of a part of a semiconductor device of a comparative example. FIG. 9 is a figure corresponding to FIG. 2 of the first embodiment.

[0169] FIG. 10 is a schematic top view of a part of a semiconductor device of a comparative example. FIG. 10 is a top view on the first plane F1. FIG. 10 is a figure corresponding to FIG. 3 of the first embodiment. FIG. 9 is a cross-section taken along DD' of FIG. 10.

[0170] The semiconductor device of the comparative example is an RC-IGBT 900 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0171] The semiconductor device of the comparative example is different from the RC-IGBT 100 of the first embodiment in that the fourth gate electrode 54 in the boundary region 103 is not connected to the third gate electrode pad 106. The fourth gate electrode 54 in the boundary region 103 is electrically connected to, for example, the upper electrode 12. Further, the semiconductor device of the comparative example is different from the RC-IGBT 100 of the first embodiment in that the boundary emitter region 35 is not provided in the boundary region 103.

[0172] The RC-IGBT 900 of the comparative example is different from the RC-IGBT 900 of the first embodiment in that no transistor is provided in the boundary region 103 and the boundary region 103 does not operate as an IGBT.

[0173] For example, consider the case where the RC-IGBT 900 is used as a switching element in an inverter circuit. When the IGBT of the RC-IGBT 900 is in the on state, a high voltage is applied to the lower electrode 14 with respect to the upper electrode 12, and a current flows from the lower electrode 14 toward the upper electrode 12. When the IGBT of the RC-IGBT 900 is turned off, the current flowing from the lower electrode 14 toward the upper electrode 12 is blocked.

[0174] For example, when the load of the inverter circuit includes an inductor, after the IGBT in the transistor region 101 is turned off, the diode in the diode region 102 is turned on, and a reflux current flows from the upper electrode 12 toward the lower electrode 14.

[0175] At the boundary between the transistor region 101 and the diode region 102, the transistor region 101 and the diode region 102 interfere with each other, which may cause deterioration of the characteristics of the RC-IGBT 900. For example, when the diode in the diode region 102 is in the on state, the injection of holes from the cell contact region 30, which is a high-concentration p-type region in the transistor region 101, increases the carrier density in the drift region 27 of the diode, and the recovery loss of the diode increases.

[0176] To avoid interference between the transistor region 101 and the diode region 102, the RC-IGBT 900 is provided with a boundary region 103 where neither the IGBT nor the diode exists between the transistor region 101 and the diode region 102. By providing the boundary region 103, the degradation of the characteristics of the RC-IGBT 900 is suppressed.

[0177] However, the boundary region 103 becomes an inactive region that does not directly contribute to the operation of the IGBT in the transistor region 101 and the operation of the diode in the diode region 102.

[0178] The RC-IGBT 100 of the first embodiment includes a transistor having a fourth gate electrode 54 that is simultaneously driven with a transistor having a third gate electrode 53 in the boundary region 103.

[0179] The transistor having the fourth gate electrode 54 enters the on-operation at the time t1 in FIG. 6 and becomes in the on-state. When the transistor having the fourth gate electrode 54 becomes in the on-state, electrons are injected from the boundary emitter region 35 into the drift region 27 in the boundary region 103.

[0180] Therefore, compared with the RC-IGBT 900 of the comparative example, the amount of electrons injected into the drift region 27 increases. Correspondingly, the amount of holes injected from the collector region 26 into the drift region 27 also increases. Therefore, the turn-on time of the RC-IGBT 100 can be further shortened. Thus, the turn-on loss of the RC-IGBT 100 is further reduced.

[0181] In the RC-IGBT 100, it is preferable that the p-type impurity concentration of the boundary base region 34 is lower than the p-type impurity concentration of the cell base region 28. By making the p-type impurity concentration of the boundary base region 34 lower than the p-type impurity concentration of the cell base region 28, the threshold voltage of the transistor having the fourth gate electrode 54 becomes lower than the threshold voltages of the transistors having the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53.

[0182] Therefore, for example, when a turn-on voltage is applied to the fourth gate electrode 54, the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 simultaneously at time t1, the transistor having the fourth gate electrode 54 starts the on-operation earlier. Accordingly, the amount of electrons injected into the drift region 27 increases earlier. Accordingly, the turn-on time of the RC-IGBT 100 can be further shortened. Thus, the turn-on loss of the RC-IGBT 100 is further reduced.

[0183] Also, by making the p-type impurity concentration of the boundary base region 34 lower than the p-type impurity concentration of the cell base region 28, when the diode in the diode region 102 is in the on-state, the injection of holes generated from the boundary base region 34 of the boundary region 103 into the drift region 27 can be suppressed. Accordingly, the increase in the carrier density in the drift region 27 of the diode is suppressed, and the increase in the recovery loss of the diode can be suppressed. For example, the p-type impurity concentration of the boundary base region 34 may be substantially equal to that of the anode region 32 of the diode region 102.

[0184] Also, the occupation area ratio of the boundary contact region 36 on the first surface F1 of the boundary region 103 is preferably smaller than the occupation area ratio of the cell contact region 30 on the first surface F1 of the transistor region 101. The occupation area ratio of the boundary contact region 36 on the first surface F1 of the boundary region 103 is preferably 1 / 2 or less of the occupation area ratio of the cell contact region 30 on the first surface F1 of the transistor region 101. For example, the occupation area ratio of the boundary contact region 36 may be substantially equal to the occupation area ratio of the diode contact region 33 of the diode region 102.

[0185] By making the occupied area ratio of the boundary contact region 36 on the first surface F1 of the boundary region 103 smaller than the occupied area ratio of the cell contact region 30 on the first surface F1 of the transistor region 101, when the diode in the diode region 102 is in the on state, the injection of holes from the boundary base region 34 of the boundary region 103 into the drift region 27 can be suppressed. Therefore, an increase in the carrier density in the drift region 27 of the diode can be suppressed, and an increase in the recovery loss of the diode can be suppressed. Also, by making the occupied area ratio of the boundary contact region 36 substantially equal to the occupied area ratio of the diode contact region 33 in the diode region 102, when the diode in the diode region 102 is in the on state, it becomes possible to equalize the amount of holes injected into the drift region 27 in the diode region 102 and the boundary region 103. Therefore, the boundary region 103 can also contribute to the operation as a diode.

[0186] Also, it is preferable that the occupied area ratio of the fourth gate electrode 54 in a cross section parallel to the first surface F1 of the boundary region 103 is larger than the occupied area ratio of the third gate electrode 53 in the above cross section of the transistor region 101. By increasing the occupied area ratio of the fourth gate electrode 54, in the boundary region 103, the amount of electrons injected into the drift region 27 further increases. Therefore, the turn-on time of the RC-IGBT 100 can be further shortened. Thus, the turn-on loss of the RC-IGBT 100 is further reduced. On the other hand, when the IGBT is in the on state after time t2, by not arranging the transistor having the first gate electrode 51 that operates in the on state and the transistor having the second gate electrode 52 in the boundary region 103, only the transistor having the fourth gate electrode 54 in the boundary region 103 with a low threshold voltage can be turned off. Therefore, it becomes possible to suppress IGBT breakdown due to the coexistence of transistors with a low threshold voltage.

[0187] As described above, according to the first embodiment, a semiconductor device and a semiconductor circuit including an RC-IGBT having an IGBT and a diode can be realized, which enables reduction of turn-on loss.

[0188] (Second Embodiment) The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that a first semiconductor region is provided between the ninth semiconductor region and the second surface. Hereinafter, some descriptions may be omitted for the content overlapping with the first embodiment.

[0189] FIG. 11 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. FIG. 11 corresponds to FIG. 2 of the first embodiment.

[0190] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0191] In the RC-IGBT200, the boundary region 103 includes the collector region 26. The collector region 26 is provided between the boundary base region 34 and the second surface F2. The collector region 26 is in contact with the lower electrode 14 in the boundary region 103.

[0192] According to the RC-IGBT200, since the boundary region 103 includes the collector region 26, the amount of electrons injected into the drift region 27 in the boundary region 103 further increases as compared with the RC-IGBT100. Therefore, the turn-on time of the RC-IGBT200 can be further shortened. Thus, the turn-on loss of the RC-IGBT200 is further reduced.

[0193] As described above, according to the second embodiment, a semiconductor device including an RC-IGBT having an IGBT and a diode and capable of reducing the turn-on loss can be realized.

[0194] (Third Embodiment) The semiconductor device of the third embodiment is provided in a semiconductor layer, provided between a second semiconductor region and a third semiconductor region, and between a second semiconductor region and a ninth semiconductor region, and further includes a twelfth semiconductor region of a second conductivity type having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region, which is different from the semiconductor device of the first embodiment. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0195] FIG. 12 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. FIG. 12 corresponds to FIG. 2 of the first embodiment.

[0196] The semiconductor device of the third embodiment is an RC-IGBT300 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0197] RC-IGBT300 includes a barrier region 37 (twelfth semiconductor region). In the transistor region 101, the barrier region 37 is provided between the drift region 27 and the cell base region 28. In the boundary region 103, the barrier region 37 is provided between the drift region 27 and the boundary base region 34. In the diode region 102, the barrier region 37 is provided between the drift region 27 and the anode region 32.

[0198] The barrier region 37 is an n-type semiconductor region. The n-type impurity concentration of the barrier region 37 is higher than the n-type impurity concentration of the drift region 27.

[0199] According to RC-IGBT300, by including the barrier region 37, when the IGBT is in the on state, the carrier density on the cell base region 28 side of the drift region 27 becomes high. Therefore, compared with RC-IGBT100, the on-resistance is reduced. Thus, the steady-state loss of RC-IGBT300 is reduced.

[0200] As described above, according to the third embodiment, a semiconductor device including an RC-IGBT having an IGBT and a diode and capable of reducing the turn-on loss can be realized.

[0201] (Fourth Embodiment) The semiconductor device of the fourth embodiment is different from the semiconductor device of the third embodiment in that the depth in the direction from the first surface to the second surface of the ninth semiconductor region is shallower than the depth in the direction from the first surface to the second surface of the third semiconductor region. Hereinafter, for the content overlapping with the first embodiment and the third embodiment, some descriptions may be omitted.

[0202] FIG. 13 is a schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment. FIG. 13 corresponds to FIG. 2 of the first embodiment.

[0203] The semiconductor device of the fourth embodiment is an RC-IGBT400 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0204] RC-IGBT400 includes a barrier region 37 (the twelfth semiconductor region). In the transistor region 101, the barrier region 37 is provided between the drift region 27 and the cell base region 28. In the boundary region 103, the barrier region 37 is provided between the drift region 27 and the boundary base region 34. In the diode region 102, the barrier region 37 is provided between the drift region 27 and the anode region 32.

[0205] The barrier region 37 is an n-type semiconductor region. The n-type impurity concentration of the barrier region 37 is higher than the n-type impurity concentration of the drift region 27.

[0206] The depth in the direction from the first surface F1 to the second surface F2 of the boundary base region 34 of RC-IGBT400 is shallower than the depth in the direction from the first surface F1 to the second surface F2 of the cell base region 28. Also, the depth in the direction from the first surface F1 to the second surface F2 of the anode region 32 is shallower than the depth in the direction from the first surface F1 to the second surface F2 of the cell base region 28.

[0207] According to the RC-IGBT400, similar to the RC-IGBT300 of the third embodiment, by including the barrier region 37, when the IGBT is in the on state, the carrier density on the cell base region 28 side of the drift region 27 increases. Therefore, the steady-state loss of the RC-IGBT400 is reduced.

[0208] Also, in the RC-IGBT400, since the boundary base region 34 is shallower than the cell base region 28, the channel length of the transistor having the fourth gate electrode 54 is shorter than the channel lengths of the transistors having the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53.

[0209] For this reason, for example, when a turn-on voltage is applied to the fourth gate electrode 54, the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 simultaneously at time t1, the transistor having the fourth gate electrode 54 starts the on operation earlier. Also, the on-current of the transistor having the fourth gate electrode 54 increases.

[0210] Therefore, the amount of electrons injected into the drift region 27 increases earlier. Therefore, the turn-on time of the RC-IGBT400 can be further shortened. Thus, the turn-on loss of the RC-IGBT400 is further reduced.

[0211] (Modification) FIG. 14 is a schematic cross-sectional view of a part of a semiconductor device according to a modification of the fourth embodiment. FIG. 14 corresponds to FIG. 13 of the fourth embodiment.

[0212] The semiconductor device according to the modification of the fourth embodiment is an RC-IGBT401 in which an IGBT and a reflux diode are formed on the same semiconductor chip.

[0213] The modified RC-IGBT401 is different from the RC-IGBT400 of the fourth embodiment in that it does not include the barrier region 37.

[0214] In the RC-IGBT 401 of the modified example, the depth in the direction from the first surface F1 to the second surface F2 of the boundary base region 34 is shallower than the depth in the direction from the first surface F1 to the second surface F2 of the cell base region 28. The RC-IGBT 401 of the modified example has the same operation as the RC-IGBT 400 of the fourth embodiment, and the turn-on loss of the RC-IGBT 401 is further reduced.

[0215] As described above, according to the fourth embodiment and the modified example, a semiconductor device including an RC-IGBT having an IGBT and a diode and capable of reducing turn-on loss can be realized.

[0216] (Fifth Embodiment) In the semiconductor device of the fifth embodiment, the diode region further includes a first-conductivity-type thirteenth semiconductor region provided between the second semiconductor region and the second surface in the semiconductor layer. The second electrode is different from the semiconductor device of the first embodiment in that it is in contact with the thirteenth semiconductor region. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0217] FIG. 15 is a schematic cross-sectional view of a part of the semiconductor device of the fifth embodiment. FIG. 15 corresponds to FIG. 2 of the first embodiment.

[0218] The semiconductor device of the fifth embodiment is an RC-IGBT 500 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0219] The RC-IGBT 500 includes a p-type region 38 (thirteenth semiconductor region) in the semiconductor layer 10 of the diode region 102. The p-type region 38 is provided between the drift region 27 and the second surface F2. The p-type region 38 is provided between the anode region 32 and the second surface F2.

[0220] The p-type region 38 is in contact with the second surface F2. The p-type region 38 is in contact with the lower electrode 14.

[0221] The p-type region 38 is, for example, alternately arranged with the cathode region 31 in the second direction.

[0222] The p-type region 38 is a p + -type semiconductor region.

[0223] According to the RC-IGBT 500, by including the p-type region 38, oscillation during the recovery operation of the diode in the diode region 102 is suppressed.

[0224] As described above, according to the fifth embodiment, a semiconductor device including an RC-IGBT having an IGBT and a diode can be realized, which enables reduction of turn-on loss.

[0225] In the first to fifth embodiments, the case where the semiconductor layer is single-crystalline silicon has been described as an example, but the semiconductor layer is not limited to single-crystalline silicon. For example, other single-crystalline semiconductors such as single-crystalline silicon carbide may be used.

[0226] In the first to fifth embodiments, the case where the trenches are arranged in a stripe shape in parallel has been described as an example, but the present invention can also be applied to a mesh-shaped trench or a dot-shaped trench where the trenches intersect.

[0227] In the first to fifth embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type has been described as an example, but it is also possible to set the first conductivity type to n-type and the second conductivity type to p-type.

[0228] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0229] 10 Semiconductor layer 12 Upper electrode (first electrode) 14 Lower electrode (second electrode) 21 First gate trench (first trench) 22 Second gate trench (second trench) 23 Third gate trench (third trench) 24 Fourth gate trench (fourth trench) 25 Diode trench (fifth trench) 26 Collector region (first semiconductor region) 27 Drift region (second semiconductor region) 28 Cell base region (third semiconductor region) 29 Cell emitter region (fourth semiconductor region) 30 Cell contact region (fifth semiconductor region) 31 Cathode region (sixth semiconductor region) 32 Anode region (seventh semiconductor region) 33 Diode contact region (eighth semiconductor region) 34 Boundary base region (ninth semiconductor region) 35 Boundary emitter region (tenth semiconductor region) 36 Boundary contact region (eleventh semiconductor region) 37 Barrier region (twelfth semiconductor region) 38 p-type region (thirteenth semiconductor region) 41 First gate insulating film 42 Second gate insulating film 43 Third gate insulating film 44 Fourth gate insulating film 45 Diode insulating film (insulating film) 51 First gate electrode 52 Second gate electrode 53 Third gate electrode 54 Fourth gate electrode 55 Diode conductive layer (conductive layer) 100 RC-IGBT (semiconductor device) 101 Transistor region 102 Diode region 103 Boundary region 104 First gate electrode pad (first electrode pad) 105 Second gate electrode pad (second electrode pad) 106 Third gate electrode pad (third electrode pad) 150 Gate driver circuit (control circuit) 200 RC-IGBT (semiconductor device) 300 RC-IGBT (semiconductor device) 400 RC-IGBT (semiconductor device) 401 RC-IGBT (semiconductor device) 500 RC-IGBT (semiconductor device) F1 First surface F2 Second surface

Claims

1. a semiconductor layer having a first surface and a second surface facing the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface; a third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; a fourth semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface; a fifth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the third semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the third semiconductor region; a first trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; a third trench provided on the first surface side of the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; A transistor region including, The semiconductor layer, The second semiconductor region, A sixth semiconductor region of a second conductivity type, provided in the semiconductor layer, provided between the second semiconductor region and the second surface, and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region; A seventh semiconductor region of a first conductivity type, provided in the semiconductor layer, provided between the second semiconductor region and the first surface; An eighth semiconductor region of a first conductivity type, provided in the semiconductor layer, provided between the seventh semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the seventh semiconductor region; A fifth trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region; A conductive layer provided in the fifth trench; An insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region; A first electrode in contact with the eighth semiconductor region; A second electrode in contact with the sixth semiconductor region; A diode region including, The semiconductor layer, The second semiconductor region, A ninth semiconductor region of a first conductivity type, provided in the semiconductor layer, provided between the second semiconductor region and the first surface; A tenth semiconductor region of a second conductivity type, provided in the semiconductor layer, provided between the ninth semiconductor region and the first surface; An eleventh semiconductor region of a first conductivity type, provided in the semiconductor layer, provided between the ninth semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the ninth semiconductor region; A plurality of fourth trenches provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region; A fourth gate electrode provided in the fourth trench; A fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region; A first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region; The second electrode, Including a boundary region provided between the transistor region and the diode region. A first electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the first gate electrode; A second electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the second gate electrode; A third electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode; comprising; A semiconductor device in which, in a direction from the first surface toward the second surface of the plurality of fourth trenches, the second electrode is in contact with the first semiconductor region or the second semiconductor region. The semiconductor device according to claim 1, wherein the second electrode is in contact with the second semiconductor region.

2. A semiconductor layer having a first surface and a second surface facing the first surface; A first semiconductor region of a first conductivity type provided in the semiconductor layer; A second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface; A third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; A fourth semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface; A fifth semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the third semiconductor region; A first trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A first gate electrode provided in the first trench; A first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; A second trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A second gate electrode provided in the second trench; A second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; A third trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A third gate electrode provided in the third trench; A third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; A first electrode provided on the side of the first surface with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region; A second electrode provided on the side of the second surface with respect to the semiconductor layer and in contact with the first semiconductor region; A transistor region including; The semiconductor layer; The second semiconductor region; A sixth semiconductor region of the second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the second surface, and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region; A seventh semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; An eighth semiconductor region of the first conductivity type provided in the semiconductor layer, provided between the seventh semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the seventh semiconductor region; A fifth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region; A conductive layer provided in the fifth trench; An insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region; The first electrode in contact with the eighth semiconductor region; The second electrode in contact with the sixth semiconductor region; A diode region including; The semiconductor layer; The second semiconductor region; A ninth semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface; A tenth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the ninth semiconductor region and the first surface; It is provided in the semiconductor layer, provided between the ninth semiconductor region and the first surface, and has a first conductivity type with a first conductivity type impurity concentration higher than that of the ninth semiconductor region. The eleventh semiconductor region of the first conductivity type, A fourth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region; A fourth gate electrode provided in the fourth trench; A fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region; The first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region; The second electrode; Including a boundary region provided between the transistor region and the diode region; A first electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the first gate electrode; A second electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the second gate electrode; A third electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode; Comprising; A semiconductor device in which the occupied area ratio of the fourth gate electrode in a cross-section parallel to the first surface of the boundary region is larger than the occupied area ratio of the third gate electrode in the cross-section of the transistor region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first conductivity type impurity concentration of the ninth semiconductor region is lower than the first conductivity type impurity concentration of the third semiconductor region.

5. The semiconductor device according to any one of claims 1 to 4, wherein the occupied area ratio of the eleventh semiconductor region on the first surface of the boundary region is smaller than the occupied area ratio of the fifth semiconductor region on the first surface of the transistor region.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a twelfth semiconductor region of the second conductivity type provided in the semiconductor layer, between the second semiconductor region and the third semiconductor region, and between the second semiconductor region and the ninth semiconductor region, and having a second conductivity type impurity concentration higher than that of the second semiconductor region.

7. The depth in the direction from the first surface to the second surface of the ninth semiconductor region is shallower than the depth in the same direction of the third semiconductor region. The semiconductor device according to any one of claims 1 to 6.

8. The diode region is provided in the semiconductor layer, and further includes a first-conductivity-type thirteenth semiconductor region provided between the second semiconductor region and the second surface. The second electrode is in contact with the thirteenth semiconductor region. The semiconductor device according to any one of claims 1 to 7.

9. The conductive layer is electrically connected to the first electrode. The semiconductor device according to any one of claims 1 to 8.

10. Apply a first turn-on voltage to the first electrode pad. Apply a second turn-on voltage to the second electrode pad. Apply a third turn-on voltage to the third electrode pad. After applying the first turn-on voltage to the first electrode pad, the second turn-on voltage to the second electrode pad, and the third turn-on voltage to the third electrode pad, apply a third turn-off voltage to the third electrode pad. After applying the third turn-off voltage to the third electrode pad, apply a second turn-off voltage to the second electrode pad. After applying the second turn-off voltage to the second electrode pad, apply a first turn-off voltage to the first electrode pad. The semiconductor device according to any one of claims 1 to 9.

11. A semiconductor layer having a first surface and a second surface facing the first surface, A first-conductivity-type first semiconductor region provided in the semiconductor layer, A second-conductivity-type second semiconductor region provided in the semiconductor layer and between the first semiconductor region and the first surface, A first-conductivity-type third semiconductor region provided in the semiconductor layer and between the second semiconductor region and the first surface, A second-conductivity-type fourth semiconductor region provided in the semiconductor layer and between the third semiconductor region and the first surface, A first-conductivity-type fifth semiconductor region provided in the semiconductor layer and between the third semiconductor region and the first surface, having a first-conductivity-type impurity concentration higher than the first-conductivity-type impurity concentration of the third semiconductor region. A first trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A first gate electrode provided in the first trench; A first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; A second trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A second gate electrode provided in the second trench; A second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; A third trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A third gate electrode provided in the third trench; A third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; A first electrode provided on the side of the first surface with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region; A second electrode provided on the side of the second surface with respect to the semiconductor layer and in contact with the first semiconductor region; A transistor region including; The semiconductor layer; The second semiconductor region; A sixth semiconductor region of a second conductivity type provided in the semiconductor layer between the second semiconductor region and the second surface and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region; A seventh semiconductor region of a first conductivity type provided in the semiconductor layer between the second semiconductor region and the first surface; An eighth semiconductor region of a first conductivity type provided in the semiconductor layer between the seventh semiconductor region and the first surface and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the seventh semiconductor region; A fifth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region; A conductive layer provided in the fifth trench; An insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region; A first electrode in contact with the eighth semiconductor region; A second electrode in contact with the sixth semiconductor region; A diode region including the above; The semiconductor layer; The second semiconductor region; A ninth semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; A tenth semiconductor region of a second conductivity type provided in the semiconductor layer and between the ninth semiconductor region and the first surface; An eleventh semiconductor region of a first conductivity type provided in the semiconductor layer and between the ninth semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the ninth semiconductor region; A fourth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region; A fourth gate electrode provided in the fourth trench; A fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region; A first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region; The second electrode; Including the above, a boundary region provided between the transistor region and the diode region; A first electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the first gate electrode; A second electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the second gate electrode; A third electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode; Comprising; Applying a first turn-on voltage to the first electrode pad; Applying a second turn-on voltage to the second electrode pad; Applying a third turn-on voltage to the third electrode pad; After applying the first turn-on voltage to the first electrode pad, applying the second turn-on voltage to the second electrode pad, and applying the third turn-on voltage to the third electrode pad, a third turn-off voltage is applied to the third electrode pad, After applying the third turn-off voltage to the third electrode pad, a second turn-off voltage is applied to the second electrode pad, A semiconductor device that applies a first turn-off voltage to the first electrode pad after applying the second turn-off voltage to the second electrode pad.

12. A semiconductor device according to any one of claims 1 to 9, A control circuit that drives the semiconductor device, applies a first turn-on voltage to the first electrode pad, applies a second turn-on voltage to the second electrode pad, applies a third turn-on voltage to the third electrode pad, applies the first turn-on voltage to the first electrode pad, applies the second turn-on voltage to the second electrode pad, applies the third turn-on voltage to the third electrode pad, then applies a third turn-off voltage to the third electrode pad, applies the third turn-off voltage to the third electrode pad, then applies a second turn-off voltage to the second electrode pad, applies the second turn-off voltage to the second electrode pad, and then applies a first turn-off voltage to the first electrode pad. A semiconductor circuit comprising:

13. A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of a first conductivity type provided in the semiconductor layer, A second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first surface, A third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first surface, A fourth semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first surface, A fifth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the third semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the third semiconductor region, A first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; a third trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the side of the first surface with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region; a second electrode provided on the side of the second surface with respect to the semiconductor layer and in contact with the first semiconductor region; a transistor region including; the semiconductor layer; the second semiconductor region; a sixth semiconductor region of a second conductivity type provided in the semiconductor layer, between the second semiconductor region and the second surface, and having a higher second conductivity type impurity concentration than the second conductivity type impurity concentration of the second semiconductor region; a seventh semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; an eighth semiconductor region of a first conductivity type provided in the semiconductor layer, between the seventh semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the seventh semiconductor region; a fifth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region; a conductive layer provided in the fifth trench; An insulating film provided between the conductive layer and the second semiconductor region, and between the conductive layer and the seventh semiconductor region, The first electrode in contact with the eighth semiconductor region, The second electrode in contact with the sixth semiconductor region, A diode region including, The semiconductor layer, The second semiconductor region, A ninth semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, A tenth semiconductor region of a second conductivity type provided in the semiconductor layer and between the ninth semiconductor region and the first surface, An eleventh semiconductor region of a first conductivity type provided in the semiconductor layer, between the ninth semiconductor region and the first surface, and having a higher first conductivity type impurity concentration than the first conductivity type impurity concentration of the ninth semiconductor region, A fourth trench provided on the side of the first surface in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region, A fourth gate electrode provided in the fourth trench, A fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region, The first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region, The second electrode, Including a boundary region provided between the transistor region and the diode region, A first electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the first gate electrode, A second electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the second gate electrode, A third electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode, A semiconductor device comprising A control circuit that drives the semiconductor device, applies a first turn-on voltage to the first electrode pad, applies a second turn-on voltage to the second electrode pad, applies a third turn-on voltage to the third electrode pad, applies the first turn-on voltage to the first electrode pad, applies the second turn-on voltage to the second electrode pad, applies the third turn-on voltage to the third electrode pad, then applies a third turn-off voltage to the third electrode pad, after applying the third turn-off voltage to the third electrode pad, applies a second turn-off voltage to the second electrode pad, after applying the second turn-off voltage to the second electrode pad, applies a first turn-off voltage to the first electrode pad, and a semiconductor circuit comprising the same.

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