Improvement of the Programming Process of a Field Programmable Gate Array Using Partial Reconfiguration

Abstract

To provide a method for improving speed and efficiency of configuring a digital electronic integrated circuit (IC), and a computer readable medium.SOLUTION: A method includes: compiling and storing primitive bitstreams for different primitive functions that can be written and implemented on a particular IC; receiving an input to designate a functional logic of an algorithm to be implemented on the particular IC, using a reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the functional logic; obtaining, from a digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; and using one or more partial reconfiguration operations, writing the subset of the primitive bitstreams to the particular IC.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One technical field of the present disclosure is the programming of field programmable gate array (FPGA) integrated circuits (ICs) and other types of programmable ICs. Another technical field is partial reconfiguration (PR) in the field of FPGA programming.

Background Art

[0002] The approaches described in this section of the specification are approaches that could be pursued, but are not necessarily approaches that have been previously devised or pursued. Thus, unless otherwise specified, none of the approaches described in this section should be assumed to be eligible as prior art solely for the reason that they are included in this section.

[0003] A field programmable gate array (FPGA) integrated circuit is a semiconductor device having a matrix of configurable logic blocks (CLBs) that can be configured to generate different complex digital circuits. The CLBs are connected via programmable interconnects that span the area of the FPGA. The FPGA may also include random access memory, digital signal processor (DSP) slices, or other logic elements. The CLBs can be configured to generate logic operations such as AND and XOR, which are then concatenated in series and / or in parallel with other logic elements on the FPGA to generate a specified digital circuit.

[0004] FPGA configuration is described using a hardware description language (HDL) such as Verilog or VHDL. A program described in HDL is compiled using dedicated software to generate a bitstream containing the configuration information of a specific target FPGA. VIVADO is an example of an integrated design environment that can be used to describe and compile an HDL design to generate a bitstream for a Xilinx FPGA.

[0005] FPGA has proven to be very powerful for implementing high-speed DSP or highly parallel DSP algorithms. FPGAs are commercially available, for example, from Xilinx, Inc. The FPGA has enabled the production of reconfigurable digital electronic products. An example is Moku:Lab developed by Liquid Instruments Pty Ltd. However, current technologies for programming FPGAs have several drawbacks.

[0006] Programming an FPGA usually requires specialized knowledge that can be time-consuming to acquire. In many cases, compilation tools are only available from the FPGA manufacturer or vendor and have interfaces specific to their chips. Users need to spend time installing and learning these tools. Depending on the complexity, the development time can be long. Furthermore, the time to compile a completed program, including design changes or the entire development, can range from a few minutes to several hours depending on the complexity. Today's developers faced with making relatively simple changes to an FPGA program do not want to wait hours for the entire bitstream to be recompiled and distributed before loading it onto the FPGA.

[0007] Based on these problems, there is a need to improve the technology of FPGA programming, and FPG There is a long-standing but unmet specific need for a way to significantly reduce the compilation time of a program.

Summary of the Invention

[0008] The appended claims may serve as a summary of the present invention.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0010] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention. The embodiments are described in terms of the following outline: 1. Basic Technology 2. General Overview of Embodiments 3. Structural and Functional Examples of Embodiments 4. Implementation Example - Overview of Hardware 1. Basic Technologies DSP algorithms can often be described symbolically using block diagrams. In some commercial systems, a graphical user interface (GUI) of the block diagram is used to enable the design of algorithms for digital integrated circuits (ICs) such as FPGAs. Simulink and LabVIEW are commercial examples of tools that provide a block diagram environment that can facilitate the design, verification, and implementation of software-based digital systems for FPGAs and other target platforms. These systems remove some of the complexity of programming the target platform, but still require long compilation times and can lengthen the development time.

[0011] GNUradio is an example of a tool that provides an environment for dragging and dropping individual functional blocks together and observing their interactions on a host processor connected to GNUradio-compatible hardware. In this system, the designer does not need to generate source code for deployment to an external processing system. However, GNUradio is not suitable for high-bandwidth hardware-based applications.

[0012] In partial reconfiguration (PR), the FPGA-programmed circuit can be divided into individually compilable regions, resulting in the generation of region bitstreams. Each region bitstream can be individually loaded into an existing FPGA, so the existing region bitstream is effectively swapped out with the new one. The latest FPGAs can support hundreds of individual regions that are each independently configurable.

[0013] Partial reconfiguration (PR) is an FPGA configuration technique that enables dynamic changes to functional modules within an active design while the rest of the FPGA continues to operate. Using PR, hardware modules can be changed at various points during the execution of the FPGA, allowing large or complex designs to be adapted to smaller FPGAs. An example is a software-defined radio where different modulation and demodulation protocols are swapped at runtime. PR is available, for example, in the Xilinx ZYNQ family of FPGAs.

[0014] Using PR, the circuit design is split into reconfigurable logic and non-reconfigurable logic. The term static logic is used for all logic elements on the FPGA that are not reconfigurable, while the term reconfigurable logic refers to the logic elements that are reconfigurable. A reconfigurable module (RM) (or "module") is the HDL description of the logic that can be placed within a reconfigurable partition (RP) (or "partition"). Each RP is a physical collection of dedicated FPGA logic elements that are only within that partition. A reconfigurable frame (RF) represents the smallest reconfigurable area that can be defined as an RP. Multiple RFs can be included in a single RP and encapsulated within it. A partial bitstream is a generated file that contains information about the configuration details and the location of the RM.

[0015] When the design is separated into static logic and reconfigurable logic, the reconfigurable logic is divided into RP sections and all RMs of each partition are identified. Each bitstream contains configuration data and location data. Thus, a separate single bitstream is generated for each module at all locations of all RPs. Therefore, if the same functional module is required at two different RPs, two bitstreams are required. Modules and partitions are subject to other constraints that are not relevant to the present disclosure but may affect the implementation of a particular circuit. These constraints are described in detail in other publications.

[0016] 2. General Overview of Embodiments In one embodiment, a method is disclosed for improving the speed and efficiency of configuring a digital integrated circuit (IC) that supports partial reconfiguration, where a particular IC has a plurality of reconfigurable partitions and a plurality of primitive variations that are configurable in each of the reconfigurable partitions, which, when executed using one or more processors, causes the one or more processors to compile and store, using digital storage, a plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented in the particular IC before writing a configuration bitstream to the particular IC, receive an input for specifying the functional logic of an algorithm to be implemented in the particular IC using reconfigurable logic, automatically determine a subset of primitive functions that includes a particular primitive function corresponding to the functional logic, retrieve from the digital storage a subset of primitive bitstreams corresponding to the subset of primitive functions, and write the subset of primitive bitstreams to the particular IC using one or more partial reconfiguration operations, and the method is executed by one or more computing devices.

[0017] In another embodiment, a field programmable gate array (FPGA) digital integrated circuit that supports partial reconfiguration is provided, where a particular FPGA has a plurality of reconfigurable partitions and a plurality of primitive variations that are configurable within each of the reconfigurable partitions, and a method for improving the programming speed and efficiency of the field programmable gate array (FPGA) digital integrated circuit is disclosed. The method includes compiling and storing, using digital storage, a plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented on a particular FPGA before writing a configuration bitstream to the particular FPGA, receiving an input for specifying functional logic of an algorithm implemented on the particular FPGA using partially reconfigurable logic, automatically determining a subset of primitive functions that includes a particular primitive function corresponding to a graphical block, retrieving, from the digital storage, a subset of primitive bitstreams corresponding to the subset of primitive functions, and writing the subset of primitive bitstreams to the particular FPGA using one or more partial reconfiguration operations. The method is executed by one or more computing devices.

[0018] Embodiments assume that all block diagrams of FPGA algorithms can be described using N discrete block types connected in a matrix of M block regions. While specific embodiments are described specifically for use with FPGAs, the methods of the present disclosure can be more generally applied to other programmable integrated circuits and do not require the use of FPGAs.

[0019] One approach could be to pre-compile the bitstreams for all possible block diagram connections and then select based on the user's block diagram. This involves storage and compilation of N^M full bitstreams. As M and / or N increase beyond small values, the storage requirements and compilation time of this approach become infeasible. The storage and compilation time increase exponentially or polynomially with the increase in M or N. Each partial bitstream is approximately 100 kB and compilation takes approximately 5 minutes depending on the complexity. For M = N = 100, compilation time of approximately 5 * 100^100 minutes and storage of 100^98 GB are then required.

[0020] In an embodiment, a partial reconfiguration (PR) technique is employed where each of the M regions is defined as being partially reconfigurable and a single partial bitstream for each of the N block types is pre-compiled for each of the M regions. In this context, "pre" means before the end-user computer uses a graphical or non-graphical tool to design an algorithm, and when the design process starts, the user has available a pre-compiled library of a number of bitstreams corresponding to the available N block types that can be configured to implement the algorithm. Thus, only compilation and storage of M * N bitstreams are required. For M = N = 100, only 50,000 minutes of compilation time and 1 GB of storage are then required. This approach depends to some extent on predicting the specific functions required by the user algorithm or application and pre-computing the bitstreams for those functions.

[0021] In some embodiments, a single partial bitstream for fewer than all of the N block types is pre-compiled, and the bitstreams for the other block types required to fully deploy the algorithm to the target platform are generated at design time and Or it is compiled just before deployment. In some embodiments, a subset of block types fewer than N are selected for pre-compilation based on the popularity of the block types in past use by the current user or other users, and thus the subset includes the block types most likely to be selected in a particular design. For example, the compilation agent 122 may detect user selections of particular block types within the IDE 120, either alone in storage or in combination with data received in a similar manner from other instances of the compilation agent running on different host computers of unrelated users, and be programmed to send a report of the user selections to the compilation server process 132. Thus, a crowdsourcing report on the actual selection of block types can influence which block types are pre-compiled on the server side. Alternatively, user input and / or configuration data can specify which block types are pre-compiled and which are compiled at design time or deployment time. This approach allows the user to balance the time savings and efficiency benefits of storing a library of pre-compiled bitstreams against the computational burden of pre-compiling. Other embodiments, aspects, and features will become apparent from the overall disclosure and the appended claims.

[0022] 3. Structural and functional examples of embodiments FIG. 1 shows an exemplary distributed computer system that can be used to implement an example. In the description of the figures of the drawings, the term "primitive" refers to a grouping of logic for an application of a DSP or FPGA 110 that is compiled into a single partial bitstream.

[0023] In one embodiment, the client computing device 102 is communicatively coupled to the server 106 directly or indirectly via one or more networks 104.

[0024] The client computing device 102 can include a desktop computer, laptop computer, mobile computing device, workstation, or other computing device that can interface with an FPGA 110 programmed to implement a user's algorithm. In some embodiments, the client computing device 102 also interfaces with peripheral electronics 112 that can include one or more of a processor development board, analog-to-digital converter, digital-to-analog converter, network connection, power converter, etc. in various embodiments.

[0025] The client computing device 102 hosts or executes an integrated development environment (IDE) 120, which is an application program configured to support the creation, management, and compilation of an FPGA program 114. In some embodiments, the IDE 120 generates and enables user interaction with a graphical user interface that enables programming of DSP algorithms by connecting graphical blocks, icons, or widgets representing computing functions.

[0026] In some embodiments, a compile agent 122 is hosted or executed using the client computing device 102, integrated with or as a separate program from the IDE 120, and programmed or configured to interoperate with a compatible compile server process 132 in the server 106, as further described. In some embodiments, the compile agent 122 determines which bitstream primitives to obtain from the server 106 and how to F It is programmed to determine where to place within the PGA110. Using these elements, the client computing device 102 may generate or obtain a set of compiled bitstreams 124 to be written to the FPGA110 to achieve programming of the FPGA. In some embodiments, the IDE 120 and the compilation agent 122 execute a communication or messaging protocol between the server 106 and the networked data storage 140 that includes or controls compiled bitstream primitives 142, as further described in other sections, and are configured or programmed to execute software and firmware to control client tasks and store the compiled bitstream 124 for the primitives programmed in the FPGA110. Depending on the number of primitives and / or storage requirements, the storage of the compiled bitstream 124 may be shared by the server 106 using the storage 140 or may be fully executed.

[0027] The FPGA110 supports PR. In one embodiment, the FPGA110 is a very large unit having multiple regions each containing a sufficient number of processing elements for a configuration that may require the most resources that a programmed algorithm may need. A large number of resources are expected to be distributed across many discrete regions. One embodiment may be most preferably implemented with a larger FPGA where the user has less concern about space, but the methods described herein are usable regardless of device size, and a large FPGA or other large platform is not a requirement.

[0028] Network 104 generally represents a local area network, wide area network, Internet network, or any combination of the Internet that uses any of a terrestrial link, satellite link, wired link, or wireless link. Client computing device 102 and server 106 each host an interface to network 104 that is compatible with the protocols for transport, session, and application traffic carried over network 104. The specific protocol used over network 104 is not important if client computing device 102 and server 106 can communicate using digital electronic messages and asynchronous protocols, stateless protocols, or stateful protocols to exchange requests, responses, and data payloads.

[0029] In one embodiment, server 106 comprises any of a desktop computer, a rack-mounted computer, or one or more virtual computing instances within a public or private cloud computing center. Server 106 may comprise processes that execute on a server computer or cluster along with other processes, servers, or applications. Server 106 may be implemented using virtualization of an operating system, such as using containerization of DOCKER or KUBERNETES. Server 106 includes or is programmed to access storage 140 that may comprise cloud-based digital data storage or other networked data storage.

[0030] In one embodiment, server 106 stores the source code 130 of FPGA primitive functions, which is further described in other sections of this specification. Server 106 is configured or programmed to compile the source code 130 into bitstream primitives stored in storage 140, as indicated by the compiled bitstream 142, or a compile server process 132 that also hosts or executes. Importantly, in the embodiment, the source code 130 of all functional primitives available for use in the reconfigurable partition of FPGA 110 is compiled prior to any programming activity by client computing device 102, stored in storage 140, and waits for a request for a bitstream from the client computing device. Compile server process 132 may use programs, libraries, or functions obtained in advance from the vendor of FPGA 110 or otherwise compatible with FPGA 110.

[0031] The primitive bitstream 142 may implement any of a number of different substantial signal processing functions. Examples of primitives that can be used in various embodiments include signal multipliers, signal multiplexers, signal mixers, digital filters, oscillators, integrators, trigonometric calculations, fast Fourier transforms, PID controllers, phase-locked loops, integrators, differentiation factors, sine wave generators, direct digital synthesizers, direct form one single-section infinite impulse response filters, DC gain.

[0032] In the example of FIG. 1, server 106 is programmed or configured to store a primitive compiled bitstream 142 using storage 140. Depending on the number of primitives and / or storage requirements, this task can be shared and fully executed by client computing device 102. Compile server process 132 is also programmed or configured to fetch compiled bitstream 142 in response to a request from client computing device 102 and send it to client computing device 102, as further described.

[0033] One embodiment was described in which certain operations occur on client computing device 102, communicate with server 106 via network 104, and storage 140 is managed in relation to the server. However, other embodiments may be implemented entirely on a single host computer or virtual computing instance, without the need for a client-server architecture. Further, storage 140 may be located on the host computer, associated with a virtual computing instance, or separate digital storage of precompiled bitstreams need not be separated from client computing device 102 or any other computer used in the design of the algorithm. For example, a virtual computing instance such as a single host computer or client computing device 102 may host all of the functional elements and data storage devices shown in FIG. 1 as an integrated system. Or, although the architecture of FIG. 1 may be used, a set of precompiled bitstreams may be delivered from server 106 to client computing device 102 as a package or unit for local storage on the client computing device. In one embodiment, delivery of the precompiled bitstream package is performed using an installer process that is executed using any combination of client software on the client computing device and / or browser-executable code executed in the browser of the client computing device.

[0034] FIG. 2 shows an exemplary computer-implemented process according to an embodiment. The example of FIG. 2 includes functional steps that are executed at different times by client computing device 102 and server 106.

[0035] In one embodiment, at block 202, the server or server computer precompiles all possible combinations of primitives for a specified target platform. At block 204, the process stores the compiled bitstream primitives in network storage. itives.

[0036] For example, server 106 uses a compile server process to precompile primitive source code 130 into a compiled bitstream 142 stored using storage 140. The number of primitives represented by source code 130 can vary in different embodiments. For example, a specified FPGA may be defined in configuration data as supporting 100 partitions. For each partition, N different variations can be utilized to receive a compiled bitstream. A set of bitstreams for a particular region is not necessarily compatible with any other region's bitstreams. Thus, region "01" of the FPGA may support a first bitstream selected from a first particular set of 20 different bitstreams, and region "64" of the same FPGA may support a second bitstream selected from a second different particular set of 20 other bitstreams.

[0037] In some embodiments, the management action or configuration data may specify a change to a variation associated with a partition of the target FPGA. For example, if partition “64” is changed to add a phase-locked loop functional block to a variation of that partition that was not previously associated with a PLL block or one of its variations, then all bitstreams of partition “64” will need to be recompiled using server 106. However, each functional block associated with a partition may include some sets of unrelated logic instructions, improving flexibility. For example, a particular variation of 20 variations associated with partition “64” may be able to define the logic of both a PLL and an adder. In some embodiments, any two or more sets of logic may be within a functional block associated with a variation of a partition. This arrangement may be constrained by the total computing power available in the FPGA.

[0038] Asynchronously, at block 206, in a client computing device, an algorithm or program is defined or programmed using a graphical user interface. For example, a DSP algorithm may be defined. Defining a DSP algorithm may include receiving user input that specifies dragging, dropping, and connecting graphical blocks that symbolically define the operation of the DSP algorithm in the GUI interface of the IDE 120.

[0039] In some embodiments, block 206 may include receiving one or more parameter values to change the configuration of a particular functional block. Examples include register-level parameter values, or the specification of a redirect of an input or output to a specified register or other output location.

[0040] In block 208, using the client computing device 102, the algorithm is segmented or grouped into corresponding primitives. Block 208 can include determining which available RPs and variations of the FPGA 110 will receive which particular pre-compiled primitive bitstream 142 to implement the algorithm on the FPGA.

[0041] Block 208 can also include determining the association of the functional blocks of the algorithm to the available primitives pre-compiled on the server as specified in the GUI using the IDE 120. In some embodiments, block 208 is automatically executed based on a mapping table, configuration file, or other data that specifies how the functional blocks represented in the GUI correspond to particular primitives and / or bitstreams of the server 106. Alternatively, the IDE 120 can provide a GUI widget, either natively or under the control of the compilation agent 122, that selects a functional block within the GUI and accepts input to specify a particular primitive for implementing that block. At this point, the client computing device 102 has determined the identifiers of all pre-compiled bitstreams 142 that are necessary to implement the algorithm on the FPGA and that can be swapped for RPs and variations of RPs on the FPGA.

[0042] At this point, the client computing device 102 has determined the identifiers of all pre-compiled bitstreams 142 that are necessary to implement the algorithm on the FPGA and that can be swapped for RPs and variations of RPs on the FPGA.

[0043] In block 210, the client computing device 102 sends a request to the server 106 to obtain the bitstream of the specified primitive. One or more requests may be sent. The one or more requests collectively specify all pre-compiled bitstreams 142 that are necessary to implement the algorithm on the FPGA and that can be swapped for RPs and variations of RPs on the FPGA.

[0044] In block 212, at server 106, bitstream primitives corresponding to regions and groups of DSP algorithms are fetched from storage 140 or other networked storage, and a copy is returned to client computing device 102 in a response over network 104. After being received, the compiled bitstream 142 may be stored in client computing device 102 in the form of compiled bitstream 124.

[0045] In block 214, the fetched bitstream is deployed to the FPGA. Compilation agent 122 may cooperate with IDE 120 to cause the received compiled bitstream 124 to be written to the specified FP and variations of FPGA 110. When block 214 is complete, the FPGA is programmed with all of the reconfigurable logic designed using the GUI of IDE 120 and implemented using the pre-compiled bitstream 142 of primitives associated with the design. These steps are performed substantially faster than conventional approaches that would require bitstream compilation at this point to deploy the algorithm to an IC.

[0046] FIG. 3A shows an exemplary system architecture of an FPGA with partial reconfiguration. In one embodiment, two inputs "in1", "in2" are indirectly connected to two sets of three rows, each having five sequentially connected DSP block PR regions denoted "1.1" to "6.5". A plurality of interconnects 302 enable any connection between rows. The interconnects 302 may be implemented in different ways in different embodiments. Examples include large multiplexing networks, high-speed AXI data buses, or PR regions with variations for different connections.

[0047] Each of the DSP PR regions 1.1 to 6.5 is identical and can be configured as one of N variants, each described using different bitstream primitives from within the pre-compiled bitstream 142. The interface for each variant is the same and includes inputs "in1", "in2", and outputs "Out1", "Out2", as well as connections to the configuration AXI bus 304. Each variation includes logic for different purposes and output multiplexing to select which signals are passed to each output.

[0048] Certain embodiments refer to the use of up to 20 variations and logic for approximately 20 functional blocks, although other embodiments may use other counts of these elements, specifically, there is no limit to the number of different types of logic that can be defined for use in a particular variation. Examples of possible functional blocks that can be used in various embodiments of the PR region configuration include signal multipliers, signal multiplexers, signal mixers, digital filters, oscillators, integrators, trigonometric operations, fast Fourier transforms, PID controllers, phase-locked loops, integrators, differentiators, sine wave generators, direct digital synthesizers, direct form one single-section infinite impulse response filters, DC gain, nulls. Further, complex functional blocks can result in bitstreams that are split across two or more variations of the FPGA region.

[0049] Figure 3B shows an example of a complex DSP algorithm that can be designed using the GUI of the IDE to select and graphically connect functional blocks representing signal processing circuits. The example of Figure 3B includes a block diagram of a frequency modulation control system, and it can be seen that the signal processing functions can include a sine wave generator (Sine Gen), demodulation, a controller, a scanner, and an IIR. Blocks 310, 312 grouped inside the dashed lines are examples of elements that can be grouped into a single bitstream primitive.

[0050] Figure 3C shows an example of implementing FIG. 3B within the architecture of FIG. 3A. In FIG. 3C, the functional blocks of FIG. 3B are assigned to specific RPs or regions of the architecture of FIG. 3A and are appropriately labeled in FIG. 3C to indicate these associations. For example, region 1.1 of FIG. 3A is assigned to Sine Gen logic, and 1.2 is assigned to a demodulator, etc. The selection of the regions associated with the interconnect 302 and the bus 304 achieves the implementation of the logic of FIG. 3B in a specific chip layout.

[0051] Figure 3D shows a variation of the aforementioned architecture where the low-level PR modules are secondary functions. In this example, boxes N.1, N.2, N.X represent larger PR regions that can be configured as single-channel versions of existing devices, e.g., devices available in Moku:Lab. This arrangement allows the user to create a very complex system using a single hardware unit. The low-level PR modules 1.1, 1.2, 1.3 to 6.3 continue to be useful for further customization to meet specific use cases or user requirements. Thus, this architecture shows the possibility of integrating an FPGA with a larger PR region dedicated to complex functions with low-level modules that can be reconfigured using a pre-compiled bitstream 142, swapping other functions on the chip without interrupting the use of the larger PR region and the main functions of the chip.

[0052] Figure 4 shows a variation of another architecture where the devices are split into two categories: measurement or monitoring devices and signal generation or controller devices. PR regions 402, 404, 406 are specific to the signal generation or controller devices, and PR region 408 is specific to the measurement or monitoring devices. Using this arrangement maintains the same functionality as the Moku:Lab system while increasing flexibility. Additionally, if two variations are assigned to the signal generation or controller devices, the resources required for the FPGA will not be significantly higher than those of currently available Moku:Lab devices.

[0053] The embodiment provides many advantages over previous embodiments. The main advantage is that, from the user's perspective, compile time is completely eliminated. The client computing device 102 can obtain pre-compiled versions of the bitstreams of each functional block required to program the FPGA without the long delays associated with local compilation of the FPGA blocks. Furthermore, all the tools necessary to achieve compilation are pre-installed and managed on the server computer 106 and provided as a service to the client computing device 102. Therefore, the user of the client computing device 102 does not need to install or learn chip-specific or vendor-specific compilation tools.

[0054] 4. Implementation Example - Hardware Overview According to one embodiment, the technology described herein is implemented by at least one computing device. The technology can be implemented in whole or in part using a combination of at least one server computer and / or other computing devices connected using a network such as a packet data network. The computing device can include at least one general-purpose hardware processor programmed to execute the technology according to program instructions in firmware, memory, other storage, or a combination. Such a computing device may achieve the described technology by combining custom hardwired logic, ASIC, or FPGA with custom programming. The computing device can be a server computer, workstation, personal computer, portable computer system, handheld device, mobile computing device, wearable device, body-mounted or implantable device, smartphone, smart appliance, networking device, autonomous or semi-autonomous device such as a robot or unmanned ground vehicle or unmanned aircraft, any other electronic device incorporating hardwired logic and / or program logic for implementing the described technology, one or more virtual computing machines or instances within a data center, and / or a network of server computers and / or personal computers.

[0055] FIG. 5 is a block diagram showing an exemplary computer system that may implement an embodiment. In the example of FIG. 5, the computer system 500 and the instructions for implementing the disclosed technology in hardware, software, or a combination of hardware and software are schematically represented, for example, as boxes and circles, with the same level of detail generally used by those of ordinary skill in the art of the technology related to this disclosure for communicating about computer architecture and the implementation of computer systems.

[0056] Computer system 500 includes an input / output (I / O) subsystem 502, which may include a bus and / or other communication mechanism(s) for communicating information and / or instructions between components of computer system 500 via electronic signal paths. I / O subsystem 502 may include an I / O controller, a memory controller, and at least one I / O port. Electronic signal paths are represented schematically in the drawings, for example, as lines, single-headed arrows, or double-headed arrows.

[0057] At least one hardware processor 504 is coupled to the I / O subsystem 502 for processing information and instructions. The hardware processor 504 may include, for example, a general-purpose microprocessor or microcontroller and / or an embedded system or special-purpose microprocessor such as a graphics processing unit (GPU) or digital signal processor or ARM processor. The processor 504 may include an integrated arithmetic logic unit (ALU) or may be coupled to a separate ALU.

[0058] The computer system 500 comprises a processor 504 that processes data and instructions. The processor 504 may also include one or more units of memory 506, such as a main memory, coupled to the I / O subsystem 502 for electronically and digitally storing instructions. The memory 506 may include volatile memory, such as various forms of random access memory (RAM) or other dynamic storage devices. The memory 506 may also be used to store temporary variables or other intermediate information during execution of instructions to be executed by the processor 504. When such instructions are stored on a non-transitory computer-readable storage medium accessible to the processor 504, the computer system 500 may be rendered into a special-purpose machine customized to perform the operations specified in the instructions.

[0059] Computer system 500 further includes non-volatile memory, such as read-only memory (ROM) 508 or other static storage devices connected to I / O subsystem 502, for storing information and instructions for processor 504. ROM 508 may include various forms of programmable ROM (PROM), such as erasable PROM (EPROM) or electrically erasable PROM (EEPROM). The unit of persistent storage 510 may include various forms of non-volatile RAM (NVRAM), such as flash memory, or solid-state storage such as a CD-ROM or DVD-ROM, magnetic disk or optical disk, and may be connected to I / O subsystem 502 for storing information and instructions. Storage 510 is an example of a non-transitory computer-readable medium that can be used to store instructions and data that, when executed by processor 504, cause a computer-implemented method to execute and implement the techniques herein.

[0060] Instructions in the memory 506, ROM 508, or storage 510 may include one or more sets of instructions compiled as a module, method, object, function, routine, or call. The instructions may be compiled as an application program including one or more computer programs, operating system services, or mobile apps. The instructions may include an operating system and / or system software, one or more libraries supporting multimedia, programming, or other functions, data protocol instructions or stacks for implementing TCP / IP, HTTP, or other communication protocols, file format processing instructions for parsing or rendering files encoded using HTML, XML, JPEG, MPEG, or PNG, user interface instructions for rendering or interpreting commands for a graphical user interface (GUI), command line interface, or text user interface, application software such as an office suite, internet access application, design and manufacturing application, graphics application, audio application, software engineering application, educational application, game, or miscellaneous application. The instructions may implement a web server, web application server, or web client. The instructions may be compiled as a presentation layer, application layer, and data storage layer such as a relational database system that may or may not use Structured Query Language (SQL), object store, graph database, flat file system, or other data storage.

[0061] Computer system 500 may be connected to at least one output device 512 via I / O subsystem 502. In one embodiment, output device 512 is a digital computer display. Examples of displays that may be used in various embodiments include touch screen displays or light emitting diode (LED) displays or liquid crystal displays (LCD) or electronic paper displays. Computer system 500 may include other types (s) of output devices 512 in addition to or in place of the display device. Examples of other output devices 512 include printers, ticket printers, plotters, projectors, sound cards or video cards, speakers, buzzers or piezoelectric devices or other audible devices, lamps or LEDs or LCD indicators, tactile devices, actuators or servos.

[0062] At least one input device 514 is connected to I / O subsystem 502 to communicate signals, data, command selections, or gestures to processor 504. Examples of input devices 514 include touch screens, microphones, still and video digital cameras, alphanumeric and other keys, keypads, keyboards, graphic tablets, image scanners, joysticks, clocks, switches, buttons, dials, slides, and / or various types of sensors such as force sensors, motion sensors, thermal sensors, accelerometers, gyroscopes, and inertial measurement unit (IMU) sensors, and / or wireless such as cellular or Wi-Fi, radio frequency (RF) or infrared (IR) transceivers, and various types of transceivers such as global positioning system (GPS) transceivers.

[0063] Another type of input device is the control device 516, which may perform cursor control or other automated control functions, such as navigation in a graphical interface on a display screen, alternatively or in addition to the input function. The control device 516 may be a touchpad, mouse, trackball, or cursor direction keys for communicating direction information and command selections to the processor 504 and for controlling the movement of the cursor on the display 512. The input device may have at least two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), such that the device can specify a position within a plane. Another type of input device is a wired, wireless, or optical control device, such as a joystick, wand, console, steering wheel, pedal, gear shift mechanism, or other type of control device. The input device 514 may include a combination of multiple different input devices, such as a video camera and a depth sensor.

[0064] In another embodiment, the computer system 500 may include an Internet of Things (IoT) device in which one or more of the output device 512, input device 514, and control device 516 are omitted. Or, in such an embodiment, the input device 514 may include one or more cameras, motion detectors, thermometers, microphones, seismic detectors, other sensors or detectors, measurement devices or encoders, and the output device 512 may include a dedicated display, such as a single-wire LED or LCD display, one or more indicators, a display panel, a meter, a valve, a solenoid, an actuator, or a servo.

[0065] When computer system 500 is a mobile computing device, input device 514 may include a global positioning system (GPS) receiver coupled to a GPS module that can triangulate with a plurality of GPS satellites and determine and generate geographic location or position data, such as latitude and longitude values of the geophysical location of computer system 500. Output device 512 may include hardware, software, firmware, and interfaces for generating location reporting packets, notifications, pulse or heartbeat signals, or other repetitive data transmissions that identify the location of computer system 500, either alone or in combination with other application-specific data, directed to host 524 or server 530.

[0066] Computer system 500 may implement the techniques described herein using customized hardwired logic, at least one ASIC or FPGA, firmware, and / or program instructions or logic, which, when loaded, used, or executed in combination with the computer system, program the computer system to operate as a special purpose machine or cause the computer system to operate as a special purpose machine. According to one embodiment, the techniques herein are performed by computer system 500 in response to processor 504 executing at least one sequence of at least one instruction included in main memory 506. Such instructions may be read into main memory 506 from another storage medium, such as storage 510. Execution of the sequence of instructions included in main memory 506 causes processor 504 to perform the process steps described herein. In an alternative embodiment, wiring circuitry may be used in place of, or in combination with, software instructions.

[0067] ​As used herein, the term "storage medium" refers to any non-transitory medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such a storage medium may comprise a non-volatile medium and / or a volatile medium. Non-volatile media include, for example, optical or magnetic disks such as storage 510. Volatile media include dynamic memory such as memory 506. Common forms of storage media include, for example, hard disks, solid state drives, flash drives, magnetic data storage media, any optical data storage media, or physical data storage media, memory chips, and the like.

[0068] A storage medium is different from, but can be used in combination with, a transmission medium. A transmission medium participates in the transfer of information between storage media. For example, a transmission medium includes coaxial cables, copper wire, and fiber optics including the wires that make up a bus of I / O subsystem 502. A transmission medium may take the form of acoustic or light waves such as those generated during radio wave and infrared data communications.

[0069] Various forms of media may be involved in carrying at least one sequence of at least one instruction to the processor 504 for execution. For example, the instructions may initially be carried on the magnetic disk or solid state drive of a remote computer. The remote computer can load the instructions into its dynamic memory and use a modem to transmit the instructions via a communication link such as an optical fiber or coaxial cable or telephone line. A modem or router local to the computer system 500 can receive the data on the communication link and convert the data into a format readable by the computer system 500. For example, a receiver such as a radio frequency antenna or an infrared detector can receive data carried by a radio or optical signal, and appropriate circuitry can provide the data to the I / O subsystem 502, such as placing the data on a bus. The I / O subsystem 502 carries the data to the memory 506, from where the processor 504 retrieves and executes the instructions. The instructions received by the memory 506 may optionally be stored in the storage 510 either before or after execution by the processor 504.

[0070] The computer system 500 also includes a communication interface 518 coupled to the bus 502. The communication interface 518 provides bi-directional data communication coupled to at least one communication network link(s) 520 that is directly or indirectly connected to at least one communication network such as the network 522 or a public or private cloud on the Internet. For example, the communication interface 518 may be an Ethernet networking interface, an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem for providing a data communication connection to a corresponding type of communication line, such as an Ethernet cable or any type of metal cable, or an optical fiber line or a telephone line. The network 522 is a local area network (LAN), a wide area network (WAN), a campus ne Broadly represents a local area network, the Internet, or any combination thereof. The communication interface 518 may include a LAN card for providing a data communication connection to a compatible LAN, or a cellular telephone interface that is wired to transmit or receive cellular data according to cellular radio networking standards, or a satellite radio interface that is wired to transmit or receive digital data according to satellite radio networking standards. In any such implementation, the communication interface 518 transmits and receives electrical, electromagnetic, or optical signals via a signal path that carries a digital data stream representing various types of information.

[0071] The network link 520 typically uses, for example, satellite, cellular, Wi-Fi, or also BLUETOOTH technology to provide electrical, electromagnetic, or optical data communication, either directly or via at least one network, to other data devices. For example, the network link 520 may provide a connection to a host computer 524 via a network 522.

[0072] Furthermore, network link 520 may provide a connection to other computing devices via network 522 or via an internetworking device and / or computer operated by an Internet service provider (ISP) 526. ISP 526 provides data communication services via a worldwide packet data communication network represented as the Internet 528. Server computer 530 may be connected to the Internet 528. Server 530 broadly represents any computer, data center, virtual machine or virtual computing instance, or a computer running a containerized program system such as DOCKER or KUBERNETES, with or without a hypervisor. Server 530 may be implemented using multiple computers or instances and may represent an electronic digital service that is accessed and used by sending web service requests, Uniform Resource Locator (URL) strings with parameters within an HTTP payload, API calls, application service calls, or other service calls. Computer system 500 and server 530 may form elements of a distributed computing system including other computers, processing clusters, server farms, or other computer compilations that cooperate to perform tasks or run applications or services. Server 530 may include a set of one or more instructions compiled as a module, method, object, function, routine, or call. The instructions may be compiled as an application program including one or more computer programs, operating system services, or mobile apps.The commands may include operating systems and / or system software, one or more libraries that support multimedia, programming or other functions, data protocol commands or stacks for implementing TCP / IP, HTTP or other communication protocols, file format processing commands for parsing or rendering files encoded using HTML, XML, JPEG, MPEG or PNG, user interface commands for rendering or interpreting commands for a graphical user interface (GUI), command line interface or text user interface, application software such as office suites, Internet access applications, design and manufacturing applications, graphics applications, audio applications, software engineering applications, educational applications, games or miscellaneous applications. The server 530 may comprise a web application server hosting a presentation layer, an application layer, and a data storage layer such as a relational database system that may or may not use Structured Query Language (SQL), an object store, a graph database, a flat file system, or other data storage.

[0073] The computer system 500 can send messages and receive data and instructions including program code via a network, network link 520, and communication interface 518. In the example of the Internet, the server 530 may send the requested code for an application program via the Internet 528, ISP 526, local network 522, and communication interface 518. The received code may be executed by the processor 504 upon receipt and / or stored in the storage 510, or other non-volatile storage for later execution.

[0074] The execution of the instructions described in this section may be implemented in the form of a process in the form of an instance of a computer program, consisting of the program code and its current activity. Depending on the operating system (OS), a process may consist of multiple execution threads that execute instructions simultaneously. In this context, a computer program is a passive set of instructions, but a process may be the actual execution of those instructions. There may be several processes associated with the same program; for example, opening several instances of the same program often means that multiple processes are running. Multitasking may be implemented to allow multiple processes to share the processor 504. While each processor 504 or core of the processor executes a single task at a time, the computer system 500 may be programmed to implement multitasking so that each processor can switch between the running tasks without having to wait for each task to complete. In certain embodiments, the switch may be executed when a task is performing an input / output operation, when a task indicates that it is switchable, or when a hardware interrupt occurs. Time sharing may be implemented to enable fast response of interactive user applications by executing context switches quickly to make it appear as if multiple processes are being executed in parallel simultaneously. In certain embodiments, for security and reliability, the operating system may prevent direct communication between independent processes and provide a strictly mediated and controlled inter-process communication function.

[0075] In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the invention, and what the applicant intends to be the scope of the invention, is the literal equivalent scope of the set of patent claims issued from this application in the specific form in which such claims are issued, including any subsequent corrections.

Claims

1. A digital integrated circuit (IC) that supports partial reconfiguration, wherein a particular IC configures a digital integrated circuit (IC) having a plurality of reconfigurable partitions, and a method for configuring the digital integrated circuit (IC), comprising: receiving an input for specifying functional logic of an algorithm to be implemented in the particular IC using reconfigurable logic; determining, in response to the input, a subset of primitive functions including a particular primitive function corresponding to the functional logic; obtaining, from digital storage, a subset of precompiled primitive bitstreams corresponding to the subset of primitive functions; writing the subset of precompiled primitive bitstreams to the particular IC using one or more partial reconfiguration operations, wherein the method is executed by one or more computing devices. A method.

2. The method of claim 1, wherein the particular IC includes a field programmable gate array (FPGA) having M reconfigurable partitions and N variations for each of the reconfigurable partitions, and the plurality of precompiled primitive bitstreams include compiled bitstreams for a plurality of different primitive functions that can be written to and implemented for all combinations of M and N on the FPGA, resulting in storing M * N primitive functions.

3. Before writing a configuration bitstream to the particular IC, using a server communicatively coupled to a client computer system, compiling the plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented for the particular IC, and storing the plurality of precompiled primitive bitstreams using the digital storage; sending, from the client computer system to the server, a request to provide the subset of precompiled primitive bitstreams corresponding to the subset of primitive functions. sending, from the server to the client computer system, a response including the subset of the precompiled primitive bitstreams corresponding to the subset of the primitive functions; The method according to claim 1, further comprising. **Claim 4** Determining the subset of primitive functions including specific primitive functions corresponding to the functional logic further includes determining specific partitions and variations for each of the primitive functions and storing metadata identifying the specific partitions and variations, and sending the request further includes sending the metadata along with the request. The method according to claim 3. **Claim 5** Adapted for use in an FPGA including a plurality of rows each having a plurality of DSP block partial reconfiguration regions connected in sequence, and a plurality of interconnects enabling arbitrary connections between the rows, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from the primitive bitstream, each of the variants having one or more inputs, one or more outputs, and being connected to a configuration AXI bus. The method according to claim 1. **Claim 6** The method according to claim 5, adapted for use in the FPGA, wherein each of the variants includes logic for different purposes and has output multiplexing for selecting which signals are passed to the one or more outputs. **Claim 7** Adapted for use in an FPGA including a plurality of rows each having a plurality of DSP block partial reconfiguration regions connected in sequence, and a plurality of interconnects enabling arbitrary connections between the rows, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from the primitive bitstream, each of the variants having two or more inputs, two or more outputs, and being connected to a configuration AXI bus, A first set of one or more of the DSP block partial reconfiguration regions is a larger PR region that can be configured as a single-channel version of the device, A second set of one or more DSP block partial reconfiguration regions is adapted to implement low-level functions, The method according to claim 1.

8. Adapted for use in an FPGA including a plurality of DSP block partial reconfiguration regions, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from within the primitive bitstream, each of the variants having two or more inputs, two or more outputs, and being connected to a configuration AXI bus, A first set of one or more of the DSP block partial reconfiguration regions is a larger PR region configured for a signal generation device or a controller device, The method according to claim 1, wherein a second set of one or more of the DSP block partial reconfiguration regions is configured for a measuring device or a monitoring device.

9. Further comprising receiving an input in a graphical user interface for selecting and connecting graphical blocks representing the functional logic of the algorithm to be implemented in the specific IC, the graphical blocks being related to reconfigurable logic, the method according to claim 1.

10. One or more non-transitory computer-readable storage media storing a sequence of instructions for configuring a digital electronic integrated circuit (IC) that supports partial reconfiguration, the specific IC having a plurality of reconfigurable partitions, and when executed using one or more processors, causing the one or more processors to, Receive an input for specifying functional logic of an algorithm to be implemented in the specific IC using reconfigurable logic; and Determine a subset of primitive functions including a specific primitive function corresponding to the functional logic. Obtaining, from the digital storage, a subset of pre-compiled primitive bitstreams corresponding to the subset of the primitive functions; Executing, using one or more partial reconfiguration operations, to write the subset of the pre-compiled primitive bitstreams to the specific IC; A non-transitory computer-readable storage medium. **Claim 11** The computer-readable medium according to claim 10, further comprising a sequence of instructions, when executed, the specific IC comprises a field programmable gate array (FPGA) having M reconfigurable partitions and N variations for each of the reconfigurable partitions, and can be written to and implemented for all combinations of M and N on the FPGA, causing the plurality of primitive bitstreams for a plurality of different primitive functions to be compiled, stored, and as a result, M*N primitives to be stored. **Claim 12** When executed, Before writing the configuration bitstream to the specific IC, using a server communicatively coupled to the client computer system to compile the plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented for the specific IC, and using the digital storage to store the plurality of pre-compiled primitive bitstreams, Causing the client computer system to send a request to the server to provide the subset of the pre-compiled primitive bitstreams corresponding to the subset of the primitive functions, Causing the server to send a response to the client computer system including the subset of the pre-compiled primitive bitstreams corresponding to the subset of the primitive functions. The computer-readable medium according to claim 10, further comprising a sequence of instructions. **Claim 13** Determining the set of primitive functions including specific primitive functions corresponding to the functional logic, when executed, causes determination of specific partitions and variations for each of the primitive functions, and further includes a sequence of instructions for storing metadata identifying the specific partitions and variations, and transmitting the request further includes transmitting the metadata along with the request, the computer-readable medium according to claim 12.

14. A plurality of rows each having a plurality of identical DSP block partial reconfiguration regions sequentially connected, and a plurality of interconnections enabling arbitrary connections between the rows, adapted for use in an FPGA, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from the primitive bitstream, each of the variants having one or more inputs and one or more outputs and being connected to a configuration AXI bus, the computer-readable medium according to claim 10.

15. Each of the variants includes logic for different purposes and has output multiplexing for selecting which signals are passed to the one or more outputs, the computer-readable medium according to claim 14, adapted for use in the FPGA.

16. Adapted for use in an FPGA having a plurality of DSP block partial reconfiguration regions, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from the primitive bitstream, each of the variants having two or more inputs and two or more outputs and being connected to a configuration AXI bus, a first set of one or more of the DSP block partial reconfiguration regions is a larger PR region that can be configured as a single-channel version of the device, a second set of one or more DSP block partial reconfiguration regions is adapted to implement low-level functions, the computer-readable medium according to claim 10.

17. Adapted for use in an FPGA that includes a plurality of rows each having a plurality of DSP block partial reconfiguration regions connected in sequence, and a plurality of interconnects that enable arbitrary connections between the rows, each of the DSP block partial reconfiguration regions being configurable as one of N variants using different bitstream primitives from within the primitive bitstream, each of the variants having two or more inputs and two or more outputs and being connected to a configuration AXI bus, A first set of one or more of the DSP block partial reconfiguration regions is a larger PR region configured for a signal generation device or a controller device, A second set of one or more of the DSP block partial reconfiguration regions is configured for a measurement device or a monitoring device, The computer-readable medium according to claim 10.

18. The computer-readable medium according to claim 10, further including a sequence of instructions that, when executed, cause a graphical user interface for selecting and connecting graphical blocks representing functional logic of an algorithm to be implemented in the particular IC to receive input, the graphical blocks being related to reconfigurable logic.

19. The method according to claim 1, wherein the digital storage includes storage selected from a group consisting of networked data storage, storage of a host computer, storage associated with a virtual computing instance, and combinations thereof.

20. The subset of primitive functions includes a second subset of primitive functions corresponding to the functional logic, A second subset of the primitive bitstream corresponding to the second subset of primitive functions is not pre-compiled into the primitive bitstream, Compiling, using a computing device, the second subset of the primitive bitstream for the second subset of primitive functions, Writing, using one or more partial reconfiguration operations, the second subset of the primitive bitstream to the particular IC. The method according to claim 1, comprising

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