Pulse neural network hardware accelerator and data processing method

Abstract

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic information technology, and more particularly, to a spiking neural network hardware accelerator and a data processing method. BACKGROUND

[0002] Spiking Neural Network (SNN) is the third generation of neural network, which simulates the way of biological neural network processing information in the brain, and uses electrical activity pulses to transmit and process information. Its background technology mainly comes from the research of brain in neuroscience and the pursuit of efficient computing model in the field of artificial intelligence, as follows: Biological basis: the brain is the perfect place to find inspiration to develop more efficient neural networks, and the operation principle of its internal synapses and neurons provides direction for the development of SNN. Biological neurons are connected through synapses, when the pulse of presynaptic neuron reaches postsynaptic neuron, and the membrane potential of postsynaptic neuron reaches threshold, the postsynaptic neuron will fire a pulse. Spike-timing-dependent plasticity (STDP) is a mechanism of synaptic plasticity, which adjusts synaptic weights based on the spike timing relationship between pulse neurons, which is very similar to the learning and memory process in biological nervous system, and provides an important theoretical basis for SNN to realize biologically reasonable learning rules.

[0003] Neuromorphic engineering promotes: from 2012 to 2019, the computing power and data generation rate required by deep learning models increased exponentially, and the problem of high energy consumption became increasingly prominent. Neuromorphic engineering is committed to imitating the computing principle of the brain to reduce the energy consumption of artificial intelligence systems. Neuromorphic sensors are inspired by biological sensors such as retina or cochlea, which usually record signal changes rather than regular sampling, and only generate "pulse" signals when changes occur. The neuromorphic algorithm based on this kind of signal processing gave birth to the spiking neural network.

[0004] Improvement needs for traditional neural networks: traditional artificial neural networks (ANN), such as deep convolutional neural network (DCNN), use rate-based coding, and hardware implementation consumes a lot of energy. In SNN, each neuron uses at most one pulse, and most neurons do not fire at most times, so the energy consumption is small. The deep network composed of SNN is an efficient and energy-saving neural network, and only a few peaks of each image are used as features, which is suitable for the implementation of neuromorphic hardware.

[0005] Theory and model development: The concept of spiking neural networks was first proposed in the late 1990s, and around 2000 it began to receive widespread attention in the field of computational neuroscience and artificial intelligence. The Izhikevich neuron dynamics model proposed by Eugene Izhikevich is widely used in SNN, and the research on the dynamics and computational function of spiking neurons by Wulfram Gerstner and other scholars has laid a foundation for the theoretical and practical development of SNN technology.

[0006] As shown in Figure 1 , a single synapse core receives spikes from the network into an input buffer, the axon is represented by a horizontal line, the dendrite is represented by a vertical line, and the neuron (represented by a triangle) sends spikes into the network. A synapse is connected between the axon and the dendrite, represented by a black dot. The synapses of each core are organized into a synapse crossbar. The output of each neuron is connected to the input buffer of the axon in communication with it. This axon may be in communication with the neuron or located in a different core, in which case communication occurs through a routing network. The computation of a synapse core performs the following steps.

[0007] 1) The synapse core receives spikes from the network and stores them in the input buffer.

[0008] 2) When a 1 kHz synchronous trigger signal called tick arrives, spikes are distributed from the input buffer to the corresponding horizontal axons.

[0009] 3) When there is a synaptic connection between the axon and the vertical dendrite, the spike from the axon is transmitted to the neuron through the dendrite.

[0010] 4) Each neuron integrates its incoming spikes and updates its membrane potential.

[0011] 5) When all spikes are integrated into the neuron, a leakage value is subtracted from the membrane potential.

[0012] 6) If the updated membrane potential exceeds the threshold, a spike is generated and sent to the network. All calculations must be completed within the current clock cycle, which spans 1 millisecond. Although the order of spikes from the network may differ due to network delays, core calculations are deterministic within tick due to the input buffer.

[0013] As shown in Figure 2 , due to the spiking nature of SNN, the training of the model cannot use traditional gradient descent algorithms because spikes are not differentiable. The existing mainstream solutions are to use alternative gradient, ANN2SNN weight conversion, etc. to train the SNN model.

[0014] The area and computing power cannot be well balanced. For SNN, the high parallelism of neurons is one of the important characteristics, and the existing technologies are all implemented at the cost of sacrificing area to achieve high computing power, resulting in high cost and inability to be widely applied. For example, IBM's TrueNorth and Tsinghua's Tianji core. For resource-limited edge terminals, the full neurons of an SNN network cannot be deployed, and the computing power and throughput are greatly reduced. SUMMARY

[0015] In order to solve the problem that the resource-limited edge terminal SNN hardware processor cannot perform high-parallel computing, the application provides a spiking neural network hardware accelerator and a data processing method, which can greatly improve the data processing acceleration performance.

[0016] Specifically, the first aspect of the application provides a spiking neural network hardware accelerator, comprising: A low-power three-stage pipeline CPU module is configured to receive input data, schedule SNN network acceleration instructions, and send the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface. The asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic cores, and an on-chip network. The pulse data encoding and decoding module encodes the input data into a pulse form and sends it to the neuromorphic core. The neuromorphic core is configured to perform calculation based on the pulse form data. The on-chip network is configured to communicate between the neuromorphic cores. The connection between the presynaptic and postsynaptic neurons in the neuromorphic core is realized by a synaptic cross array.

[0017] In an embodiment, the neuromorphic core adopts a crossbar switch matrix structure to represent the connection relationship between the presynaptic and postsynaptic neurons, and adds a pulse input buffer to each crosspoint synapse structure.

[0018] In an embodiment, the pulse data encoding and decoding module is specifically configured to: According to the signal type and amplitude of the input data, dynamically select an encoding mode.

[0019] In an embodiment, the neuromorphic core uses a LIF model to perform membrane potential update through a hardware circuit, and the specific mode is as follows:

[0020]

[0021] wherein, , V(t) represents the membrane voltage of the neuron at time t, , V(t) represents the membrane voltage of the neuron at time t, I(t) represents the synaptic current, represents a spike emission threshold, and α represents a leakage coefficient, is a coefficient.

[0022] In an embodiment, the neuromorphic kernel dynamically updates the synaptic current according to the STDP learning rule, and the change amount of the synaptic weight is:

[0023]

[0024] wherein, represents the time difference between the pre-synaptic and post-synaptic pulse emissions, represents the weight change due to the time difference between the pre-synaptic and post-synaptic pulse emissions, if , the pre-synaptic and post-synaptic pulse emissions are irrelevant, , and is a time constant, is a learning rate, represents the increase amount of the synaptic weight, represents the decrease amount of the synaptic weight.

[0025] In an embodiment, the on-chip network is specifically used for scheduling the transmission of pulses between different neural kernels according to the priority of the pulse data, constructing a topology structure, and simulating the information interaction and decision-making process of a biological neural network.

[0026] In an embodiment, the on-chip network is further used for: According to the pulse results output by the neural kernel, dynamically planning the transmission path according to the data packet identifier, and automatically shutting down part of the idle links and reducing the clock frequency of the routing node during the task idle period.

[0027] In an embodiment, the pulse data encoding and decoding module is further used for: According to the pulse results output by the neural kernel, counting the number of pulses and the phase distribution in a fixed time window, mapping the digital decision results, and feeding back to the low-power three-stage pipeline CPU module through the coprocessor interface.

[0028] Based on the same inventive concept, the second aspect of the present application provides a data processing method based on the pulse neural network hardware accelerator of the first aspect, comprising: receiving input data through the low-power three-stage pipeline CPU module, scheduling the SNN network acceleration instructions, and sending the input data to the asynchronous edge SNN hardware accelerator module through the coprocessor interface; The input data is encoded into pulse form by the pulse data codec module and sent into the neuromorphic kernel, the neuromorphic kernel performs calculation based on the pulse form data, and the on-chip network neuromorphic kernel intercommunication, wherein the connection between the presynaptic and postsynaptic neurons in the neuromorphic kernel is realized by a synaptic crossbar array.

[0029] In an embodiment, the neuromorphic kernel adopts a crossbar matrix structure to represent the connection relationship between the presynaptic and postsynaptic neurons, and adds a pulse input buffer to each crosspoint synapse structure.

[0030] Compared with the prior art, the advantages and beneficial technical effects of the present application are as follows: The application discloses a kind of pulse neural network hardware accelerator, including low-power three-stage pipeline CPU module and asynchronous asynchronous edge SNN hardware accelerator module, adopt "low-power three-stage pipeline CPU+ coprocessor interface+ asynchronous edge SNN hardware accelerator" architecture, let CPU be responsible for task scheduling and basic pre-processing, accurately unload SNN computing task to accelerator, reasonable distribution of task is realized.Meanwhile, the synaptic crossbar array used between the presynaptic and postsynaptic neurons in the neuromorphic kernel does not excessively occupy area on the basis of improving neuron connection density and signal transmission parallelism;Pulse cache mechanism increases synapse throughput, improves the computing power output in unit area.This design balances area and computing power, so that SNN network can be efficiently run in the edge end with limited resources, avoids the decline of computing power and throughput caused by unable to unfold all neurons, reduces cost, is conducive to the wide application of SNN in edge device.

[0031] Further, the present application provides a hardware basis for efficient training of SNN on edge device through the cooperative design of neuron synapse of Crossbar structure (crossbar matrix structure) in neuromorphic kernel and pulse cache mechanism.Crossbar structure realizes parallelization of synapse signal transmission and weight interaction among multiple groups of neurons, and pulse cache guarantees orderly processing in high-concurrency pulse scenario, so that SNN model can directly learn and optimize at pulse level in edge end, reduces the dependence on complex training methods such as substitute gradient, reduces the difficulty of SNN model training, and improves the training efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0033] Figure 1A TrueNorth neuromorphic kernel architecture diagram in the prior art; Figure 2 A schematic diagram of a traditional gradient descent learning algorithm; Figure 3 An architecture diagram of the pulse neural network hardware accelerator proposed in the present application; Figure 4 A neuromorphic kernel structure schematic diagram in the embodiment of the present application; Figure 5 A synapse structure schematic diagram in the embodiment of the present application; Figure 6 A LIF neuron structure schematic diagram in the embodiment of the present application; Figure 7 A structure diagram of a three-stage pipeline CPU in the embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiment provides a pulse neural network hardware accelerator, which comprises: A low-power three-stage pipeline CPU module is configured to receive input data, schedule SNN network acceleration instructions, and send the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface. The asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels, and an on-chip network, wherein the pulse data encoding and decoding module encodes the input data into a pulse form and sends the pulse form into the neuromorphic kernels, the neuromorphic kernels are configured to perform calculation based on the pulse form data, and the on-chip network is configured to realize communication between the neuromorphic kernels, wherein the connection between the presynaptic neuron and the postsynaptic neuron in the neuromorphic kernel is realized by using a synapse cross array.

[0035] Specifically, to solve the problems in the prior art, the present application proposes a pulse neural network hardware accelerator, which can greatly improve the data processing acceleration performance. Figure 3 As shown in the figure, the edge SNN processor designed in the present application comprises a low-power three-stage pipeline CPU module and an asynchronous edge SNN hardware accelerator module. The CPU is responsible for scheduling SNN network acceleration instructions and data transfer, and the input data enters the SNN hardware accelerator through a coprocessor interface. The asynchronous edge SNN hardware accelerator mainly comprises a pulse data encoding and decoding module, L neuromorphic kernels, and an on-chip network. The pulse data encoding and decoding module is mainly configured to encode the input data into a pulse form to send into the neuromorphic kernels for calculation, and the on-chip network is configured to realize communication between the neuromorphic kernels. The structure of the three-stage pipeline CPU is as shown in the figure. Figure 7

[0036] The neuromorphic kernel structure is as shown in the figure. Figure 4 ​As shown, the connection between the pre-synaptic and post-synaptic neurons is realized by a synaptic cross array, the number of pre-synaptic and post-synaptic neuron dendrites and axons can be determined by configuration, and the structure simulates the process of biological neuron information transmission, when the pre-synaptic neuron transmits a pulse through the axon, the stimulation is transmitted to the post-synaptic neuron through the synaptic structure, and the post-synaptic neuron receives the pulse through the dendrite structure. The present application uses Crossbar structure to represent the connection relationship between pre-synaptic and post-synaptic neurons, and the cross point represents the synaptic structure. Compared with the traditional neuron-synapse structure realized based on network layer, the present application greatly saves resources by multiplexing corssbar structure, and is suitable for edge implementation.

[0037] The realized synaptic internal structure is as shown in Figure 5 For the traditional synaptic cross array, there is no pulse buffer unit inside the cross point, so the cross array can only process one or part of the pulse input at a time, which results in small throughput and limited single-core computing capacity. The present application adds a pulse input buffer to each cross point synaptic structure based on Crossbar, which increases the parallelism of multi-channel pulse input. When multiple intensive pulses enter the same post-synaptic neuron, they can be stored in the synaptic pulse input buffer, thereby increasing the throughput of the neuromorphic core.

[0038] The neuron adopts a LIF neuron structure, as shown in Figure 6 The circuit is described according to the following formula.

[0039] The neuromorphic core receives a pulse sequence and starts a brain-like operation. Using the Leaky-Integrate-and-Fire neuron model, the hardware circuit updates the membrane potential in real time:

[0040]

[0041] Wherein is the membrane voltage of the neuron at time t, is the synaptic current, is the spike emission threshold, and alpha (leakage coefficient) is configured by the task scenario (for example, when processing slow physiological signals, alpha is 0.8, which prolongs the membrane potential decay and preserves the long-term characteristics of the signal), and Isyn (synaptic current) is dynamically updated according to the STDP learning rule: the STDP rule is improved on the basis of the Hebb rule, considering the time sequence of neuron pulse emission, which can better meet the actual situation of biological nervous system operation. Assuming that the pre-synaptic neuron is i, the post-synaptic neuron is j, and the weight connecting them is If the pulse emission time of i is earlier than the pulse emission time of j This leads to long-term potential (LTP). It will increase. Conversely, it will trigger long-term depression (LTD). It will decrease. The change in synaptic weights. As shown below:

[0042]

[0043] in, t is the time difference between the presynaptic and postsynaptic pulse firing. If If t = 0, then the firing of presynaptic and postsynaptic pulses is independent, W( t)=0. τ+ and τ Let η be the time constant and η be the learning rate. Typically, the value of η+ should be greater than η. This ensures that the increase in synaptic weights is greater than the decrease, thereby guaranteeing that network learning is enhanced, ensuring convergence speed, helping the network adapt to and learn input patterns more quickly, and improving learning efficiency.

[0044] Changes in synaptic weights Weighting changes due to the time difference between presynaptic and postsynaptic pulse firing , This represents the change in weight caused by a set of consecutive pulses, while It is obtained by summing up the weight changes of all previous and subsequent pulses relative to the current pulse.

[0045] When multiple kernels run in parallel, the on-chip network schedules the transmission of pulses between different kernels based on the priority of pulse data (e.g., pulses marked with "fault features" are given high priority and routed preferentially). This constructs topologies such as convolutional connections (for image-based SNN tasks) and fully connected connections (for classification and decision-making tasks), simulating the information interaction and decision-making process of biological neural networks.

[0046] Network-on-Chip (NoC): The NoC serves as the communication hub between kernels and between the kernel and codec modules, employing an asynchronous wormhole routing protocol. When the neuromorphic kernel outputs a pulse result (such as a "device failure" decision pulse), the routing nodes dynamically plan the transmission path based on the packet identifier (including the target module ID, such as the "result pulse packet" returned to the CPU). This involves avoiding congested links, monitoring data volume and latency in each channel, and automatically switching routes. Simultaneously, during idle periods (such as data acquisition intervals or when the SNN model is waiting for new input), the NoC automatically shuts down some idle links and reduces the clock frequency of the routing nodes. Combined with overall system-level power management, this achieves hardware-level energy efficiency optimization.

[0047] The pulse sequence output by the neuromorphic kernel, such as a decision pulse representing "healthy / faulty" "normal / abnormal", is fed back to the pulse data codec module for decoding. By counting the number of pulses and the phase distribution in a fixed time window, a digital decision result (such as 100 pulses corresponding to "device failure" and 20 pulses corresponding to "normal") is mapped and fed back to the CPU through the coprocessor interface. The CPU drives the edge device to perform actions according to the result: triggering an alarm device in an industrial scenario, recording fault time; in a wearable device, pushing a health warning and adjusting the monitoring frequency.

[0048] The technical key points of the application are as follows: Focus on SNN acceleration of edge devices, build a dedicated architecture with "low-power three-stage pipeline CPU + coprocessor interface + asynchronous edge SNN hardware accelerator" as the core, CPU is responsible for task scheduling and basic preprocessing, offload SNN computing tasks to the accelerator through the coprocessor interface, and improve the efficiency of SNN task processing in edge scenarios.

[0049] The neurons and synapses of the neuromorphic kernel adopt the Crossbar structure, which simulates the parallel connection characteristics of biological synapses, realizes the parallelization of synaptic signal transmission and weight interaction between multiple groups of neurons, and improves the connection density of neurons and the parallel degree of signal transmission.

[0050] The pulse buffer mechanism is introduced in the synaptic module to temporarily store the pulse signals to be processed, and release them to the synaptic computing unit in order through a preset scheduling strategy (such as priority and timing matching), avoiding pulse transmission conflicts and congestion, and significantly increasing the synaptic data throughput.

[0051] The modules in the asynchronous edge SNN hardware accelerator work together, the pulse data codec module adapts to the pulse conversion of edge multi-source heterogeneous input, the neuromorphic kernel relies on Crossbar synapses and pulse buffer to perform efficient computation, and the on-chip network ensures fast data interaction between modules, which together promote edge SNN acceleration.

[0052] The following points are protected: The edge SNN acceleration dedicated architecture includes the composition of "low-power three-stage pipeline CPU + coprocessor interface + asynchronous edge SNN hardware accelerator", the connection relationship between modules, the function division, and the cooperative processing logic for edge SNN tasks.

[0053] The Crossba structure is adopted in the neuromorphic kernel, which covers the circuit implementation of the structure, the layout method in the neuron connection, and the implementation scheme of multi-neuron parallel synaptic interaction.

[0054] The pulse cache mechanism in the synaptic module, including the hardware structure (such as circuit form, storage logic) of the pulse cache, the scheduling strategy (priority scheduling, timing scheduling, etc.) and the technical means for improving the synaptic throughput through the same.

[0055] The cooperative working mechanism of each module in the asynchronous edge SNN hardware accelerator, including the pulse data encoding and decoding module, the neuromorphic kernel (including Crossbar synapse, pulse cache), the data interaction process between the on-chip network, the control instruction interaction logic and the cooperative technology suitable for edge SNN acceleration.

[0056] Based on the same inventive concept, the embodiment also provides a data processing method based on the foregoing pulse neural network hardware accelerator, comprising: Receiving input data through a low-power three-stage pipeline CPU module, scheduling SNN network acceleration instructions, and sending input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; Encoding the input data into pulse form through the pulse data encoding and decoding module and sending it into the neuromorphic kernel, calculating based on the pulse form data through the neuromorphic kernel, and communicating between the neuromorphic kernels through the on-chip network, wherein the connection between the presynaptic and postsynaptic neurons in the neuromorphic kernel is realized by the synaptic crossbar array.

[0057] Specifically, the data processing method mainly includes the following three stages: I. Data input and initial flow (taking a typical task in an edge intelligent scene as an example, such as SNN inference driven by multi-modal sensor data) Multi-source data acquisition and aggregation: In an edge deployment scene (such as intelligent industrial monitoring, wearable health devices), various sensors (temperature, vibration, bioelectricity sensors, etc.) collect original physical signals, which are converted into digital signals (such as analog voltage signals quantized into 0-255 grayscale value type numerical sequences) through a sensor interface, and temporarily stored in the cache area of the edge storage module. At the same time, if there are historical task data (such as device past abnormal vibration waveform, user health benchmark physiological data), load them from non-volatile storage (such as eMMC) to the cache, and aggregate with real-time collected data to provide multi-dimensional input for SNN calculation.

[0058] CPU preliminary scheduling and preprocessing: The low-power three-stage pipeline CPU reads data from the cache and starts the preprocessing process according to the task type (such as device fault detection, health status classification). Through the SNN adaptation instruction in the reduced instruction set, the data is denoised (such as using the moving average algorithm to accelerate hardware, and the light computing unit in the execution stage completes the data average operation in the sliding window), and the features are cropped (such as retaining the signal frequency band related to the SNN task, such as extracting the effective components of the brain electrical signal in the 0.5-30Hz band of the bioelectric signal). At the same time, the CPU sends preliminary configuration signals to the asynchronous edge SNN hardware accelerator through the coprocessor interface based on the asynchronous communication protocol, such as marking the range of neuro-morphic kernel numbers to be activated (2-4 for simple tasks, and 8-16 for complex fault diagnosis) according to the task complexity, to prepare for subsequent acceleration calculation.

[0059] II. Asynchronous edge SNN hardware accelerator processing stage Pulse data encoding and decoding: After CPU preprocessing, the data is sent to the pulse data encoding and decoding module through the asynchronous FIFO buffer and handshake signal interaction of the coprocessor interface. If the processing device is a vibration signal (numerical sequence), the encoding algorithm dynamically selects according to the signal amplitude: low amplitude normal vibration segment, frequency encoding (such as amplitude 0-50 corresponding to pulse frequency 0-500Hz, the numerical value is mapped to pulse firing period through hardware circuit), highlighting the signal smooth change; high amplitude abnormal vibration segment, switch to phase encoding (different phase intervals correspond to amplitude intervals, such as 0°-90° phase pulse representing amplitude 50-100), accurately capturing mutation characteristics. The encoded pulse sequence carries data feature labels (such as "abnormal vibration feature pulse stream" label), and is sent to the neuro-morphic kernel through the asynchronous routing channel of the network on chip (NoC).

[0060] Neuro-morphic kernel: The neuro-morphic kernel receives the pulse sequence and starts the brain-like operation. The specific formula is described in the previous section and will not be repeated here.

[0061] When multiple kernels are parallel, the network on chip (NoC) schedules the transmission of pulses between different kernels according to the priority of pulse data (such as pulses marked with "fault feature" are given high priority and are routed first), constructs topological structures such as convolutional connections (processing image SNN tasks) and fully connected (classification decision tasks), and simulates the information interaction and decision-making process of biological neural networks.

[0062] Network on chip: The network on chip (NoC) is the communication hub between kernels and between kernels and encoding and decoding modules, and uses an asynchronous wormhole routing protocol.

[0063] III. Result output and system coordination Pulse decoding and decision execution: the pulse sequence output by the neuromorphic kernel (such as the decision pulse representing "healthy / faulty", "normal / abnormal") is fed back to the pulse data codec module for decoding. By counting the number of pulses and phase distribution in a fixed time window, the digital decision result (such as 100 pulses corresponding to "device failure" and 20 pulses corresponding to "normal") is mapped and fed back to the CPU through the coprocessor interface. The CPU drives the edge device to perform actions according to the result: triggering an alarm device in an industrial scenario, recording fault time; in a wearable device, pushing health warnings and adjusting monitoring frequency.

[0064] Overall, the beneficial technical effects of the technical solution of the present application are as follows: In view of the problem in the prior art that SNN is difficult to use traditional gradient descent algorithm for training due to non-differentiable pulses, and needs to rely on complex methods such as alternative gradient and ANN2snn weight conversion, the present application provides a hardware basis for efficient training of SNN on edge devices through the cooperative design of neuron synapses in the Crossbar structure of the neuromorphic kernel and the pulse cache mechanism. The Crossbar structure realizes the parallelization of synaptic signal transmission and weight interaction among multiple groups of neurons, and the pulse cache ensures orderly processing in high-concurrency pulse scenarios. Combined with the online learning algorithm STDP, the SNN model can directly learn and optimize at the pulse level on the edge, reducing the dependence on complex training methods such as alternative gradient, reducing the difficulty of SNN model training, and improving the training efficiency.

[0065] For the problem in the prior art that SNN sacrifices area for high computing power, resulting in high cost, and cannot deploy all neurons on the resource-limited edge, thereby reducing computing power and throughput, the present application focuses on the key role of the SNN acceleration exclusive architecture of edge devices. The architecture of "low-power three-stage pipeline CPU + coprocessor interface + asynchronous edge SNN hardware accelerator" enables the CPU to be responsible for task scheduling and basic preprocessing, and accurately offloads SNN computing tasks to the accelerator, realizing reasonable allocation of tasks. At the same time, the Crossbar structure does not excessively occupy area on the basis of improving neuron connection density and signal transmission parallelism; the pulse cache mechanism increases synaptic throughput and improves the computing power output per unit area. This design balances area and computing power, enabling efficient operation of SNN network on the resource-limited edge, avoiding the reduction of computing power and throughput due to the inability to deploy all neurons, reducing cost, and facilitating the widespread application of SNN in edge devices.

[0066] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, a system or a computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer-readable program code.

[0067] The present application is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing machine, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in one or more of the flowchart and / or block diagrams. Figure 1 one or more functions specified in one or more of the flowchart and / or block diagrams.

[0068] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the scope of the application. It should be apparent that the application is susceptible to various modifications and alternative forms evident to those skilled in the art without departing from the spirit and scope of the application. Accordingly, the application is intended to embrace all such alternatives, modifications and variations as fall within the scope of the claims, along with all equivalents thereof.

Claims

1. A spiking neural network hardware accelerator, characterized in that, include: The low-power three-stage pipelined CPU module is used to receive input data, schedule SNN network acceleration instructions, and send the input data to the asynchronous edge SNN hardware accelerator module through the coprocessor interface. The asynchronous edge SNN hardware accelerator module includes a pulse data encoding and decoding module, L neuromorphic kernels, and an on-chip network. The pulse data encoding and decoding module encodes the input data into pulse form and sends it to the neuromorphic kernel. The neuromorphic kernel is used for computation based on the pulse data. The on-chip network is used for communication between neuromorphic kernels. The connection between presynaptic and postsynaptic neurons in the neuromorphic kernel is implemented using a synaptic crossover array.

2. The spiking neural network hardware accelerator of claim 1, wherein, The neuromorphic kernel uses a cross-switch matrix structure to represent the pre- and post-synaptic connections, and adds a pulse input buffer to each cross-synaptic structure.

3. The spiking neural network hardware accelerator of claim 2, wherein, The pulse data encoding / decoding module is specifically used for: The encoding method is dynamically selected based on the signal type and amplitude of the input data.

4. The spiking neural network hardware accelerator of claim 1, wherein, The neuromorphic kernel uses the LIF model and performs membrane potential updates via hardware circuitry, specifically as follows: wherein, , respectively represent the membrane voltage of a neuron , at a certain time instant, represents the synaptic current, represents the spike emission threshold, and a represents the leakage coefficient, is a coefficient.

5. The spiking neural network hardware accelerator of claim 4, wherein, The neuromorphic kernel dynamically updates synaptic currents according to the STDP learning rule, and the change in synaptic weights is: wherein, denotes the time difference between the pre- and post-synaptic spike, denotes the change in weight due to the time difference between the pre- and post-synaptic spike, if then the pre- and post-synaptic spike are independent of each other, , and is a time constant, is a learning rate, denotes the amount of increase of the synaptic weight, denotes the amount of decrease of the synaptic weight.

6. The spiking neural network hardware accelerator of claim 1, wherein, The on-chip network is specifically used to schedule the transmission of pulses between different neural kernels based on the priority of pulse data, construct a topology, and simulate the information interaction and decision-making process of biological neural networks.

7. The spiking neural network hardware accelerator of claim 1, wherein, On-chip networks are also used for: Based on the pulse results output by the neural kernel, the transmission path is dynamically planned according to the packet identifier, and some idle links are automatically shut down and the clock frequency of the routing nodes is reduced during the idle period of the task.

8. The spiking neural network hardware accelerator of claim 1, wherein, The pulse data encoding / decoding module is also used for: Based on the pulse results output by the neural kernel, the number of pulses and phase distribution within a fixed time window are statistically analyzed, mapped to digital decision results, and fed back to the low-power three-stage pipeline CPU module through the coprocessor interface.

9. A data processing method based on the pulse neural network hardware accelerator according to any one of claims 1 to 8, characterized in that, include: The input data is received through a low-power three-stage pipelined CPU module, the SNN network acceleration instructions are scheduled, and the input data is sent to the asynchronous edge SNN hardware accelerator module through the coprocessor interface. The input data is encoded into pulse form by the pulse data encoding and decoding module and sent to the neuromorphic kernel. The neuromorphic kernel performs calculations based on the pulse data and communicates with each other through the on-chip network. The connection between presynaptic and postsynaptic neurons in the neuromorphic kernel is realized by the synaptic crossover array.

10. The data processing method of claim 9, wherein, The neuromorphic kernel uses a cross-switch matrix structure to represent the pre- and post-synaptic connections, and adds a pulse input buffer to each cross-synaptic structure.

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