Semiconductor device

Abstract

To provide a semiconductor device that is less prone to the fluctuation in the electrical characteristic due to miniaturization.SOLUTION: A semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions, a gate insulating film provided over the oxide semiconductor film, and a first electrode overlapping the first region on the gate insulating film, and the first region is a CAAC oxide semiconductor region, and the pair of second regions and the pair of third regions are amorphous oxide semiconductor regions containing a dopant, and the dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention to be disclosed relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor in this specification is a semiconductor device, and an electric optical device, a semiconductor circuit, and an electronic device including the transistor are all included in the semiconductor device.

Background Art

[0003] Most of the transistors used in flat panel displays typified by liquid crystal display devices and light emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon formed on a glass substrate, or polycrystalline silicon. Further, transistors using the silicon semiconductor are also used in integrated circuits (ICs) and the like.

[0004] Instead of the above silicon semiconductor, a technique of using a metal oxide exhibiting semiconductor characteristics for a transistor has been attracting attention. In this specification, a metal oxide exhibiting semiconductor characteristics will be referred to as an oxide semiconductor.

[0005] For example, as the oxide semiconductor, a technique of manufacturing a transistor using zinc oxide, an In-Ga-Zn-O-based oxide and using the transistor for a switching element of a pixel of a display device or the like has been disclosed (see Patent Document 1 and Patent Document 2).

[0006] Further, in a transistor using an oxide semiconductor, a highly conductive oxide semiconductor containing nitrogen is provided as a buffer layer between the source region and the drain region and between the source electrode and the drain electrode. By providing , a technique for reducing the contact resistance between the oxide semiconductor and the source and drain electrodes is disclosed (see Patent Document 3).

[0007] Also, as a method of self-aligning the source and drain regions of a transistor using an oxide semiconductor, a method of exposing the surface of the oxide semiconductor and performing argon plasma treatment to reduce the resistivity of the oxide semiconductor in the exposed portion is disclosed (see Non-Patent Document 1).

[0008] However, in this method, by exposing the surface of the oxide semiconductor and performing argon plasma treatment, the oxide semiconductor in the portions that are to become the source and drain regions is also etched simultaneously, and the source and drain regions become thinner (see FIG. 8 of Non-Patent Document 1). As a result, the resistance of the source and drain regions increases, and the probability of defective products due to overetching accompanying the thinning also increases.

[0009] This phenomenon becomes prominent when the ion species used for plasma treatment of the oxide semiconductor has a large atomic radius.

[0010] If the oxide semiconductor layer has a sufficient thickness, there is no problem. However, when the channel length is 200 nm or less, in order to prevent the short-channel effect, the thickness of the oxide semiconductor layer in the channel portion is required to be 20 nm or less, preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, the above plasma treatment is not preferable.

[0011] ​​​​​​​​​​​​​ Patent Document 1 Japanese Patent Application Laid-Open No. 2007-123861 Patent Document 2 Japanese Patent Application Laid-Open No. 2007-96055 Patent Document 3 Japanese Patent Application Laid-Open No. 2010-135774 Non-Patent Document

[0012] Non-Patent Document 1 S. Jeon et al. ”180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application”, IEDM Tech. Dig., p.504, 2010. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0013] In an integrated circuit using transistors, miniaturization of the transistors is necessary for integration .

[0014] In the miniaturization of transistors, transistors with an extremely short channel length exhibit variations in electrical characteristics such as a decrease in threshold voltage . This phenomenon is called the short-channel effect, and suppressing this short-channel effect is one of the problems in transistor miniaturization .

[0015] Transistors using an oxide semiconductor are known to have a small off-current at room temperature compared to transistors using silicon, which is considered to be because there are few carriers generated by thermal excitation, that is, the carrier density is small . That is, it is considered to be because the carrier density is small

[0016] One aspect of the present invention is to provide a semiconductor device in which variations in electrical characteristics due to miniaturization are less likely to occur. This is the problem to be solved.

Means for Solving the Problem

[0017] The means for solving the above problem is to provide a region containing a dopant in an oxide semiconductor film including a channel formation region in a transistor using an oxide semiconductor. Specifically, a pair of amorphous regions containing a dopant are provided at two locations in the oxide semiconductor film including the channel formation region, and a difference is provided in the dopant concentration of each region. By doing so, the electric field generated in the drain region of the oxide semiconductor film can relax the electric field applied to the channel formation region, so that the short-channel effect can be suppressed. In this specification, the dopant is a general term for elements added to the oxide semiconductor film including the channel formation region. Further, the oxide semiconductor in the channel formation region is non-single crystal. Specifically, when viewed from a direction perpendicular to the ab plane of the non-single crystal, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c axis, it includes a crystal portion in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. In this specification, the crystal portion is referred to as a c-axis oriented crystal, and the oxide semiconductor having the c-axis oriented crystal is referred to as a CAAC oxide semiconductor (CAAC-OS: c-axis aligned crystaline oxide semiconductor). Further, by making the channel formation region a CAAC oxide semiconductor region, variations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be suppressed, and the reliability of the semiconductor device can be improved. That is, two pairs of amorphous regions containing a dopant are provided in the oxide semiconductor film including the channel formation region, and a difference is provided in the dopant concentration of each region. By doing so, the electric field generated in the drain region of the oxide semiconductor film can relax the electric field applied to the channel formation region, so that the short-channel effect can be suppressed. In this specification, the dopant is a general term for elements added to the oxide semiconductor film including the channel formation region. Further, the oxide semiconductor in the channel formation region is non-single crystal. Specifically, when viewed from a direction perpendicular to the ab plane of the non-single crystal, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c axis, it includes a crystal portion in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. In this specification, the crystal portion is referred to as a c-axis oriented crystal, and the oxide semiconductor having the c-axis oriented crystal is referred to as a CAAC oxide semiconductor (CAAC-OS: c-axis aligned crystaline oxide semiconductor).

[0018] Further, by making the channel formation region a CAAC oxide semiconductor region, variations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be suppressed, and the reliability of the semiconductor device can be improved. That is, when viewed from a direction perpendicular to the ab plane of the non-single crystal, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c axis, it includes a crystal portion in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. In this specification, the crystal portion is referred to as a c-axis oriented crystal, and the oxide semiconductor having the c-axis oriented crystal is referred to as a CAAC oxide semiconductor (CAAC-OS: c-axis aligned crystaline oxide semiconductor). Further, by making the channel formation region a CAAC oxide semiconductor region, variations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be suppressed, and the reliability of the semiconductor device can be improved. In this specification, the crystal portion is referred to as a c-axis oriented crystal, and the oxide semiconductor having the c-axis oriented crystal is referred to as a CAAC oxide semiconductor (CAAC-OS: c-axis aligned crystaline oxide semiconductor). S: c-axis aligned crystaline oxide semiconductor Further, by making the channel formation region a CAAC oxide semiconductor region, variations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be suppressed, and the reliability of the semiconductor device can be improved. That is, variations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be suppressed, and the reliability of the semiconductor device can be improved. In this specification, the crystal portion is referred to as a c-axis oriented crystal, and the oxide semiconductor having the c-axis oriented crystal is referred to as a CAAC oxide semiconductor (CAAC-OS: c-axis aligned crystaline oxide semiconductor).

[0019] Therefore, one aspect of the present invention is a first region and a pair of second regions in contact with the side surface of the first region and a pair of third regions in contact with the side surfaces of the pair of second regions, an oxide semiconductor film including the same, and an acid a gate insulating film provided on the oxide semiconductor film, and a first electrode overlapping the first region on the gate insulating film The first region is a CAAC oxide semiconductor region, and the pair of second regions and the pair of third regions are amorphous oxide semiconductor regions containing a dopant. The dopant concentration of the pair of third regions is higher than that of the pair of second regions. A semiconductor device is provided. The pair of second regions and the pair of third regions are provided on the side surfaces of the gate insulating film and the first electrode The dopant concentration of the pair of third regions is higher than that of the pair of second regions. A semiconductor device is provided.

[0020] The oxide semiconductor film is preferably an oxide semiconductor film containing two or more elements selected from In, Ga, Sn, and Zn is preferred.

[0021] In the semiconductor device, the pair of third regions have a second electrode and a third electrode electrically connected thereto is provided.

[0022] The pair of second regions and the pair of third regions can be formed self-aligned by adding a dopant through a sidewall insulating film provided on the side surfaces of the gate insulating film and the first electrode. That is, by providing a sidewall insulating film, the pair of second regions can be made into regions where the amount of dopant added is small (hereinafter referred to as low-concentration regions in this specification). And the pair of third regions can be made into regions where the amount of dopant added is large (hereinafter referred to as high-concentration regions in this specification). is provided. That is, by providing a sidewall insulating film, the pair of second regions can be made into regions where the amount of dopant added is small (hereinafter referred to as low-concentration regions in this specification). And the pair of third regions can be made into regions where the amount of dopant added is large (hereinafter referred to as high-concentration regions in this specification). That is, by providing a sidewall insulating film, the pair of second regions can be made into regions where the amount of dopant added is small (hereinafter referred to as low-concentration regions in this specification). ). And the pair of third regions can be made into regions where the amount of dopant added is large (hereinafter referred to as high-concentration regions in this specification). ). Further, by providing a sidewall insulating film, the pair of second regions can be made into regions for channel formation A first region that functions as a region, and a pair of third regions that function as a source region and a drain region can be formed therebetween.

[0023] The dopants added to the pair of second regions and the pair of third regions are one or more elements selected from hydrogen or noble gas elements and the dopant concentration contained in the pair of second regions and the pair of third regions is preferably 1×10 19 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less. Further, the dopant concentration of the pair of second regions is 5×10 atoms 18 / cm or more and 5×10 3 atoms / cm 19 less than, and the dopant 3 concentration of the pair of third regions is preferably 5×10 atoms / cm 19 or more and 1×10 3 atoms / cm 22 or less. 3 It is even more preferable that this be the case.

[0024] Also, in the semiconductor device according to one aspect of the present invention, the second electrode and the third electrode may be in a form in contact with the upper surface of the pair of third regions, or may be in a form in contact with the lower surface of the pair of third regions.

[0025] The range in which the gate insulating film is formed varies depending on the manner of forming the sidewall insulating film. Specifically, there are a form in which the range in which the gate insulating film is formed is on the first region, the second region, and the third region and a form in which it is only on the first region.

[0026] When the sidewall insulating film is a nitride insulating film and the gate insulating film is an oxide insulating film , due to the etching selectivity between the nitride insulator and the oxide insulator, the gate insulating film functions as an etching stopper when forming the sidewall insulating film, and can suppress excessive etching of the oxide semiconductor film in contact with the bottom surface of the gate insulating film. As a result, the semiconductor device of this configuration has a structure in which the gate insulating film remains on the first region, the pair of second regions, and the pair of third regions. When both the sidewall insulating film and the gate insulating film are made of an oxide insulator film, the gate insulating film provided on the pair of second regions and the pair of third regions can be etched by utilizing the etching selectivity between the oxide insulator film and the first electrode. As a result, the semiconductor device of this configuration has a structure in which the gate insulating film remains on the first region. The addition of dopants for forming the low-concentration region and the high-concentration region of the transistor, which is one aspect of the present invention, can be performed using the ion doping method, the ion implantation method, or the like. Furthermore, instead of the ion doping method or the ion implantation method, dopants can also be added by generating plasma in a gas atmosphere containing the dopants to perform plasma treatment on the object to be added.

[0027] When using an element with a large atomic radius such as a noble gas as the dopant and adding it by the above plasma treatment, it is preferably performed in a state where the gate insulating film covers the oxide semiconductor film (a state where the gate insulating film is provided on the first region, the pair of second regions, and the pair of third regions). Because in the manufacturing process of the transistor, when the above plasma treatment is performed with the oxide semiconductor film exposed,

[0028]

[0029]

[0029] ​​​​When this is done, the portions that will become a pair of third regions of the oxide semiconductor film are etched to thin the film. This is because there is a possibility of this occurring.

[0030] By doing so, etching of the portions that will become the high-concentration regions of the oxide semiconductor film can be prevented, and thinning of the high-concentration regions can be suppressed. In addition, the interface between the oxide semiconductor film and the gate insulating film can be kept clean, so that the electrical characteristics and reliability of the transistor can be improved.

Advantages of the Invention

[0031] According to one aspect of the present invention, a semiconductor device using an oxide semiconductor with good electrical characteristics and reliability and that is easy to miniaturize can be provided.

Brief Description of the Drawings

[0032]

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DETAILED DESCRIPTION OF THE INVENTION

[0033] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repeated description thereof will be omitted. Moreover, in each drawing described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. In addition, the terms such as first, second, and third used in this specification are attached to avoid confusion of components and are not numerically limiting. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. The functions of "source" and "drain" change when the direction of current changes in the circuit operation, etc. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repeated description thereof will be omitted. Moreover, in each drawing described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0034] Moreover, in each drawing described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Moreover, in each drawing described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0035] In addition, the terms such as first, second, and third used in this specification are attached to avoid confusion of components and are not numerically limiting. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. For example, "the first" can be appropriately replaced with "the second" or "the third" and described. The functions of "source" and "drain" change when the direction of current changes in the circuit operation, etc.

[0036] The functions of "source" and "drain" change when the direction of current changes in the circuit operation, etc. may be interchanged. Therefore, in this specification, the terms "source" and "drain" shall be used interchangeably. (Embodiment 1)

[0037] In this embodiment, the structure and manufacturing method of a transistor, which is an aspect of the present invention, will be described with reference to FIGS. 1 to 3.

[0038] <Structure and Characteristics of Transistor 100> FIG. 1(A) is a plan view of transistor 100. In FIG. 1(A), the underlying insulating film 102, gate insulating film 111, and interlayer insulating film 117 are not shown for convenience.

[0039] From FIG. 1(A), a first electrode 113 and a sidewall insulating film 115 provided on the side of the first electrode 113 are provided on the oxide semiconductor film 103. Then, the second electrode 119a and the third electrode 119b are provided on a pair of third regions 109a, 109b of the oxide semiconductor film 103 through openings 116a, 116b. Also, the second electrode 1 19a and the third electrode 119b are in contact with the upper surfaces of the pair of third regions 109a, 109b and are in contact with them. Transistor 100 is a top-gate structure and a top-contact type transistor .

[0040] FIG. 1(B) is a cross-sectional view of transistor 100 taken along the line A-B. From FIG. 1(B), an underlying insulating film 102 is provided on the substrate 101, and on the underlying insulating film 102, a first region 105, a pair of second regions 107a, 107b, and a pair of third regions 109a, 109 b including an oxide semiconductor film 103 are provided. A pair of second regions 107a, 107b is provided in contact with the side surface of the first region 105. A pair of third regions 109a, 109 b is provided in contact with the side surfaces of the pair of second regions 107a, 107b.

[0041] A gate insulating film 111 is provided on the oxide semiconductor film 103. On the gate insulating film 111 is provided a first electrode 113 that overlaps with the first region 105. On the side surface of the first electrode 11 3 are provided sidewall insulating films 115a, 115b (sidewall insulating film 115 ).

[0042] On the gate insulating film 111, the first electrode 113, and the sidewall insulating films 115a, 115b is provided an interlayer insulating film 117.

[0043] The second electrode 119a and the third electrode 119b are provided in contact with the pair of third regions 109a, 109b through openings 116a, 116b provided in the gate insulating film 111 and the interlayer insulating film 11 7. Note that the gate insulating film 111 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b.

[0044] The ends of the second electrode 119a and the third electrode 119b may be tapered, but the end of the first electrode 113 is preferably perpendicular. By making the end of the first electrode 113 perpendicular and forming an insulating film that becomes the sidewall insulating film 115 (sidewall insulating film 115a, 115b) on the first electrode 113 and performing highly anisotropic etching it becomes possible to form the sidewall insulating film 115 (sidewall insulating film 115a, 115b).

[0045] ​​Further, although details will be described later, from FIGS. 1(A) and 1(B), a pair of second regions 107a, 107b correspond to regions where the oxide semiconductor film 103 overlaps with the sidewall insulating film 115. And the sidewall insulating film 115 (sidewall insulating films 115a, 115b) may have a curved shape at least in part other than the regions in contact with the side surface of the first electrode 113 and the gate insulating film 111.

[0046] The oxide semiconductor film 103 including the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a , 109b is a metal oxide containing two or more elements selected from In, Ga, Sn, and Zn. Note that the metal oxide has a band gap of 2 eV or more , preferably 2.5 eV or more, more preferably 3 eV or more. Thus, by using a metal oxide with a wide band gap, the off-current of the transistor 100 can be reduced.

[0047] In the transistor 100, the first region 105 functions as a channel formation region.

[0048] The first region 105 is the CAAC oxide semiconductor region described above. The CAAC oxide semiconductor is not a single crystal, nor is it formed only of amorphous material. Also, the CAAC oxide semiconductor includes crystallized portions (crystalline portions), but in some cases, the boundaries between one crystalline portion and another crystalline portion cannot be clearly distinguished. A part of the oxygen contained in the CAAC oxide semiconductor may be substituted with nitrogen. Also, the c-axes of the individual crystalline portions constituting the CAAC oxide semiconductor are in a certain direction (for example, the plane of the substrate supporting the CAAC oxide semiconductor or the CAAC oxide semiconductor plane). plane). They may be aligned in a direction perpendicular to the surface, film surface, interface, etc. of the conductor film. Alternatively, CAAC acid The normal of the ab plane of each crystal part constituting the CAAC oxide semiconductor is in a certain direction (for example, the surface of the substrate supporting the CAAC oxide semiconductor, the surface, film surface, interface, etc. of the CAAC oxide semiconductor film). It may face a perpendicular direction). Note that the CAAC oxide semiconductor becomes a conductor, semiconductor, or insulator depending on its composition and the like. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. And, depending on its composition and the like, it becomes a conductor, semiconductor, or insulator. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. And, depending on its composition and the like, it becomes a conductor, semiconductor, or insulator. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. And, depending on its composition and the like, it becomes a conductor, semiconductor, or insulator. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. And, depending on its composition and the like, it becomes a conductor, semiconductor, or insulator. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. And, depending on its composition and the like, it becomes a conductor, semiconductor, or insulator. And the CAAC oxide semiconductor becomes transparent or opaque to visible light depending on its composition and the like. As an example of the CAAC oxide semiconductor, when observed from a direction perpendicular to the formed surface, the formed substrate surface, or the interface, a triangular or hexagonal atomic arrangement is observed, and when observing its formed cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Materials are mentioned. (or nitrogen atoms) are mentioned.

[0049] Also, the hydrogen concentration in the first region 105 is 1×10 20 atoms / cm 3 or less, preferably is 1×10 19 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less. The transistor 100 in which the first region 105, which is the channel formation region, is a CAAC oxide semiconductor region and the hydrogen concentration is reduced has stable electrical characteristics because the variation in the threshold voltage is small before and after light irradiation and before and after the BT (gate thermal bias) stress test, and can be said to be a highly reliable transistor. And the transistor 100 in which the first region 105, which is the channel formation region, is a CAAC oxide semiconductor region and the hydrogen concentration is reduced has stable electrical characteristics because the variation in the threshold voltage is small before and after light irradiation and before and after the BT (gate thermal bias) stress test, and can be said to be a highly reliable transistor. And the transistor 100 in which the first region 105, which is the channel formation region, is a CAAC oxide semiconductor region and the hydrogen concentration is reduced has stable electrical characteristics because the variation in the threshold voltage is small before and after light irradiation and before and after the BT (gate thermal bias) stress test, and can be said to be a highly reliable transistor. And the transistor 100 in which the first region 105, which is the channel formation region, is a CAAC oxide semiconductor region and the hydrogen concentration is reduced has stable electrical characteristics because the variation in the threshold voltage is small before and after light irradiation and before and after the BT (gate thermal bias) stress test, and can be said to be a highly reliable transistor.

[0050] The pair of second regions 107a and 107b and the pair of third regions 109a and 109b have a conductivity rate of 10 S / cm or more and 1000 S / cm or less, preferably 100 S / cm or more and 1000 S / cm or less, preferably 100 S / cm or more and 1000 S It shall be below / cm. Also, the conductivity of the pair of third regions 109a and 109b is higher than that of the pair of second regions 107a and 107b. Note that if the conductivity is too low, the on-current of the transistor 100 will decrease.

[0051] Also, the pair of second regions 107a and 107b and the pair of third regions 109a and 109b are amorphous regions containing a dopant. The pair of second regions 107a and 107b and the pair of third regions 109a and 109b have added thereto at least one element selected from hydrogen or noble gas elements as a dopant.

[0052] Increasing the dopant concentration of the pair of second regions 107a and 107b and the pair of third regions 109a and 109b can increase the carrier density, but if the dopant concentration is increased too much, the dopant will inhibit the movement of carriers, resulting in a decrease in the conductivity of the pair of second regions 107a and 107b and the pair of third regions 109a and 109b.

[0053] Therefore, the dopant concentration of the pair of second regions 107a and 107b and the pair of third regions 109a and 109b is preferably 5×10 atoms / cm 18 or more and 1×10 3 atoms / cm 22 or less. Further, the dopant concentration of the pair of third regions 109a and 109b is higher than the dopant concentration of the pair of second regions 107a and 107b. Specifically, 3 the dopant concentration of the pair of second regions 107a and 107b is 5×10 atoms / cm 18 or more and 5×10 atoms / cm 3 or less, and 19 ​3 is less than, and the dopant concentrations of a pair of third regions 109a, 1 09b are 5×10 19 atoms / cm 3 or more and 1×10 22 atom s / cm 3 is preferably below. Also, the difference in these dopant concentrations is due to the fact that sidewall insulating films 115 (sidewall insulating films 115a, 115b) are provided for the transistor 100, and they are formed in self-alignment in the process of adding dopants.

[0054] The pair of third regions 109a, 109b function as the source region and drain region of the transistor 100. The transistor 100 has an amorphous region (low concentration region and high concentration region) with a difference in dopant concentration provided at both ends of the first region 105 of the channel formation region, so that the electric field applied to the first region 105, which is the channel formation region, can be relaxed. Specifically, a pair of second regions 107a, 107b, which are low concentration regions, and a pair of third regions 109a, 109b, which are high concentration regions, are provided at both ends of the first region 105 of the channel formation region, so that the transistor 100 exhibits an effect in which almost no bending occurs at the band edge in the channel formed in the first region 105. Therefore, by providing a pair of second regions 107a, 1 07b and a pair of third regions 109a, 109b, the short-channel effect can be suppressed. 07b and a pair of third regions 109a, 109b, the transistor 100 exhibits an effect in which almost no bending occurs at the band edge in the channel formed in the first region 105. Therefore, by providing a pair of second regions 107a, 1 07b and a pair of third regions 109a, 109b, the short-channel effect can be suppressed.

[0055] <Method for fabricating the transistor 100> Next, a method for fabricating the transistor 100 will be described with reference to FIGS. 2 and 3.

[0056] A base insulating film 102 is formed on the substrate 101. The base insulating film 102 is formed by a sputtering method, C It can be formed by the VD method, the coating method, etc. There is no limitation on the thickness of the underlying insulating film 102, but the thickness of the underlying insulating film 102 is preferably 50 nm or more.

[0057] The substrate 101 is not greatly limited in terms of material, etc., but it is necessary to have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 101. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 101.

[0058] Also, a flexible substrate may be used as the substrate 101. When transistors are provided on the flexible substrate, the transistors may be directly fabricated on the flexible substrate, or transistors may be fabricated on another substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off the transistors and transfer them to the flexible substrate, it is advisable to provide an easily peelable region between the above-mentioned other substrate and the transistors.

[0059] In addition to preventing the diffusion of impurities (such as alkali metals such as Li and Na, etc.) from the substrate 101, the underlying insulating film 102 prevents the substrate 101 from being etched during the etching process in the manufacturing process of the transistor 100.

[0060] Also, as the underlying insulating film 102, oxide insulating films such as silicon oxide films, gallium oxide films, aluminum oxide films, etc., or nitride insulating films such as silicon nitride films, aluminum nitride films, etc. A single-layer structure of an insulating film selected from a film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film, or a laminated structure thereof is used. Note that the underlying insulating film 102 preferably contains oxygen at the portion in contact with the oxide semiconductor film 103. When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used.

[0061] When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed. When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed. When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed. When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed. When forming the underlying insulating film 102 by a sputtering method, a silicon target, a quartz target, an aluminum target, an aluminum oxide target, etc. may be used, and it may be formed in an atmosphere gas containing oxygen. The ratio of oxygen in the atmosphere gas should be 6% by volume or more with respect to the whole atmosphere gas. Preferably, it is 50% by volume or more. By increasing the ratio of oxygen gas in the atmosphere gas, an insulating film that releases oxygen by heating can be formed.

[0062] It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used. It is also preferable that the hydrogen in the target is removed as much as possible. Specifically, by using an oxide target with an OH group of 100 ppm or less, preferably 10 ppm or less, more preferably 1 ppm or less, the hydrogen concentration in the underlying insulating film 102 can be reduced, and the electrical characteristics and reliability of the transistor 100 can be improved. For example, fused quartz is preferable because it is easy to have an OH group of 10 ppm or less and has a low cost. Of course, a target of synthetic quartz with a low OH group concentration may also be used.

[0063] Furthermore, in the fabrication of the transistor 100, since alkali metals such as Li and Na are impurities, it is preferable to reduce their content. When using a glass substrate containing impurities such as alkali metals for the substrate 101, in order to prevent the intrusion of alkali metals, it is preferable to form the above nitride insulating film as the underlying insulating film 102, and further, on the above nitride insulating film, the above acid Furthermore, in the fabrication of the transistor 100, since alkali metals such as Li and Na are impurities, it is preferable to reduce their content. When using a glass substrate containing impurities such as alkali metals for the substrate 101, in order to prevent the intrusion of alkali metals, it is preferable to form the above nitride insulating film as the underlying insulating film 102, and further, on the above nitride insulating film, the above acid Furthermore, in the fabrication of the transistor 100, since alkali metals such as Li and Na are impurities, it is preferable to reduce their content. When using a glass substrate containing impurities such as alkali metals for the substrate 101, in order to prevent the intrusion of alkali metals, it is preferable to form the above nitride insulating film as the underlying insulating film 102, and further, on the above nitride insulating film, the above acid Furthermore, in the fabrication of the transistor 100, since alkali metals such as Li and Na are impurities, it is preferable to reduce their content. When using a glass substrate containing impurities such as alkali metals for the substrate 101, in order to prevent the intrusion of alkali metals, it is preferable to form the above nitride insulating film as the underlying insulating film 102, and further, on the above nitride insulating film, the above acid It is preferable to stack an oxide insulating film.

[0064] Here, silicon oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition. For example, it refers to a substance containing oxygen in the range of 50 atomic % or more and 70 atomic % or less, nitrogen in the range of 0.5 atomic % or more and 15 atomic % or less, silicon in the range of 25 atomic % or more and 35 atomic % or less, and hydrogen in the range of 0 atomic % or more and 10 atomic %. Further, silicon nitride oxide refers to a substance having a higher nitrogen content than oxygen in its composition. For example, it refers to a substance containing oxygen in the range of 5 atomic % or more and 30 atomic % or less, nitrogen in the range of 20 atomic % or more and 55 atomic % or less, silicon in the range of 25 atomic % or more and 35 atomic % or less, and hydrogen in the range of 10 atomic % or more and 25 atomic %. However, the above ranges are those measured using the Rutherford Backscattering Spectrometry (RBS) or the Hydrogen Forward Scattering (HFS). Also, the content ratio of the constituent elements takes a value such that the total does not exceed 100 atomic %. Moreover, since it is preferable that the underlying insulating film 102 contains oxygen at the portion in contact with the oxide semiconductor film 103, an insulating film that releases oxygen upon heating may be used as the underlying insulating film 102. Note that "releases oxygen upon heating" means that the amount of oxygen released, converted to oxygen atoms, is 1.0×10 atoms / cm or more, preferably 3.0×10 atoms / cm or more, as determined by TDS (Thermal Desorption Spectroscopy: temperature-programmed desorption gas spectrometry) analysis.

[0065] Further, since it is preferable that the underlying insulating film 102 contains oxygen at the portion in contact with the oxide semiconductor film 103, an insulating film that releases oxygen upon heating may be used as the underlying insulating film 102. Note that "releases oxygen upon heating" means that the amount of oxygen released, converted to oxygen atoms, is 1.0×10 atoms / cm or more, preferably 3.0×10 atoms / cm or more, as determined by TDS (Thermal Desorption Spectroscopy: temperature-programmed desorption gas spectrometry) analysis. 18 3 20 3 ​​​​​​​​​​​​​​​

[0066] The method for quantifying the oxygen release amount by converting it into oxygen atoms through TDS analysis will be described below.

[0067] The gas release amount during TDS analysis is proportional to the integral value of the spectrum. Therefore, the gas release amount can be calculated based on the ratio of the integral value of the spectrum of the insulating film to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral value of the spectrum of a sample containing a predetermined atom.

[0068] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as the standard sample, and the TDS analysis results of the insulating film, the oxygen molecule release amount (N O2 ) of the insulating film can be obtained by Equation 1. Here, it is assumed that all the spectra detected at mass number 32 obtained from the TDS analysis are derived from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as the possibility of its existence is low. Also, for oxygen molecules containing oxygen atoms with mass numbers 17 and 18, which are isotopes of oxygen atoms, they are not considered because their natural abundance ratios are extremely low.

[0069]

Equation

[0070]

[0070] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integral value of the spectrum when the standard sample is subjected to TDS analysis. Here, let the reference value of the standard sample be N / S H2 / S. S H2 is the integral value of the spectrum when the insulating film is subjected to TDS analysis. O2 is the integral value of the spectrum when the insulating film is subjected to TDS analysis. It is. α is a coefficient that affects the spectral intensity in the TDS analysis. Regarding the details of Equation 1, refer to Japanese Patent Laid-Open No. 6-275697. The numerical value of the oxygen emission amount described above was measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Denso Kagaku Corporation, with a silicon wafer containing 1×10 16 atoms / cm 3 of hydrogen atoms as a standard sample. It is the measured value.

[0071] Also, in the TDS analysis, part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the emission amount of oxygen molecules, the emission amount of oxygen atoms can also be estimated. Note that N is the emission amount of oxygen molecules. In the insulating film, the emission amount of oxygen in terms of oxygen atoms is twice the emission amount of oxygen molecules.

[0072] Note that O2 N is the emission amount of oxygen molecules. In the insulating film, the emission amount of oxygen in terms of oxygen atoms is twice the emission amount of oxygen molecules.

[0073] As an example of an insulating film from which oxygen is released by heating, there is silicon oxide (SiO X ( X>2)) in which oxygen is excessive. Silicon oxide (SiO X (X>2)) in which oxygen is excessive means that it contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method. By using an insulating film from which oxygen is released by heating as the underlying insulating film 102, oxygen is supplied to the oxide semiconductor film 103, and the interface states between the underlying insulating film 102 and the oxide semiconductor film 103 are

[0074] adjusted. ​​​​can be reduced. Therefore, charges and the like that may be generated due to the operation of the transistor 100 can be prevented from being trapped at the interface between the underlying insulating film 102 and the oxide semiconductor film 103, and the transistor 100 can be made into a transistor with less degradation of electrical characteristics. 100 can be made into a transistor with less degradation of electrical characteristics.

[0075] Furthermore, charges may be generated due to oxygen deficiency in the oxide semiconductor film 103. Generally, in an oxide semiconductor, a part of the oxygen deficiency becomes a donor and generates electrons as carriers. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated. That is, also in the transistor 100, a part of the oxygen deficiency in the oxide semiconductor film 103 becomes a donor and generates electrons as carriers, causing the threshold voltage of the transistor 100 to vary in the negative direction. And in the oxide semiconductor film 103, the generation of the electrons is remarkable in the oxygen deficiency near the interface between the oxide semiconductor film 103 and the underlying insulating film 102. By sufficiently releasing oxygen from the underlying insulating film 102 to the oxide semiconductor film 103, the oxygen deficiency in the oxide semiconductor film 103 that causes the threshold voltage to vary in the negative direction can be compensated.

[0076] That is, by using an insulating film that releases oxygen by heating for the underlying insulating film 102, the interface level between the oxide semiconductor film 103 and the underlying insulating film 102, and the oxygen deficiency in the oxide semiconductor film 103 can be reduced, and the influence of charge trapping at the interface between the oxide semiconductor film 103 and the underlying insulating film 102 can be minimized. That is, by using an insulating film that releases oxygen by heating for the underlying insulating film 102, the interface level between the oxide semiconductor film 103 and the underlying insulating film 102, and the oxygen deficiency in the oxide semiconductor film 103 can be reduced, and the influence of charge trapping at the interface between the oxide semiconductor film 103 and the underlying insulating film 102 can be minimized. That is, by using an insulating film that releases oxygen by heating for the underlying insulating film 102, the interface level between the oxide semiconductor film 103 and the underlying insulating film 102, and the oxygen deficiency in the oxide semiconductor film 103 can be reduced, and the influence of charge trapping at the interface between the oxide semiconductor film 103 and the underlying insulating film 102 can be minimized. That is, by using an insulating film that releases oxygen by heating for the underlying insulating film 102, the interface level between the oxide semiconductor film 103 and the underlying insulating film 102, and the oxygen deficiency in the oxide semiconductor film 103 can be reduced, and the influence of charge trapping at the interface between the oxide semiconductor film 103 and the underlying insulating film 102 can be minimized.

[0077] Next, an oxide semiconductor film 103 is formed on the underlying insulating film 102.

[0078] Specifically, an oxide semiconductor film 140 whose entire film is a CAAC oxide semiconductor film is formed, and then After that, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b are formed by adding a dopant to the oxide semiconductor film 140, and the oxide semiconductor film 103 is formed. Therefore, a method for manufacturing the oxide semiconductor film 140, which is a CAAC oxide semiconductor film before adding the dopant to form the pair of second regions 107a, 107b and the pair of third regions 109a, 109b, will be described. There are two methods for manufacturing the oxide semiconductor film 140, which is a CAAC oxide semiconductor film.

[0079] One method is a method of forming an oxide semiconductor while heating a substrate (for convenience, referred to as the 1 step method), and the other method is a method of forming the oxide semiconductor in two steps and performing two heat treatments for manufacturing (for convenience, referred to as the 2 step method).

[0080] First, a method of forming the oxide semiconductor film 140 by the 1 step method will be described. First, using the oxide semiconductor material described for the oxide semiconductor film 103, it is formed by sputtering while heating the substrate 101 on which the underlying insulating film 102 is formed. Incidentally, the oxide semiconductor film formed in this step is, for convenience, referred to as the oxide semiconductor film 130. The temperature for heating the substrate 101 is preferably 200°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, and the oxide semiconductor film 130 may be formed to have a thickness of 1 nm or more and 50 nm or less.

[0081] Here, the sputtering apparatus for forming the oxide semiconductor film 130 will be described in detail below.

[0082] First, using the oxide semiconductor material described for the oxide semiconductor film 103, it is formed by sputtering while heating the substrate 101 on which the underlying insulating film 102 is formed. Incidentally, the oxide semiconductor film formed in this step is, for convenience, referred to as the oxide semiconductor film 130. The temperature for heating the substrate 101 is preferably 200°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, and the oxide semiconductor film 130 may be formed to have a thickness of 1 nm or more and 50 nm or less. Here, the sputtering apparatus for forming the oxide semiconductor film 130 will be described in detail below. The temperature for heating the substrate 101 is preferably 200°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, and the oxide semiconductor film 130 may be formed to have a thickness of 1 nm or more and 50 nm or less. The temperature for heating the substrate 101 is preferably 200°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, and the oxide semiconductor film 130 may be formed to have a thickness of 1 nm or more and 50 nm or less.

[0083] Here, the sputtering apparatus for forming the oxide semiconductor film 130 will be described in detail below. will be described in detail below.

[0084] The processing chamber for forming the oxide semiconductor film 130 preferably has a leak rate of 1×10 -10 Pa·m 3 / second or less. Thereby, when forming by the sputtering method, the incorporation of impurities into the film can be reduced.

[0085] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. External leakage means that gas flows into the vacuum system from outside due to minute holes, seal failures, etc. Internal leakage is caused by leakage from partitions such as valves within the vacuum system and outgassing from internal members. To make the leak rate 1×10 Pa·m -10 / second or less, 3 it is necessary to take measures against both external and internal leaks.

[0086] To reduce external leakage, the opening and closing parts of the processing chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external leakage. Also, by using a metal material coated with passivation such as iron fluoride, aluminum oxide, or chromium oxide, the outgassing gas containing hydrogen generated from the metal gasket can be suppressed, and internal leakage can also be reduced.

[0087] The member used as the inner wall of the processing chamber may be aluminum, chromium, titanium, zirconium, nickel, or vanadium, which has little outgassing gas containing hydrogen, or an alloy material coated with at least one of these and containing iron, chromium, and nickel, etc. An alloy material containing at least one of bismuth and nickel is rigid, heat-resistant, and suitable for processing. Here, in order to reduce the surface area of the inner wall of the processing chamber, reducing the surface unevenness of the member by polishing or the like can reduce the released gas. Alternatively, the member may be coated with a passivation such as iron fluoride, aluminum oxide, or chromium oxide.

[0088] Furthermore, it is preferable to provide a purification device for the atmospheric gas immediately before introducing the atmospheric gas into the processing chamber. At this time, the length of the pipe from the purification device to the processing chamber is set to 5 m or less, preferably 1 m or less. By setting the length of the pipe to 5 m or less or 1 m or less, the influence of the released gas from the pipe can be further reduced accordingly.

[0089] The exhaust of the processing chamber is preferably performed by appropriately combining a roughing pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbomolecular pump, and a cryopump. While the turbomolecular pump is excellent in exhausting large-sized molecules, its exhaust capacity for hydrogen and water is low. Therefore, it is effective to use a combination of a cryopump with a high exhaust capacity for water and a sputter ion pump with a high exhaust capacity for hydrogen.

[0090] The adsorbates present in the processing chamber are adsorbed on the inner wall and do not affect the pressure of the processing chamber, but they cause gas release when the processing chamber is evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with a high exhaust capacity to desorb as much as possible the adsorbates present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbates, the processing chamber may be baked. Baking can increase the desorption rate of the adsorbates by about 10 times. ​​​​​​​​​​​​​can be achieved. Baking may be performed at 100°C or higher and 450°C or lower. At this time, when removing the adsorbed substance while introducing an inert gas, the desorption rate of substances such as water that are difficult to desorb by simply exhausting can be further increased.

[0091] In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used.

[0092] When forming the oxide semiconductor film 130 by the sputtering method, as the target, a metal oxide target containing zinc can be used. Further, a metal oxide target containing two or more elements selected from indium, gallium, tin, and zinc can be used. Examples of the target include quaternary metal oxides such as In-Sn-Ga-Zn-based metal oxides, ternary metal oxides such as In-Ga-Zn-based metal oxides, In-Sn-Zn-based metal oxides, In-Al-Zn-based metal oxides, Sn-Ga-Zn-based metal oxides, Al-Ga-Zn-based metal oxides, Sn-Al-Zn-based metal oxides, In-Hf-Zn-based metal oxides, In-La-Zn-based metal oxides, In-Ce-Zn-based metal oxides, In-Pr-Zn-based metal oxides, In-Nd-Zn-based metal oxides, In-Sm-Zn-based metal oxides, In-Eu-Zn-based metal oxides, In-Gd-Zn-based metal oxides, In-Tb-Zn-based metal oxides, In-Dy-Zn-based metal oxides, In-Ho-Zn-based metal oxides, In-Er-Zn-based metal oxides, In-Tm-Zn-based metal oxides, In-Yb-Zn-based metal oxides, In-Lu-Zn-based metal oxides, binary metal oxides such as In-Zn-based metal oxides, Sn-Zn-based metal oxides. Metal oxides, In-Ga-based metal oxides, or single-component metal oxides containing indium, tin, zinc, etc. Targets such as metal oxides can be used.

[0093] As an example of the target, a metal oxide target (In-Ga-Zn-based metal oxide) containing In, Ga, and Zn is used, with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio] . Also, targets with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio], or targets with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [mole ratio], or targets with a composition ratio of In2O3:Ga2O3:ZnO = 2:1:8 [mole ratio] can also be used. Note that as the ambient gas, a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed gas of noble gas and oxygen can be appropriately used. Also, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed as the ambient gas. By using the above sputtering apparatus, an oxide semiconductor film 130 with reduced hydrogen incorporation can be formed. Moreover, the underlying insulating film 102 and the oxide semiconductor film 130 may be continuously formed under vacuum. For example, after removing impurities containing hydrogen on the surface of the substrate 101 by heat treatment or plasma treatment, the underlying insulating film 102 is formed without exposing it to the atmosphere, and then the oxide semiconductor film 130 is formed without exposing it to the atmosphere. By doing so, impurities containing hydrogen on the surface of the substrate 101 are reduced, and at the interface between the substrate 101 and the underlying insulating film 102, and between the underlying insulating film 102 and

[0094]

[0095]

[0096] It is possible to suppress the adhesion of atmospheric components to the interface with the oxide semiconductor film 130. As a result, a transistor 100 with good electrical characteristics and high reliability can be fabricated.

[0097] Next, a first photolithography process is performed to form a resist mask on the oxide semiconductor film 130. Using the resist mask, processing is performed in a first etching process to form an island-shaped oxide semiconductor film 132. Note that, in addition to the photolithography process, the resist mask can appropriately use an inkjet method, a printing method, or the like.

[0098] In the first etching process, it is preferable to etch so that the ends of the island-shaped oxide semiconductor film 132 become tapered. By making the ends of the island-shaped oxide semiconductor film 132 tapered, the coverage of the gate insulating film 111 formed later can be improved. When using the photolithography process, it can be made tapered by etching while retracting the resist mask.

[0099] The first etching process may be dry etching or wet etching, or these may be combined. As the etching solution for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide solution (31 wt% hydrogen peroxide water: 28 wt% ammonia water: water = 5:2:2 (volume ratio)), or the like can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0100] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (such as CCl4) is preferred.

[0101] In addition, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0102] As dry etching, a parallel plate type RIE (Reactive Ion Etchi ng) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. In order to be able to process into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

[0103] After forming the oxide semiconductor film 132, a heat treatment is performed to form the oxide semiconductor film 140. The temperature of the heat treatment is set to 150°C or higher and 650°C or lower, preferably 250°C or higher and 450°C or lower, and is performed in an oxidizing atmosphere or an inert atmosphere. Here, the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or nitrogen oxide. In addition, the inert atmosphere refers to an atmosphere in which the aforementioned oxidizing gas is less than 10 ppm and is filled with nitrogen or a rare gas. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the more the ratio of the crystal region to the amorphous region can form an oxide semiconductor film, but heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity. Note that the heat treatment may be performed after forming the gate insulating film 111 after forming the oxide semiconductor film 13 2. ​

[0104] The above heat treatment releases hydrogen from the oxide semiconductor film 132 and diffuses a part of the oxygen contained in the base insulating film 102 into the vicinity of the interface between the oxide semiconductor film 132 and the oxide semiconductor film 132 in the base insulating film 102. There is no particular limitation on the heat treatment apparatus used for the heat treatment, and it may be provided with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or , a GRTA (Gas Rapid Thermal Anneal) apparatus, an LRTA (L

[0105] amp Rapid Thermal Anneal) apparatus, etc., an RTA (Rapid T hermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium ium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. hermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium ium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. ium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. ium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. ium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. is an apparatus for performing heat treatment using high-temperature gas.

[0106] Here, a method of forming the oxide semiconductor film 140 by a two-step method will be described.

[0107] A first oxide semiconductor film is formed, and a first heat treatment is performed at 40 0 °C or higher and 750 °C or lower in an atmosphere of nitrogen, oxygen, a noble gas, or dry air. By the first heat treatment, a first crystalline oxide semiconductor film having a crystal region is formed in a region including the surface of the first oxide semiconductor film. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and a second heat treatment is performed at 40 0 °C or higher and 750 °C or lower to crystallize the first crystalline oxide semiconductor film. is formed. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and a second heat treatment is performed at 40 0 °C or higher and 750 °C or lower to crystallize the first crystalline oxide semiconductor film. As a length seed, crystal growth is performed upward to crystallize the entire second oxide semiconductor film (to form the second crystalline oxide semiconductor film). The first crystalline oxide semiconductor film formed as described above and the second crystalline oxide semiconductor film are used as the oxide semiconductor film 130, and the above first photolitho graphy process and the above first etching process are performed to form the oxide semiconductor film 132, and 1 By performing the heat treatment performed after the formation of the oxide semiconductor film 132 described in the step method, the oxide semiconductor film 140 can be formed. Note that the heat treatment apparatus used for the first heat treatment and the second heat treatment may be any of the heat treatment apparatuses used for the heat treatment performed after the formation of the oxide semiconductor film 132 described in the 1step method.

[0108] Next, a gate insulating film 111 and a first electrode 113 are formed on the oxide semiconductor film 140 ( see Fig. 3(A)). The gate insulating film 111 can be formed in the same manner as the underlying insulating film 102. The thickness of the gate insulating film 111 is preferably 1 nm or more and 300 nm or less, more preferably 5 nm or more and 50 nm or less.

[0109] The gate insulating film 111 uses a single-layer structure of an insulating film selected from a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film, or a laminated structure thereof. In the gate insulating film 111, it is preferable that oxygen is included in the portion in contact with the oxide semiconductor film 103. Also, an insulating film that releases oxygen by heating may be used. By using an insulating film that releases oxygen by heating as the gate insulating film 111, defects generated in the oxide semiconductor film 103 can be repaired and deterioration of the electrical characteristics of the transistor 100 can be suppressed. ​

[0110] Also, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x> 0, y>0, z>0), hafnium aluminate (HfAl x O y (x>0, y>0) ), and other high-k materials can be used. High-k materials have a high dielectric constant. Therefore, for example, it is possible to obtain the same gate insulating film capacitance as when a silicon oxide film is used as the gate insulating film. Therefore, the physical thickness of the gate insulating film can be increased while maintaining the gate The gate insulating film 111 can be formed of the high-k material in a single layer structure. Alternatively, it may be used as a laminated structure with the insulating film.

[0111] The first electrode 113 is formed by forming a conductive film using the above-mentioned conductive material by a sputtering method. A second photolithography step is performed to form a resist mask over the conductive film, and then The resist mask is used in a second etching process to form a first electrode 113. The thickness of the first electrode 113 is not particularly limited, and may vary depending on the electrical resistance of the conductive material used and the manufacturing process. The time required for this can be determined appropriately.

[0112] The gate insulating film 111 and the conductive film to be the first electrode 113 are not exposed to the air. It is preferable to form the layers continuously.

[0113] The first electrode 113 is made of a conductive material such as aluminum, titanium, chromium, nickel, copper, or iron. A single substance composed of lutetium, zirconium, molybdenum, silver, tantalum, or tungsten A metal or an alloy having the same as a main component is used as a single-layer structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon A two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film A two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film, and an aluminum film laminated on the titanium film There is a three-layer structure in which a titanium film is further formed thereon. In addition, a transparent conductive material containing indium oxide Tin oxide or zinc oxide may be used. The first electrode 113 also functions as a wiring

[0114] Also, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen An Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (InN, ZnN, etc.) is preferably provided between the first electrode 113 and the gate insulating film 111. These films have a work function of 5 eV, preferably 5.5 eV Or more, and in the electrical characteristics of the transistor 100, the threshold voltage can be shifted to make the transistor 100 a so-called normally-off transistor For example, when an In-Ga-Zn-O film containing nitrogen is used, an In-Ga-Zn-O film having a nitrogen concentration higher than that of at least the oxide semiconductor film 140, specifically 7 atomic% or more Is used

[0115] Next, sidewall insulating films 115a and 115b are formed. The sidewall insulating film 115 (including the sidewall insulating films 115a and 115b) is the base insulating film 102 and the gate Insulating film 11 ​​​​​​It is formed of any of the insulating films described by the insulating film 111.

[0116] The transistor 100 has a gate insulating film 111 provided in any of the regions of the first region 105, the pair of second regions 107a and 107b, and the pair of third regions 109a and 109b. To achieve such a structure, the gate insulating film 111 and the sidewall insulating film 115 (including the sidewall insulating films 115a and 115b) may be made of insulating films with different etching rates. By adopting such a structure, when forming the sidewall insulating film 115, the gate insulating film 111 can function as an etching stopper. By using the gate insulating film 111 as an etching stopper, excessive etching of the oxide semiconductor film 140 can be suppressed. Further, the end point (endpoint) of the etching when forming the sidewall insulating film 115 can be easily detected. Also, by making the gate insulating film 111 function as an etching stopper, it becomes easier to control the width of the sidewall insulating film 115 (the width where the sidewall insulating films 115a and 115b in Fig. 1(B) are in contact with the gate insulating film 111). The range of the pair of second regions 107a and 107b, which are low-concentration regions, is determined corresponding to the width of the sidewall insulating film 115 (the width where the sidewall insulating films 115a and 115b in Fig. 1(B) are in contact with the gate insulating film 111). Increasing the range of the low-concentration region can relax the electric field applied to the first region 105 that functions as a channel formation region.

[0117] First, on the gate insulating film 111 and the first electrode 113, sidewall insulating films 115a, ​​​​​​​​​​​​​​Form an insulating film 114 that becomes 115b (see Fig. 3(B)). The insulating film 114 can be formed in the same manner as the underlying insulating film 102 and can be any of the insulating films listed above. The thickness of the insulating film 114 is not particularly limited, but by performing a third etching process on the insulating film 114, sidewall insulating films 115a and 115b are formed (see Fig. 3(C)). The third etching process is highly anisotropic etching, and the sidewall insulating films 115a and 115 b can be self-aligned by performing a highly anisotropic etching process on the insulating film 114. Here, as the highly anisotropic etching, dry etching is preferable, and for example, as the etching gas, gases containing fluorine such as trifluoromethane (CHF3), octafluorocyclobutane (C4F8), and tetrafluoromethane (CF4) can be used, and rare gases such as helium (He) and argon (Ar) or hydrogen (H2) can be added. Further, as the dry etching, it is preferable to use a reactive ion etching method (RIE method) in which a high-frequency voltage is applied to the substrate.

[0118] Also, since the dopant concentration of the pair of second regions 107a and 107b corresponds to the thickness of the sidewall insulating films 115a and 115b, the thicknesses of the sidewall insulating films 115a and 115b and further the thickness of the first electrode 113 can be determined so that the dopant concentration of the pair of second regions 107a and 107b becomes the above-mentioned values. Here, the thickness of the sidewall insulating films 115a and 115b refers to the distance from the surface in contact with the gate insulating film 111 to the topmost part of the surface in contact with the first electrode 113.

[0119] Also, the ranges of a pair of second regions 107a and 107b, which are low-concentration regions, are the sidewalls of the width of the sidewall insulating film 115 (here, the widths of the sidewall insulating films 115a and 115b in Fig. 1(B) that are in contact with the gate insulating film 111). Further, since the width of the sidewall insulating film 115 corresponds to the thickness of the first electrode 113, the thickness of the first electrode 113 may be determined so that the ranges of the pair of second regions 107 a and 107b are within a desired range.

[0120] Next, a process of adding a dopant 150 to the oxide semiconductor film 140 is performed to form the oxide semiconductor film 103 (see Fig. 3(D)).

[0121] The dopant 150 to be added is one or more elements selected from either hydrogen or noble gas elements. As a method of adding the dopant 150 to the oxide semiconductor film 140, an ion doping method or an ion implantation method can be used. By using the ion doping method or the ion implantation method, the addition depth (added region) of the dopant 150 becomes easier to control, and the dopant 150 can be accurately added to the oxide semiconductor film 140. Also, when adding the dopant 150 by the ion doping method or the ion implantation method, the substrate 101 may be heated. Further, instead of the ion doping method or the ion implantation method, plasma may be generated in a gas atmosphere containing the dopant to be added, and plasma treatment may be performed on the object to be added to add the dopant. Hydrogen functions as an electron donor (donor) in the oxide semiconductor film 140, and the oxide semiconductor film

[0122] ​​​​​N-type the oxide semiconductor film 140. Also, the noble gas element creates defects in the oxide semiconductor film 140 and N-types the oxide semiconductor film 140. Note that hydrogen diffuses easily, and if hydrogen diffuses into the first region 105 which is the channel formation region, the transistor characteristics may deteriorate. For this reason, it is preferable to use a noble gas element as the dopant 150.

[0123] Also, when adding an element with a large atomic radius such as a noble gas as the dopant 150 by the above plasma treatment, it is preferable that the gate insulating film is provided over the first region, the pair of second regions, and the pair of third regions. For example, if the transistor 100 is in a form in which the pair of third regions 109a and 109b serving as the source region and the drain region are exposed, when the above plasma treatment is performed, the portions of the oxide semiconductor film 140 that become the pair of third regions 109a and 109b may be etched and thinned. By performing the process with the gate insulating film 111 provided over the first region 105, the pair of second regions 107a and 107b, and the pair of third regions 109a and 109b, the gate insulating film 111 can prevent etching of the portions of the oxide semiconductor film 140 that become the pair of third regions 109a and 109b, and suppress thinning. In addition, the interface between the oxide semiconductor film 103 and the gate insulating film 111 can be kept clean, so that the electrical characteristics and reliability of the transistor 100 can be improved.

[0124] When adding the dopant 150 to the oxide semiconductor film 140, the dopant 150 passes through the gate insulating film 111 and the sidewall insulating films 115a and 115b and is added to the oxide semiconductor film 140. Then, the amount of the dopant 150 added to the oxide semiconductor film 140 is the The region added by passing only through the gate insulating film 111 is less than the region added by passing through the gate insulating film 111 and the sidewall insulating films 115a and 115b. Therefore, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b are formed by self-alignment (see Fig. 3(E)). Further, the dopant 150 is not added to the oxide semiconductor film 140 in the region overlapping with the first electrode 113. Moreover, the pair of second regions 107a, 107b and the pair of third regions 109a, 109b have reduced crystallinity due to the damage caused by the addition of the dopant 150 and become amorphous regions. Also, by adjusting the amount of the dopant 150 added, etc., the amount of damage can be reduced, and the pair of second regions 107a, 107b and the pair of third regions 109a, 109b can be formed so as not to become completely amorphous regions. In that case, the pair of second regions 107a, 107b and the pair of third regions 109a, 109b are regions having a larger ratio of amorphous regions than at least the first region 105. In addition, after adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as the heat treatment performed when forming the oxide semiconductor film 140, but a temperature at which the pair of second regions 107a, 107b and the pair of third regions 109a, 109b do not crystallize is preferable. It should be noted that the process of adding the dopant 150 to the oxide semiconductor film 140 may be performed multiple times. When the process of adding the dopant 150 to the oxide semiconductor film 140 is performed multiple times, the dopant

[0125] Furthermore, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b are reduced in crystallinity due to the damage caused by the addition of the dopant 150 and become amorphous regions. Also, by adjusting the amount of the dopant 150 added, etc., the amount of damage can be reduced, and a pair of second regions 107a, 107b and a pair of third regions 109a, 109b can be formed so as not to become completely amorphous regions. In that case, a pair of second regions 107 a, 107b and a pair of third regions 109a, 109b are regions having a larger ratio of amorphous regions than at least the first region 105

[0126] Also, after adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as the heat treatment performed when forming the oxide semiconductor film 140, but a temperature at which a pair of second regions 107a, 107b and a pair of third regions 109a, 109b do not crystallize is preferable.

[0127] Note that the process of adding the dopant 150 to the oxide semiconductor film 140 may be performed multiple times . When the process of adding the dopant 150 to the oxide semiconductor film 140 is performed multiple times, the dopant The dopant 150 may be the same in all cases for multiple times, or may be changed for each process. For example, after forming the first electrode 113 as shown in FIG. 3(A), a process of adding the dopant 150 (first addition process) is performed once, and after forming the sidewall insulating films 115a and 115b, a process of adding the dopant 150 again (second addition process) may be performed. The dopant 150 in the first addition process and the second addition process may be the same element or different elements.

[0128] Next, an insulating film that will become the interlayer insulating film 117 is formed on the gate insulating film 111, the sidewall insulating films 115a and 115b, and the first electrode 113, and a third photolithography process and a fourth etching process are performed on the insulating film and the gate insulating film 111 to form openings 116a and 116b. The third photolithography process and the fourth etching process may be the same as the first photolithography process and the first etching process.

[0129] The interlayer insulating film 117 may be formed by using a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride film, and may be formed by a sputtering method, a CVD method, or the like. At this time, it is preferable to use a film that hardly releases oxygen by heating for the interlayer insulating film 117. This is to prevent the resistivity of the pair of second regions 107a and 107b and the pair of third regions 109a and 109b from decreasing. Specifically, by the CVD method, using silane gas as the main material, selecting appropriate source gases from nitrogen oxide gas, nitrogen gas, hydrogen gas, and rare gas, and mixing and forming them may be sufficient. Also, the substrate temperature may be 300°C or higher and 550°C or lower. By using the CVD method, a film that hardly releases oxygen by heating can be obtained. ​

[0130] Next, through the openings 116a and 116b, it is connected to a pair of third regions 109a and 109b to form a second electrode 119a and a third electrode 119b (see FIG. 1(B)).

[0131] The second electrode 119a and the third electrode 119b each also function as wiring, and are formed using the same materials as those described for the first electrode 113.

[0132] Also, in the transistor 100, a pair of third regions 109a and 109b that are in contact with the second electrode 119a and the third electrode 119b are regions with a high conductivity to which a dopant has been added. Therefore, since the contact resistance between the second electrode 119a and the third electrode 119b and the pair of third regions 109a and 109b can be reduced, the on-current of the transistor 100 can be increased.

[0133] The second electrode 119a and the third electrode 119b are formed by forming a conductive film using the above-described conductive material in the same manner as the first electrode 113, and performing a fourth photolithography process and a fifth etching process on the conductive film. Note that the fourth photolithography process and the fifth etching process may be the same as the first photolithography process and the first etching process.

[0134] From the above, the transistor 100 can be manufactured.

[0135] Thus, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. ​​By sufficiently reducing the size, the area occupied by the semiconductor device becomes smaller, so the number of semiconductor devices produced increases. As a result, the manufacturing cost per semiconductor device is suppressed. Also, since the semiconductor device is miniaturized while maintaining the same functions, when the size is made the same, a semiconductor device with even higher functions can be realized. In addition, effects such as higher operating speed and lower power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. The number of semiconductor devices produced increases. As a result, the manufacturing cost per semiconductor device is suppressed. Also, since the semiconductor device is miniaturized while maintaining the same functions, when the size is made the same, a semiconductor device with even higher functions can be realized. In addition, effects such as higher operating speed and lower power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. Also, since the semiconductor device is miniaturized while maintaining the same functions, when the size is made the same, a semiconductor device with even higher functions can be realized. In addition, effects such as higher operating speed and lower power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. In addition, effects such as higher operating speed and lower power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various accompanying effects can be obtained. Note that this embodiment can be appropriately combined with other embodiments.

[0136] (Embodiment 2) In this embodiment, a transistor 200 having a configuration partially different from that of the transistor 100 shown in Embodiment 1 will be described. In this embodiment, a transistor 200 having a configuration partially different from that of the transistor 100 shown in Embodiment 1 will be described.

[0137] 〈Structure and characteristics of transistor 200〉 The transistor 200 is a transistor having a different shape of the gate insulating film 111 of the transistor 100. The transistor 200 is a transistor having a different shape of the gate insulating film 111 of the transistor 100.

[0138] FIG. 4(A) is a plan view of the transistor 200. Note that in FIG. 4(A), the underlying insulating film 202, the gate insulating film 211, and the interlayer insulating film 217 are not shown for the sake of simplicity. FIG. 4(A) is a plan view of the transistor 200. Note that in FIG. 4(A), the underlying insulating film 202, the gate insulating film 211, and the interlayer insulating film 217 are not shown for the sake of simplicity.

[0139] From FIG. 4(A), on the oxide semiconductor film 203, a first electrode 213 and a sidewall insulating film 215 provided on the side surface of the first electrode 213 are provided. Then, the second electrode 219a and the third electrode 219b are connected to the oxide semiconductor film through the openings 216a and 216b. From FIG. 4(A), on the oxide semiconductor film 203, a first electrode 213 and a sidewall insulating film 215 provided on the side surface of the first electrode 213 are provided. Then, the second electrode 219a and the third electrode 219b are connected to the oxide semiconductor film through the openings 216a and 216b. From FIG. 4(A), on the oxide semiconductor film 203, a first electrode 213 and a sidewall insulating film 215 provided on the side surface of the first electrode 213 are provided. Then, the second electrode 219a and the third electrode 219b are connected to the oxide semiconductor film through the openings 216a and 216b. It is provided on the third regions 209a and 209b of 203. Also, the second electrode 219a and the third electrode 219b are in contact with the upper surfaces of the third regions 209a and 209b. The transistor 200 is a top-gate structure and a top-contact type transistor.

[0140] FIG. 4(B) is a cross-sectional view taken between C and D in the transistor 200. From FIG. 4(B), an underlying insulating film 202 is provided on the substrate 201, and on the underlying insulating film 202, a first region 205, a pair of second regions 207a and 207b, and a pair of third regions 209a and 209 b including an oxide semiconductor film 203 are provided. The pair of second regions 207a and 207b are provided in contact with the side surfaces of the first region 205. The pair of third regions 209a and 209 b are provided in contact with the side surfaces of the pair of second regions 207a and 207b.

[0141] A gate insulating film 211 is provided on the oxide semiconductor film 203. The gate insulating film 211 is in contact with the first region 205. On the gate insulating film 211, a first electrode 213 overlapping the first region 205 is provided. Sidewall insulating films 215a and 215b are provided in contact with the side surfaces of the first electrode 213.

[0142] The second electrode 219a and the third electrode 219b are in contact with the upper surfaces of the pair of third regions 209a and 209b through openings 216a and 216b in an interlayer insulating film 217 provided on the first electrode 213 and the sidewall insulating films 215a and 215b.

[0143] The ends of the second electrode 219a and the third electrode 219b may be tapered, but the first ​The end of the electrode 213 of 1 is preferably in a vertical shape. The end of the first electrode 213 is made vertical, and an insulating film that becomes the sidewall insulating film 215 (sidewall insulating films 215a, 215b) is formed on the first electrode 213, and anisotropic etching is performed to form the sidewall insulating film 215 (sidewall insulating films 215a, 215b). Also, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. And, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. And, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. can be formed.

[0144] Also, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. And, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. And, from FIG. 4(A), the second regions 207a, 207b correspond to the regions where the oxide semiconductor film 203 overlaps with the sidewall insulating film 215. And the sidewall insulating film 215 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 213 and the gate insulating film 211. has a curved shape.

[0145] Since the gate insulating film 111 of the transistor 100 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b, the openings 116a, 116b are provided in the gate insulating film 111 and the interlayer insulating film 117. However, since the gate insulating film 211 of the transistor 200 is in contact with only the first region 205, the openings 216a, 216b are provided only in the interlayer insulating film 217. Since the gate insulating film 111 of the transistor 100 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b, the openings 116a, 116b are provided in the gate insulating film 111 and the interlayer insulating film 117. However, since the gate insulating film 211 of the transistor 200 is in contact with only the first region 205, the openings 216a, 216b are provided only in the interlayer insulating film 217. Since the gate insulating film 111 of the transistor 100 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b, the openings 116a, 116b are provided in the gate insulating film 111 and the interlayer insulating film 117. However, since the gate insulating film 211 of the transistor 200 is in contact with only the first region 20�, the openings 216a, 216b are provided only in the interlayer insulating film 217. Since the gate insulating film 111 of the transistor 100 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b, the openings 116a, 116b are provided in the gate insulating film 111 and the interlayer insulating film 117. However, since the gate insulating film 211 of the transistor 200 is in contact with only the first region 205, the openings 216a, 216b are provided only in the interlayer insulating film 217. Since the gate insulating film 111 of the transistor 100 is in contact with the first region 105, the pair of second regions 107a, 107b, and the pair of third regions 109a, 109b, the openings 116a, 116b are provided in the gate insulating film 111 and the interlayer insulating film 117. However, since the gate insulating film 211 of the transistor 200 is in contact with only the first region 205, the openings 216a, 216b are provided only in the interlayer insulating film 217.

[0146] Also, in the transistor 200, since the gate insulating film 211 is in contact with the first region 205, the gate insulating film 211 does not cover along the shape (step) of the oxide semiconductor film 203. In other words, there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203. Since there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203, the transistor 200 has a leakage current caused by the gate insulating film 211 Also, in the transistor 200, since the gate insulating film 211 is in contact with the first region 205, the gate insulating film 211 does not cover along the shape (step) of the oxide semiconductor film 203. In other words, there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203. Since there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203, the transistor 200 has a leakage current caused by the gate insulating film 211 Also, in the transistor 200, since the gate insulating film 211 is in contact with the first region 205, the gate insulating film 211 does not cover along the shape (step) of the oxide semiconductor film 203. In other words, there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203. Since there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203, the transistor 200 has a leakage current caused by the gate insulating film 211 Also, in the transistor 200, since the gate insulating film 211 is in contact with the first region 205, the gate insulating film 211 does not cover along the shape (step) of the oxide semiconductor film 203. In other words, there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203. Since there is no portion of the gate insulating film 211 that straddles the step of the oxide semiconductor film 203, the transistor 200 has a leakage current caused by the gate insulating film 211 has no portion that straddles the step of the oxide semiconductor film 203, the transistor 200 has a leakage current caused by the gate insulating film 211 can reduce it and increase the breakdown voltage of the gate insulating film 211. Therefore, even if the gate insulating film 211 is thinned to nearly 5 nm and used, the transistor can operate. Note that by thinning the gate insulating film 211, the short-channel effect can be suppressed and the operating speed of the transistor can be increased.

[0147] Furthermore, since there is no step-over portion in the gate insulating film 211 of the transistor 200, there is almost no parasitic capacitance generated between the first electrode 213 and the pair of second regions 207a, 207b and the pair of third regions 209a, 20 9b. Therefore, even when the channel length of the transistor 200 is reduced, the variation in the threshold voltage

[0148] <Method for fabricating transistor 200> Next, a method for fabricating the transistor 200 will be described with reference to FIGS. 2 and 5.

[0149] Before forming the insulating film 210 that will become the gate insulating film 211 in the method for fabricating the transistor 200 (the step of forming the oxide semiconductor film 140 in FIG. 2) is the same as that of the transistor 100, so reference can be made to Embodiment 1 (see FIG. 2). Note that the substrate 201 and the underlying insulating film 202 may have the same configurations as the substrate 101 and the underlying insulating film 102 described in Embodiment 1.

[0150] Next, an insulating film 210 is formed over the oxide semiconductor film 140. The insulating film 210 is formed using a material that can be used as the gate insulating film 111 in Embodiment 1. Then, a conductive film 212 that will become the first electrode 213 is formed over the insulating film 210 (see FIG. 5(A)). The It is formed of a conductive material that can be used for the first electrode 113 described in Embodiment 1. Note that, as in Embodiment 1, the sputtering method may be used as the method for forming the conductive film 212. That's fine.

[0151] Also, the insulating film 210 and the conductive film 212 are preferably formed continuously without being exposed to the atmosphere. That's preferable.

[0152] The insulating film 210 and the conductive film 212 are processed to form the gate insulating film 211 and the first electrode 213. By this processing, a gate insulating film 211 having a shape different from that of the gate insulating film 111 of the transistor 100 can be formed. Note that the processing of the insulating film 210 and the conductive film 212 may be performed as appropriate using the photolithography process and the etching process described in Embodiment 1. The thickness of the gate insulating film 211 may be appropriately determined based on the content described in Embodiment 1. That's fine. That's fine. That's fine.

[0153] Next, an insulating film 214 that will become sidewall insulating films 215a and 215b is formed over the oxide semiconductor film 140, the gate insulating film 211, and the first electrode 213 (see FIG. 5(B)). The insulating film 214 is formed of a material that can be used as the base insulating film 102 in Embodiment 1. Then, the insulating film 214 is processed to form sidewall insulating films 215a and 215b (see FIG. 5(C)). The method of processing the insulating film 214 into the sidewall insulating films 215a and 215b may be the same as the method of processing the insulating film 114 into the sidewall insulating films 115a and 115b described in Embodiment 1. That's fine. That's fine. That's fine. That's fine.

[0154] Also, the thicknesses of the sidewall insulating films 215a and 215b are such that later, the oxide semiconductor film 203 Refers to the topmost part of the surface in contact with the first electrode 213 from the surface in contact with the oxide semiconductor film 140. And the dopant concentrations of the pair of second regions 207a and 207b formed later correspond to the thicknesses of the sidewall insulating films 215a and 215b. Therefore, in order for the dopant concentrations of the pair of second regions 207a and 207b to be the values described in Embodiment 1, it is only necessary to determine the thicknesses of the sidewall insulating films 215a and 215b, and further, the thickness of the first electrode 213.

[0155] In addition, the range of the pair of second regions 207a and 207b, which are low-concentration regions, is determined corresponding to the width of the sidewall insulating film 215 (here, the width of the sidewall insulating films 215a and 215b in FIG. 4(B) in contact with the oxide semiconductor film 203). Increasing the range of the low-concentration region can relax the electric field applied to the first region 205 that functions as a channel formation region. Since the width of the sidewall insulating film 215 corresponds to the thickness of the first electrode 213, it is only necessary to determine the thickness of the first electrode 213 so that the range of the pair of second regions 207a and 207b becomes the desired range.

[0156] Next, a process of adding a dopant 150 to the oxide semiconductor film 140 is performed (see FIG. 5(D)). The process of adding the dopant 150 to the oxide semiconductor film 140 may be performed in the same manner as in Embodiment 1. By the process here, the first region 205, the pair of second regions 207a, 207b, and the pair of third regions 209a and 209b are formed (see FIG. 5(E)). Note that the first region 205, the pair of second regions 207a, 2 07b, and the pair of third regions 209a and 209b formed by the process here are the first regions described in Embodiment 1.​​​​​​​​​​ 105, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b It has the same configuration as

[0157] Furthermore, the addition of the dopant 150 can be performed by methods other than implantation by the ion doping method or ion implantation method. For example, plasma is generated in a gas atmosphere containing the dopant, and the plasma is irradiated onto the additive (here, the oxide semiconductor film 140). This is a plasma treatment. As the device for generating the plasma, a dry etching device, a plasma CVD device, a high-density plasma CVD device, etc. can be used in this way. Also, the plasma treatment may be performed while heating the substrate 201.

[0158] When a portion that becomes a pair of third regions 209a, 209b of the oxide semiconductor film 140 is exposed, as in the case of the transistor 200, if a rare gas element is used as the dopant and added by plasma treatment, as described in Embodiment 1, the portion that becomes the pair of third regions 209a, 209b may be etched and thinned. Therefore, when a portion of the oxide semiconductor film 140 that becomes the pair of third regions 209a, 209b is exposed, it is preferable to use hydrogen as the dopant. a, 209b

[0159] Note that the process of adding the dopant 150 to the oxide semiconductor film 140 can be performed multiple times in the same manner as in Embodiment 1.

[0160] Also, after adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as the heat treatment performed when forming the oxide semiconductor film 140, but for a pair of second regions ​​The temperatures at which the second regions 207a and 207b and the pair of third regions 209a and 209b do not crystallize are preferred.

[0161] Next, the interlayer insulating film 217, the openings 216a and 216b, the second electrode 219a, and the third electrode 219b may be formed in the same manner as the interlayer insulating film 117, the openings 116a and 116b, the second electrode 119a, and the third electrode 119b described in the first embodiment. Thus, the transistor 200 can be fabricated (see Fig. 4(B)).

[0162] The transistor 200 described in this embodiment can achieve the same effects as those of the first embodiment. It should be noted that this embodiment can be appropriately combined with other embodiments.

[0163] (Embodiment 3) In this embodiment, a transistor 300 having a configuration partially different from that of the transistor shown in the previous embodiments will be described.

[0164] 〈Structure and Characteristics of Transistor 300〉 The transistor 300 is different from the transistor 200 in the surface in contact with the pair of third regions 209a and 209b of the second electrode 219a and the third electrode 219b.

[0165] Fig. 6(A) is a plan view of the transistor 300. Note that in Fig. 6(A), the underlying insulating film 302, the gate insulating film 311, and the interlayer insulating film 317 are not shown for the sake of simplicity.

[0166] From Fig. 6(A), on the oxide semiconductor film 303, a first electrode 313 and a sidewall insulating film 315 provided on the side surface of the first electrode 313 are provided. Then, the second electrode The 319a and the third electrode 319b are in contact with the lower surfaces of the third regions 309a and 309b of the oxide semiconductor film 303. The transistor 300 is a bottom-contact type transistor with a top-gate structure.

[0167] FIG. 6(B) is a cross-sectional view taken between E and F in the transistor 300. From FIG. 6(B), an underlying insulating film 302 is provided on the substrate 301, and on the underlying insulating film 302, there are provided an oxide semiconductor film 303 including a first region 305, a pair of second regions 307a and 307b, and a pair of third regions 309a and 309b, as well as a second electrode 319a and a third electrode 319b. The pair of second regions 307a and 307b are provided in contact with the side surfaces of the first region 305. The pair of third regions 309a and 309b are provided in contact with the side surfaces of the pair of second regions 307a and 307b.

[0168] A gate insulating film 311 is provided on the oxide semiconductor film 303. The gate insulating film 311 is in contact with the first region 305. On the gate insulating film 311, a first electrode 313 that overlaps with the first region 305 is provided. On the side surfaces of the first electrode 313, sidewall insulating films 315a and 315b are provided in contact.

[0169] An interlayer insulating film 317 is provided on the gate insulating film 311, the first electrode 313, and the sidewall insulating films 315a and 315b.

[0170] The ends of the second electrode 319a and the third electrode 319b may be tapered, but the ends of the first electrode 313 are preferably perpendicular. ​​​​​​​​​It has a straight shape, and an insulating film that becomes the sidewall insulating film 315 (sidewall insulating films 315a, 315b) is formed on the first electrode 313, and by performing highly anisotropic etching, the sidewall insulating film 315 (sidewall insulating films 315a, 315b) can be formed.

[0171] Also, from FIG. 6(A), the second regions 307a, 307b correspond to regions where the oxide semiconductor film 303 overlaps with the sidewall insulating film 315. And the sidewall insulating film 315 has a curved shape at least in part other than the regions in contact with the side surface of the first electrode 313 and the gate insulating film 311.

[0172] Also, in the transistor 300, since the gate insulating film 311 is in contact with the first region 305, the gate insulating film 311 does not cover along the shape (step) of the oxide semiconductor film 303. In other words, there is no portion of the gate insulating film 311 that crosses over the step of the oxide semiconductor film 303. Since there is no portion of the gate insulating film 311 that crosses over the step of the oxide semiconductor film 303, the transistor 300 can reduce the leakage current caused by the gate insulating film 311 and increase the breakdown voltage of the gate insulating film 311. Therefore, even if the gate insulating film 311 is thinned to nearly 5 nm and used, the transistor can operate. In addition, by thinning the gate insulating film 311, the short-channel effect can be suppressed and the operating speed of the transistor can be increased.

[0173] Furthermore, since the transistor 300 has no step-crossing portion of the gate insulating film 311, the first electrode 313, the pair of second regions 307a, 307b, and the pair of third regions 309a, 30 ​​​​​​​​​There is almost no parasitic capacitance generated between 9b. Therefore, even when the channel length of the transistor 300 is reduced, the variation in the threshold voltage can be reduced.

[0174] Also, the transistor 300 shown in FIG. 6 has a form in which the gate insulating film 311 is provided only in the region where it contacts the first electrode 313. However, the gate insulating film 311 may be provided on the third regions 309a and 309b (and further, the second electrode 319a and the third electrode 319b) in the same manner as in the first embodiment.

[0175] <Method for manufacturing the transistor 300> Next, a method for manufacturing the transistor 300 will be described with reference to FIG. 7.

[0176] A base insulating film 302 is formed on the substrate 301, and a conductive film that will become the second electrode 319a and the third electrode 319b is formed on the base insulating film 302. The conductive film is processed to form the second electrode 319a and the third electrode 319b. The substrate 301 and the base insulating film 302 may have the same configuration as the substrate 101 and the base insulating film 102 described in the first embodiment. The conductive film may be formed of a conductive material that can be used for the second electrode 119a and the third electrode 119b described in the first embodiment. Note that the conductive film may be formed by a sputtering method in the same manner as in the first embodiment. Further, the processing of the conductive film may be performed by appropriately using the photolithography process and the etching process described in the first embodiment.

[0177] An oxide semiconductor film 340 is formed on the base insulating film 302, the second electrode 319a, and the third electrode 319b (see FIG. 7(A)). The oxide semiconductor film 340 is the oxide semiconductor film described in the first embodiment. It can be formed in the same manner as the oxide semiconductor film 140 (see FIG. 2).

[0178] Next, a gate insulating film 311 and a first electrode 313 are formed on the second electrode 319a, the third electrode 319b, and the oxide semiconductor film 340. First, an insulating film that will become the gate insulating film 311 is formed on the oxide semiconductor film 340. The gate insulating film 311 and the first electrode 313 may be formed in the same manner as the gate insulating film 211 and the first electrode 213 in Embodiment 2.

[0179] Next, an insulating film 314 that will become sidewall insulating films 315a and 315b is formed on the oxide semiconductor film 340, the gate insulating film 311, and the first electrode 313 (see FIG. 7(B)). The insulating film 314 can be formed of a material that can be used as the base insulating film 102 in Embodiment 1. Then, the insulating film 314 is processed to form the sidewall insulating films 315a and 315b (see FIG. 7(C)). The method of processing the insulating film 314 into the sidewall insulating films 315a and 315b may be the same as the method of processing the insulating film 114 into the sidewall insulating films 115a and 115b described in Embodiment 1.

[0180] Also, the thickness of the sidewall insulating films 315a and 315b refers to the distance from the surface in contact with the oxide semiconductor film 340, which will later become the oxide semiconductor film 303, to the topmost part of the surface in contact with the first electrode 313. And since the dopant concentration of the pair of second regions 307a and 307b to be formed later corresponds to the thickness of the sidewall insulating films 315a and 315b, the dopant concentration of the pair of second regions 307a and 307b becomes the value described in Embodiment 1. Thus, the thickness of the sidewall insulating films 315a and 315b, and further the thickness of the first electrode 313 ​​​​​​​​​​​​​​It is only necessary to determine the

[0181] In addition, the ranges of the pair of second regions 307a and 307b that are low-concentration regions are the sidewalls It is determined corresponding to the width of the sidewall insulating film 315 (here, the widths of the sidewall insulating films 315a and 315b in FIG. 6(B) in contact with the oxide semiconductor film 340). If the range of the low-concentration region is increased the electric field applied to the first region 305 that functions as a channel formation region can be relaxed. Since the width of the sidewall insulating film 315 corresponds to the thickness of the first electrode 313 it is only necessary to determine the thickness of the first electrode 313 so that the ranges of the pair of second regions 307a and 307b become a desired range.

[0182] Next, a process of adding the dopant 150 to the oxide semiconductor film 340 is performed (see FIG. 7(D) ). The process of adding the dopant 150 to the oxide semiconductor film 340 may be performed in the same manner as in Embodiment 1. By the process here, the first region 305, the pair of second regions 307a 307b and the pair of third regions 309a and 309b are formed (see FIG. 7(E)). Note that the first region 305, the pair of second regions 307a, 3 07b and the pair of third regions 309a and 309b formed by the process here have the same configuration as the first region 105, the pair of second regions 107a and 107b, and the pair of third regions 109a and 109b described in Embodiment 1.

[0183] Furthermore, the transistor 300 is in a form in which the dopant 150 is added in a state where a part of the oxide semiconductor film 340 is exposed, similar to the transistor 200. Therefore, as the method of adding the dopant 1 50, plasma treatment can be used in the same manner as in Embodiment 2. Note ​​​​​, the plasma treatment is the same as the plasma treatment described in Embodiment 2.

[0184] When a portion that becomes a pair of third regions 309a and 309b of the oxide semiconductor film 340 is exposed as in the transistor 300, if a rare gas element is used as a dopant and added by plasma treatment, as described in Embodiment 1, the portion that becomes the pair of third regions 309a and 309b may be etched and thinned. Therefore, when a portion of the oxide semiconductor film 340 that becomes the pair of third regions 309a and 309b is exposed, it is preferable to use hydrogen as a dopant.

[0185] Also, even in the case where the gate insulating film 311 is provided on the third regions 309a and 309b (and also on the second electrode 319a and the third electrode 319b) in the same manner as in Embodiment 1, the process of adding the dopant 150 to the oxide semiconductor film 340 can be performed. At this time, the dopant 150 passes through the gate insulating film 311 and the sidewall insulating films 315a and 315b and is added to the oxide semiconductor film 340. In such a case, a rare gas element can be used as the dopant 150 without problems.

[0186] Note that the process of adding the dopant 150 to the oxide semiconductor film 340 can be performed a plurality of times in the same manner as in Embodiment 1.

[0187] Also, after adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as the heat treatment performed when forming the oxide semiconductor film 340, but a temperature at which the pair of second regions 307a and 307b and the pair of third regions 309a and 309b do not crystallize is preferable. ​​​​​​​​​​​​​

[0188] Next, on the first electrode 313, the second electrode 319a, the third electrode 319b, and the sidewall insulating films 315a and 315b, an interlayer insulating film 317 is formed in the same manner as the interlayer insulating film 117 described in Embodiment 1. Thus, the transistor 300 can be fabricated (see Fig. 6(B)). (See Fig. 6(B)).

[0189] The transistor 300 described in this embodiment can achieve the same effects as those in Embodiment 1. Note that this embodiment can be appropriately combined with other embodiments.

[0190] (Embodiment 4) In this embodiment, in the transistors shown in Embodiments 1 to 3, the influence of the first region, the pair of second regions, and the pair of third regions included in the oxide semiconductor film on the electrical characteristics of the transistor is described using a band diagram. Note that the transistor 300 shown in Fig. 6 is taken as an example for description. The influence of the first region, the pair of second regions, and the pair of third regions included in the oxide semiconductor film on the electrical characteristics of the transistor is described using a band diagram. Note that the transistor 300 shown in Fig. 6 is taken as an example for description. The influence of the first region, the pair of second regions, and the pair of third regions included in the oxide semiconductor film on the electrical characteristics of the transistor is described using a band diagram. Note that the transistor 300 shown in Fig. 6 is taken as an example for description. The influence of the first region, the pair of second regions, and the pair of third regions included in the oxide semiconductor film on the electrical characteristics of the transistor is described using a band diagram. Note that the transistor 300 shown in Fig. 6 is taken as an example for description.

[0191] Figs. 8(A) and 8(B) show the energy band diagrams (schematic diagrams) of the cross-section between G and H of the transistor 300 (see Fig. 6(B)). Note that Fig. 8(B) shows the case where the voltage between the source region and the drain region is set to an equipotential (VD = 0V). The transistor 300 is a transistor having an oxide semiconductor film 303 including a first region 305 (referred to as OS1), a pair of second regions 307a and 307b (referred to as OS2) and a pair of third regions 309a and 309b (referred to as OS3), and second electrodes 319a and third electrodes 319b (referred to as metal). is a transistor having an oxide semiconductor film 303 including a first region 305 (referred to as OS1), a pair of second regions 307a and 307b (referred to as OS2) and a pair of third regions 309a and 309b (referred to as OS3), and second electrodes 319a and third electrodes 319b (referred to as metal). and a pair of third regions 309a and 309b (referred to as OS3), and second electrodes 319a and third electrodes 319b (referred to as metal). and a pair of third regions 309a and 309b (referred to as OS3), and second electrodes 319a and third electrodes 319b (referred to as metal).

[0192] The channel formation region of the transistor 300 is formed by OS1, and OS1 purifies the oxide semiconductor to a high purity by removing and desorbing impurities such as moisture (including hydrogen) in the film as much as possible to make it a true (type I) oxide semiconductor, or an oxide semiconductor approaching true as much as possible and is formed thereby. By doing so, the Fermi level (Ef) can be set to the same level as the true Fermi level (E i).

[0193] In addition, the low concentration region of the transistor 300 is formed by OS2, and the source region and the drain region are formed by OS3. Similar to OS1, OS2 and OS3 purify the oxide semiconductor to a high purity by removing and desorbing impurities such as moisture (including hydrogen) in the film as much as possible to make it a true (type I) oxide semiconductor, or an oxide semiconductor approaching true as much as possible. After that, one or more dopants selected from either hydrogen or noble gas elements are added so that they function as donors or oxygen deficiencies occur. As a result, OS2 and OS 3 have a higher carrier density than OS1, and the position of the Fermi level is closer to the conduction band .

[0194] Fig. 8(A) shows the relationship of the band structure of the vacuum level (denoted as Evac), the first region 305 (denoted as OS1), a pair of second regions 307a, 307b (denoted as OS2), a pair of third regions 309a, 309 b (denoted as OS3), the second electrode 319a and the third electrode 319b (denoted as metal) . Here, IP is the ionization potential, Ea is the electron affinity, Eg is the band gap, and Wf is the work function. Also, Ec is the lower end of the conduction band, Ev is the upper end of the valence band, and Ef is the Fermi level. Note that the symbol shown at the end of each symbol is 1 for OS1 Let 2 represent OS2, 3 represent OS3, and m represent metal. Here, Wf_m is assumed to be 4.1 eV (such as titanium) as the metal.

[0195] OS1 is a highly purified oxide semiconductor, and since its carrier density is extremely low, Ef_1 is assumed to be approximately in the middle of Ec and Ev. Also, OS2 and OS3 are oxide semiconductors with a high carrier density due to the addition of dopants, and Ec_2 and Ef_2, Ec_3 and Ef_3 are approximately the same. The oxide semiconductors represented by OS1, OS2, and OS3 have a bandgap (E g) of 3.15 eV and an electron affinity (Ea) of 4.3 eV. It is said that

[0196] As shown in FIG. 8(B), when OS1, which is the channel formation region, contacts OS2, which is the low-concentration region, carrier movement occurs so that the Fermi levels of OS1 and OS2 match, and the band edges of OS1 and OS2 bend. Furthermore, when OS2, which is the low-concentration region, contacts OS3, which is the source region and the drain region, carrier movement occurs so that the Fermi levels of OS2 and OS3 match, and the band edges of OS2 and OS3 bend. Additionally, when OS3, which is the source region and the drain region, contacts metal, carrier movement occurs so that the Fermi levels of OS3 and me tal match, and the band edge of OS3 bends. [[ID=Z6]] bends.

[0197] The contact can be made ohmic, and the contact resistance can be reduced. . As a result, the on-current of the transistor 300 can be increased. Also, since the bending of the band edge of the OS1 can be reduced, the short-channel effect of the transistor 300 can be reduced.

[0198] (Embodiment 5) In this embodiment, an example of a transistor different from the transistor shown in the previous embodiment will be described with reference to FIG. 9.

[0199] FIG. 9(A) is a cross-sectional view of the transistor 400, and FIG. 9(B) is an enlarged view of the dotted line portion in FIG. 9(A).

[0200] The structure of the transistor 400 is as follows. An underlying insulating film 402 is provided on the substrate 401. On the underlying insulating film 402, an oxide semiconductor film 403 including a first region 405, a pair of second regions 407a, 4 07b, a pair of third regions 409a, 409b, and a pair of fourth regions 410a, 410b is provided. Second electrodes 419a and 419b are provided on the pair of fourth regions 410a, 410b. On the first region 405, the pair of second regions 407a, 407b, the pair of third regions 409a, 409b, and the pair of fourth regions 410a, 410b, the second electrodes 419a and 419b, a gate insulating film 411 is provided. A first electrode 413 is provided on the gate insulating film 411 so as to overlap the first region 405.

[0201] The transistor 400 has a top-gate structure and is a top-contact type transistor. Unlike the transistor 100, the transistor 200, and the transistor 300, a pair of fourth regions 410a and 410b are provided.

[0202] The substrate 401, the underlying insulating film 402, the first region 405, the gate insulating film 411, the first electrode 4 13, the second electrode 419a, and the third electrode 419b can be formed in the same manner as the substrate 10 1, the underlying insulating film 102, the first region 105, the gate insulating film 111, the first electrode 113, the second electrode 119a, and the third electrode 119b described in Embodiment 1.

[0203] The first region 405, which is a channel formation region, is a CAAC oxide semiconductor region described in Embodiment 1, and the pair of fourth regions 410a and 410b are also CAAC oxide semiconductor regions described in Embodiment 1. The pair of second regions 407a and 407b and the pair of third regions 4 09a and 409b are amorphous regions containing a dopant, and the dopant is the same as that described in Embodiment 1. Further, the dopant concentrations of the pair of second regions 407a and 407b and the dopant concentrations of the pair of third regions 409a and 409b are different. The dopant concentration ranges of the pair of second regions 407a and 407b and the pair of third regions 409a and 409b are the dopant concentration ranges described in Embodiment 1. The transistor 400 forms regions (the first region 405, the pair of second regions 407a and 407b, the pair of third regions 409a and 409b, the pair of fourth regions 410a and 410b) with different dopant concentrations by using the first

[0204] electrode 413, the second electrode 419a, and the third electrode 419b after forming the oxide semiconductor film 140 described in Embodiment 1. The electrode 413, the second electrode 419a, and the third electrode 419b are used to form regions with different dopant concentrations (the first region 405, the pair of second regions 407a and 407b, the pair of third regions 409a and 409b, the pair of fourth regions 410a and 410b). The regions 409a, 409b, and the pair of fourth regions 410a and 410b) can be formed. It cuts.

[0205] A pair of third regions 409a and 409b are formed because the second electrode 419a and the third electrode 419b are in a tapered shape. Also, by thinning the thickness of the second electrode 419a and the third electrode 41 9b, the range of the pair of third regions 409a and 409b can be expanded. It can be done.

[0206] Note that the transistors 100, 200, and 300 use the first electrodes and sidewall insulating films provided in their respective transistors to form regions with different dopant concentrations (the first region, the pair of second regions, and the pair of third regions in their respective transistors).

[0207] From the above, the transistor 400 has, via the first region 405 which is the channel formation region, a pair of second regions 407a and 407b and a pair of third regions 40 9a and 409b with different dopant concentrations provided, and can relax the electric field applied to the first region 405 which is the channel formation region, so the short-channel effect can be suppressed.

[0208] In addition to the transistor 400, as an example of a transistor different from the transistors shown in the above embodiment, the transistor 500 will be described. FIG. 9(C) is a cross-sectional view of the transistor 500, and FIG. 9(D) is an enlarged view of the dotted line portion of FIG. 9(C).

[0209] FIG. 9(C) is a cross-sectional view of the transistor 500, and FIG. 9(D) is an enlarged view of the dotted line portion of FIG. 9(C). It is an enlarged view.

[0210] The structure of the transistor 500 is as follows. An underlying insulating film 402 is provided on the substrate 401. are provided. On the base insulating film 402, a first electrode 413 and a gate insulating film 411 covering the first electrode 413 are provided. On the gate insulating film 411, a first region 40 5, a pair of second regions 407a and 407b, a pair of third regions 409a and 409b, and a pair of fourth regions 410a and 410b including an oxide semiconductor film 403 are provided. On the pair of fourth regions 410a and 410b, a second electrode 419a and a third electrode 419b are provided are provided. On the first region 405, an insulating film 420 is provided.

[0211] The transistor 500 is a bottom gate structure and a top contact type transistor. Different from the transistors 100, 200, and 300, a pair of fourth regions 410a and 410b are provided.

[0212] The substrate 401, the base insulating film 402, the first region 405, the gate insulating film 411, the first electrode 4 13, the second electrode 419a, and the third electrode 419b can be formed in the same manner as the substrate 10 1, the base insulating film 102, the first region 105, the gate insulating film 111, the first electrode 113, the second electrode 119a, and the third electrode 119b described in Embodiment 1. Since the transistor 500 has a bottom gate structure, the first electrode 413 is preferably tapered in the same manner as the second electrode 419a and the third electrode 419b. By forming the first electrode 4 13 in a tapered shape, the covering property of the gate insulating film 411 can be improved.

[0213] The first region 405, which is a channel formation region, is the CAAC oxide semiconductor described in Embodiment 1. The pair of fourth regions 410a and 410b are also CAAC regions described in the first embodiment. The pair of second regions 407a and 407b and the pair of third regions 407a and 407b are oxide semiconductor regions. 409a and 409b are amorphous regions containing dopants, and the dopants are The same as that described in the embodiment 1. In addition, the dopant of the pair of second regions 407a and 407b The dopant concentration of the first region 409a is different from the dopant concentration of the pair of third regions 409a, 409b. The dopant of the pair of second regions 407a, 407b and the pair of third regions 409a, 409b The range of the dopant concentration is the range of the dopant concentration described in the first embodiment.

[0214] The transistor 500 includes the oxide semiconductor film 411 described in Embodiment 1 over the gate insulating film 411. After forming the insulating film 140, the second electrode 419a, the third electrode 419b, and the insulating film 420 are formed. By using this, regions with different dopant concentrations (first region 405, a pair of second regions 407a, 407b, a pair of third regions 409a, 409b, a pair of fourth regions 410a, 410 The insulating film 420 can be formed by adding a dopant to the first region 405. It is necessary to form the film thick enough so that it does not get damaged.

[0215] The pair of third regions 409a and 409b are connected to the second electrode 419a and the third electrode 419b. The second electrode 419a and the third electrode 419b are formed in a tapered shape. By reducing the thickness of the pole 419b, the range of the pair of third regions 409a, 409b is expanded. It is possible.

[0216] The transistors 100, 200, and 300 are By using the first electrode and the sidewall insulating film provided in the transistor, dopants Regions with different concentrations (the first region, a pair of second regions, and a pair of third regions in each transistor) are formed in the transistor.

[0217] As described above, the transistor 500 has, via the first region 405 which is the channel formation region, A pair of second regions 407a and 407b and a pair of third regions 40 9a and 409b with different dopant concentrations are provided, and the electric Field applied to the first region 405 which is the channel formation region can be relaxed, so that the short-channel effect can be suppressed.

[0218] (Embodiment 6) In this embodiment, with reference to FIG. 10, a resistive element Using an oxide semiconductor to which dopants are added will be described.

[0219] FIG. 10(A) shows a resistive element 600. The configuration of the resistive element 600 will be described below. An underlying insulating film 602 is provided on a substrate 601. An oxide semiconductor film 603 to which dopants are added is provided on the underlying insulating film 602. Conductive films 604a and 604b are provided on the oxide semiconductor film 603. That is, the resistive element 600 uses the oxide semiconductor film 60 3 as a resistor. The oxide semiconductor film 603 to which dopants are added can be formed, for example, by adding dopants after the gate insulating film 211 And the first electrode 213 are not formed on the oxide semiconductor film 140 (see FIGS. 5(A) and (B)) shown in Embodiment 2. In addition, the conductive films 604a and 604b can be formed of a conductive material that can be used for the first Electrode described in the previous embodiment.

[0220] ​​ Figure 10(B) shows the resistive element 610. The configuration of the resistive element 610 will be described below. A base insulating film 602 is provided on a substrate 601. An oxide semiconductor film 603 with a dopant added is provided on the base insulating film 602. An insulating film 606 is provided on the oxide semiconductor film 603. Conductive films 604a and 604b are provided in contact with a part of the insulating film 606 and the oxide semiconductor film 603. In the resistive element 610, the oxide semiconductor film 603 also serves as a resistor. The oxide semiconductor film 603 with a dopant added can be formed, for example, by adding a dopant after forming a gate insulating film 211 and a first electrode 213 are not formed on the oxide semiconductor film 140 (see FIGS. 5(A) and (B)) shown in Embodiment 2. The insulating film 606 can be appropriately formed using the base insulating film, gate insulating film, and interlayer insulating film described in the previous embodiments. Also, the conductive films 604a and 604b can be formed of a conductive material that can be used for the first electrode described in the previous embodiments. From the above, the resistive element 610 can make the current path of the oxide semiconductor film 603 in contact with the conductive films 604a and 604b that function as a resistor constant, and is a resistive element having a higher-precision resistance value.

[0221] (Embodiment 7) FIG. 11(A) shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) that constitutes a semiconductor device. The memory cell is composed of a transistor 1160 that uses a material other than an oxide semiconductor for the channel formation region and a transistor 1162 that uses an oxide semiconductor for the channel formation region.

[0222] The transistor 1162 using an oxide semiconductor in the channel formation region can be manufactured according to the previous embodiment. It can be manufactured.

[0223] As shown in FIG. 11(A), one of the gate electrode of the transistor 1160 and the source electrode or drain electrode of the transistor 1162 is electrically connected. Also, the first wiring (1st Line: also referred to as the source line) and the source electrode of the transistor 1160 are electrically connected, and the second wiring (2nd Line: also referred to as the bit line) and the drain electrode of the transistor 1160 are electrically connected. And, the third wiring (3rd Line: also referred to as the first signal line) and the other of the source electrode or drain electrode of the transistor 1162 are electrically connected, and the fourth wiring (4th Line: also referred to as the second signal line) and the gate electrode of the transistor 1162 are electrically connected.

[0224] Since the transistor 1160 using a material other than an oxide semiconductor, for example, single crystal silicon, in the channel formation region can operate at a sufficiently high speed, by using the transistor 1160,

[0224] it is possible to read the stored content at high speed. Also, the transistor 1162 using an oxide semiconductor in the channel formation region has a feature that the off-current is smaller than that of the transistor 1160.

[0225] Therefore, by turning off the transistor 1162, it is possible to hold the potential of the gate electrode of the transistor 1160 for an extremely long time.

[0225] By taking advantage of the feature that the potential of the gate electrode can be held, information can be written, held, and read as follows.

[0226] First, writing and holding of information will be described. First, the potential of the fourth wiring is set as the potential at which the transistor 1162 is turned on, and the transistor 1162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1160 (writing). After that, the potential of the fourth wiring is set as the potential at which the transistor 1162 is turned off, and the transistor 1162 is turned off. As a result, the potential of the gate electrode of the transistor 1160 is held (holding). Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time.

[0227] Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time. Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned on, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is the potential at which the transistor 1160 is turned off, the off-state of the transistor 1160 will be held for a long time.

[0228] Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change. Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change. Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change. Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change. Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change. Next, reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring in a state where the on-state or off-state of the transistor 1160 is held, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Also, when the transistor 1160 is in the off-state, the potential of the second wiring does not change.

[0229] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential to read the information.

[0230] Next, the rewriting of information will be described. The rewriting of information is performed in the same way as the writing and holding of the above information. That is, the potential of the fourth wiring is set as the potential at which the transistor 1162 is turned on, and the transistor 1162 is turned on. Thereby, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 1160. After that, the potential of the fourth wiring is set as the potential at which the transistor 1162 is turned off, and the transistor 1162 is turned off, so that the new information is held.

[0231] As described above, the memory cell according to the disclosed invention can directly rewrite the information by writing the information again. Therefore, the erasing operation required in a flash memory or the like is not necessary, and a decrease in the operation speed due to the erasing operation can be suppressed. That is, high-speed operation of the semiconductor device having the memory cell is realized.

[0232] Also, an example of the circuit diagram of the memory cell developed from the memory cell of FIG. 11(A) is shown in FIG. 11(B).

[0233] The memory cell 1100 shown in FIG. 11(B) includes a first wiring SL (source line), a second wiring BL (bit line), a third wiring S1 (first signal line), a fourth wiring S2 (second signal line), a fifth wiring WL (word line), a transistor 1164 (first transistor), a transistor 1161 (second transistor), and a transistor 1163 (third transistor). ​​​It is composed of a transistor 1164 and a transistor 1163. The transistor 1164 and the transistor 1163 use a material other than an oxide semiconductor for the channel formation region, and the transistor 1161 uses an oxide semiconductor for the channel formation region. Here, one of the gate electrode of the transistor 1164 and the source electrode or the drain electrode of the transistor 1161 is electrically connected. Also, the first wiring SL is electrically connected to the source electrode of the transistor 1164, the drain electrode of the transistor 1164 is electrically connected to the source electrode of the transistor 1163. And the second wiring BL is electrically connected to the drain electrode of the transistor 1163, the third wiring S1 is electrically connected to the other of the source electrode or the drain electrode of the transistor 1161, the fourth wiring S2 is electrically connected to the gate electrode of the transistor 1161, and the fifth wiring WL is electrically connected to the gate electrode of the transistor 1163. Next, the operation of the circuit will be specifically described.

[0234] When writing to the memory cell 1100, the first wiring SL is set to 0V, the fifth wiring WL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "1", the third wiring S1 is set to 2V, and when writing data "0", the third wiring S1 is set to 0V. At this time, the transistor 1163 is in the off state and the transistor 1161 is in the on state. Note that at the end of writing, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0V to turn off the transistor 1161.

[0235]

[0236]

[0237] ​​​​​​​​​​​​​​ As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of transistor 1164 is about 2V, and after writing data "0", the potential of node A is about 0V. Charge corresponding to the potential of the third wiring S1 is accumulated in node A, but the off-current of transistor 1161 is smaller than that of a transistor using single-crystalline silicon in the channel formation region, and the potential of the gate electrode of transistor 1164 is held for a long time.

[0238] Next, when reading the memory cell, the first wiring SL is set to 0V, the fifth wiring WL is set to 2 V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the read circuit connected to the second wiring BL is put into an operating state. At this time, transistor 1163 is in an on state and transistor 1161 is in an off state.

[0239] If the data is "0", that is, when node A is in a state of about 0V, transistor 1164 is in an off state , so the resistance between the second wiring BL and the first wiring SL is in a high state. On the other hand, if the data is "1", that is, when node A is in a state of about 2V, transistor 1164 is in an on state , so the resistance between the second wiring BL and the first wiring SL is in a low state. The read circuit can read data "0" and "1" based on the difference in the resistance state of the memory cell. Note that although the second wiring BL was set to 0V during writing, it may be in a floating state or charged to a potential of 0V or higher. Although the third wiring S1 was set to 0V during reading, it may be in a floating state or charged to a potential of 0V or higher.

[0240] ​​​​​​Note that data "1" and data "0" are for convenience of definition and may be reversed. Also, the above-described operating voltage is an example. The operating voltage should be selected such that transistor 1 164 is in the off state when data "0" is present, and transistor 1164 is in the on state when data "1" is present. Also, transistor 1161 should be in the on state during writing and in the off state otherwise. Also, transistor 1163 should be in the on state during reading. In particular, instead of 2V, the power supply potential VDD of the surrounding logic circuit may be used.

[0241] In this embodiment, for simplicity of understanding, the memory cell of the minimum storage unit (1 bit) has been described. However, the configuration of the memory cell is not limited to this. A plurality of memory cells may be appropriately connected to form a more advanced semiconductor device. For example, a plurality of the above memory cells may be used to form a NAND-type or NOR-type semiconductor device. The configuration of the wiring is not limited to FIGS. 11(A) and 11(B) and may be changed as appropriate.

[0242] FIG. 12 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m×n bits.

[0243] The semiconductor device shown in FIG. 12 includes m fifth wirings WL(1) to WL(m) and fourth wirings S 2(1) to S2(m), n second wirings BL(1) to BL(n) and third wirings S1 (1) to S1(n), and a plurality of memory cells 1100(1, 1) to 1100(m, n) arranged in a matrix of m rows (vertical) × n columns (horizontal) (m and n are natural numbers), a memory cell array 1110, a second wiring and third wiring drive circuit 1111, and a fourth wiring and fifth wiring drive circuit 1112. It is composed of peripheral circuits such as a wiring drive circuit 1113 and a read circuit 1112. As other peripheral circuits, a refresh circuit or the like may be provided.

[0244] As a representative of each memory cell, consider the memory cell 1100(i, j). Here, the memory cell 1100(i, j) (where i is an integer from 1 to m and j is an integer from 1 to n) is connected to the second wiring BL(j), the third wiring S1(j), the fifth wiring WL(i), the fourth wiring S2(i), and the first wiring, respectively. The first wiring potential Vs is applied to the first wiring. Also, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are connected to the second wiring and the third wiring drive circuit 1111, and the read circuit 1112. Also, the fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the fourth wiring and the fifth wiring drive circuit 1113.

[0245] The operation of the semiconductor device shown in FIG. 12 will be described. In this configuration, writing and reading are performed for each row.

[0246] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, the first wiring potential Vs is set to 0V, the fifth wiring WL(i) is set to 0V, the second wirings BL(1) to BL(n) are set to 0V, and the fourth wiring S2(i) is set to 2V. At this time, the transistor 1161 is in the on state. The third wirings S1(1) to S1(n) are set to 2V for the columns where data "1" is written and 0V for the columns where data "0" is written. Note that at the end of writing, before the potential of the third wirings S1(1) to S1(n) changes, the fourth wiring S2(i) is set to 0V. ​​​​​​​​​​​​​Turn off transistor 1161. Also, set the non - selected fifth wiring WL to 0V and the non - selected fourth wiring S2 to 0V.

[0247] As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of transistor 1164 of the memory cell where data "1" has been written is about 2V, and the potential of node A of the memory cell where data "0" has been written is about 0V (see FIGS. 11(B) and 12). Also, the potential of node A of the non - selected memory cell does not change.

[0248] When reading the memory cells 1100(i, 1) to 1100(i, n) in the i - th row, set the first wiring potential Vs to 0V, the fifth wiring WL(i) to 2V, the fourth wiring S2(i) to 0V , the third wirings S1(1) to S1(n) to 0V, and activate the reading circuit connected to the second wirings BL(1) to BL(n). In the reading circuit, for example, data "0" and "1" can be read from the difference in the resistance states of the memory cells. Also, set the non - selected fifth wiring WL to 0V and the non - selected fourth wiring S2 to 0V. Although the second wiring BL was 0V during writing, it may be in a floating state or charged to a potential of 0V or higher. Although the third wiring S1 was 0V during reading, it may be in a floating state or charged to a potential of 0V or higher.

[0249] Note that data "1" and data "0" are for convenience of definition and may be reversed. Also, the operating voltages described above are just examples. The operating voltage should be such that transistor 1 164 is in the off state for data "0" and transistor 1164 is in the on state for data "1". In addition, transistor 1161 is in the on state during writing and in the off state otherwise. In addition, if transistor 1163 is selected to be in the on state during reading, it is good. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit may be used.

[0250] (Embodiment 8) In this embodiment, an example of a circuit diagram of a memory cell having a capacitive element is shown. In FIG. 13(A), the memory cell 1170 shown includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 1171 (first transistor), and a trans istor 1172 (second transistor), and a capacitive element 1173. Transistor 1171 uses a material other than an oxide semiconductor for the channel formation region, and trans istor 1172 uses an oxide semiconductor for the channel formation region.

[0251] Here, one of the gate electrode of transistor 1171, the source electrode or the drain electrode of transistor 1172, and one electrode of capacitive element 1173 are electrically connected. In addition, the first wiring SL and the source electrode of transistor 1171 are electrically connected, the second wiring BL and the drain electrode of transistor 1171 are electrically connected, and the third wiring S1 and the other of the source electrode or the drain electrode of transistor 1172 are electrically connected, the fourth wiring S2 and the gate electrode of transistor 1172 are electrically connected to each other, and the fifth wiring WL and the other electrode of capacitive element 1173 are electrically connected. .

[0252] Next, the operation of the circuit will be specifically described.

[0253] When writing to the memory cell 1170, set the first wiring SL to 0V, the fifth wiring WL to 0V, the second wiring BL to 0V, and the fourth wiring S2 to 2V. When writing data "1", set the third wiring S1 to 2V, and when writing data "0", set the third wiring S1 to 0V. At this time, the transistor 1172 is in the on state. When the writing is completed, before the potential of the third wiring S1 changes, set the fourth wiring S2 to 0V to turn off the transistor 1172.

[0254] As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1171 is about 2V, and after writing data "0", the potential of node A is about 0V.

[0255] When reading the memory cell 1170, set the first wiring SL to 0V, the fifth wiring WL to 2V, the fourth wiring S2 to 0V, the third wiring S1 to 0V, and activate the reading circuit connected to the second wiring BL. At this time, the transistor 1172 is in the off state.

[0256] The state of the transistor 1171 when the fifth wiring WL is set to 2V will be described. The potential of node A that determines the state of the transistor 1171 depends on the capacitance C1 between the fifth wiring WL and node A and the capacitance C2 between the gate electrode, source electrode, and drain electrode of the transistor 1171.

[0257] Note that although the third wiring S1 is set to 0V during reading, it may be in a floating state or charged to a potential of 0V or higher. Data "1" and data "0" are for convenience of definition, ​The opposite is also fine.

[0258] The potential of the third wiring S1 during writing is set to a value that is lower than the value that the transistor 1172 is turned off after writing. In addition, when the potential of the fifth wiring WL is 0V, the transistor 1171 is in an off state. The potentials of data "0" and "1" can be selected within the range. When the potential is data "0", the transistor 1171 is turned off, and when the potential is data "1", the transistor 1171 is turned off. In this case, the transistor 1171 is turned on. The threshold voltage of the transistor 1171 is also an example. Any threshold value may be used as long as it is within the range.

[0259] Also, a selection transistor having a first gate electrode and a second gate electrode; An example of a NOR type semiconductor memory device using memory cells having the following structure will be described with reference to FIG. 13(B). I will explain.

[0260] The semiconductor device according to one embodiment of the present invention shown in FIG. 13B has I rows (I is a natural number of 2 or more) J A memory cell array having a plurality of memory cells arranged in a matrix in columns (J is a natural number). It is equipped with (i).

[0261] The memory cell array shown in FIG. 13B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix (a natural number of which is i) and i word lines W L (word lines WL_1 to WL_i), and i capacitance lines CL (capacitance lines CL_1 to CL_i). a capacitance line CL_i) and i gate lines BGL (gate lines BGL_1 to BGL _i), j bit lines BL (bit lines BL_1 to BL_j), and source lines It includes SL and

[0262] Furthermore, each of the plurality of memory cells 1180 (also referred to as memory cell 1180(M,N) (where , N is a natural number from 1 to j, and M is a natural number from 1 to i)) includes a transistor 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ).

[0263] Note that in a semiconductor memory device, the capacitance element is composed of a first capacitance electrode, a second capacitance electrode, and a dielectric layer that overlaps the first capacitance electrode and the second capacitance electrode. The capacitance element accumulates charges according to the voltage applied between the first capacitance electrode and the second capacitance electrode.

[0264] Transistor 1181(M,N) is an N-channel transistor and has a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. Note that in the semiconductor memory device of this embodiment, transistor 1181 does not necessarily have to be an N-channel transistor.

[0265] One of the source electrode and the drain electrode of transistor 1181(M,N) is connected to bit line BL _N, the first gate electrode of transistor 1181(M,N) is connected to word line WL _M, and the second gate electrode of transistor 1181(M,N) is connected to gate line BG L_M. By configuring one of the source electrode and the drain electrode of transistor 1181(M,N) to be connected to bit line BL_N, data can be selectively read out for each memory cell.

[0266] Transistor 1181(M,N) functions as a selection transistor in memory cell 1180(M,N).

[0267] As transistor 1181(M,N), a transistor using an oxide semiconductor for the channel formation region can be used.

[0268] Transistor 1182(M,N) is a P-channel transistor. Note that in the semiconductor memory device of this embodiment, transistor 1182 does not necessarily have to be a P-channel transistor.

[0269] One of the source electrode and the drain electrode of transistor 1182(M,N) is connected to source line SL, and the other of the source electrode and the drain electrode of transistor 1182(M,N) is connected to bit line BL_N. The gate electrode of transistor 1182(M,N) is connected to the other of the source electrode and the drain electrode of transistor 1181(M,N).

[0270] Transistor 1182(M,N) functions as an output transistor in memory cell 1180(M,N). As transistor 1182(M,N), for example, a transistor using single-crystal silicon for the channel formation region can be used.

[0271] The first capacitor electrode of capacitor element 1183(M,N) is connected to capacitor line CL_M, and the second capacitor electrode of capacitor element 1183(M,N) is connected to the other of the source electrode and the drain electrode of transistor 1181(M,N). Note that capacitor element 1183(M,N) functions as a holding capacitor.

[0272] ​​​​​​​​​​​​The voltages of each of the word lines WL_1 to WL_i are controlled by a driving circuit using, for example, a decoder.

[0273] The voltages of each of the bit lines BL_1 to BL_j are controlled by a driving circuit using, for example, a decoder.

[0274] The voltages of each of the capacitance lines CL_1 to CL_i are controlled by a driving circuit using, for example, a decoder.

[0275] The voltages of each of the gate lines BGL_1 to BGL_i are controlled using, for example, a gate line driving circuit.

[0276] The gate line driving circuit is constituted by a circuit including, for example, a diode and a capacitive element in which a first capacitive electrode is electrically connected to the anode of the diode and the gate line BGL.

[0277] By adjusting the voltage of the second gate electrode of the transistor 1181, the threshold voltage of the transistor 1181 can be adjusted. Therefore, the threshold voltage of the transistor 1181 functioning as a selection transistor can be adjusted, and the current flowing between the source electrode and the drain electrode of the transistor 1181 in the off state can be made as small as possible. Thus, the data holding period in the memory circuit can be lengthened. Further, since the voltages required for data writing and reading can be made lower than those of a conventional semiconductor device, the power consumption can be reduced.

[0278] (Embodiment 9) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment will be described with reference to FIG. 14. ​

[0279] FIG. 14(A) shows an example of a semiconductor device having a configuration corresponding to a so-called DRAM (Dynamic Random Access Memory). The memory cell array 1120 shown in FIG. 14(A) has a configuration in which a plurality of memory cells 1130 are arranged in a matrix . The memory cell array 1120 also has m first wirings and n second wirings . In the present embodiment, the first wiring is referred to as a bit line BL, and the second wiring is referred to as a word line WL .

[0280] The memory cell 1130 is composed of a transistor 1131 and a capacitive element 1132 . The gate electrode of the transistor 1131 is connected to the first wiring (word line WL) . One of the source electrode or the drain electrode of the transistor 1131 is connected to the second wiring (bit line BL), and the other of the source electrode or the drain electrode of the transistor 1131 is connected to one of the electrodes of the capacitive element . The other electrode of the capacitive element is connected to a capacitance line CL and is given a constant potential . The transistor shown in the previous embodiment is applied to the transistor 1131 .

[0281] The transistor using the oxide semiconductor shown in the previous embodiment in the channel formation region has a feature that the off-current is smaller than that of a transistor using single crystal silicon in the channel formation region . Therefore, when the transistor is applied to the semiconductor device shown in FIG. 14(A) recognized as a so-called DRAM , it is possible to obtain a substantial non-volatile memory .

[0282] FIG. 14(B) shows an example of a semiconductor device having a configuration corresponding to a so-called SRAM (Static Random Access M emory). The memory cell array 1140 shown in FIG. 14(B) has a configuration in which a plurality of memory cells 1150 are arranged in a matrix. Further, the memory cell array 1140 has a plurality of first wirings (word lines WL), second wirings (bit lines BL), and third wirings (inverted bit lines / BL).

[0283] The memory cell 1150 has a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, a fifth transistor 1155 , and a sixth transistor 1156. The first transistor 1151 and the second transistor 1152 function as selection transistors. Further, among the third transistor 1153 and the fourth transistor 1154, one is an n-channel transistor (here the fourth transistor 1154), and the other is a p-channel transistor (here the third transistor 1153). That is, a CMOS circuit is formed by the third transistor 1153 and the fourth transistor 1154. Similarly, a CMOS circuit is formed by the fifth transistor 1155 and the sixth transistor 1156.

[0284] The first transistor 1151, the second transistor 1152, the fourth transistor 115 4, and the sixth transistor 1156 are n-channel transistors, and the transistors shown in the previous embodiment can be applied. The third transistor 1153 and the fifth transistor 1155 are p-channel transistors, other than oxide semiconductors Use a material (e.g., single-crystalline silicon, etc.) for the channel formation region.

[0285] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. It can be used in combination.

[0286] (Embodiment 10) A CPU (Central Processing Unit) can be configured by using at least a part of transistors using an oxide semiconductor for the channel formation region.

[0287] Fig. 15(A) is a block diagram showing a specific configuration of the CPU. The CPU shown in Fig. 15(A) has, on a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, an erasable programmable read-only memory (ROM) 1199, and a ROM interface (ROM I / F) 1189. The substrate 1190 uses a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a glass substrate, etc. The ROM 1199 and the ROM I / F 1189 may be provided on a separate chip. Of course, the CPU shown in Fig. 15(A) is only an example showing a simplified configuration thereof, and an actual CPU has various configurations depending on its application. nit) 1191, an ALU controller 1192, an instruction decoder 1193 , an interrupt controller 1194, a timing controller 1195, registers 11 96, a register controller 1197, a bus interface (Bus I / F) 119 8, an erasable programmable read-only memory (ROM) 1199, and a ROM interface (ROM I / F) 1 189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM I / F 1189 may be provided on a separate chip. Of course, the CPU shown in Fig. 15(A) is only an example showing a simplified configuration thereof, and an actual CPU has various configurations depending on its application.

[0288] Instructions input to the CPU via the Bus I / F 1198 are input to the instruction decoder 1193, decoded, and then sent to the ALU controller 1192, the interrupt controller 1194, the timing controller 1195, etc. Controller 1194, register controller 1197, timing controller 119 is input to 5.

[0289] ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU.

[0290] 2, instruction decoder 1193, interrupt controller 1194, and register controller 1197 to generate signals for controlling the operation timing. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above various circuits.

[0291] In the CPU shown in FIG. 15(A), a storage element is provided in the register 1196. The storage element of the register 1196 can use the storage element described in Embodiment 8.

[0292] In the CPU shown in FIG. 15(A), the register controller 1197 is the ALU 1191 In accordance with the instruction from , the holding operation in register 1196 is selected. That is, in the memory element included in register 1196, it is selected whether to hold data by a phase inversion element or to hold data by a capacitance element. When holding data by a phase inversion element is selected, the power supply voltage is supplied to the memory element in register 1196. When holding data in the capacitance element is selected, data is rewritten to the capacitance element, and the supply of the power supply voltage to the memory element in register 1196 can be stopped. Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below. In FIG. 15(B) and FIG. 15(C), an example of the configuration of a memory circuit including a transistor using an oxide semiconductor in the channel formation region is shown for the switching element that controls the supply of the power supply potential to the memory element. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. In accordance with the instruction from , the holding operation in register 1196 is selected. That is, in the memory element included in register 1196, it is selected whether to hold data by a phase inversion element or to hold data by a capacitance element. When holding data by a phase inversion element is selected, the power supply voltage is supplied to the memory element in register 1196. When holding data in the capacitance element is selected, data is rewritten to the capacitance element, and the supply of the power supply voltage to the memory element in register 1196 can be stopped. Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below.

[0293] Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below. Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below. Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below. Regarding power supply stop, as shown in FIG. 15(B) or FIG. 15(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. This can be achieved. The circuits of FIG. 15(B) and FIG. 15(C) will be described below.

[0294] In FIG. 15(B) and FIG. 15(C), an example of the configuration of a memory circuit including a transistor using an oxide semiconductor in the channel formation region is shown for the switching element that controls the supply of the power supply potential to the memory element. In FIG. 15(B) and FIG. 15(C), an example of the configuration of a memory circuit including a transistor using an oxide semiconductor in the channel formation region is shown for the switching element that controls the supply of the power supply potential to the memory element. In FIG. 15(B) and FIG. 15(C), an example of the configuration of a memory circuit including a transistor using an oxide semiconductor in the channel formation region is shown for the switching element that controls the supply of the power supply potential to the memory element.

[0295] The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143. The memory device shown in FIG. 15(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, the memory element described in Embodiment Mode 8 can be used for each memory element 1142. To each memory element 1142 included in the memory element group 1143, a high-level power supply potential VDD is supplied via the switching element 1141. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are applied to each memory element 1142 included in the memory element group 1143.

[0296] In FIG. 15B, a switching element 1141 is formed by using an oxide semiconductor as a channel formation region. The transistor has a gate electrode connected to the Switching is controlled by signal SigA.

[0297] In FIG. 15B, the switching element 1141 has only one transistor. However, there is no particular limitation to the configuration, and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0298] In addition, in FIG. 15B, the switching element 1141 The supply of a high-level power supply potential VDD to each memory element 1142 is controlled. Even if the supply of the low-level power supply potential VSS is controlled by the switching element 1141, good.

[0299] In addition, in FIG. 15C, each memory element 1142 included in the memory element group 1143 is provided with a switch. A low-level power supply potential VSS is supplied via the switching element 1141. An example is shown in FIG. 11. The switching element 1141 controls the switching of each memory element included in the memory element group 1143. The supply of a low-level power supply potential VSS to 1142 can be controlled.

[0300] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. A ting element is provided, and even when the operation of the CPU is temporarily stopped and the supply of the power voltage is stopped, it is possible to hold data and reduce power consumption. Specifically, for example, even while the user of a personal computer has stopped inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. Although the CPU has been taken as an example here for explanation, it is also applicable to LSIs such as DSP (Digital Signal Processor), custom LSI, and FPGA (Field Programmable Gate Array). This embodiment can be implemented in appropriate combination with the above embodiment. Description of Reference Numerals

[0301] 100 Transistor 101 Substrate 102 Underlying insulating film

[0302] 103 Oxide semiconductor film 105 First region

[0303] 107a Second region 107b Second region 109a Third region 109b Third region 111 Gate insulating film 113 First electrode 114 Insulating film 115 Sidewall insulating film 115a Sidewall insulating film 115b Sidewall insulating film 117 Interlayer insulating film 119a Second electrode 119b Third electrode 116a Opening 116b Opening ​​​​​ 130 Oxide semiconductor film 132 Oxide semiconductor film 140 Oxide semiconductor film 150 Dopant 200 Transistor 201 Substrate 202 Underlying insulating film 203 Oxide semiconductor film 205 First region 207a Second region 207b Second region 209a Third region 209b Third region 210 Insulating film 211 Gate insulating film 212 Conductive film 213 First electrode 215 Sidewall insulating film 215a Sidewall insulating film 215b Sidewall insulating film 216a Opening 216b Opening 214 Insulating film 217 Interlayer insulating film 219a Second electrode 219b Third electrode 300 Transistor 301 Substrate 302 Underlying insulating film 303 Oxide semiconductor film 305 First region 307a Second region 307b Second region 309a Third region 309b Third region 311 Gate insulating film 313 First electrode 314 Insulating film 315 Sidewall insulating film 315a Sidewall insulating film 315b Sidewall insulating film 317 Interlayer insulating film 319a Second electrode 319b Third electrode 340 Oxide semiconductor film 400 Transistor 401 Substrate 402 Underlying insulating film 403 Oxide semiconductor film 405 First region 407a Second region 407b Second region 409a Third region 409b Third region 410a Fourth region 410b Fourth region 411 Gate insulating film 413 First electrode 419a Second electrode 419b Third electrode 420 Insulating film 500 Transistor 600 Resistive element 601 Substrate 602 Underlying insulating film 603 Oxide semiconductor film 604a Conductive film 604b Conductive film 606 Insulating film 610 Resistive element 1100 Memory cell 1110 Memory cell array 1111 Wiring drive circuit 1112 Readout circuit 1113 Wiring drive circuit 1120 Memory cell array 1130 Memory cell 1131 Transistor 1132 Capacitive element 1140 Memory cell array 1141 Switching element 1142 Memory element 1143 Group of memory elements 1150 Memory cell 1151 Transistor 1152 Transistor 1153 Transistor 1154 Transistor 1155 Transistor 1156 Transistor 1160 Transistor 1161 Transistor 1162 Transistor 1163 Transistor 1164 Transistor 1170 Memory Cell 1171 Transistor 1172 Transistor 1173 Capacitive Element 1180 Memory Cell 1181 Transistor 1182 Transistor 1183 Capacitive Element 1189 ROM Interface 1190 Substrate 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM

Claims

1. a first insulating film; a first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode; a second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode; an oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the second conductive film, and having a channel formation region; a second insulating film having a region in contact with the upper surface of the oxide semiconductor film and functioning as a gate insulating film; a third conductive film having a region in contact with the upper surface of the second insulating film and functioning as a gate electrode; a third insulating film having a region in contact with the upper surface of the third conductive film; and in a cross-sectional view in the channel length direction, the oxide semiconductor film has a first region overlapping with the third conductive film, a pair of second regions adjacent to the first region, and a pair of third regions located outside the pair of second regions; the second region has a region not in contact with the third insulating film; the third region has a region in contact with the third insulating film; the first conductive film has no region overlapping with the second insulating film and no region overlapping with the third conductive film; the second conductive film has no region overlapping with the second insulating film and no region overlapping with the third conductive film, a semiconductor device.

2. a first insulating film; a first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode; a second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode; an oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the second conductive film, and having a channel formation region; a second insulating film having a region in contact with the upper surface of the oxide semiconductor film and functioning as a gate insulating film; a third conductive film having a region in contact with the upper surface of the second insulating film and functioning as a gate electrode; a third insulating film having a region in contact with the upper surface of the third conductive film; and in a cross-sectional view in the channel length direction, the oxide semiconductor film has a first region overlapping with the third conductive film, a pair of second regions adjacent to the first region, and a pair of third regions located outside the pair of second regions; The second region has a region that does not contact the third insulating film. The third region has a region that contacts the third insulating film. The first conductive film has no region overlapping with the second insulating film and no region overlapping with the third conductive film. The second conductive film has no region overlapping with the second insulating film and no region overlapping with the third conductive film. The first insulating film contains oxygen. The first conductive film and the second conductive film contain molybdenum. The oxide semiconductor film contains indium, gallium, and zinc. The second insulating film contains oxygen and silicon. The third conductive film has a first titanium film, an aluminum film on the first titanium film, and a second titanium film on the aluminum film. The third insulating film contains oxygen and silicon, and a semiconductor device.

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