Semiconductor device and manufacturing method thereof, power amplifier circuit, and electronic device

Abstract

The embodiments of this application provide a semiconductor device and its manufacturing method, a power amplifier circuit, and an electronic device, which relate to the field of semiconductor technology and reduce the impact on a semiconductor device caused by arranging a backside via. The semiconductor device includes a substrate, a channel layer and a barrier layer sequentially arranged on the substrate in a stacked manner, a source, a gate, and a drain arranged on the barrier layer, a backside via penetrating a region from the substrate to the barrier layer below the source, and a backside conductive layer covering the backside via and the substrate backside, and the source is in contact with the backside conductive layer and connected to the backside conductive layer.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor devices and methods for manufacturing the same, power amplifier circuits, and electronic equipment. [Background technology]

[0002] 2. Description of the Related Art With the development of semiconductor technology, semiconductor devices with high thermal conductivity, high electron drift velocity, high temperature resistance, and stable chemical properties have been widely used in high frequency, high temperature, and microwave fields.

[0003] For example, when a semiconductor device is used in an integrated circuit such as a power amplifier circuit, the source of the semiconductor device needs to be grounded. In order to reduce the parasitic capacitance and inductance of the semiconductor device, a backside via structure is usually used. The source of the semiconductor device is connected to the backside of the semiconductor through a backside via so that the source of the semiconductor device is directly grounded.

[0004] However, in current technology, when the source of a high-power device needs to be grounded, a backside via is placed under the source. Thus, the size of the source increases, and as a result, the size and performance of the semiconductor device are affected. Therefore, how to reduce the impact of the backside via on the semiconductor device becomes a technical problem that currently needs to be solved by those skilled in the art. Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, a power amplifier circuit, and an electronic device for reducing the impact on the semiconductor device caused by the placement of a backside via.

[0006] To achieve the above objectives, the following technical solutions are used in this application:

[0007] According to a first aspect of an embodiment of the present application, there is provided a semiconductor device including: a substrate; a channel layer and a barrier layer sequentially arranged on the substrate in a stacked manner; a source, a gate, and a drain arranged on the barrier layer; a backside via penetrating a region from the substrate to the barrier layer below the source; and a backside conductive layer covering the backside via and a backside surface of the substrate, wherein the source is in contact with and connected to the backside conductive layer.

[0008] In this embodiment of the present application, the source is in direct ohmic contact with the barrier layer, and a backside via is located under the source. Thus, the backside via is disposed under the source, and the backside conductive layer is in direct contact with and connected to the source through the backside via. A signal is directly conducted from the source to the backside conductive layer, thereby shortening the transmission path to the source. This reduces the inductance of the semiconductor device and increases the frequency of the semiconductor device. Furthermore, the width of the backside via can be appropriately set as required, and there is no need to further reduce the width of the backside via, thereby reducing the difficulty and yield of the backside via manufacturing process and improving the yield and reliability of the backside conductive layer, thereby improving the yield and reliability of the semiconductor device. Therefore, the size of the device source is reduced, thereby enabling small and low-cost semiconductor devices to be manufactured.

[0009] In some embodiments, the work function of the source material is in the range of 4.3 eV to 6 eV. The source material is selected as a metal (e.g., titanium, gold, and platinum) or an alloy containing elements with a high work function and stable chemical properties, and no longer contains reactive metals such as aluminum. In the process of manufacturing a semiconductor device, the source can block the etching of the backside via, thereby avoiding corrosion in the wet processing of the backside via process. As a result, even if the source touches the backside via process, no damage will occur to the source. Therefore, to obtain the above-mentioned semiconductor device through manufacturing, the source does not need to avoid the backside via. This manufacturing process is simple and does not require increased processing difficulty. It is easy to implement.

[0010] In some embodiments, the source material comprises at least one of the elements titanium, gold, and platinum. There are several common metallic elements.

[0011] In some embodiments, the source includes at least one conductive layer. When the source includes one conductive layer, the structure is simple and the manufacturing process is simple. When the source includes multiple conductive layers, the properties of different materials can be combined so that the stress and resistivity of the source can be adjusted. The source can further include a conductive layer that functions to prevent diffusion between multiple metal layers. This avoids damage to the semiconductor device caused by volume expansion of the source.

[0012] In some embodiments, the source includes a first conductive layer and a second conductive layer stacked in order. The first conductive layer includes titanium elements, and the second conductive layer includes gold elements, with the first conductive layer contacting and connecting to the barrier layer. The titanium elements are disposed on the surface of the stacked semiconductor layer (e.g., the barrier layer). While performing a conductive function, they may also perform an adhesive function. This improves the effectiveness of connecting the source and drain to the stacked semiconductor layer.

[0013] In some embodiments, the thickness of each conductive layer is within the range of 1 nm to 10,000 nm. By appropriately setting the film thickness of each conductive layer, the resistance of the source and drain can be reduced without the need for an auxiliary electrode. The structure is simple, the process steps are few, and the manufacturing efficiency is high.

[0014] In some embodiments, the source has a planar structure. The planar structure of the source simplifies the structure and the manufacturing process. Also, after the source is divided into a structure including a plurality of strip patterns by providing openings in the source, it is not necessary to consider how to interconnect the plurality of strip structures.

[0015] In some embodiments, the source has an opening, and the opening is located above the backside via. In this embodiment of the present application, the source is not corroded due to etching in the backside via manufacturing process. In other words, even if the source is touched during the backside via process, the source will not be damaged. Therefore, it is not necessary to set the opening above the source larger than the size of the backside via to avoid corrosion caused by the backside via process. This reduces the size of the source and the overall size of the semiconductor device.

[0016] In some embodiments, the semiconductor device further includes a thickened source disposed on a surface of the source, which is equivalent to increasing the thickness of the source and decreasing the resistance of the source, thereby improving the current carrying capability of the semiconductor device.

[0017] In some embodiments, the semiconductor device further includes a thickening source disposed on a surface of the source, the thickening source contacting the backside conductive layer through the opening.

[0018] In some embodiments, the semiconductor device further includes a thickened drain disposed on a surface of the drain, which is equivalent to increasing the thickness of the drain and reducing the resistance of the drain, thereby improving the current carrying capability of the semiconductor device.

[0019] In some embodiments, the semiconductor device further includes a field plate. The field plate is disposed on the side of the gate away from the substrate, between the gate and the drain, and overlaps with the projection of the gate. Electric field peaks tend to occur at the gate. Therefore, disposing the field plate on the gate can adjust the electric field distribution within the semiconductor device. This allows the electric field distribution to be uniform, and electric field peaks are avoided.

[0020] According to a second aspect, there is provided a power amplifier circuit, the power amplifier circuit including a packaging structure and a semiconductor device according to any one of the first aspects, wherein the semiconductor device is packaged inside the packaging structure.

[0021] The power amplifier circuit provided in this embodiment of the present application includes the semiconductor device in the first aspect, and the beneficial effects of the power amplifier circuit are the same as those of the semiconductor device, and the details will not be described again here.

[0022] According to a third aspect, there is provided an electronic device including a power amplifier and an antenna, wherein the power amplifier is configured to amplify a radio frequency signal and output the amplified radio frequency signal to an antenna for external radiation, the power amplifier including a power amplifier circuit according to the second aspect.

[0023] The electronic device provided in this embodiment of the present application includes the semiconductor device in the first aspect. The beneficial effects of the electronic device are the same as those of the semiconductor device. The details will not be described again here.

[0024] According to a fourth aspect, there is provided a method for manufacturing a semiconductor device, the method including: sequentially forming a channel layer and a barrier layer arranged in a stacked manner on a substrate; forming a source, a gate, and a drain on the barrier layer; forming a backside via under the source, the backside via penetrating a region from the substrate to the barrier layer under the source; forming a backside conductive layer on a backside of the substrate, the backside conductive layer covering the backside via and the backside of the substrate; and the source being in contact with the backside conductive layer and connected to the backside conductive layer.

[0025] According to the semiconductor device manufacturing method provided in this embodiment of the present application, when the source is formed, the source material is selected as a metal (e.g., titanium, gold, and platinum) with a high work function and stable chemical properties, and no longer contains reactive metals. The source material or manufacturing process is adjusted so that the source forms an ohmic contact directly with the barrier layer. In the process of manufacturing the semiconductor device, the source is enabled to block the etching of the backside via, thereby avoiding corrosion in the wet processing of the backside via process. Thus, the finally formed backside via is disposed below the source, and the backside conductive layer is connected to the source by directly contacting the source through the backside via. Signals are conducted directly from the source to the backside conductive layer, thus shortening the transmission path to the source. This reduces the inductance of the semiconductor device and can increase the frequency of the semiconductor device. In addition, the width of the backside via can be appropriately set as required, and there is no need to further reduce the width of the backside via, which reduces the difficulty and yield of the backside via manufacturing process and improves the yield and reliability of the backside conductive layer, thereby improving the yield and reliability of the semiconductor device. Therefore, the size of the device source is reduced, and therefore, smaller, lower cost semiconductor devices can be obtained through manufacturing.

[0026] In some embodiments, forming a backside via under the source includes creating a via in a film layer under the source from the backside of the substrate by using a dry etching process to form a backside via, and removing etching by-products remaining in the via by dry etching or wet etching. [Brief explanation of the drawings]

[0027] [Figure 1A] 1 is a schematic diagram of a terminal framework according to an embodiment of the present application; [Figure 1B] 1 is a schematic diagram of a base station framework according to an embodiment of the present application; [Figure 1C]1 is a schematic diagram of a framework of a power amplifier circuit according to an embodiment of the present application; [Figure 2A] 1 is a schematic top view of an integrated circuit according to one embodiment of the present application; [Figure 2B] FIG. 2 is a schematic top view of another integrated circuit according to an embodiment of the present application. [Figure 2C] FIG. 2C is a cross-sectional view taken along the A1-A2 direction in FIG. 2B. [Figure 3A] FIG. 10 is a schematic top view of yet another integrated circuit according to an embodiment of the present application. [Figure 3B] FIG. 3B is a cross-sectional view taken along the B1-B2 direction of FIG. 3A. [Figure 4] 1 is a flowchart of manufacturing a semiconductor device according to one embodiment of the present application. [Figure 5A] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5B] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5C] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5D] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5E] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5F] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 5G] 5A-5G are schematic diagrams of a manufacturing process for a semiconductor device according to one embodiment of the present application. [Figure 6A] 1 is a schematic diagram of a structure of a semiconductor device according to an embodiment of the present application; [Figure 6B] FIG. 2 is a schematic diagram of another semiconductor device structure according to an embodiment of the present application. [Figure 6C] 1 is a schematic diagram of a structure of yet another semiconductor device according to an embodiment of the present application. [Figure 7A] FIG. 1 is a schematic top view of a structure of yet another semiconductor device according to an embodiment of the present application. [Figure 7B] 1 is a schematic top view of yet another semiconductor device structure according to an embodiment of the present application. [Figure 7C] FIG. 7C is a cross-sectional view taken along the C1-C2 direction of FIG. 7B. [Figure 8] 1 is a schematic diagram of a structure of yet another semiconductor device according to an embodiment of the present application. [Figure 9A] 1 is a schematic diagram of yet another semiconductor device structure according to an embodiment of the present application. [Figure 9B] 2 is a schematic diagram of a structure of a further semiconductor device according to an embodiment of the present application; [Figure 9C] 1 is a schematic diagram of a structure of a still further semiconductor device according to an embodiment of the present application. [Figure 10A] 1 is a schematic diagram of a structure of a still further semiconductor device according to an embodiment of the present application. [Figure 10B] 1 is a schematic diagram of a structure of a still further semiconductor device according to an embodiment of the present application. [Figure 10C] 1 is a schematic diagram of yet another semiconductor device structure according to an embodiment of the present application. [Figure 11] 1 is a schematic diagram of a structure of yet another semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, the technical solutions in the embodiments of this application will be described with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part, rather than all, of the embodiments of this application.

[0029] The following describes technical terms used in the embodiments of this application.

[0030] Semiconductor: A semiconductor is a material whose conductivity lies between that of a conductor and that of an insulator at room temperature. Semiconductors include intrinsic and extrinsic semiconductors. A pure semiconductor without impurities or defects and containing the same concentration of electrons and holes is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an extrinsic or non-intrinsic semiconductor. Impurities doped into an extrinsic semiconductor can provide a certain concentration of carriers (e.g., holes or electrons). An extrinsic semiconductor doped with an electron-donating impurity (e.g., pentavalent phosphorus) is also called an electron semiconductor or N-type (negative) semiconductor. An impurity semiconductor doped with a hole-donating impurity (e.g., trivalent boron) is also called a hole semiconductor or P-type (positive) semiconductor. Doping can increase the conductivity of an intrinsic semiconductor. Generally, the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, a layer structure in a device fabricated by using a semiconductor (or semiconductor material) is referred to as a semiconductor layer.

[0031] Hereinafter, the terms "first," "second," and the like in the embodiments of this application are intended merely for ease of description and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Therefore, features qualified by "first," "second," or the like may explicitly or implicitly include one or more features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0032] In the embodiments of this application, "upper", "lower", "left", and "right" are not limited to being defined relative to the orientation of components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarity, and may change correspondingly based on changes in the orientation of components in the accompanying drawings.

[0033] In the embodiments of this application, unless otherwise required by context, throughout the specification and claims, the term "comprising" is to be interpreted as "open and inclusive," i.e., "including, but not limited to." In this description, terms such as "one embodiment," "some embodiments," "one example embodiment," "for example," "some examples," or the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or example is included in at least one embodiment or example of the present disclosure. General references to such terms do not necessarily refer to the same embodiment or example. Furthermore, the particular feature, structure, material, or characteristic may be included in any one or more embodiments or examples in any suitable manner.

[0034] When describing some embodiments, the terms "electrically connected" and "connected" and their extensions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. In another example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. However, the term "electrically connected" may also indicate that two or more components are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this specification.

[0035] In the embodiments of this application, "and / or" simply describes an association relationship to describe related objects, and represents that three relationships may exist. For example, A and / or B may represent the following three cases: only A exists, both A and B exist, and only B exists. Also, the character " / " in this specification generally indicates an "or" relationship between related objects.

[0036] Unless otherwise defined, all scientific and technical terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art. In this application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following items" or similar expressions means any combination of the items, including a singular item or any combination of multiple items. For example, at least one of a, b, or c can represent a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c may be singular or plural.

[0037] In the embodiments of this application, implementation examples are described with reference to cross-sectional views, plan views, and / or equivalent circuit diagrams used as idealized examples in the accompanying drawings. In the accompanying drawings, thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the accompanying drawings may occur due to factors such as manufacturing techniques and / or tolerances. Therefore, implementation examples should not be construed as limited to the shapes of regions shown in this specification, but rather include deviations in shape caused by factors such as manufacturing. For example, etched regions shown as rectangles typically have curved characteristics. Therefore, the regions shown in the accompanying drawings are exemplary in nature, and their shapes are not intended to represent the actual shapes of regions of devices and are not intended to limit the scope of implementation examples.

[0038] One embodiment of this application provides an electronic device. The electronic device may be different types of user equipment or terminal equipment, such as a lidar driver, a laser, a detector, a radar, and a 5G (5th generation mobile network) communication device. Alternatively, the electronic device may be a network device, such as a base station. Alternatively, the electronic device may be a device, such as a power amplifier, used in the electronic device. The specific form of the electronic device is not particularly limited in the embodiments of this application.

[0039] For example, the electronic device provided in this embodiment of the application is a mobile phone. Figure 1A is a schematic diagram of the configuration of a mobile phone 100. The mobile phone 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headset jack 170D, a sensor module 180, a camera 190, a display 191, and the like.

[0040] It can be understood that the configuration shown in this embodiment of this application does not constitute a specific limitation on the mobile phone 100. In some other embodiments of this application, the mobile phone 100 may include more or fewer components than those shown in the figures, some components may be combined, some components may be separated, or different component arrangements may be used. The components shown in the figures may be implemented in hardware, software, or a combination of software and hardware.

[0041] Processor 110 may include one or more processing units. For example, processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be separate components or may be integrated into one or more processors.

[0042] Further memory may be located within processor 110 and configured to store instructions and data. In some embodiments, the memory within processor 110 is a cache. The memory may store instructions or data that have been used or are repeatedly used by processor 110. When processor 110 needs to use those instructions or data again, those instructions or data can be retrieved directly from the memory. This avoids repeated accesses, reduces latency for processor 110, and improves system efficiency.

[0043] In some embodiments, processor 110 may include one or more interfaces, which may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, a universal serial bus (USB) interface, and / or the like.

[0044] The charging management module 140 is configured to receive a charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive the charging input of the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive the wireless charging input via a wireless charging coil of the mobile phone 100. The charging management module 140 provides power to the mobile phone by using the power management module 141 while charging the battery 142.

[0045] Power management module 141 is configured to connect to battery 142, charging management module 140, and processor 110. Power management module 141 receives input from battery 142 and / or charging management module 140 and provides power to processor 110, internal memory 121, display 191, camera 190, wireless communication module 160, etc. Power management module 141 may also be configured to monitor parameters such as battery capacity, battery cycle count, and battery health (leakage or impedance). In some other embodiments, power management module 141 may instead be located within processor 110. In some other embodiments, power management module 141 and charging management module 140 may instead be located within the same device.

[0046] The wireless communication function of the mobile phone 100 may be implemented by an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, a modem processor, a baseband processor, and the like.

[0047] Antenna 1 and Antenna 2 are configured to transmit and receive electromagnetic wave signals. Each antenna in mobile phone 100 may be configured to cover one or more communication bands. Different antennas may be further multiplexed to improve antenna utilization. For example, Antenna 1 may be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, antennas may be used in combination with tuning switches.

[0048] Mobile communication module 150 may provide wireless communication solutions for mobile phone 100, including 2G, 3G, 4G, 5G, and the like. Mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), and the like. Mobile communication module 150 may receive electromagnetic waves via antenna 1, perform processing, such as filtering or amplification, on the received electromagnetic waves, and send the electromagnetic waves to a modem processor for demodulation. Mobile communication module 150 may also amplify signals modulated by the modem processor and convert the signals into electromagnetic waves for emission via antenna 1. In some embodiments, at least some functional modules in mobile communication module 150 may be located within processor 110. In some embodiments, at least some functional modules of mobile communication module 150 may be located within the same device as at least some modules of processor 110.

[0049] The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a low-frequency baseband signal to be transmitted into a medium-frequency signal. The demodulator is configured to demodulate a received electromagnetic signal into a low-frequency baseband signal. The demodulator then sends the low-frequency baseband signal obtained through demodulation to the baseband processor for processing. The low-frequency baseband signal is processed by the baseband processor and then sent to the application processor. The application processor outputs a sound signal by using an audio device (such as, but not limited to, speaker 170A or receiver 170B) or displays an image or video by display 191. In some embodiments, the modem processor may be an independent component. In some other embodiments, the modem processor may be separate from the processor 110 and located within the same device as the mobile communication module 150 or other functional modules.

[0050] The wireless communication module 160 may provide wireless communication solutions applied to the mobile phone 100, such as a wireless local area network (WLAN) (e.g., a wireless fidelity (Wi-Fi) network), Bluetooth (BT), a global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 may be one or more devices integrating one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 may further receive signals to be transmitted from the processor 110, perform frequency modulation and amplification on the signals, and convert the signals into electromagnetic waves for emission via the antenna 2.

[0051] In some embodiments, within mobile phone 100, antenna 1 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, such that mobile phone 100 can communicate with networks and other devices using wireless communication technologies that may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, IR technologies, and / or the like. GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a BeiDou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS), and / or a satellite-based augmentation system (SBAS).

[0052] The mobile phone 100 implements display functionality by using a GPU, a display 191, an application processor, and the like. The GPU is a microprocessor for image processing and is connected to the display 191 and the application processor. The GPU is configured to perform mathematical and geometric calculations and render images. The processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0053] The display 191 is configured to display images, videos, and the like. The display 191 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini-LED, a micro-LED, a micro-OLED, a quantum dot light-emitting diode (QLED), or the like. In some embodiments, the mobile phone 100 may include one or N displays 194, where N is a positive integer greater than 1. The mobile phone 100 may implement a photography function by using an ISP, a camera 190, a video codec, a GPU, the display 191, an application processor, and the like.

[0054] The ISP may be configured to process data fed back by the camera 190. For example, when taking a picture, the shutter is pressed and light is transmitted through the lens to the camera's photosensitive elements. The light signal is converted into an electrical signal, which the camera's photosensitive elements send to the ISP for processing, converting the electrical signal into a visible image. The ISP may also perform algorithmic optimization for image noise, brightness, and skin tone. The ISP may also optimize parameters such as exposure and color temperature for the shooting scenario. In some embodiments, the ISP may be located within the camera 190.

[0055] The camera 190 is configured to capture still images or video. An optical image of a subject is generated through a lens and projected onto a photosensitive element. The photosensitive element may be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal and sends the electrical signal to an ISP, which converts the electrical signal into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into an image signal in a standard format, such as RGB or YUV. In some embodiments, the mobile phone 100 can include one or N cameras 190, where N is a positive integer greater than 1.

[0056] The external memory interface 120 may be configured to connect to an external memory card, such as a microSD card, to expand the storage capabilities of the mobile phone 100. The external memory card communicates with the processor 110 through the external memory interface 120 to perform data storage functions. For example, files such as music and videos may be stored on the external storage card.

[0057] Internal memory 121 may be configured to store one or more computer programs, which include instructions. Processor 110 may execute the instructions stored in internal memory 121 to enable mobile phone 100 to perform various functional applications, data processing, and the like. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system. The program storage area may further store one or more applications (e.g., Gallery or Contacts) and the like. The data storage area may store data (e.g., photos and contacts) and the like created during use of mobile phone 100. Internal memory 121 may also include high-speed random access memory and may further include non-volatile memory, such as one or more disk storage components, flash storage devices, or universal flash storage (UFS). In some other embodiments, the processor 110 may run instructions stored in the internal memory 121 and / or in memory located within the processor to enable the mobile phone 100 to perform various functional applications and data processing.

[0058] The mobile phone 100 may implement audio functions, such as music playback and recording, via an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headset jack 170D, and an application processor.

[0059] Audio module 170 is configured to convert digital audio information to analog audio signal output, and further configured to convert analog audio input to digital audio signals. Audio module 170 may also be configured to encode and decode audio signals. In some embodiments, audio module 170 may be located within processor 110, or some functional modules within audio module 170 may be located within processor 110.

[0060] The speaker 170A, also referred to as a "loudspeaker," is configured to convert audio electrical signals into sound signals. The mobile phone 100 can use the speaker 170A to play music and receive hands-free calls.

[0061] The receiver 170B, also referred to as an "earphone," is configured to convert an audio electrical signal into a sound signal. When the mobile phone 100 receives a call or voice message, the receiver 170B can be placed near a person's ear so that the sound can be heard.

[0062] The microphone 170C, also referred to as a "mike" or "mic," is configured to convert sound signals into electrical signals. When making a call or sending a voice message, a user may input a sound signal into the microphone 170C by bringing their mouth close to the microphone 170C and making a sound. One or more microphones 170C may be disposed on the mobile phone 100. In some other embodiments, two microphones 170C may be disposed on the mobile phone 100 to collect sound signals and further implement noise suppression functions. In some other embodiments, three, four, or more microphones 170C may instead be disposed on the mobile phone 100 to collect sound signals, suppress noise, further identify sound sources, implement directional recording functions, etc.

[0063] The headset jack 170D is configured to connect to a wired headset and may be a USB interface 130, a 3.5 mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0064] The sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, an optical proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

[0065] In the embodiments of this application, the touch sensor is also referred to as a "touch control component." The touch sensor may be arranged within the display 191 such that the touch sensor and the display 191 form a touch screen, also referred to as a "touch screen." The touch sensor is configured to detect a touch operation performed on or near the touch sensor. The touch sensor may communicate the detected touch operation to an application processor to determine the type of touch event. A visual output associated with the touch operation may be provided using the display 191. In some other embodiments, instead, a touch panel of a touch sensor array formed by a plurality of touch sensors may be arranged on the surface of the display panel in the form of an external attachment. In some other embodiments, instead, the touch sensor may be arranged at a position different from the position of the display 191. The form of the touch sensor is not limited in this embodiment of this application. For example, the touch sensor may be a component such as a capacitor or a varistor.

[0066] Additionally, the mobile phone 100 may further include one or more components, such as buttons, motors, indicators, and a subscriber identity module (SIM) card interface, which are not limited to the embodiments of this application.

[0067] For example, the electronic device provided in this embodiment of the application is a 5G base station, which can be divided into different architectures, such as a baseband processing unit (BBU), an active antenna unit (AAU), a central unit-distribute unit (CU-DU), an AAU, a BBU, a remote radio unit (RRU), an antenna, a CU-DU-RRU-antenna, and an integrated 5G node base station (gNB).

[0068] 1B shows an example of a base station 200 with a BBU-RRU architecture. The base station 200 may include a BBU 21, an RRU 22, and an antenna 23. The BBU 21 and the RRU 22 are connected via optical fiber, and the interface between the BBU 21 and the RRU 22 is based on the common public radio interface (CPRI) and the open base station architecture initiative (OBSAI). The BBU 21 processes a generated baseband signal using the RRU 22 and then sends the processed baseband signal to the antenna 23 for transmission. The RRU 22 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier (PA) 223, and a filter 224. The digital intermediate frequency module 221 is configured to perform modulation and demodulation, digital up- and down-conversion, digital-to-analog conversion (D / A), and the like, of the baseband signal sent via the optical fiber to form an intermediate frequency signal. The transceiver module 222 completes the conversion from the intermediate frequency signal to a radio frequency signal. The power amplifier 223 is configured to amplify the power of the low-power radio frequency signal. The filter 224 is configured to filter the radio frequency signal and then transmit the radio frequency signal via the antenna 23.

[0069] An embodiment of the present application further provides a power amplifier circuit, which can be used in the power amplifier of the mobile communication module 150 or the wireless communication module 160 of the mobile phone 100 shown in Fig. 1A, or can be used in the power amplifier of the RRU 22 of the base station 200 shown in Fig. 1B. Certainly, the specific application scenario is not limited to the mobile phone 100 shown in Fig. 1A and the base station 200 shown in Fig. 1B. It can be understood that any electronic device that needs to amplify a signal by using a power amplifier circuit in a power amplifier belongs to the application scenario of the embodiment of the present application.

[0070] For example, Figure 1C shows a power amplifier circuit 30. The power amplifier circuit 30 includes an integrated circuit 31 and a packaging structure 32. The integrated circuit 31 is packaged inside the packaging structure 32. As shown in Figure 1C, a specific packaging structure for the power amplifier circuit 30 is provided. The integrated circuit 31 is packaged within the packaging structure 32 of the power amplifier circuit 30.

[0071] 1C, the package structure 32 specifically includes a heat dissipation base substrate 321. To improve the conductivity and heat dissipation of the heat dissipation base substrate 321, the heat dissipation base substrate 321 may use a composite material, such as a laminate structure formed by copper (Cu) / molybdenum (Mo) / copper (Cu). The integrated circuit 31 is bonded to the heat dissipation base substrate 321 through silver sintering or directly welded.

[0072] The integrated circuit 31 includes at least one transistor. Some electrodes of the transistor (e.g., source S) are electrically connected to the heat dissipation base substrate 321 to ground the source S. Some electrodes of the transistor (e.g., drain D and gate G) are connected to pins through wire bonding using gold wires. These pins are placed on an insulating layer (e.g., insulating ceramic), and the insulating layer is bonded to the heat dissipation base substrate 321 using an insulating adhesive.

[0073] The package structure 32 also includes a package housing 322. The package housing 322 is bonded to a heat dissipation base substrate 321 using an insulating adhesive, and one end of the pin is exposed from the package structure for connection to another circuit. The integrated circuit 31 is disposed in a space surrounded by the package housing 322 and the heat dissipation base substrate 321.

[0074] A high electron mobility transistor (HEMT) device is a semiconductor device that is widely used as a transistor in integrated circuits 31 due to its advantages, such as high breakdown field, high channel electron concentration, high electron mobility, and high temperature stability. In the following, for illustration purposes, an example is taken in which the semiconductor device provided in this embodiment of this application is a HEMT device.

[0075] In some application scenarios (for example, the integrated circuit 31 is a circuit structure in a power amplifier circuit), the source of the HEMT device needs to be grounded. A ground cable is drawn out from the top of the source. Therefore, the ground cable overlaps with other leads in the HEMT device, generating parasitic capacitance. Also, as shown in FIG. 1C , a heat dissipation base substrate 321 is located on the backside of the HEMT device. The ground cable is drawn out to the heat dissipation base substrate 321, which increases the length of the ground cable and increases the inductance.

[0076] As a result, in some embodiments, a backside via structure is typically used to reduce the parasitic capacitance and inductance of the HEMT device. The source of the HEMT device is directly connected to the backside of the HEMT device through a backside via for grounding. In this way, the overlap of the source, gate, and drain leads and the length of the ground cable can be reduced, and the parasitic capacitance and inductance of the HEMT device can be reduced.

[0077] In addition, due to limitations of factors such as process, the design of the backside via may increase the width of the source (S), which will affect the overall size of the HEMT device. Therefore, how to reduce the size of the source in the backside via structure to reduce the impact of the source size on the size of the HEMT device becomes a technical problem that needs to be solved by those skilled in the art.

[0078] Based on the location of the backside via in the HEMT device, the backside via is generally classified into active area backside via and passive area backside via. The active area backside via is one or more backside via structures located under the source. The passive area backside via is one or more backside vias located corresponding to the location of the passive area after multiple sources are connected to one location of the passive area.

[0079] In some embodiments, as shown in FIG. 2A , an embodiment of the present application provides an integrated circuit 31. The integrated circuit 31 includes a plurality of HEMT devices. The backside vias of the HEMT devices are located outside the sources S, and the backside vias are located under the source bonding pads. The backside vias are fabricated in passive areas to bring the sources S of the HEMT devices out to the backside for grounding.

[0080] In the structure shown in FIG. 2A, the backside via does not need to be located under the source S in the active region, so the size of the source S can be set as required, and the area of the source S does not need to be increased due to the presence of the backside via, and therefore the size of the HEMT device can be reduced.

[0081] However, as shown in Figure 2A, a backside via structure is placed in the passive area to electrically connect the sources S of multiple HEMT devices to the source bonding pads. Therefore, in the region where the source S intersects with the gate (gate, G), the source S needs to cross the intersection area via a dielectric bridge (a dielectric layer is placed in the region where the source S intersects with the gate G, and the sources S on both sides of the gate G are electrically connected via cross bridges on the dielectric layer) or an air bridge (the source S jumps over the region where the source S intersects with the gate G, ensuring a gap between the source S and the gate G) to be electrically connected to the source bonding pad.

[0082] As a result, it is necessary to fabricate an air bridge or dielectric bridge within the HEMT device, which complicates the process. The air bridge structure is unstable and prone to cracks in the passivation layer during subsequent processes. Furthermore, the crossing of the source S with the gate G can result in large parasitic capacitance. In addition, because the backside via is located under the source bonding pad, the path for transmitting the signal from the source bonding pad to the source S is long. This increases the inductance of the HEMT device and affects the frequency characteristics of the HEMT device.

[0083] Based on this, in order to reduce the inductance of the HEMT device, in some embodiments, an embodiment of this application provides an integrated circuit 31, as shown in FIG. 2B. The integrated circuit 31 includes a plurality of HEMT devices. A backside via is located under the source S of the HEMT device. The backside via is fabricated in the active region to bring the source S of the HEMT device out to the backside for grounding.

[0084] By locating the backside via under the source S, the path for transmitting a signal to the source S can be shortened, and the inductance of the HEMT device can be reduced.

[0085] However, the material of the source S usually contains a reactive metal, such as aluminum. Therefore, there are two main process problems in the manufacturing process of a HEMT device. First, in the process of forming a backside via through etching on the backside, the source S cannot block the backside via etching, and the backside via etching cannot stop at the bottom surface of the source S. Second, wet etching in the backside via process will corrode the metal of the source S. Therefore, as shown in FIG. 2C (a cross-sectional view along the A1-A2 direction in FIG. 2B), an opening can be provided in the source S. The direction from the source S to the drain D is defined as the width direction (first direction X). To avoid damage to the source S due to the backside via process, it is necessary to ensure that the width M1 of the opening is larger than the width M2 of the backside via to prevent the source S from being touched during the backside via process. That is, the outline of the opening surrounds the outline of the backside via, and a gap L exists between the outline of the opening and the outline of the backside via. The gap L at various locations (e.g., the gaps L1 and L2 on the left and right sides in FIG. 2C) may be the same or different. To ensure that the source S is not damaged, the value of the gap L is typically in the range of 500 nm to 50,000 nm.

[0086] The width M of the source S is equal to the width M1 of the opening plus the width of the non-opening. Therefore, the introduction of the gap L increases the width M1 of the opening on the source S (M1 = M2 + L1 + L2), which results in an increase in the area of the HEMT device. In addition, after the opening is formed on the source S, a thickened source needs to be formed on the source S to block the backside via etching, and the thickened source does not form an ohmic contact with the barrier layer.

[0087] Therefore, to reduce the width M1 of the source S, in some embodiments, the width M2 of the backside via is reduced so that the width M1 of the opening is reduced, thereby reducing the size of the source S.

[0088] However, reducing the width M2 of the backside via increases the depth-to-width ratio of the backside via, which may increase the process difficulty of forming the backside via. Furthermore, reducing the width M2 of the backside via increases the difficulty of forming a backside conductive layer that covers the surface of the backside via and contacts the source S, which affects the yield and reliability of the backside conductive layer, and as a result, the yield and reliability of the HEMT device are affected.

[0089] Based on this, in some embodiments, another HEMT device structure is provided to solve the problem of the large size of the source S. The structure of the HEMT device will be described below with some examples.

[0090] Example 1

[0091] As shown in Figure 3A, one embodiment of this application provides an integrated circuit 31. The integrated circuit 31 includes a plurality of HEMT devices. A backside via is located under the source S of the HEMT device. The backside via is fabricated in the active region to bring the source S of the HEMT device out to the backside for grounding.

[0092] As shown in FIG. 3B (a cross-sectional view taken along the B1-B2 direction in FIG. 3A), it is not necessary to provide an opening in the source S.

[0093] 2C do not exist because there is no need to provide an opening in the source S. Therefore, the width M2 of the backside via is independent of the width M of the source S. Specifically, increasing the width M2 of the backside via does not necessarily increase the width M of the source S, provided that the size of the width M2 of the backside via is smaller than the width M of the source. Thus, the width M2 of the backside via can be designed to be sufficiently large without necessarily increasing the size of the source S.

[0094] A method for manufacturing the HEMT device shown in FIG. 3B will now be described.

[0095] As shown in FIG. 4, the manufacturing method of the HEMT device includes the following steps.

[0096] S10: As shown in FIG. 5A, a laminated semiconductor layer is formed on a substrate 41.

[0097] In some embodiments, the stacked semiconductor layers on the substrate 41 include a nucleation layer, a graded buffer layer, a channel layer 42, an insertion layer, a barrier layer 43, and a cap layer arranged in a stacked manner. The channel layer 42 and the barrier layer 43 form a heterojunction, and a two-dimensional electron gas (2DEG) 44 is generated above the channel layer 42.

[0098] FIG. 5A shows a method for forming a laminated semiconductor layer, where step S10 includes the following steps.

[0099] S11: A nucleation layer is formed on the substrate 41.

[0100] The substrate 41 can be, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a sapphire substrate, or a diamond substrate. The material of the substrate 41 is not limited in this embodiment of this application.

[0101] The nucleation layer is formed on the substrate 41. In other words, as shown in Figure 5A, the nucleation layer is disposed on the substrate 41. For example, the nucleation layer is disposed on the surface of the substrate 41.

[0102] The nucleation layer can be formed, for example, by using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0103] The material of the nucleation layer may include, for example, one or more of GaN (gallium nitride), AlGaN (aluminum gallium nitride), and AlN (aluminum nitride).

[0104] The nucleation layer is intended to improve epitaxial quality and facilitate the growth of the top epitaxy.

[0105] S12: Form a graded buffer layer on the nucleation layer.

[0106] Alternatively, this can be understood as forming a graded buffer layer on the side of the nucleation layer away from the substrate 41 .

[0107] 5A, the graded buffer layer is disposed on the side of the nucleation layer that is remote from the substrate 41. For example, the graded buffer layer is disposed on the surface of the nucleation layer that is remote from the substrate 41.

[0108] The graded buffer layer can be formed, for example, by epitaxially growing an AlGaN graded layer whose Al (aluminum) composition gradually decreases using an MOCVD process.

[0109] For example, by using an MOCVD process, Al 0.8 Ga 0.2 N layer, Al 0.5 Ga 0.5 N layer and Al 0.2 Ga 0.8 N layers are formed in sequence to form a graded buffer layer.

[0110] To suppress the mobility reduction caused by electron scattering, the graded buffer layer typically uses a non-doped structure.

[0111] The function of the graded buffer layer is as follows: the band gap of the graded buffer layer is different from that of the channel layer 42, which results in a deeper potential well depth of the heterojunction formed by the barrier layer 43 and the channel layer 42. This increases the limit of the two-dimensional electron gas. Also, the buffer layer is usually thick and is the main structure of the device to withstand voltage.

[0112] S13: A channel layer 42 is formed on the graded buffer layer.

[0113] Alternatively, this can be understood as the channel layer 42 being formed on the side of the graded buffer layer remote from the substrate 41 .

[0114] As can be seen from the above description, both the nucleation layer and the graded buffer layer are formed on the substrate 41. Therefore, the channel layer 42 formed on the side of the graded buffer layer farther from the substrate 41 is also located on the substrate 41.

[0115] The channel layer 42 can be formed by using, for example, the MOCVD method or the MBE method.

[0116] The material of the channel layer 42 may include, for example, one or more of GaN, AlGaN, InAlN (indium aluminum nitride), AlN, and ScAlN (scandium aluminum nitride).

[0117] In some embodiments, the thickness of the channel layer 42 is in the range of 100 nm to 5000 nm, for example, the thickness of the channel layer 42 is 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, or 4500 nm.

[0118] S14: An insertion layer is formed on the channel layer 42.

[0119] Alternatively, this can be understood as the insertion layer being formed on the side of the channel layer 42 that is farther from the substrate 41. In other words, as shown in Figure 5A, the insertion layer is disposed on the side of the channel layer 42 that is farther from the substrate 41. For example, the insertion layer is disposed on the surface of the channel layer 42 that is farther from the substrate 41 to improve the mobility of the two-dimensional electron gas 44.

[0120] The insertion layer can be formed by using, for example, an MOCVD method or an MBE method.

[0121] S15: A barrier layer 43 is formed on the insertion layer.

[0122] Alternatively, this may be understood as the barrier layer 43 being formed on the side of the insertion layer remote from the substrate 41. In other words, as shown in Figure 5A, the barrier layer 43 is disposed on the side of the insertion layer remote from the substrate 41. For example, the barrier layer 43 is disposed on the surface of the insertion layer remote from the substrate 41.

[0123] The barrier layer 43 can be formed by using, for example, the MOCVD method or the MBE method.

[0124] The material of the barrier layer 43 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.

[0125] The material of the channel layer 42 is different from the material of the barrier layer 43, and the channel layer 42 and the barrier layer 43 form a heterostructure. For example, the material of the channel layer 42 includes GaN, and the material of the barrier layer 43 includes AlGaN.

[0126] In some embodiments, the thickness of the barrier layer 43 is in the range of 2 nm to 50 nm. For example, the barrier layer 43 has a thickness of 25 nm and is made of AlGaN with an aluminum composition of 25%. For example, the thickness of the barrier layer 43 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or 45 nm.

[0127] The barrier layer 43 is usually undoped. By utilizing the work function difference between the barrier layer 43 and the subsequently formed gate (usually made of a metal material), a barrier layer capable of conducting current in one direction is formed under the gate. This ensures the gate's ability to control the channel layer 42, and can also effectively suppress the electrical leakage problem of the gate.

[0128] S16: A cap layer is formed on the barrier layer 43.

[0129] Alternatively, this may be understood as a cap layer being formed on the side of the barrier layer 43 that is remote from the substrate 41. As shown in Figure 5A, the cap layer is disposed on the side of the barrier layer 43 that is remote from the substrate 41. For example, the cap layer is disposed on the surface of the barrier layer 43 that is remote from the substrate 41.

[0130] The cap layer can be formed, for example, by using an MOCVD method or an MBE method.

[0131] The material of the cap layer may be, for example, GaN or Si3N4 (silicon nitride). It may be understood that the cap layer should not affect the ohmic contact between the source and drain and the barrier layer 43. The above effect may be achieved by doping or patterning the cap layer (exposing the barrier layer 43).

[0132] The thickness of the cap layer is too small to protect the barrier layer 43. If the cap layer is too thick, the thickness of the HEMT device may be increased. Thus, in some embodiments, the thickness of the cap layer may be, for example, in the range of 1 nm to 20 nm. For example, the thickness of the cap layer is 5 nm, 10 nm, or 15 nm.

[0133] That is, as shown in FIG. 5A, the stacked semiconductor layers on a substrate 41 include a nucleation layer, a graded buffer layer, a channel layer 42, an insertion layer, a barrier layer 43, and a cap layer arranged in a stacked manner.

[0134] However, in this embodiment of the present application, when the laminated semiconductor layer is formed, it is not necessary to perform all of the above-mentioned steps S11-S16. Some of these steps may be performed. Alternatively, other steps may be added, provided that a heterostructure including at least the channel layer 42 and the barrier layer 43 is formed on the substrate 41.

[0135] For ease of explanation, as shown in FIG. 5B, in the subsequent process, only an example in which the laminated semiconductor layer formed on the substrate 41 includes a channel layer 42 and a barrier layer 43 is used for illustration.

[0136] S20: As shown in FIG. 5B, a source 45 and a drain 46 are formed on the laminated semiconductor layer.

[0137] For example, if a cap layer is located as the uppermost layer in the laminated semiconductor layers, the source 45 and drain 46 are formed on the cap layer. Alternatively, if a barrier layer 43 is located as the uppermost layer in the laminated semiconductor layers, the source 45 and drain 46 are formed on the barrier layer 43. Regardless of which structure is used, it is only necessary to ensure that the source 45 and drain 46 form ohmic contact with the barrier layer 43.

[0138] FIG. 5B shows a method for forming the source 45 and the drain 46, where S20 includes the following steps.

[0139] S21: A photoresist is prepared to cover the laminated semiconductor layers, and photoetching is performed to form a source bonding pad opening in the region where the source 45 is to be formed, and a drain bonding pad opening in the region where the drain 46 is to be formed.

[0140] For example, see FIG. 5B. First, photoresist can be coated on the laminated semiconductor layer, and a light-shielding plate (photomask) is configured to shield the photoresist. The shape of the light-shielding plate is shown in FIG. 5B. The areas where electrodes (e.g., source and drain) will be formed are set as light-transmitting areas, and the remaining areas are light-non-transmitting areas. Then, after the coated photoresist is hardened, the photoresist in the light-transmitting areas is activated by shining light on the light-shielding plate, and the photoresist in the light-transmitting areas is removed to form source bonding pad openings and drain bonding pad openings.

[0141] It should be noted that all photoresists mentioned in the specific implementation of the embodiments of this application are positive photoresists. That is, the photoresists are activated after irradiation, and the activated photoresists are then removed. It is true that in actual processing, negative photoresists may be used instead. It should be noted that negative photoresists are not activated after irradiation, but are activated in the absence of irradiation. Therefore, when negative photoresists are used, the light-transmitting and non-light-transmitting areas of the light-shielding plate in the drawings need to be swapped. Specifically, the original light-transmitting areas become non-light-transmitting areas, and the original non-light-transmitting areas become light-transmitting areas, and other processes remain unchanged. Both the method using positive photoresist and the method using negative photoresist are within the scope of protection of the embodiments of this application.

[0142] S22: Donor impurities are implanted through the source bonding pad opening and the drain bonding pad opening to form doped regions after activation.

[0143] Donor impurities can be implanted through the source and drain bond pad openings using an ion implantation process. The donor impurities can be, for example, silicon ions, and the donor impurities can be a single element or a mixture of elements. The implantation of the donor impurities can reduce the resistivity of the ohmic contact resistance between the source 45 and drain 46 and the barrier layer 43, and can also reduce the resistivity of the barrier layer 43.

[0144] S23: Remove the photoresist and activate the donor impurity carriers by using an annealing process to form an N-type doped region.

[0145] Indeed, the implanted donor impurity carriers may alternatively be activated by using an annealing process in other subsequent film layer fabrication.

[0146] S24: Next, a photoresist is prepared to cover the laminated semiconductor layer, and photoetching is performed to form a source bonding pad opening in the region where the source 45 is to be formed, and a drain bonding pad opening in the region where the drain 46 is to be formed.

[0147] S25: A metal film is formed over the photoresist, and the metal film fills the source bonding pad opening and the drain bonding pad opening.

[0148] For example, the metal film can be manufactured by using a metal deposition process, a sputtering process, an evaporation process, or an electroplating process.

[0149] S26: The photoresist is removed, leaving the source 45 located in the source bonding pad opening and the drain 46 located in the drain bonding pad opening.

[0150] The material of the source 45 and the drain 46 may be a single material, an alloy, or a multi-layered metal.

[0151] In some embodiments, the work function of the material of source 45 and drain 46 is in the range of 4.3 eV to 6 eV.

[0152] For example, the material of the source 45 and the drain 46 includes at least one of the following elements: titanium (Ti, work function 4.33 eV), gold (Au, work function 5.1 eV), and platinum (Pt, work function 5.65 eV). For example, the material of the source 45 and the drain 46 includes titanium nitride.

[0153] In some embodiments, the material of the source 45 and drain 46 does not include the element aluminum (Al).

[0154] In some embodiments, the source 45 and the drain 46 include at least one conductive layer.

[0155] For example, the source 45 and the drain 46 include a conductive layer, and the material of the conductive layer may include elements such as titanium, gold, platinum, etc. The source 45 and the drain 46 have a single-layer structure, which allows for a simple manufacturing process and high production efficiency.

[0156] Alternatively, for example, source 45 and drain 46 may include multiple conductive layers, each of which may be made of the same or different materials.

[0157] The source 45 and drain 46 may include multiple conductive layers, blending the properties of different materials together to tune the stress and resistivity of the source 45 and drain 46. The source 45 and drain 46 may further include conductive layers that act as diffusion barriers between multiple metal layers, thereby avoiding damage to the HEMT device caused by volume expansion of the source 45 and drain 46.

[0158] In some embodiments, when the source 45 and the drain 46 include one conductive layer, the material of the conductive layer can include, for example, elemental titanium.

[0159] In the case where the source 45 and the drain 46 include multiple conductive layers, the source 45 is used as an example. For example, the source 45 includes a first conductive layer and a second conductive layer stacked in order. The first conductive layer includes titanium elements, and the second conductive layer includes gold elements. The first conductive layer contacts the barrier layer 43 and is connected to the barrier layer 43.

[0160] Titanium elements are disposed on the surface of the stacked semiconductor layer (e.g., barrier layer 43), which serves both a conductive function and an adhesive function, improving the effectiveness of the connection of the source 45 and drain 46 to the stacked semiconductor layer.

[0161] After comprehensively considering the stress and resistivity of the source 45 and the drain 46, in some embodiments, the thickness of each conductive layer of the source 45 and the drain 46 is in the range of 1 nm to 10,000 nm. For example, the thickness of the conductive layer is 100 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, or 9000 nm.

[0162] Certainly, the thicknesses of the conductive layers may be equal or unequal, which is not limited in this embodiment of the present application and may be appropriately set as needed.

[0163] By appropriately setting the film thickness of each conductive layer, it is possible to reduce the resistance of the source 45 and the drain 46 without the need to provide an auxiliary electrode. The structure is simple, the number of process steps is small, and manufacturing efficiency is high.

[0164] As shown in FIG. 5B, the source 45 and the drain 46 are disposed on the surface of a laminated semiconductor layer (for example, the barrier layer 43), and the source 45 is the conductive structure closest to the laminated semiconductor layer (for example, the barrier layer 43).

[0165] Alternatively, this can be understood as the source 45 and drain 46 being the first layer of a conductive structure disposed on a stacked semiconductor layer (e.g., barrier layer 43), with no other conductive structure disposed between the source 45 and drain 46.

[0166] In some embodiments, the source 45 is of a planar structure, as shown in FIG. 5B.

[0167] Alternatively, this is understood as no structures, such as openings or hollow patterns, are arranged in the source 45 .

[0168] The planar structure of the source 45 simplifies the structure and the manufacturing process, and there is no need to consider how to interconnect the multiple strip structures after the source 45 is divided into structures including multiple strip patterns by providing openings in the source 45.

[0169] S30: As shown in FIG. 5C, a gate 49 is formed between the source 45 and the drain 46.

[0170] The material of the gate 49 may be, for example, a metal having a high work function, such as nickel (Ni, work function 4.6 eV), gold, or the like. The gate 49 is disposed on the barrier layer 43 and forms a Schottky contact with the barrier layer 43.

[0171] In some embodiments, as shown in FIG. 5C, step S30 includes the following steps.

[0172] S31: A first dielectric layer 47 is formed on the source 45 and the drain 46.

[0173] The material of the first dielectric layer 47 may be an insulating dielectric, such as silicon nitride, silicon oxide, or aluminum oxide. The thickness of the first dielectric layer 47 may be in the range of 10 nm to 200 nm. For example, the thickness of the first dielectric layer 47 is 50 nm, 100 nm, or 150 nm.

[0174] For example, first dielectric layer 47 may be formed by using a process such as plasma enhanced chemical vapor deposition, atomic layer deposition, or low pressure chemical vapor deposition.

[0175] 5C, the first dielectric layer 47 formed in step S31 may expose the source 45 and the drain 46. Alternatively, the first dielectric layer 47 formed in step S31 may cover the source 45 and the drain 46. Then, patterning is performed in another subsequent step to expose the source 45 and the drain 46.

[0176] S32: Form a gate bonding pad opening 48 in the first dielectric layer 47.

[0177] The method for forming the gate bonding pad opening 48 is as follows: For example, a photoresist may be formed on the first dielectric layer 47 as a mask to expose the gate bonding pad opening 48. An etching process (dry etching or wet etching) is used to form the gate bonding pad opening 48. The photoresist is removed.

[0178] If the first dielectric layer 47 exposes the source 45 and the drain 46, the process of forming the gate bond pad opening 48 in the first dielectric layer 47 can be completed simultaneously with the process of exposing the source 45 and the drain 46 on the first dielectric layer 47. Alternatively, the two processes can be completed in a few steps.

[0179] The size of the gate bond pad opening 48 limits the size of the gate 49 that is formed. In some embodiments, the gate bond pad opening 48 is a trench. The width of the trench is in the range of 10 nm to 1000 nm. For example, the width of the trench is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm.

[0180] S33: Form gate 49.

[0181] The process for forming gate 49 can be, for example, the same as the process for forming source 45 and drain 46. See above. Gate bond pad opening 48 in first dielectric layer 47 is located between source 45 and drain 46, and the ultimately formed gate 49 is also located between source 45 and drain 46.

[0182] It should be noted that in this embodiment of the present application, as shown in the above process, the source 45 and the drain 46 can be formed first simultaneously, and then the gate 49 is formed. Alternatively, the gate 49 may be formed first, and then the source 45 and the drain 46 are formed simultaneously. Alternatively, the source 45, the drain 46, and the gate 49 may be formed simultaneously.

[0183] S40: As shown in FIG. 5D, a field plate (FP) 51 is formed.

[0184] The material of the field plate 51 can be any conductive material. The field plate 51 is disposed on the side of the gate 49 away from the substrate 41 and overlies the region between the gate 49 and the drain 46. The orthogonal projection of the field plate 51 onto the substrate 41 overlaps with the orthogonal projection of the gate 49 onto the substrate 41.

[0185] In some embodiments, as shown in FIG. 5D, step S40 includes the following steps.

[0186] S41: A second dielectric layer 50 is formed.

[0187] The material of the second dielectric layer 50 may be an insulating dielectric such as silicon nitride, silicon oxide, or aluminum oxide. The thickness of the second dielectric layer 50 may be in the range of 50 nm to 1000 nm. For example, the thickness of the second dielectric layer 50 is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm.

[0188] For example, the second dielectric layer 50 may be formed by using a process such as plasma enhanced chemical vapor deposition, atomic layer deposition, or low pressure chemical vapor deposition.

[0189] 5D, the second dielectric layer 50 formed in step S41 may expose the source 45 and the drain 46. Alternatively, the second dielectric layer 50 formed in step S41 may cover the source 45 and the drain 46. Then, patterning is performed in another subsequent step to expose the source 45 and the drain 46.

[0190] S42: Form the field plate 51.

[0191] The method for forming the field plate 51 may be the same as the method for forming the source 45 and the drain 46. See above.

[0192] The field plate 51 can be floating and not loaded with any signal. Alternatively, the field plate 51 may contact the source 45, and the field plate 51 may also contact the gate 49.

[0193] An electric field peak is likely to occur at the position of the gate 49. Therefore, the electric field distribution in the HEMT device can be adjusted by placing a field plate 51 on the gate 49. This makes it possible to make the electric field distribution uniform, and electric field peaks are avoided.

[0194] S50: As shown in FIG. 5E, a thickened source 52 and a thickened drain 53 are formed.

[0195] The thickened source 52 is disposed on the source 45, in contact with the source 45, and connected to the source 45. The thickened drain 53 is disposed on the drain 46, in contact with the drain 46, and connected to the drain 46.

[0196] The material of the thickened source 52 and the thickened drain 53 is not limited and may be the same as or different from the material of the source 45 and the drain 46. The method for manufacturing the thickened source 52 and the thickened drain 53 may also be the same as the method for manufacturing the source 45 and the drain 46. Please refer to the related descriptions above.

[0197] The thickness of the thickened source 52 and the thickened drain 53 may be, for example, in the range of 500 nm to 10,000 nm, for example, 1,000 nm, 2,000 nm, 3,000 nm, 4,000 nm, 5,000 nm, 6,000 nm, 7,000 nm, 8,000 nm, or 9,000 nm.

[0198] The thickened source 52 and the thickened drain 53 are provided, which is equivalent to increasing the thickness of the source 45 and the drain 46 and decreasing the resistance of the source 45 and the drain 46, thereby improving the current-carrying capability of the semiconductor device. However, it should be noted that the size of the thickened source 52 and the thickened drain 53 does not have to be the same as the size of the source 45 and the drain 46, and may be larger or smaller than the size of the source 45 and the drain 46, all of which can improve the current-carrying capability.

[0199] S60: Deposit a peripheral passivation or waterproof layer over the device.

[0200] Specifically, a passivation layer (comprising a dielectric material) or a waterproof layer (comprising a waterproof material) is wrapped around the device to protect it.

[0201] S70: Form a backside via 54 under the source 45, as shown in FIG. 5F.

[0202] The backside via 54 penetrates the region from the substrate 41 to the barrier layer 43 below the source 45. Alternatively, this can be understood as the backside via 54 penetrating from the backside of the substrate 41 on the side farther from the channel layer 42 to the surface of the source 45 on the side closer to the substrate 41. In other words, the backside via 54 penetrates the laminated semiconductor layers on the substrate 41 to reach the surface of the source 45 on the side closer to the substrate 41.

[0203] In some embodiments, as shown in FIG. 5F, step S70 includes the following steps.

[0204] S71: The back surface of the substrate 41 is thinned.

[0205] After the front side processing of the substrate 41 is completed, it is necessary to perform backside processing of the substrate 41 to perform the connection from the source 45 through the device to the backside. After the front side processing of the substrate 41 is completed, the requirement for the support strength of the substrate 41 is reduced. Therefore, the substrate 41 can be thinned first before forming the backside via 54 in the substrate 41. This can reduce the difficulty of forming the backside via 54. Also, the thickness of the semiconductor device that is finally formed can be reduced.

[0206] In some embodiments, the thickness of the thinned substrate 41 is in the range of 10 μm to 500 μm, for example, the thickness of the thinned substrate 41 is 100 μm, 200 μm, 300 μm, or 400 μm.

[0207] S72: A via is formed from the back surface of the substrate 41 to the film layer above the source 45 on the substrate 41 side, forming a back surface via 54.

[0208] The film layer on the source 45 on the substrate 41 side may be the substrate 41 and a laminated semiconductor layer disposed on the substrate 41 .

[0209] For example, first, photoresist is coated on the backside of the substrate 41. A mask plate is used to expose the photoresist. The photoresist is developed, and the photoresist is used as a mask to expose the area where the backside via 54 will be formed. A dry or wet etching process is used to create a via in the film layer above the source 45 on the substrate 41 side to form the backside via 54. The photoresist is then removed.

[0210] Certainly, other mask layers, such as metal mask layers or dielectric mask layers, may be used as hole masks. Also, when stacked semiconductor layers on the substrate 41 are etched, the substrate 41 may be used as a mask.

[0211] In order to reduce the manufacturing difficulty of the backside via 54 and the subsequent back metal layer, the width of the backside via 54 can be set large, and may even be equal to the width of the source 45. The size of the backside via 54 is not limited in this embodiment of the present application, and can be appropriately selected after comprehensively considering factors such as the process.

[0212] S73: The etching by-products 55 remaining in the backside via 54 are removed by dry etching or wet etching.

[0213] The photoresist may be removed in step S72 or after step S73.

[0214] The etching solution for the wet etch may include, for example, solutions such as hydrochloric acid, nitric acid, potassium hydroxide (KOH), or tetramethylammonium hydroxide (TMAH).

[0215] S80: As shown in FIG. 5G, a backside conductive layer 56 is formed on the backside of the substrate 41, and the backside conductive layer 56 contacts and is connected to the source 45 through the backside via 54.

[0216] 5G, the backside conductive layer 56 covers the surface of the backside via 54 and the backside of the substrate 41. The source 45 is in direct contact with the backside conductive layer 56 and is connected to the backside conductive layer 56.

[0217] The material of the back conductive layer 56 may include, for example, gold and titanium gold. The thickness of the back conductive layer 56 may be, for example, within a range of 500 nm to 30,000 nm. The back conductive layer 56 may be manufactured by using, for example, an electroplating process, a vapor deposition process, or a sputtering process.

[0218] It should be noted that the method for manufacturing a semiconductor device provided in this embodiment of the present application is not limited to the steps described above, and other steps may be added or some of the steps may be removed as necessary. Furthermore, the order of the steps in the manufacturing method described above is merely an example and may be adjusted and replaced as necessary.

[0219] As shown in FIG. 6A , a semiconductor device manufactured using the above-described manufacturing method includes a substrate 41, a channel layer 42, and a barrier layer 43 sequentially stacked on the substrate 41. The channel layer 42 and the barrier layer 43 form a heterojunction, generating a two-dimensional electron gas 44 within the channel layer 42. A source 45 and a drain 46 are disposed on the surface of the barrier layer 43 and form ohmic contact with the barrier layer 43. The source 45 has a planar structure and is the conductive structure closest to the barrier layer 43. A gate 49 is disposed on the barrier layer 43, between the source 45 and the drain 46. A field plate 51 is disposed on the side of the gate 49 away from the substrate 41, between the gate 49 and the drain 46, and overlaps with the projection of the gate 49.

[0220] A backside via 54 is located under the source 45, and the backside via 54 penetrates from the backside of the substrate 41 farther from the channel layer 42 to the surface of the source 45 closer to the substrate 41. A backside conductive layer 56 is disposed on the backside of the substrate 41, and is in contact with and connected to the source 45 through the backside via 54.

[0221] 5G, the semiconductor device further includes a thickened source 52 and a thickened drain 53. The thickened source 52 is disposed on the source 45, in contact with the source 45, and connected to the source 45. The thickened drain 53 is disposed on the drain 46, in contact with the drain 46, and connected to the drain 46.

[0222] In some embodiments, as shown in FIG. 6B, the semiconductor device further includes a nucleation layer and a graded buffer layer sequentially arranged in a stacked manner between the substrate 41 and the channel layer 42, an insertion layer arranged between the channel layer 42 and the barrier layer 43, and a cap layer arranged on the surface of the barrier layer 43.

[0223] Depending on the different material of the cap layer, for example, the cap layer may be disposed between the source 45 and drain 46 and the barrier layer 43, as shown in FIG. 6B.

[0224] Alternatively, for example, as shown in FIG. 6C, openings exposing the source 45 and drain 46 are provided in the cap layer, and the source 45 and drain 46 are in direct contact with the barrier layer 43.

[0225] The operating principle of a HEMT device is as follows: The source 45 and drain 46 form separate conductive ohmic contacts with the barrier layer 43, and the gate 49 forms a Schottky contact with the barrier layer 43. The dashed line in the channel layer 42 represents the 2DEG 44, which is generated by polarization at the heterojunction formed by the channel layer 42 and the barrier layer 43 within the HEMT device. The 2DEG 44 is used to efficiently guide electrons under the application of an electric field. The source 45 and drain 46 are configured to allow the 2DEG 44 to flow within the channel layer 42 between the source 45 and drain 46 under the application of an electric field, and the 2DEG 44 within the channel layer 42 creates conduction between the source 45 and drain 46. The gate 49 is disposed between the source 45 and drain 46 and is configured to allow or block the passage of the 2DEG 44 to control the conduction or blocking of the HEMT device.

[0226] Note that after a HEMT device based on any of the above-described HEMT devices is used in an integrated circuit 31, in some embodiments, the back surface conductive layers 56 of multiple HEMT devices included in the integrated circuit 31 are in contact with and connected to each other. Alternatively, in some embodiments, in multiple HEMT devices included in the integrated circuit 31, the back surface conductive layers 56 of some of the HEMT devices are in contact with and connected to each other. Alternatively, in some embodiments, in multiple HEMT devices included in the integrated circuit 31, the back surface conductive layers 56 of those HEMT devices are independent from each other.

[0227] In this embodiment of the present application, the source 45 is in direct ohmic contact with the barrier layer 43, and a backside via 54 is located below the source 45. Thus, the backside via 54 is disposed below the source 45, and the backside conductive layer 56 is in direct contact with and connected to the source 45 through the backside via 54. A signal is directly conducted from the source 45 to the backside conductive layer 56, thereby shortening the transmission path to the source 45. This reduces the inductance of the semiconductor device and increases the frequency of the semiconductor device. In addition, the width of the backside via 54 can be appropriately set as required, and there is no need to further reduce the width of the backside via 54, thereby reducing the difficulty and yield of the manufacturing process of the backside via 54 and improving the yield and reliability of the backside conductive layer 56, thereby improving the yield and reliability of the semiconductor device. Therefore, the size of the device source 45 is reduced, thereby enabling small and low-cost semiconductor devices to be manufactured.

[0228] Optionally, in the process of manufacturing a semiconductor device, the material of the source 45 is selected as a metal (e.g., titanium, gold, and platinum) or alloy containing elements with high work function and stable chemical properties, and no longer contains reactive metals such as aluminum, so that the source 45 can block the etching of the backside via and avoid corrosion in the wet processing of the backside via process.

[0229] Optionally, an alloy can be used or the process completed to prevent the source 45 from being corroded due to etching in the backside via 54 fabrication process.

[0230] As a result, even if the source 45 is touched during the backside via process, no damage will occur to the source 45. Therefore, it is not necessary to specifically position the source 45 away from the backside via 54 to avoid corrosion caused by the backside via process, which reduces the size of the source 45 and the overall size of the semiconductor device.

[0231] Example 2

[0232] The difference between Example 2 and Example 1 is that the source 45 has an aperture.

[0233] As shown in FIG. 7A, the source 45 of the semiconductor device is no longer a planar structure but has an opening 451, which is located above the backside via .

[0234] The shape of the opening 451 is not limited, and the shape of the opening 451 in FIG. 7A is merely an example.

[0235] It can be understood that the source 45 has an opening 451 , but the placement of the opening 451 should not affect the signal transmission on the source 45 .

[0236] In some embodiments, as shown in FIG. 7A, the source 45 has an opening 451, but the source 45 is still an interconnected structure everywhere.

[0237] In some other embodiments, as shown in Figure 7B, openings 451 in source 45 divide source 45 into multiple strip structures. As shown in Figure 7C (a cross-sectional view along direction C1-C2 in Figure 7B), the strip structures can be interconnected using, for example, thickened source 52. Specifically, each portion of source 45 contacts and is connected to thickened source 52, realizing interconnection between all portions of source 45.

[0238] 8, in some embodiments, the semiconductor device further includes a thickened source 52 and a thickened drain 53. The thickened source 52 contacts and is connected to the backside conductive layer 56 through the opening 451 in the source 45.

[0239] Regarding the structural relationship between the opening 451 and the backside via 54, in some embodiments, the width M1 of the opening 451 is equal to or less than the width M2 of the backside via 54.

[0240] Compared to the need for the width M1 of the opening 451 to be larger than the width M2 of the backside via 54, the width M1 of the opening 451 being equal to or smaller than the width M2 of the backside via 54 is equivalent to reducing the width M1 of the opening 451, and as a result, the width of the source 45 can be reduced.

[0241] Based on the structural relationship between the source 45 and the backside conductive layer 56 resulting from the structural relationship between the opening 451 and the backside via 54, in some embodiments, the backside conductive layer 56 is closer to the left side of the gate 49 and farther from the right side of the gate 49, and the left and / or right side of the backside conductive layer 56 contacts and is connected to the source 45.

[0242] In some embodiments, the left and right sides of the backside conductive layer 56 make precise, grazing contact with the source 45, as shown in FIG.

[0243] In other words, there is no gap between the left and right sides of the opening 451 and the backside via 54 .

[0244] In some other embodiments, the left side of the backside conductive layer 56 makes exact, grazing contact with the source 45, with a gap between the right side of the backside conductive layer 56 and the source 45, as shown in FIG. 9A.

[0245] In other words, there is no gap between the left side of the opening 451 and the backside via 54, and there is a gap between the right side of the opening 451 and the backside via 54.

[0246] In some other embodiments, the left side of the backside conductive layer 56 is bonded exactly to the source 45, with a gap between the right side of the backside conductive layer 56 and the source 45, as shown in FIG. 9B.

[0247] In other words, there is no gap between the left side of the opening 451 and the backside via 54, and there is a gap between the right side of the opening 451 and the backside via 54.

[0248] In some other embodiments, the left side of the backside conductive layer 56 is bonded to the source 45 and the right side of the backside conductive layer 56 makes exact grazing contact with the source 45, as shown in FIG. 9C.

[0249] In other words, there is no gap between the left and right sides of the opening 451 and the backside via 54 .

[0250] In some other embodiments, the right side of the backside conductive layer 56 makes exact, grazing contact with the source 45, with a gap between the left side of the backside conductive layer 56 and the source 45, as shown in FIG. 10A.

[0251] In other words, there is no gap between the right side of the opening 451 and the backside via 54, and there is a gap between the left side of the opening 451 and the backside via 54.

[0252] In some other embodiments, the right side of the backside conductive layer 56 is bonded exactly to the source 45, with a gap between the left side of the backside conductive layer 56 and the source 45, as shown in FIG. 10B.

[0253] In other words, there is no gap between the right side of the opening 451 and the backside via 54, and there is a gap between the left side of the opening 451 and the backside via 54.

[0254] In some other embodiments, the right side of the backside conductive layer 56 is bonded to the source 45 and the left side of the backside conductive layer 56 makes exact grazing contact with the source 45, as shown in FIG. 10C.

[0255] In other words, there is no gap between the left and right sides of the opening 451 and the backside via 54 .

[0256] In some other embodiments, the right side of the backside conductive layer 56 is bonded to the source 45 and the left side of the backside conductive layer 56 is bonded to the source 45, as shown in FIG.

[0257] In other words, there is no gap between the left and right sides of the opening 451 and the backside via 54 .

[0258] In this embodiment of the present application, a backside via 54 is disposed under the source 45. An opening 451 is disposed in the source 45, but the source 45 may not be corroded by etching in the manufacturing process of the backside via 54. That is, even if the source 45 is touched during the backside via process, no damage will occur to the source 45. Therefore, it is not necessary to set the opening of the source 45 larger than the size of the backside via to avoid corrosion caused by the backside via 54 process. In other words, the width M1 of the opening 451 is equal to or smaller than the width M2 of the backside via 54, and there is no gap between the left and / or right sides of the backside via 54 and the opening 451. That is, the left and / or right sides of the backside conductive layer 56 contact and are connected to the source 45. Therefore, the opening 451 is disposed in the source 45 as needed. However, the size of the opening 451 can be reduced, thereby reducing the size of the source 45 and avoiding an increase in the size of the semiconductor device.

[0259] Although the semiconductor device provided in the embodiment of this application is an HEMT device in the above example, the semiconductor device is not limited to being an HEMT device. The semiconductor device provided in the embodiment of this application may be any semiconductor device whose source needs to be grounded.

[0260] The above description is merely a specific implementation of this application, and the scope of protection of this application is not limited thereto. Any modifications or substitutions within the technical scope disclosed in this application will fall within the scope of protection of this application. Therefore, the scope of protection of this application is subject to the scope of protection of the claims.

Claims

1. A semiconductor device, A substrate; a channel layer and a barrier layer sequentially arranged on the substrate in a stacked manner; a source, a gate, and a drain disposed on the barrier layer; a backside via extending from the substrate to the barrier layer below the source; a backside conductive layer covering the backside via and the backside surface of the substrate, the source being in contact with the backside conductive layer and connected to the backside conductive layer; and the source material comprises at least one of the elements titanium, gold, and platinum; the source has an opening, the opening is located above the backside via, and the width of the opening is smaller than the width of the backside via; The semiconductor device further includes a thickening source disposed on a surface of the source, the thickening source contacting the backside conductive layer through the opening. Semiconductor devices.

2. 2. The semiconductor device of claim 1, wherein the work function of the material of the source is in the range of 4.3 eV to 6 eV.

3. The semiconductor device of claim 1 or 2, wherein the source comprises at least one conductive layer.

4. 4. The semiconductor device of claim 3, wherein the source comprises a first conductive layer and a second conductive layer stacked in order, the first conductive layer containing titanium elements, the second conductive layer containing gold elements, and the first conductive layer contacting and connected to the barrier layer.

5. 5. The semiconductor device of claim 3, wherein the thickness of each conductive layer is in the range of 1 nm to 10,000 nm.

6. The semiconductor device further comprises a field plate; the field plate is disposed on a side of the gate away from the substrate, is positioned between the gate and the drain, and overlaps with a projection of the gate; 6. The semiconductor device according to claim 1.

7. A power amplifier circuit comprising: a package structure; and a semiconductor device according to claim 1 , wherein the semiconductor device is packaged inside the package structure.

8. 10. An electronic device comprising: a power amplifier and an antenna, the power amplifier configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for external radiation, the power amplifier comprising the power amplifier circuit according to claim 7.

9. A method for manufacturing a semiconductor device, comprising: forming a channel layer and a barrier layer in sequence on a substrate, the channel layer and the barrier layer being arranged in a stacked manner; forming a source, a gate, and a drain on the barrier layer; forming a backside via below the source, the backside via penetrating from the substrate to the barrier layer below the source; forming a back surface conductive layer on the back surface of the substrate, the back surface conductive layer covering the back surface via and the back surface of the substrate, and the source being in contact with the back surface conductive layer and connected to the back surface conductive layer; Having that, the source material comprises at least one of the elements titanium, gold, and platinum; the source is formed to have an opening, the opening being located above the backside via, the width of the opening being smaller than the width of the backside via; The method further includes forming a thickened source on a surface of the source, the thickened source contacting the backside conductive layer through the opening. A method for manufacturing semiconductor devices.

10. forming a backside via under the source; creating a via in a film layer below the source by using a dry etching process from the backside of the substrate to form the backside via; removing etching by-products remaining in the vias by dry etching or wet etching; The method for manufacturing a semiconductor device according to claim 9, comprising:

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