semiconductor devices

Abstract

The semiconductor device includes a metal base, a wall, a lid, a semiconductor die, and at least one capacitor. The wall is disposed on the metal base with an opening inside the wall. The lid is disposed on the wall. The semiconductor die is disposed on the metal base. The semiconductor die is surrounded by a wall that is disposed in the opening. The capacitor is disposed on the wall. A first end of the capacitor is electrically connected to the semiconductor die and a second end of the capacitor is electrically connected to the metal base.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Existing transistor devices for cellular infrastructure, such as laterally diffused metal-oxide semiconductor (LDMOS) or gallium nitride (GaN), are facing increasing demands for higher operating power and bandwidth, both of which require transistor packaging sizes to increase to keep up with power demands.

[0003] U.S. Patent Application Publication No. 2006 / 0138654 discloses an example of a semiconductor device in which the heat dissipation characteristics of a package for accommodating a semiconductor die are improved. A semiconductor device used at microwave frequencies is configured in this way, and for example, a semiconductor die for amplifying high-frequency signals and various circuit boards connected to the semiconductor die are disposed within the package. The package is composed of a bottom plate for fixing the semiconductor die and the circuit board, a wall disposed around the bottom plate to enclose the semiconductor die and the circuit board, and a lid for covering an upper opening formed by the wall. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2006 / 0138654 Summary of the Invention

[0005] The present disclosure provides a semiconductor device. The semiconductor device includes a metal base, a wall, a lid, a semiconductor die, and at least one capacitor. The wall is disposed on the metal base and has an opening inside the wall. The lid is disposed on the wall. The semiconductor die is disposed on the metal base. The semiconductor die is surrounded by a wall that is disposed in the opening. The capacitor is disposed on the wall. A first end of the capacitor is electrically connected to the semiconductor die, and a second end of the capacitor is electrically connected to the metal base. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing the structure of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II shown in FIG. [Figure 3] FIG. 3 is an enlarged plan view showing the connection structure of the first capacitor of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the connection structure of the first capacitor taken along line IV-IV shown in FIG. [Figure 5] FIG. 5 is a perspective view showing the structure of a semiconductor device according to a modified example of the first embodiment of the present disclosure. [Figure 6] FIG. 6 is an enlarged perspective view showing the connection structure between the capacitor and the semiconductor die of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a perspective view showing the semiconductor device shown in FIG. 6 with a lid attached. [Figure 8] FIG. 8 is a perspective view showing the structure of a semiconductor device according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a perspective view showing the structure of the semiconductor device shown in FIG. 8 with a lid attached. [Figure 10] FIG. 10 is a plan view showing the structure of a semiconductor device of a comparative example. [Figure 11] FIG. 11 is a cross-sectional view of the semiconductor device shown in FIG. 10 taken along line XI-XI. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] To allow better compatibility to support higher bandwidths, external video bandwidth (VBW) leads are introduced to packages such as the package described in U.S. Patent No. 6,277,999. Traditionally, the core package has always been ceramic and only single-layered. Because ceramic has a high dielectric constant, the top metallization artwork has an immediate impact (negative impact in this example). This current approach has not previously been adopted in printed circuit board technology.

[0008] [Effects of this disclosure] According to the present disclosure, it is possible to reduce the amount of inductance that is ultimately formed as a series LC resonance.

[0009] [Description of the embodiments of the present disclosure]

[0013] Embodiments of the present disclosure will be listed and described. According to one aspect of the present disclosure, a semiconductor device is provided, including a metal base, a wall, a lid, a semiconductor die, and at least one capacitor. The wall is disposed on the metal base and has an opening inside the wall. The lid is disposed on the wall. The semiconductor die is disposed on the metal base. The semiconductor die is surrounded by a wall disposed in the opening. The capacitor is disposed on the wall. A first end of the capacitor is electrically connected to the semiconductor die, and a second end of the capacitor is electrically connected to the metal base.

[0010] In the semiconductor device described above, the capacitor is disposed on the wall, with a first end of the capacitor electrically connected to the semiconductor die and a second end of the capacitor electrically connected to the metal base. Therefore, in this embodiment, the length of the wire bond connecting the semiconductor die and the capacitor is reduced. As a result, in this embodiment, the amount of inductance ultimately formed as a series LC resonance is reduced. Furthermore, this embodiment does not affect the characteristics of the capacitor. As a result, the circuit performance of the semiconductor device can be improved.

[0011] In one embodiment, the semiconductor device may further include a first upper pattern disposed on the wall and a second upper pattern disposed on the wall. The first upper pattern may electrically connect a first end of the capacitor to the semiconductor die. The second upper pattern may electrically connect a second end of the capacitor to the metal base. In this embodiment, the wall may have a protrusion on an inner side of the wall. The first upper pattern may include a region provided on the protrusion of the wall, and the region of the first upper pattern may be electrically connected to a drain pad of the semiconductor die by a wire. Therefore, in this embodiment, the length of the wire bond connecting the semiconductor die and the capacitor is further reduced. As a result, in this embodiment, the amount of inductance ultimately formed as a series LC resonance is further reduced, improving the circuit performance of the semiconductor device.

[0012] In one embodiment, the semiconductor device may further include a third upper pattern and a fourth upper pattern disposed on the wall. The third upper pattern may be electrically connected to the first upper pattern. The fourth upper pattern may be electrically connected to the second upper pattern and may be electrically connected to the metal base through a via hole.

[0013] In one embodiment, the semiconductor device may further include a frame disposed on the wall. The frame may include a first upper pattern, a first lower pattern, and a dielectric sandwiched between the first upper pattern and the first lower pattern. In this embodiment, the first upper pattern may be electrically connected to a first end of the capacitor by solder or a conductive adhesive. The solder may be made of gold-tin (AuSn) alloy solder paste or silver solder paste. The conductive adhesive may be made of silver-filled epoxy or low-temperature indium film. The first lower pattern may be electrically connected to the first upper pattern by a first via hole penetrating the dielectric, or may be electrically connected to the semiconductor die by a wire.

[0014] In the above embodiment, the frame may further include a second upper pattern and a second lower pattern. The second upper pattern and the second lower pattern may sandwich a dielectric therebetween. In this semiconductor device, the second upper pattern may be electrically connected to a second end of the capacitor by solder or a conductive adhesive, and the second lower pattern may be electrically connected to the second upper pattern by a second via hole penetrating the dielectric and may be connected to the metal base. The solder may be made of gold-tin (AuSn) alloy solder paste or silver solder paste. The conductive adhesive may be made of silver-filled epoxy or low-temperature indium film.

[0015] In one embodiment, the metal base may be made of a material with a high thermal conductivity of 50 W / (m·K) or more, which may be copper or a copper alloy, and the wall may be made of glass microfiber reinforced resin or fluororesin.

[0016] In one embodiment, the semiconductor die may include a substrate and a nitride semiconductor layer disposed on a surface of the substrate.

[0017] In one embodiment, the semiconductor device may further include an impedance matching circuit disposed on the metal base. The impedance matching circuit may be surrounded by a wall and connected to the semiconductor die. In this semiconductor device, a lid may cover the semiconductor die and the impedance matching circuit.

[0018] In one embodiment, the at least one capacitor may include a first capacitor and a second capacitor, wherein the first capacitor may be disposed on a first side of the wall and the second capacitor may be disposed on a second side of the wall opposite the first side.

[0019] In one embodiment, the lid may cover a capacitor located on the wall.

[0020] In one embodiment, the semiconductor die may include a first semiconductor die and a second semiconductor die, and the opening may include a first opening and a second opening, and in the semiconductor device, the first semiconductor die may be disposed within the first opening and the second semiconductor die may be disposed within the second opening.

[0021] In one embodiment, the semiconductor device may further include a first impedance matching circuit and a second impedance matching circuit. The lid may include a first lid and a second lid. In this semiconductor device, the first lid covers the first semiconductor die and the first impedance matching circuit disposed inside the first opening, and the second lid No. 2 The second semiconductor die and the second impedance matching circuit may be covered and disposed within the opening.

[0022] In one embodiment, the lid may include a first lid and a second lid, and the at least one capacitor may include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. In this semiconductor device, the first lid may cover the first capacitor and the second capacitor, and the second lid may cover the third capacitor and the fourth capacitor.

[0023] In one embodiment, the semiconductor device may further include a first impedance matching circuit and a second impedance matching circuit, and the lid may cover the first semiconductor die, the second semiconductor die, the first impedance matching circuit, and the second impedance matching circuit.

[0024] In one embodiment, the at least one capacitor may include a first capacitor and a second capacitor disposed on the wall, and a lid may cover the first capacitor and the second capacitor.

[0025] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices according to the present disclosure will be described below with reference to the drawings. The present invention is not limited to these examples, but is defined by the claims, and is intended to include equivalents to the claims and all modifications within the scope of the claims. In the following description, the same components in the drawings will be designated by the same reference numerals, and duplicated descriptions will be omitted.

[0026] [First embodiment] Fig. 1 is a plan view showing the structure of a semiconductor device according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view of the semiconductor device taken along line II-II shown in Fig. 1. As shown in Figs. 1 and 2, a semiconductor device 10 having a package for accommodating a semiconductor die includes a metal base 11, a lid 12, a first lead 13, a second lead 14, an impedance matching circuit 15, a semiconductor die 16, a wall 20, a first capacitor 30, and a second capacitor 40.

[0027] The metal base 11 has a rectangular planar shape and is made of a metal such as copper or a copper alloy. The metal base 11 may be made of a material with a high thermal conductivity of 50 W / (m·K) or more. The metal base 11 may have a thickness of 1.05 mm or more. The metal base 11 includes an upper surface 11a and a back surface pattern 11b.

[0028] The wall 20 is a substantially rectangular frame-like member made of a dielectric material such as resin and is disposed on the metal base 11. The wall 20 has an opening 20a formed therein. The wall 20 includes a first side 21, a second side 22, a third side 23, and a fourth side 24. The first side 21 faces the second side 22, and the third side 23 faces the fourth side 24. The impedance matching circuit 15 and the semiconductor die 16 are disposed within the opening 20a defined by the first side 21 to the fourth side 24. The first side 21 further includes a protrusion 25 extending toward the semiconductor die 16, and the second side 22 further includes a protrusion 26 extending toward the semiconductor die 16. The wall 20 may be made of, for example, glass microfiber reinforced resin or fluororesin.

[0029] The lid 12 is disposed on the wall 20 to cover the impedance matching circuit 15 and the semiconductor die 16. The lid 12 is made of a metal such as aluminum oxide (AlO). The lid 12 may cover the first capacitor 30 and the second capacitor 40, as well as the impedance matching circuit 15 and the semiconductor die 16.

[0030] The first lead 13 and the second lead 14 are made of metal plate-like members, and may be made of, for example, a thin metal plate made of copper, a copper alloy, or an iron alloy. One end of the first lead 13 is joined to the upper surface 23a of the third side portion 23 of the wall 20. The first lead 13 is insulated from the main surface 11a of the metal base 11 by the third side portion 23 of the wall 20. One end of the second lead 14 is joined to the upper surface 24a of the fourth side portion 24 of the wall 20. The second lead 14 is insulated from the main surface 11a of the metal base 11 by the fourth side portion 24 of the metal wall 20.

[0031] The impedance matching circuit 15 matches the impedance between the first lead 13 and the semiconductor die 16. One end of the impedance matching circuit 15 is electrically connected to the first lead 13 via a bonding wire 17. The other end of the impedance matching circuit 15 is electrically connected to the gate electrode of the semiconductor die 16 via a bonding wire 18. As a result, the first lead 13 is electrically connected to the gate electrode of the semiconductor die 16 via the impedance matching circuit 15. The impedance matching circuit 15 is disposed on the surface 11a of the metal base 11 and fixed to the metal base 11 with an adhesive.

[0032] The semiconductor die 16 is a transistor for amplifying high-frequency signals. The semiconductor die 16 may be, for example, a transistor including a substrate and a nitride semiconductor layer, which is a layer epitaxially grown on the surface of the substrate. Examples of the substrate include a Si substrate and a SiC substrate. The nitride semiconductor layer is, for example, a GaN layer. The semiconductor die 16 is disposed on the surface 11a of the metal base 11 and fixed to the metal base 11 with an adhesive. The semiconductor die 16 is surrounded by a wall 20 so as to be disposed within the opening 20a. A gate electrode of the semiconductor die 16 is connected to the impedance matching circuit 15, and a source electrode of the semiconductor die 16 is connected to the second lead 14. A drain electrode of the semiconductor die 16 is connected to a first capacitor 30 and a second capacitor 40.

[0033] The first capacitor 30 includes a first electrode 31, a second electrode 32, and a dielectric 33. The dielectric 33 is made of ceramic and is sandwiched between the first electrode 31 and the second electrode 32. The first electrode 31 is connected to the semiconductor die 16, and the second electrode 32 is connected to the metal base 11 and grounded. The first capacitor 30 is disposed on the first side 21 of the wall 20. The second capacitor 40 includes a first electrode 41, a second electrode 42, and a dielectric 43. The dielectric 43 is made of ceramic and is sandwiched between the first electrode 41 and the second electrode 42. The first electrode 41 is connected to the semiconductor die 16, and the second electrode 42 is connected to the metal base 11 and grounded. The second capacitor 40 is disposed on the second side 22 of the wall 20. Each of the first capacitor 30 and the second capacitor 40 can be a chip capacitor instead of the vertically mounted capacitor of the comparative example described below. The first capacitor 30 and the second capacitor 40 can also be a surface mount (SMD) ceramic capacitor with a size of 0805 (2012 metric) or smaller.

[0034] Next, the connection structure of the first capacitor 30 will be described in detail with reference to FIGS. 3 and 4. The connection structure of the second capacitor 40 is similar to that of the first capacitor 30, and therefore a duplicated description will be omitted. FIG. 3 is an enlarged plan view showing the connection structure of the first capacitor 30 of the semiconductor device 10. FIG. 4 is a cross-sectional view showing the connection structure of the first capacitor 30 taken along line IV-IV in FIG. 3. As shown in FIGS. 3 and 4, in the connection structure S1, a first substrate 34 and a second substrate 35 are provided on the first side portion 21 of the wall 20. The first substrate 34 and the second substrate 35 are insulated from each other.

[0035] The first substrate 34 includes a first upper pattern 34a, a first lower pattern 34b, and a first dielectric 34c. The first upper pattern 34a is disposed on the upper surface of the first dielectric 34c, and the first lower pattern 34b is disposed on the lower surface of the first dielectric 34c. A signal via 34d is disposed within the first dielectric 34c, penetrating the first dielectric 34c and electrically connecting the first upper pattern 34a and the first lower pattern 34b. The first upper pattern 34a is a single layer and is electrically connected to the first electrode 31 of the first capacitor 30 by solder or a conductive adhesive. The first lower pattern 34b is attached to a third upper pattern 36a, which is disposed on the upper surface 21a of the first side portion 21, by solder or a conductive adhesive. The first upper pattern 34a, the first lower pattern 34b, and the third upper pattern 36a are made of copper, gold, or the like. The solder may be made of gold-tin (AuSn) alloy solder paste or silver solder paste, and the conductive adhesive may be made of silver-filled epoxy or low-temperature indium film.

[0036] The second substrate 35 includes a second upper pattern 35a, a second lower pattern 35b, and a second dielectric 35c. The second upper pattern 35a is provided on the upper surface of the second dielectric 35c, and the second lower pattern 35b is provided on the lower surface of the second dielectric 35c. A via 35d is provided in the second dielectric 35c, penetrating the second dielectric 35c and connecting the second upper pattern 35a and the second lower pattern 35b. The second upper pattern 35a is connected to the second electrode 32 of the first capacitor 30 by solder or conductive adhesive. The second lower pattern 35b is attached to a fourth upper pattern 36b, which is disposed on the upper surface 21a of the first side portion 21, by solder or conductive adhesive. The fourth upper pattern 36b is connected to a third lower pattern 36c, which is disposed on the lower surface 21b of the first side portion 21 of the wall 20, by the via 36d. The lower surface 21b on which the third lower pattern 36c is disposed is adhered to the metal base 11 with a thermally and electrically conductive conductive adhesive film 38. The second upper pattern 35a, the second lower pattern 35b, the fourth upper pattern 36b, and the third lower pattern 36c are made of copper, gold, or the like.

[0037] In the connection structure S1 described above, the first capacitor 30 is located on the wall 20, so the first capacitor 30 and the first upper pattern 34a are disposed close to the semiconductor die 16. The first upper pattern 34a also has a region 34e provided on the semiconductor die 16 side of the protrusion 25 of the wall 20. The region 34e is connected to the drain pad 16a extending from the drain electrode of the semiconductor die 16 by a wire 37. Therefore, the length of the wire 37 connected between the first upper pattern 34a (region 34e) and the drain pad 16a extending from the drain electrode of the semiconductor die 16 is shorter than the length of the wire directly connected between the drain electrode of the semiconductor die 16 and the first electrode 31 of the first capacitor 30. The first upper pattern 34a is closer to the electrode of the semiconductor die 16 than the second upper pattern 35a. The second upper pattern 35a is electrically connected to the metal base 11 of the package by via holes 35d and 36d.

[0038] In this semiconductor device 10, the VBW signal is connected by a wire bond from the drain terminal of the active transistor die (semiconductor die 16) to one end of the first capacitor 30 and / or the other end of the second capacitor 40, with the other end of the first capacitor 30 and / or the other end of the second capacitor 40 being grounded, so that these capacitors can act as short circuits for these VBW frequencies.

[0039] The useful effects obtained by the semiconductor device 10 of this embodiment configured as described above will be described in comparison with a comparative example shown in FIGS. 10 and 11 . FIG. 10 is a plan view showing the structure of the semiconductor device of the comparative example. FIG. 11 is a cross-sectional view of the semiconductor device shown in FIG. 10 taken along line XI-XI. As shown in FIGS. 10 and 11 , a semiconductor device 510 according to the comparative example includes a metal base 511, a lid, a first lead 513, a second lead 514, an impedance matching circuit 515, a semiconductor die 516, a wall 520, a first capacitor 530, and a second capacitor 540. The first capacitor 530 and the second capacitor 540 are vertical capacitors and include an upper electrode, a lower electrode, and a dielectric between the upper electrode and the lower electrode. The first capacitor 530 and the second capacitor 540 are disposed on the metal base 511 and are located inside the wall 520. In semiconductor device 510, first capacitor 530 and second capacitor 540 are connected to semiconductor die 516 by wire 537 and wire 547, respectively. Wire 537 and wire 547 are longer than wire 37 and wire 47 of semiconductor device 10.

[0040] In the above embodiment, the length of the wire bonds is significantly reduced compared to the comparative example, which reduces the amount of inductance ultimately formed as a series LC resonance. Furthermore, this embodiment does not affect the characteristics of the capacitor, improving the circuit performance of the semiconductor device 10. The external VBW function enables large-capacity surface-mount capacitors, such as those rated at 100 V and 1 μF or more.

[0041] This embodiment offers the following additional advantages over the comparative example. First, the power amplifier layout can be designed with a smaller footprint and more compact design. This is primarily due to the lead width dimension. This embodiment is more than half the size of the lead width. Second, this embodiment allows for a wider isolation path between the primary leads, reducing interference. Third, this embodiment means that the power amplifier artwork / layout can be kept smaller because there is no requirement for an external VBW lead. Fourth, this embodiment can provide up to eight primary leads, thereby increasing the maximum available output power. Finally, this embodiment can provide the necessary termination for video frequencies (<1 GHz), which are often performed internally. In the comparative example, direct wire bonding to a vertically mounted capacitor requires significantly longer wirebonds, which is not easily realized. However, this embodiment allows for shorter wirebond lengths, making it easily realized.

[0042] [Modification of the first embodiment] Next, a modified example of the first embodiment of the present disclosure will be described with reference to FIGS. 5, 6, and 7. FIG. 5 is a perspective view showing the structure of a semiconductor device according to a modified example of the first embodiment of the present disclosure. FIG. 6 is an enlarged perspective view showing the connection structure between a capacitor and a semiconductor die of the semiconductor device shown in FIG. 5. FIG. 7 is a perspective view showing the semiconductor device shown in FIG. 5 with a lid attached. As shown in FIGS. 5 to 7, a semiconductor device 110 of the modified example includes a metal base 11, a lid 12, a first lead 13, a second lead 14, an impedance matching circuit 15, a semiconductor die 16, a wall 20, a first capacitor 30, and a second capacitor 40. The impedance matching circuit 15 is made of ceramic such as aluminum oxide or aluminum nitride.

[0043] The semiconductor device 110 further includes a frame 130 and a frame 140 instead of the first dielectric 34c of the first substrate 34 and the second dielectric 35c of the second substrate 35. The frames 130 and 140 are made of a low-loss dielectric composite material (e.g., glass microfiber resin). The frame 130 is provided by commonly configuring the first dielectric 34c of the first substrate 34 and the second dielectric 35c of the second substrate 35. The first upper pattern 34a and the second upper pattern 35a are disposed on the upper surface of the frame 130. The frame 130 is provided over the entire surface of the first side portion 21 of the wall 20. Furthermore, the frame 140 is provided over the entire surface of the second side portion 22 of the wall on which the second capacitor 40 is disposed. The frame 140 is frame The frame 130 has the same function as the frame 130. The frame 130 and the frame 140 can be configured as one frame.

[0044] In this modification, the tip of the first lower pattern 34b is provided on the protruding portion 25 of the wall 20. The length of the wire 37 connected between the first lower pattern 34b and the extended portion of the drain electrode of the semiconductor die 16 is shorter than the length of the wire directly connected between the drain electrode of the semiconductor die 16 and the first electrode 31 of the first capacitor 30. The first lower pattern 34b is closer to the electrode of the semiconductor die 16 than the first upper pattern 34a. In this modification, the first upper pattern 34a is not provided on the protruding portion 25 of the wall 20. As a result, because the first upper pattern 34a does not extend toward the semiconductor die 16, solder for mounting the first capacitor 30 on the first upper pattern 34a is prevented from seeping into the package.

[0045] 7 , the semiconductor device 110 has a lid 12 disposed on the package wall 20. The lid 12 covers the impedance matching circuit 15 and the semiconductor die 16 enclosed by the wall 20. The lid 12 is in contact with a portion of the frame 130. In some examples, the lid 12 may cover the impedance matching circuit 15 and the semiconductor die 16 enclosed by the wall 20, and may also cover both the first capacitor 30 and the second capacitor 40 provided on the wall 20. In this embodiment, the lid 12 is in contact with a portion of the frame 130.

[0046] [Second embodiment] Next, a second embodiment of the present disclosure will be described with reference to FIGS. 8 and 9. FIG. 8 is a perspective view showing the structure of a semiconductor device according to the second embodiment of the present disclosure. FIG. 9 is a perspective view showing the structure of the semiconductor device shown in FIG. 8 with a lid attached. As shown in FIGS. 8 and 9, a semiconductor device 210 includes a metal base 211, a lid 12, a first lead 13, a second lead 14, an impedance matching circuit 15, a semiconductor die 16, a wall 220, a first capacitor 30, and a second capacitor 40. The connection structure of the first capacitor 30 and the connection structure of the second capacitor 40 of the semiconductor device 210 in this embodiment are similar to the connection structures of the first capacitor 30 and the second capacitor 40 of the semiconductor device 10 or 110, and therefore, redundant description will be omitted. The following description will mainly focus on the differences between the second embodiment and the first embodiment.

[0047] The wall 220 has a plurality of openings 220a, for example, two openings 220a in the drawing, inside the wall 220. As shown in Fig. 8, the semiconductor device 210 has an impedance matching circuit 15 and a semiconductor die 16 inside each opening 220a. The semiconductor device 210 also has a pair of a first capacitor 30 and a second capacitor 40 for each semiconductor die 16 provided in the opening 220a. In this embodiment, the first capacitor 30 and the second capacitor 40 are arranged on the wall 220 via a common frame 230.

[0048] The semiconductor device 210 includes a plurality of lids 12 provided on package walls 220. Each of the lids 12 covers the semiconductor die 16 and the impedance matching circuit 15 surrounded by the walls 220. The lids 12 are in contact with a portion of the frame 230. As another example, the lids 12 may cover the semiconductor die 16 and the impedance matching circuit 15 via the walls 220. The lids are in contact with a portion of the frame 230. The lids 12 may then cover the first capacitor 30 and the second capacitor 40 provided on the walls 220.

[0049] Although the semiconductor device according to the present embodiment has been described above, the present invention is not limited to this and various modifications are possible. [Explanation of symbols]

[0050] 10,110,210 Semiconductor Devices 11,211 Metal Base 12 Lid 13 Input Lead 14 Output Leads 15 Impedance matching circuit 16 Semiconductor Dies 16a Drain Pad 17, 18, 19 Wires 20,220 Wall 21 first side 22 Second Side 23 Third Side 24 Fourth Side 25,26 Protrusion 30 First capacitor 31,41 First electrode 32,42 Second electrode 33,43 Dielectric 34 First substrate 34a First upper pattern 34b First lower pattern 34c First dielectric 34d Signal via 34e area 35 Second board 35a Second upper pattern 35b Second Lower Pattern 35c Second Dielectric 35d Beer 36a Third upper surface 36b Fourth upper surface 36c Third lower surface 37 Wire 38 Conductive adhesive film 40 Second capacitor S1 Connection Structure

Claims

1. A metal base and a wall disposed on the metal base, the wall having an opening therein; a lid disposed on the wall; a semiconductor die disposed on the metal base and surrounded by the wall so as to be positioned within the opening; at least one capacitor disposed on an upper surface of the wall and outside the lid, the at least one capacitor including a first terminal and a second terminal; a semiconductor device, wherein the first terminal of the capacitor is electrically connected to the semiconductor die and the second terminal of the capacitor is electrically connected to the metal base; The semiconductor device is a first upper pattern disposed between the capacitor and the upper surface of the wall, the first upper pattern electrically connecting the first terminal of the capacitor to the semiconductor die; a second upper pattern disposed on the upper surface of the wall and electrically connecting the second terminal of the capacitor to the metal base; the wall has a metal pattern on an inner region of the wall; the first upper pattern includes the metal pattern of the wall; the metal pattern is electrically connected to a pad of the semiconductor die by a wire; the pad of the semiconductor die is a drain pad of the semiconductor die; Semiconductor devices.

2. a third upper pattern and a fourth upper pattern disposed on the wall; the third upper pattern is electrically connected to the first upper pattern, the fourth upper pattern is electrically connected to the second upper pattern and is electrically connected to the metal base through a via hole; The semiconductor device of claim 1 .

3. The metal base is made of a material with a high thermal conductivity of 50 W / (m·K) or more, The wall is made of glass microfiber reinforced resin or fluororesin.

3. The semiconductor device according to claim 1 or 2.

4. the high thermal conductivity material comprises copper or a copper alloy; The semiconductor device of claim 3 .

5. the semiconductor die includes a substrate and a nitride semiconductor layer disposed on a surface of the substrate; The semiconductor device according to any one of claims 1 to 4.

6. an impedance matching circuit disposed on the metal base, surrounded by the wall, and electrically connected to the semiconductor die; the lid covers the semiconductor die and the impedance matching circuit; The semiconductor device according to any one of claims 1 to 5.

7. the at least one capacitor includes a first capacitor and a second capacitor; the first capacitor is disposed on a first side of the wall; the second capacitor is disposed on a second side of the wall opposite the first side. The semiconductor device according to any one of claims 1 to 6.

8. the semiconductor die includes a first semiconductor die and a second semiconductor die, and the opening includes a first opening and a second opening; the first semiconductor die is disposed within the first opening and the second semiconductor die is disposed within the second opening; The semiconductor device according to any one of claims 1 to 7.

9. further comprising a first impedance matching circuit and a second impedance matching circuit; the lid includes a first lid and a second lid; the first lid covers the first semiconductor die and the first impedance matching circuit disposed within the first opening; the second lid covers the second semiconductor die and the second impedance matching circuit disposed within the second opening; The semiconductor device of claim 8.

10. the lid includes a first lid and a second lid, the at least one capacitor includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the first capacitor and the second capacitor are located outside the first lid, and the third capacitor and the fourth capacitor are located outside the second lid. The semiconductor device of claim 8.

11. further comprising a first impedance matching circuit and a second impedance matching circuit; the lid covers the first semiconductor die, the second semiconductor die, the first impedance matching circuit, and the second impedance matching circuit; The semiconductor device of claim 8.

12. the at least one capacitor includes a first capacitor and a second capacitor each disposed on the wall; the first capacitor and the second capacitor are located outside the lid; The semiconductor device of claim 8.

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