Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that comprises a diode region and an IGBT region and in which the diode region can have higher breakdown voltage than the IGBT region, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises: a transistor part 70; and a diode part 80. The transistor part 70 comprises: a first conductivity type semiconductor substrate 18; a second conductivity type first semiconductor region 14; a first conductivity type second semiconductor region 12; a gate insulation film 50; a gate electrode 51; a first conductivity type first semiconductor layer 20; a second conductivity type third semiconductor region 22; a first electrode 130; and a second electrode 24. The diode part 80 comprises: the semiconductor substrate 18; the first semiconductor region 14; the first semiconductor layer 20; a first conductivity type fourth semiconductor region 82; the first electrode 130; and the second electrode 24. Depth from a rear surface of the semiconductor substrate 18 of the first semiconductor layer 20 of the transistor part 70 is larger than depth from the rear surface of the semiconductor substrate 18 of the first semiconductor layer 20 of the diode part 80.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, power conversion circuits that convert DC to AC, DC to DC, or AC to AC voltage and current are used in a variety of fields, including industrial machinery, railway vehicles, electric vehicles, and power generation. To control these circuits, the functions of an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) connected in anti-parallel to the IGBT are used.

[0003] A reverse conducting IGBT (RC-IGBT) is known in which the IGBT and a FWD connected in anti-parallel to the IGBT are integrated on the same semiconductor substrate. - Inside the n-type drift layer, - In general, an n-type field stop (FS) layer having a higher impurity concentration than the n-type drift layer is formed.

[0004] A method for manufacturing a conventional RC-IGBT having an n-type FS layer will be described. FIGS. 26 to 28 are cross-sectional views showing a state during the manufacturing process of a conventional RC-IGBT having an n-type FS layer. First, a thick n-type FS layer that is usually used is shown. - On the front surface side of the n-type semiconductor substrate 118, a front surface element structure (not shown) such as a MOS gate (insulated gate made of metal-oxide-semiconductor), an interlayer insulating film, and a front surface electrode (electrode pad) is formed by a general method. - The mold semiconductor substrate 118 is ground from the back side until it reaches the thickness of the product to be used as a semiconductor device.

[0005] Next, n -After grinding the semiconductor substrate 118, phosphorus (P) or selenium (Se) is ion-implanted 200 from the rear surface thereof, and n - The inside of the back side of the n-type semiconductor substrate 118 is provided with an n-type semiconductor layer extending from the IGBT region to the diode region. + Then, the mold FS layer 120 is formed. The state up to this point is shown in FIG.

[0006] Next, n - Boron (B) ions are implanted 200 from the rear surface of the n-type semiconductor substrate 118. - The surface layer of the back surface of the n-type semiconductor substrate 118 + At a position shallower than the type FS layer 120, a p + This forms the mold collector region 122. The state up to this point is shown in FIG.

[0007] Next, by photolithography, - A resist mask 201 having an opening corresponding to the diode region is formed on the back surface of the semiconductor substrate 118. Next, using this resist mask 201 as a mask, - Phosphorus ions are implanted into the back surface of the n-type semiconductor substrate 118. - The p-type semiconductor substrate 118 has a surface layer on the back surface thereof, and the p-type semiconductor substrate 118 has a surface layer on the back surface thereof. + The collector region 122 is inverted to n-type to form n + This forms a mold cathode region 182. The state up to this point is shown in FIG.

[0008] Next, the resist mask 201 is removed by ashing. - The impurities ion-implanted into the n-type semiconductor substrate 118 are diffused by heat treatment. - A polyimide surface protection film is formed on the front surface of the semiconductor substrate 118. Next, a p + collector region 122 and n + A back electrode is formed in contact with the n-type cathode region 182. - The mold semiconductor substrate 118 is cut (diced) into individual chips to complete the conventional RC-IGBT.

[0009] Also known is a semiconductor device comprising: a first semiconductor layer of a first conductivity type provided in a first region; a second semiconductor layer of a second conductivity type provided in a second region; a fourth semiconductor layer of a second conductivity type provided on the first semiconductor layer and the second semiconductor layer; a fifth semiconductor layer of the first conductivity type provided on the fourth semiconductor layer; a sixth semiconductor layer of a second conductivity type provided in a part of the first region on the fifth semiconductor layer; a second electrode provided in the first region; and a third electrode provided in the second region, wherein at least one of the distance between the third semiconductor layer and the third electrode and the distance between the third semiconductor layer and the fifth semiconductor layer in the second region is shorter than the distance between the third semiconductor layer and the second electrode (see, for example, Patent Document 1 below).

[0010] Also, a semiconductor device is known in which an n-type FS layer is formed by irradiating the substrate with protons multiple times at different ranges from the rear surface side of the substrate to form first to fourth n-type layers at different depths, activating the protons, irradiating the substrate with helium from the rear surface at a position deeper than the range of the proton irradiation, introducing lattice defects, and forming a fifth n-type layer during heat treatment to adjust the amount of lattice defects (see, for example, Patent Document 2 listed below). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-139719 [Patent Document 2] International Publication No. 2017 / 047285 Summary of the Invention [Problem to be solved by the invention]

[0012] However, n + type FS layer 120, p + When the n-type collector region 122 is formed in this order, + The FS layer 120 is -The layer is formed at a uniform distance from the rear surface of the semiconductor substrate 118. In this case, a semiconductor device is manufactured in which the IGBT region and the diode region have the same breakdown voltage.

[0013] When the reverse recovery surge voltage increases due to faster switching speeds, a higher voltage is applied to the diode region than to the IGBT region. For this reason, if the IGBT region and the diode region have the same breakdown voltage, the diode region is more likely to break down first, which is a problem.

[0014] In order to solve the problems associated with the conventional technology described above, an object of the present invention is to provide a semiconductor device that includes a diode region and an IGBT region and that allows the diode region to have a higher breakdown voltage than the IGBT region, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a transistor section and a diode section. The transistor section includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate, a second semiconductor region of the first conductivity type selectively provided in a surface layer of the first semiconductor region on the side opposite to the semiconductor substrate side, a gate insulating film in contact with the first semiconductor region, a gate electrode provided on a surface of the gate insulating film opposite to the surface in contact with the first semiconductor region, a first semiconductor layer of the first conductivity type provided inside the semiconductor substrate, a third semiconductor region of a second conductivity type provided on the back surface side of the semiconductor substrate, a first electrode provided on surfaces of the first semiconductor region and the second semiconductor region, and a second electrode provided on a surface of the third semiconductor region. The diode section includes the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of a first conductivity type provided on a back surface side of the semiconductor substrate, the first electrode provided on a surface of the first semiconductor region, and the second electrode provided on a surface of the fourth semiconductor region. A depth of the first semiconductor layer of the transistor section from the back surface of the semiconductor substrate is greater than a depth of the first semiconductor layer of the diode section from the back surface of the semiconductor substrate.

[0016] In addition, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the first semiconductor layer in the transistor section is the same as the thickness of the first semiconductor layer in the diode section, and in the transistor section, the semiconductor substrate is present between the first semiconductor layer and the third semiconductor region.

[0017] Furthermore, the semiconductor device of the present invention is the above-described invention, characterized in that it comprises an active region comprising the transistor portion and the diode portion, through which current flows, and a termination structure portion arranged outside the active region and having a breakdown voltage structure surrounding the active region, the termination structure portion comprising the semiconductor substrate, the first semiconductor layer, the fourth semiconductor region, and the second electrode, and the depth of the first semiconductor layer of the diode portion from the back surface of the semiconductor substrate is the same as the depth of the first semiconductor layer of the termination structure portion from the back surface of the semiconductor substrate.

[0018] In the semiconductor device according to the present invention, the transistor section and the diode section are configured as follows in a top view: The transistor section and the diode section are included, and a current flows through the transistor section and the diode section. The transistors are characterized by being arranged in parallel within the active region.

[0019] Furthermore, to solve the above-mentioned problems and achieve the object of the present invention, a manufacturing method of a semiconductor device according to the present invention has the following features. This is a manufacturing method of a semiconductor device having a transistor portion and a diode portion. A first step of forming a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate is performed. Next, a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region opposite to the semiconductor substrate side is performed. Next, a third step of forming a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to the surface in contact with the first semiconductor region is performed in the transistor portion. Next, a fourth step of forming first electrodes on surfaces of the first semiconductor region and the second semiconductor region of the transistor portion and on a surface of the first semiconductor region of the diode portion is performed. Next, a fifth step of increasing the amount of crystal defects in a back surface layer of the semiconductor substrate corresponding to the diode portion is performed. Next, after the fifth step and before performing annealing, a sixth step is performed in which impurities of the first conductivity type are implanted from the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type. Next, a seventh step is performed in which a third semiconductor region of the second conductivity type is formed on the back surface of the semiconductor substrate corresponding to the transistor portion. Next, an eighth step is performed in which a fourth semiconductor region of the first conductivity type is formed on the back surface of the semiconductor substrate corresponding to the diode portion. Next, a ninth step is performed in which second electrodes are formed on the surfaces of the third semiconductor region and the fourth semiconductor region.

[0020] Moreover, in the method for manufacturing a semiconductor device according to the present invention, phosphorus (P) is used to form the first semiconductor layer.

[0021] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the method is carried out by ion implantation of argon (Ar), xenon (Xe) or silicon (Si) to make the amount of crystal defects in the back surface layer corresponding to the diode portion greater than the amount of crystal defects in the back surface layer corresponding to the transistor portion.

[0022] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. This method is for manufacturing a semiconductor device having a transistor portion and a diode portion. A first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. A second step is performed to selectively form a second semiconductor region of a first conductivity type in a surface layer of the first semiconductor region opposite the semiconductor substrate side. A third step is performed to form a gate insulating film in contact with the first semiconductor region and a gate electrode on the surface of the gate insulating film opposite the surface in contact with the first semiconductor region in the transistor portion. A fourth step is performed to form first electrodes on the surfaces of the first and second semiconductor regions of the transistor portion and on the surface of the first semiconductor region of the diode portion. A fifth step is performed to form a third semiconductor region of the second conductivity type by implanting impurities of the second conductivity type from the back surface side of the semiconductor substrate. A sixth step is performed to form a fourth semiconductor region of the first conductivity type by implanting impurities of the first conductivity type into the third semiconductor region corresponding to the diode portion. Next, after the sixth step and before performing annealing, a seventh step is performed in which an impurity of the first conductivity type is implanted from the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type, and an eighth step is performed in which second electrodes are formed on the surfaces of the third semiconductor region and the fourth semiconductor region.

[0023] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the impurity implanted in the fifth step is boron (B), and the impurity implanted in the sixth step is phosphorus (P) or arsenic (As).

[0024] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. This method is for manufacturing a semiconductor device having a transistor portion and a diode portion. First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region opposite the semiconductor substrate side. Next, a third step is performed to form a gate insulating film in contact with the first semiconductor region and a gate electrode on the surface of the gate insulating film opposite the surface in contact with the first semiconductor region in the transistor portion. Next, a fourth step is performed to form first electrodes on the surfaces of the first semiconductor region and the second semiconductor region in the transistor portion and on the surface of the first semiconductor region in the diode portion. Next, a fifth step is performed to form a third semiconductor region of the second conductivity type by implanting impurities of the second conductivity type from the back surface side of the semiconductor substrate. Next, a sixth step is performed in which laser annealing for activation of the third semiconductor region is performed with a laser annealing intensity for the third semiconductor region corresponding to the diode section being weaker than that for the third semiconductor region corresponding to the transistor section. Next, a seventh step is performed in which impurities of the first conductivity type are implanted from the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type. Next, an eighth step is performed in which impurities of the first conductivity type are implanted into the third semiconductor region corresponding to the diode section to form a fourth semiconductor region of the first conductivity type. Next, a ninth step is performed in which second electrodes are formed on the surfaces of the third semiconductor region and the fourth semiconductor region.

[0025] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. This method is for manufacturing a semiconductor device having a transistor section and a diode section. First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of a first conductivity type in a surface layer of the first semiconductor region opposite the semiconductor substrate side. Next, a third step is performed to form a gate insulating film in contact with the first semiconductor region and a gate electrode on the surface of the gate insulating film opposite the surface in contact with the first semiconductor region in the transistor section. Next, a fourth step is performed to form first electrodes on the surfaces of the first semiconductor region and the second semiconductor region in the transistor section and on the surface of the first semiconductor region in the diode section. Next, a fifth step is performed to form a third semiconductor region of the second conductivity type by implanting impurities of the second conductivity type from the back surface side of the semiconductor substrate. Next, a sixth step is performed to form a fourth semiconductor region of the first conductivity type by implanting impurities of the first conductivity type into the third semiconductor region corresponding to the diode section. Next, a seventh step is performed in which laser annealing is performed to activate the third semiconductor region and the fourth semiconductor region, with the intensity of the laser annealing for the fourth semiconductor region being weaker than the intensity of the laser annealing for the third semiconductor region. Next, an eighth step is performed in which impurities of the first conductivity type are implanted from the back side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type. Next, a ninth step is performed in which second electrodes are formed on the surfaces of the third semiconductor region and the fourth semiconductor region.

[0026] To solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate, a second semiconductor region of the first conductivity type selectively provided in a surface layer of the first semiconductor region on the side opposite to the semiconductor substrate side, a gate insulating film in contact with the first semiconductor region, and a gate electrode provided on a surface of the gate insulating film opposite to the surface in contact with the first semiconductor region. The semiconductor device further includes a first semiconductor layer of the first conductivity type provided inside the semiconductor substrate, a third semiconductor region of the second conductivity type provided on the back surface side of the semiconductor substrate, a first electrode provided on the surfaces of the first semiconductor region and the second semiconductor region, and a second electrode provided on the surface of the third semiconductor region. The depth of a predetermined region of the first semiconductor layer from the back surface of the semiconductor substrate is greater than the depth of a region other than the predetermined region of the first semiconductor layer from the back surface of the semiconductor substrate. an active region through which a current flows; and a termination structure portion disposed outside the active region and having a breakdown voltage structure surrounding the active region; the third semiconductor region is provided in the active region; The termination structure includes the semiconductor substrate, the first semiconductor layer, and the second electrode, and the depth of the first semiconductor layer of the active region from a rear surface of the semiconductor substrate is greater than the depth of the first semiconductor layer of the termination structure from a rear surface of the semiconductor substrate. The thickness of the third semiconductor region It's getting bigger.

[0027] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region opposite the semiconductor substrate side. Next, a third step is performed to form a gate insulating film in contact with the first semiconductor region and a gate electrode on the surface of the gate insulating film opposite the surface in contact with the first semiconductor region. Next, a fourth step is performed to form a first electrode on the surfaces of the first semiconductor region and the second semiconductor region. Next, a fifth step is performed to form a third semiconductor region of the second conductivity type by implanting impurities of the second conductivity type from the back surface side of the semiconductor substrate. Next, a sixth step is performed to activate the third semiconductor region by laser annealing, with the intensity of the laser annealing for a predetermined region of the third semiconductor region being weaker than the intensity of the laser annealing for a region other than the predetermined region of the third semiconductor region. Next, a seventh step is performed in which an impurity of the first conductivity type is implanted from the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type, and an eighth step is performed in which a second electrode is formed on the surface of the third semiconductor region.

[0028] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region opposite the semiconductor substrate side. Next, a third step is performed to form a gate insulating film in contact with the first semiconductor region and a gate electrode on the surface of the gate insulating film opposite the surface in contact with the first semiconductor region. Next, a fourth step is performed to form a first electrode on the surfaces of the first semiconductor region and the second semiconductor region. Next, a fifth step is performed to form a third semiconductor region of the second conductivity type by implanting impurities of the second conductivity type from the back surface side of the semiconductor substrate. Next, a sixth step is performed to perform laser annealing to activate the third semiconductor region. Next, a seventh step is performed to implant ions of Ar (argon) or silicon (Si) into a predetermined region of the third semiconductor region. Next, an eighth step is performed in which an impurity of the first conductivity type is implanted from the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type, and a ninth step is performed in which a second electrode is formed on the surface of the third semiconductor region.

[0029] Furthermore, in the method for manufacturing a semiconductor device according to the present invention, the sixth step is performed after the seventh step and before the eighth step.

[0030] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device comprises a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate, and a first semiconductor layer of the first conductivity type provided inside the semiconductor substrate. The semiconductor device further comprises a fourth semiconductor region of the first conductivity type provided on the back surface side of the semiconductor substrate, a first electrode provided on the surface of the first semiconductor region, and a second electrode provided on the surface of the fourth semiconductor region. The semiconductor device has an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region, wherein a depth of a predetermined region of the active region of the first semiconductor layer from the back surface of the semiconductor substrate is greater than a depth of a region other than the predetermined region of the active region of the first semiconductor layer from the back surface of the semiconductor substrate, and the termination structure comprises the semiconductor substrate, the first semiconductor layer, the fourth semiconductor region, and the second electrode, and in the area other than the predetermined area The depth of the first semiconductor layer from the rear surface of the semiconductor substrate is the same as the depth of the first semiconductor layer from the rear surface of the semiconductor substrate of the termination structure.

[0031] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of a first conductivity type in a surface layer of the first semiconductor region on the side opposite the semiconductor substrate. Next, a third step is performed to form a first electrode on the surface of the first semiconductor region. Next, a fourth step is performed to form a fourth semiconductor region of the first conductivity type by implanting impurities of the first conductivity type from the back surface side of the semiconductor substrate. Next, a fifth step is performed to activate the fourth semiconductor region by laser annealing, with the intensity of the laser annealing applied to a predetermined region of the fourth semiconductor region being weaker than the intensity of the laser annealing applied to regions other than the predetermined region of the fourth semiconductor region. Next, a sixth step is performed to form a first semiconductor layer of the first conductivity type by implanting impurities of the first conductivity type from the back surface side of the semiconductor substrate. Next, an eighth step is performed to form a second electrode on the surface of the fourth semiconductor region.

[0032] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: First, a first step is performed to form a first semiconductor region of a second conductivity type on the front surface side of a semiconductor substrate. Next, a second step is performed to selectively form a second semiconductor region of a first conductivity type in a surface layer of the first semiconductor region on the side opposite the semiconductor substrate. Next, a third step is performed to form a first electrode on the surface of the first semiconductor region. Next, a fourth step is performed to form a fourth semiconductor region of a first conductivity type by implanting impurities of the first conductivity type from the back surface side of the semiconductor substrate. Next, a fifth step is performed to perform laser annealing to activate the fourth semiconductor region. Next, a sixth step is performed to implant ions of Ar (argon) or silicon (Si) into a predetermined region of the fourth semiconductor region. Next, a seventh step is performed to form a first semiconductor layer of a first conductivity type by implanting impurities of the first conductivity type from the back surface side of the semiconductor substrate. Next, an eighth step is performed to form a second electrode on the surface of the fourth semiconductor region.

[0033] Moreover, in the method for manufacturing a semiconductor device according to the present invention, the fifth step is performed after the sixth step and before the seventh step.

[0034] According to the above-mentioned invention, in the IGBT region (transistor portion), n is provided at a position deeper than the diode region (diode portion). + Here, the deep FS layer (first semiconductor layer of the first conductivity type) is provided. - The back surface of the n-type semiconductor substrate (first conductivity type semiconductor substrate) is used as a reference. - The back side of the n-type semiconductor substrate is - p type semiconductor substrate + a second conductive type collector region (a third semiconductor region of the second conductivity type) and an n + The surface of the back electrode (second electrode) side of the cathode region (fourth semiconductor region of the first conductivity type). - The drift layer made of a semiconductor substrate (a semiconductor substrate of a first conductivity type) is thick, and the depletion layer is + This makes it difficult for the reverse recovery surge voltage to reach the front surface of the FS layer, increasing the breakdown voltage of the diode region. This ensures sufficient breakdown voltage, making the element less susceptible to breakdown even when a large reverse recovery surge voltage is applied, resulting in a highly reliable semiconductor device. [Effects of the Invention]

[0035] The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have an advantage that the diode region and the IGBT region are provided, and the diode region can be made to have a higher breakdown voltage than the IGBT region. [Brief explanation of the drawings]

[0036] [Figure 1] 1 is a plan view showing a structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 3 is a characteristic diagram showing the carrier concentration distribution in the cathode region of the semiconductor device according to the first embodiment. FIG. [Figure 4] 4 is a characteristic diagram showing the carrier concentration distribution in the FS layer of the semiconductor device according to the first embodiment. FIG. [Figure 5] 1 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view (part 1) showing a state of an active region during the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] FIG. 2 is a cross-sectional view (part 2) showing a state of an active region during the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 10 is a cross-sectional view (part 3) showing a state of an active region during the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 9] FIG. 10 is a cross-sectional view (part 1) showing a state of an active region during the manufacturing process of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 2) showing a state of an active region during the manufacturing process of a semiconductor device according to the second embodiment. [Figure 11] FIG. 10 is a cross-sectional view (part 3) showing a state of an active region during the manufacturing process of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view (part 4) showing a state of an active region during the manufacturing process of a semiconductor device according to the second embodiment. [Figure 13] FIG. 10 is a cross-sectional view (part 1) showing a state of an active region during the manufacturing process of a semiconductor device according to a third embodiment. [Figure 14] FIG. 10 is a cross-sectional view (part 2) showing a state of an active region during the manufacturing process of a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a state of an active region during the manufacturing process of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 11 is a cross-sectional view (part 1) showing a state of an active region during the manufacture of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 13 is a cross-sectional view (part 2) showing a state of an active region during the manufacture of a semiconductor device according to the fifth embodiment. [Figure 18]FIG. 13 is a cross-sectional view (part 3) showing a state of an active region during the manufacturing process of a semiconductor device according to a fifth embodiment. [Figure 19] FIG. 13 is a cross-sectional view (part 1) showing a state of an active region during the manufacture of a semiconductor device according to a sixth embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 2) showing the state of the active region during the manufacturing process of the semiconductor device according to the sixth embodiment. [Figure 21] FIG. 20 is a cross-sectional view (part 3) showing a state of an active region during the manufacturing process of a semiconductor device according to a sixth embodiment. [Figure 22] FIG. 20 is a cross-sectional view (part 4) showing a state of an active region during the manufacture of a semiconductor device according to a sixth embodiment. [Figure 23] FIG. 1 is a diagram showing a method for creating regions with strong and weak laser annealing intensity (part 1). [Figure 24] FIG. 10 is a diagram showing a method for creating regions with high and low laser annealing intensity (part 2). [Figure 25] FIG. 10 is a diagram showing a method for creating regions with strong and weak laser annealing intensity (part 3). [Figure 26] FIG. 1 is a cross-sectional view showing a state during manufacturing of a conventional RC-IGBT having an n-type FS layer (part 1). [Figure 27] FIG. 2 is a cross-sectional view showing a state during manufacturing of a conventional RC-IGBT having an n-type FS layer (part 2). [Figure 28] FIG. 10 is a cross-sectional view (part 3) showing a state during the manufacturing process of a conventional RC-IGBT having an n-type FS layer. DETAILED DESCRIPTION OF THE INVENTION

[0037] A preferred embodiment 1 of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - affixed to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these affixes, respectively. In the following description of embodiment 1 and the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. Furthermore, the terms "same" or "equivalent" should preferably be interpreted as including a difference of up to 5% in consideration of variations in manufacturing.

[0038] (Embodiment 1) The structure of the semiconductor device according to the first embodiment will be described using an RC-IGBT as an example. Fig. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment shown in Figs. 1 and 2 is an RC-IGBT 150 in which an IGBT with a trench gate structure and a diode connected in anti-parallel to the IGBT are integrated on the same semiconductor substrate (semiconductor chip).

[0039] As shown in FIG. 1, the RC-IGBT 150 includes an active region 90 and an edge termination region 91 surrounding the active region 90. The active region 90 is a region through which current flows in the on-state. The edge termination region 91 includes a breakdown voltage maintaining region that relieves the electric field on the front surface side of the semiconductor substrate in the drift region and maintains the breakdown voltage. Note that the boundary between the active region 90 and the edge termination region 91 has an n-type dielectric constant (n = 0.01) on only one side, which will be described later. + n-type emitter region 12 is provided on both sides +The active region 90 is located at the center of the dummy trench 30 where the emitter region 12 is not provided. An IGBT region (transistor portion) 70, which serves as the operating region of the IGBT, and a diode region (diode portion) 80, which serves as the operating region of the diode, are provided in parallel on the same semiconductor substrate as the active region 90.

[0040] n of the active region 90 - n-type drift layer - An n-type accumulation layer 16 may be provided on the surface layer of the front surface of the first conductivity type semiconductor substrate (first conductivity type semiconductor substrate) 18. The n-type accumulation layer 16 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. - A p-type base region (first semiconductor region of the second conductivity type) 14 is provided on the front surface side of the p-type semiconductor substrate 18, extending from the IGBT region 70 to the diode region 80. The p-type base region 14 functions as a p-type anode region in the diode region 80. An n-type semiconductor layer is formed through the p-type base region 14. - A gate trench 40 and a dummy trench 30 are provided, which reach the semiconductor substrate 18. The gate trench 40 has n-type trenches on both sides. + The p-type emitter regions 12 are provided in the IGBT region 70 and are arranged at predetermined intervals in, for example, a striped planar layout, separating the p-type base region 14 into a plurality of regions (mesa portions). A gate insulating film 50 is provided inside the gate trench 40 along the inner wall of the gate trench 40, and a gate electrode 51 is provided inside the gate insulating film 50. The dummy trenches 30 are provided in the diode region 80 and at the boundary between the IGBT region 70 and the edge termination region, and may have the same structure as the gate trench 40.

[0041] In the IGBT region 70, inside the p-type base region 14, n-type + An n-type emitter region (a second semiconductor region of the first conductivity type) 12 is selectively provided. +The p-type emitter region 12 faces the gate electrode 51 across the gate insulating film 50 provided on the inner wall of the gate trench 40. In the diode region 80, the p-type base region 14 has an n + The n-type emitter region 12 is not provided. The front surface electrode (first electrode) 130 is connected to the n-type emitter region 12 via a contact hole. + The n-type emitter region 12 is in contact with the n-type emitter region 12 and is electrically insulated from the gate electrode 51 by the interlayer insulating film 38. + An opening may be selectively provided in the p-type emitter region 12, and the front surface electrode 130 and the p-type base region 14 may be electrically connected through the opening. The front surface electrode 130 functions as the emitter electrode 52 in the IGBT region 70, and functions as the anode electrode in the diode region 80.

[0042] n - Inside the semiconductor substrate 18, there is an n-type + A field stop (FS) layer (first semiconductor layer of a first conductivity type) 20 is provided. + The FS layer 20 is connected to the p-type base region 14 and the n-type - The pn junction between the semiconductor substrate 18 and the p + It has the function of suppressing the extension of the depletion layer toward the collector region 22. + The FS layer 20 is provided at different depths in the IGBT region 70 and the diode region 80. + The n-type FS layer 20 has a wavy shape. Generally, when impurity layers are formed at different depths by ion implantation, the deeper impurity layer tends to be thicker than the shallower impurity layer. + The thickness w of the type FS layer 20 in both the IGBT region 70 and the diode region 80 was within the range of variations in manufacturing.

[0043] As shown in FIG. 2, in the IGBT region 70, n + A mold FS layer 20 is provided. +The n-type FS layer 20 may have substantially the same depth throughout the IGBT region 70 extending in the Y-axis direction as shown in FIG. + The FS layer 20 may have substantially the same depth throughout the diode region 80 extending in the Y-axis direction as shown in FIG. - The back surface of the n-type semiconductor substrate 18 is used as a reference, and the deep position is - The shallow position means that the distance from the rear surface of the n-type semiconductor substrate 18 is long. - This means that the distance from the back surface of the n-type semiconductor substrate 18 is short. - The back surface of the n-type semiconductor substrate 18 is - p type semiconductor substrate 18 + collector region 22 and n + The surface of the back electrode 24 side of the cathode region 82. + The depth d1 of the FS layer 20 is + The depth is greater than the depth d2 of the mold FS layer 20 (d1>d2). - From the back surface of the n-type semiconductor substrate 18 + The difference in depth (d1-d2) is preferably 0.5 μm or more and 3 μm or less. + Type FS layer 20 and p + Between the collector region 22, a thickness n corresponding to the depth difference (d1-d2) is - A semiconductor substrate 18 is present. + Type FS layer 20 and p + between the n-type collector region 22 - The presence of the n-type semiconductor substrate 18 + Type FS layer 20 and p + By separating the high impurity concentration region of the n-type collector region 22, the breakdown voltage in this portion is improved. + The surface of the front surface of the cathode region 82 (the surface opposite to the back electrode 24) is + A mold FS layer 20 may be provided.

[0044] As a result, in the diode region 80, the n - The thickness of the n-type semiconductor substrate 18 is large, and the depletion layer - This makes it difficult for the n-type semiconductor substrate 18 to reach the rear surface thereof, thereby increasing the breakdown voltage of the diode region 80. For example, increasing the switching speed increases the reverse recovery surge voltage, increasing the risk of element breakdown. + The FS layer 20 is shallow (n - By providing the element at a position where the distance from the rear surface of the semiconductor substrate 18 is short, it is possible to ensure a sufficient breakdown voltage, and even if a large reverse recovery surge voltage is applied, the element is less likely to be destroyed, resulting in a highly reliable semiconductor device.

[0045] Also, n - Inside the n-type semiconductor substrate 18, in the diode region 80, + Type FS layer 20 than n - A lifetime control region 72 is provided at a shallow position from the front surface of the semiconductor substrate 18, where lattice defects (indicated by x marks) such as vacancies (V) that act as lifetime killers are introduced by helium (He) irradiation. The lifetime control region 72 may extend to the vicinity of the boundary between the IGBT region 70 and the diode region 80. The lifetime control region 72 may also extend to the chip end of the edge termination region 91 (the end of the edge termination region 91 opposite the active region 90 side). - The carrier concentration of the n-type semiconductor substrate 18 is lower in the portion where the lifetime control region 72 is provided than in other portions. - This shortens the carrier lifetime of the semiconductor substrate 18, and accelerates the disappearance of carriers during reverse recovery of the diode, thereby reducing reverse recovery loss.

[0046] n - The surface layer on the back side of the n-type semiconductor substrate 18 + Type FS layer 20 than n - At a shallow position from the rear surface of the semiconductor substrate 18, a p +a second conductive type collector region (third semiconductor region) 22 is provided in the diode region 80; + A cathode region (fourth semiconductor region of the first conductivity type) 82 is provided. + The cathode region 82 is p + The back electrode (second electrode) 24 is adjacent to the p-type collector region 22. + collector region 22 and n + The surface of the cathode region 82 (n - The back surface electrode 24 functions as a collector electrode in the IGBT region 70 and as a cathode electrode in the diode region 80.

[0047] The edge termination region 91 has p + The edge termination region 91 is provided with a p well region 11. + Guard ring 92 and n-type contact with the chip edge + A p-type channel stopper 174 is provided. The channel stopper may also be p-type. A plurality of guard rings 92 may be provided from the negative side to the positive side in the X-axis direction. FIG. 2 shows an example in which a plurality of guard rings 92 are provided.

[0048] Guard ring 92 may be provided in edge termination region 91 to surround active region 90. When multiple guard rings 92 are provided, the impurity concentrations of guard rings 92 may be the same. + The gate insulating film 38 is provided on the upper surface of the interlayer insulating film 38 so as to contact the surfaces of the channel stopper 174 and the guard ring 92 .

[0049] The back surface structure of the edge termination region 91 is n-type, similar to the diode region 80. + The edge termination region 91 is provided with an n-type cathode region 82. + It is preferable that the n-type FS layer 20 is provided at a shallow position. + The depth d3 of the FS layer 20 is +The depth d3 is approximately the same as the depth d2 of the FS layer 20 (d3≒d2). + Up to the well region 11, + It is preferable that the FS layer 20 is provided at a shallow position. This increases the width of the electric field in the edge termination region 91 as shown in region A, and the p + In the well region 11, the width of the electric field is narrowed as shown in region B. Therefore, avalanche breakdown occurs in the p + This can prevent damage to the edge termination region 91, which is likely to occur in the mold well region 11.

[0050] Also, the chip end of the edge termination region 91 is + All of the well regions up to 11 are n + The type FS layer 20 does not need to be provided at a shallow position. + By providing the type FS layer 20 at a shallow position, it is possible to make it difficult for avalanche breakdown to occur at this location.

[0051] 3 is a characteristic diagram showing the carrier concentration distribution in the cathode region of the semiconductor device according to the first embodiment. In FIG. 3, the vertical axis represents the carrier concentration, and the unit is cm -3 The horizontal axis is n - 3 shows the depth from the rear surface of the semiconductor substrate 18, in μm. 15 cm -2 In + The carrier concentration when the type cathode region 82 is formed is measured by the SR method (Spreading Resistance Profiler). + It can be seen that a mold cathode region 82 has been formed.

[0052] 4 is a characteristic diagram showing the carrier concentration distribution in the FS layer of the semiconductor device according to the first embodiment. In FIG. 4, the vertical axis represents the carrier concentration, and the unit is cm -3 The horizontal axis is n -4 shows the depth from the rear surface of the semiconductor substrate 18, in μm. 12 cm -2 In + The carrier concentration in the FS layer 20 is measured by the SR method. + It can be seen that a mold FS layer 20 is formed.

[0053] (Method of manufacturing a semiconductor device according to the first embodiment) Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. Fig. 5 is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment. Figs. 6 to 8 are cross-sectional views showing the state of the active region 90 during the manufacturing of the semiconductor device according to the first embodiment. Here, Figs. 6 to 8 omit illustration of the front surface element structure.

[0054] First, n-type drift layer of the active region 90 - A MOS gate is formed by forming a gate trench 40, a gate insulating film 50, and a gate electrode 51 in this order on the front surface side of the semiconductor substrate 18 by a general method. The dummy trench 30 also forms an n-type drift layer in the active region 90 and the edge termination region 91 on the active region 90 side. - The gate trench 40 is formed on the front surface side of the n-type semiconductor substrate 18. - On the front surface side of the n-type semiconductor substrate 18, a - The n-type accumulation layer 16 may be formed at a shallow depth from the front surface of the n-type semiconductor substrate 18 by, for example, epitaxial growth.

[0055] Next, in the edge termination region 91, p-type impurities such as boron (B) are ion-implanted into the surface layer of the front surface of the substrate. + The n-type well region 11 and the guard ring 92 are selectively formed. Next, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the surface layer of the front surface of the substrate. + Mold channel stops 174 are selectively formed.

[0056] Next, p in the active region 90 and edge termination region 91 + By ion implantation of p-type impurities such as boron (B) into the active region 90 side of the well region 11, the n-type well region 11 is formed closer to the bottom of the gate trench 40 than the bottom of the gate trench 40. - The p-type base region 14 is formed at a shallow depth from the front surface of the semiconductor substrate 18. Alternatively, if an n-type accumulation layer 16 is present, the p-type base region 14 is formed at a shallow depth from the front surface of the semiconductor substrate 18. - The p-type base region 14 is formed at a shallow depth from the front surface of the semiconductor substrate 18. In the above manufacturing method, the guard ring 92 and the n-type + The p-type base region 14 was formed after the formation of the n-type channel stopper 174. However, after the formation of the p-type base region 14, the guard ring 92 and the n-type + A mold channel stopper 174 may be formed.

[0057] Next, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the p-type base region 14 of the IGBT region 70. + The emitter region 12 is selectively formed. Next, an interlayer insulating film 38 such as a BPSG film is deposited (formed) so as to cover the gate electrode 51.

[0058] Next, the interlayer insulating film 38 is patterned to form contact holes, and n-type + In the edge termination region 91, the p-type emitter region 12 is exposed, in the diode region 80, the p-type base region 14 is exposed, and in the edge termination region 91, the n-type + Type channel stopper 174, p +The well region 11 and the guard ring 92 are exposed. Next, a plug electrode (not shown) is formed inside the contact hole with a barrier metal (not shown) interposed therebetween. Next, a front surface electrode 130 is formed by, for example, sputtering, covering the entire surface of the interlayer insulating film 38 so as to contact the plug electrode inside the contact hole. A field plate electrode 94 is also formed in the edge termination region 91 by, for example, sputtering, covering a portion of the surface of the interlayer insulating film 38 so as to contact the plug electrode inside the contact hole. In this manner, the front surface element structure of the semiconductor device according to the first embodiment is formed (step S1: first to fourth steps).

[0059] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - A p-type impurity such as boron (B) is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18. - The surface layer of the entire back surface of the semiconductor substrate 18 is p + In step S2, the p-type collector region 22 is formed. If there are any areas where the p-type impurity is not implanted due to particles or the like, this will result in poor breakdown voltage. - In order to prevent the process from proceeding with the rear surface of the p-type semiconductor substrate 18 exposed, p-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point is shown in FIG.

[0060] Next, by photolithography, - A resist mask 101 having openings corresponding to the diode region 80 and the edge termination region 91 is formed on the rear surface of the semiconductor substrate 18 (step S3). Next, using the resist mask 101 as a mask, n-type impurities such as phosphorus (P) are ion-implanted 100 to form n-type impurities. - The p-type semiconductor substrate 18 has a surface layer on the back surface thereof in the diode region 80 and the edge termination region 91. + The collector region 22 is inverted to n-type to form n + The n-type cathode region 82 is formed (step S4: sixth step). +Type domain and p + A Relaxed Field of Cathode (RFC) structure is formed with the mold regions arranged. The state up to this point is shown in Figure 7.

[0061] Next, the resist mask 101 is removed by ashing. - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + The mold FS layer 20 is formed (step S5: sixth step). The state up to this point is shown in FIG.

[0062] where n + type cathode region 82 and p + Before activating the impurities implanted into the n-type collector region 22, + type cathode region 82 and p + Ion implantation is performed through the collector region 22. + type cathode region 82 and p + The amount of crystal defects is different between the n-type collector region 22 and the n-type collector region 23. + Since there are many crystal defects in the n-type cathode region 82, the n-type impurities + Therefore, in the IGBT region 70, the n-type cathode region 82 is more difficult to pass through than in the diode region 80. - At a deep position from the rear surface of the n-type semiconductor substrate 18 + The n-type FS layer 20 is formed. + The type FS layer 20 is formed in a wavy shape. Therefore, in the first embodiment, n ions can be implanted deep into the IGBT region 70 by a single ion implantation without increasing the number of process steps compared to the conventional method. + The n-type FS layer 20 is formed at a shallow position in the diode region 80. + A mold FS layer 20 can be formed.

[0063] In this way, regions with different amounts of crystal defects are formed, and annealing is not performed, and n is formed before activating the impurities. + Ion implantation is performed to form the n-type FS layer 20. +The FS layer 20 is formed in a wavy shape. + type cathode region 82 and p + For example, a rare gas element such as argon (Ar) or xenon (Xe), or an element such as silicon (Si) that does not affect the electrical properties of the substrate, may be used as the n-type collector region 22. - A region with a different amount of crystal defects may be formed by selectively implanting ions into the rear surface of the n-type semiconductor substrate 18. In this case, for example, argon is implanted into the diode region 80, and before annealing, n - By ion-implanting n-type impurities such as phosphorus into the entire rear surface of the semiconductor substrate 18, the IGBT region 70 has a higher n-type conductivity than the diode region 80. - At a deep position from the rear surface of the n-type semiconductor substrate 18 + The n-type FS layer 20 is formed. + The FS layer 20 is formed in a wavy shape. In addition, by implanting ions from a crystal orientation where channeling is likely to occur during ion implantation, the effect of forming a wavy shape due to the difference in the amount of crystal defects becomes significant, and the n-type FS layer 20 has a wavy shape. + The mold FS layer 20 can be formed.

[0064] Also, n + The ion species for forming the type FS layer 20 include phosphorus, hydrogen, arsenic (As), etc. Among them, phosphorus is preferable. The reason is that phosphorus is used to form n + By performing ion implantation to form the FS layer 20, the effect of forming a wavy shape due to the difference in the amount of crystal defects becomes significant, and the wavy n + This is because the FS layer 20 can be formed more easily. Hydrogen is a lighter element than phosphorus, so it can be implanted deeper, and a wavy n-type layer at a deeper position can be formed than when phosphorus is used. + Since arsenic is a heavier element than phosphorus, it is easy to form a wavy n layer 20 at a shallower position than when phosphorus is used. +It is necessary to implant with a large energy to form the n-type FS layer 20. Other ion species that may be used include selenium and sulfur, but they are prone to diffusion and are therefore not suitable for use in the n-type FS layer 20. + The mold FS layer 20 is less likely to be formed into a wavy shape.

[0065] Also, n - n-type impurities, such as phosphorus (P) or arsenic (As), are selectively ion-implanted into the rear surface of the n-type semiconductor substrate 18, - The surface layer on the back surface of the diode region 80 of the semiconductor substrate 18 is selectively n + The n-type cathode region 82 is formed, and then - The p-type impurity, for example, boron (B), is selectively ion-implanted into the rear surface of the semiconductor substrate 18, and the surface layer of the rear surface in the IGBT region 70 is selectively doped with p-type impurities. + After forming the n-type collector region 22, + By ion-implanting the n-type impurity that forms the n-type FS layer 20, the RFC structure is formed and the n + The n-type impurity phosphorus or arsenic has a larger mass number than the p-type impurity boron, and is more likely to cause crystal defects, so a region with a difference in the amount of crystal defects can be formed. + type cathode region 82 and p + The order in which the mold collector regions 22 are formed can be changed as appropriate.

[0066] In addition, n - The n-type semiconductor substrate 18 is ion-implanted with n-type impurities on the entire rear surface thereof. - The surface layer of the entire back surface of the semiconductor substrate 18 is n + The n-type cathode region 82 is formed, and then - p-type impurity ions are selectively implanted into the rear surface of the semiconductor substrate 18, and n-type impurity ions are implanted into the IGBT region 70. + The cathode region 82 is inverted to p-type to form p + After forming the collector region 22, + By ion-implanting n-type impurities to form the FS layer 20, an RFC structure is formed, and a wavy n-type structure is formed, which is opposite to that of the first embodiment. +In this case, the IGBT region 70 can have a larger n-type FS layer than the diode region 80. - At a shallow position from the rear surface of the n-type semiconductor substrate 18 + A mold FS layer 20 is formed.

[0067] In addition, by photolithography, - A resist mask 101 having an opening in a portion corresponding to the IGBT region 70 is formed on the rear surface of the semiconductor substrate 18, and for example, p-type impurities are ion-implanted using the resist mask 101 as a mask, to form an n-type impurity. - The surface layer on the back surface of the semiconductor substrate 18 is selectively + After forming the collector region 22, - n-type impurity ions are implanted into the surface layer of the entire rear surface of the semiconductor substrate 18, + The n-type collector region 22 is then turned into n-type. + 3. Forming the n-type cathode region 82, and then + By this manufacturing method, an n-type impurity is ion-implanted to form the n-type FS layer 20. The RFC structure is also formed, and the wavy n-type impurity is formed in contrast to the first embodiment. + In other words, in the IGBT region 70, the n-type FS layer 20 can be formed. - At a shallow position from the rear surface of the n-type semiconductor substrate 18 + A mold FS layer 20 is formed.

[0068] Next, by heat treatment (annealing), n + type cathode region 82, p + collector region 22 and n + Activate the mold FS layer 20. + Since the temperature suitable for activating the type FS layer 20 is different from the temperature suitable for activating layers formed by other impurities, n + The activation of the type FS layer 20 is + type cathode region 82 and p + This is done separately from the activation of the n-type collector region 22. + type cathode region 82 and p + Activation of the mold collector region 22 may be performed by heating with a laser. +The activation of the type FS layer 20 is + type cathode region 82 and p + Activation of mold collector region 22 may be performed by laser heating under modified processing conditions, or by furnace annealing at a relatively low temperature of approximately 400° C. or less. Next, the entire front surface of the substrate is covered with a surface protection film (not shown) such as a polyimide film, and the surface protection film is then patterned to expose front surface electrode 130 and each electrode pad.

[0069] Next, helium is irradiated from the rear surface of the substrate, and n is formed from the diode region 80 to the IGBT region 70 near the boundary with the diode region 80. - Lattice defects that act as lifetime killers are introduced into the semiconductor substrate 18 to form a lifetime control region 72.

[0070] Next, the lattice defects caused by helium irradiation are repaired by heat treatment (annealing) to adjust the amount of lattice defects in the semiconductor substrate, thereby adjusting the carrier lifetime.

[0071] Next, n + type cathode region 82 and p + A back electrode 24 is formed in contact with the collector region 22. Thereafter, the semiconductor wafer is cut (diced) into individual chips, thereby completing the RC-IGBT 150 shown in FIG.

[0072] As described above, according to the first embodiment, in the IGBT region, n is larger than in the diode region. - n type semiconductor substrate at a deep position from the back surface + The n-type FS layer is provided in the diode region. - The thickness of the semiconductor substrate is thick, and the depletion layer is n - This makes it difficult for the reverse voltage to reach the back surface of the semiconductor substrate, thereby increasing the breakdown voltage of the diode region. As a result, it is possible to ensure sufficient breakdown voltage, and even if a large reverse recovery surge voltage is applied, the element is less likely to be destroyed, resulting in a highly reliable semiconductor device.

[0073] (Embodiment 2) The structure of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment, and therefore a description thereof will be omitted.

[0074] (Method of manufacturing a semiconductor device according to the second embodiment) Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. Figures 9 to 12 are cross-sectional views showing the state of an active region 90 during the manufacturing process of a semiconductor device according to the second embodiment. Here, Figures 9 to 12 omit illustration of the front surface element structure. The same applies to the subsequent Figures 13 to 22.

[0075] First, as in the first embodiment, the n-type drift layer - A front surface element structure is formed on the front surface side of the mold semiconductor substrate 18 (first to fourth steps).

[0076] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - A p-type impurity such as boron (B) is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18. - The surface layer of the entire back surface of the semiconductor substrate 18 is p + If there are any areas where the p-type impurity is not implanted due to particles or the like, this will result in poor breakdown voltage. - In order to prevent the process from proceeding with the rear surface of the p-type semiconductor substrate 18 exposed, p-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point is shown in FIG.

[0077] Next, n -Laser annealing 102 is performed from the backside of the p-type semiconductor substrate 18 (sixth step). A laser with higher energy than the band edge is irradiated and heated to activate the ion-implanted p-type impurities. At this time, by changing the laser scanning speed or the like, regions with high and low intensity of the laser annealing 102 are created. The intensity of the laser annealing will be described later with reference to Figures 24 and 25. In Figure 10, thin arrows indicate areas with low intensity of the laser annealing 102, and thick arrows indicate areas with high intensity of the laser annealing 102. By ion implantation 100 of the p-type impurities, the p-type impurities are activated. + Crystal defects are formed in the type collector region 22, but if the laser annealing 102 is strong, many of the crystal defects are repaired by the heat, creating a region with a low density of crystal defects. On the other hand, if the laser annealing 102 is weak, many of the crystal defects are not repaired sufficiently by the heat, creating a region with a high density of crystal defects. In this way, the strength of the laser annealing 102 determines the n - A difference in the amount of crystal defects is created on the rear surface of the semiconductor substrate 18.

[0078] For example, during laser annealing 102, the laser beam is scanned in parallel, with an overlap rate (the ratio of the overlapping area) of 50% or more on the vertical axis, a pulse width of 100 ns or more and 300 ns or less at half maximum, and an energy density j of 1.6 J / cm 2 More than 2.0J / cm 2 Crystal defects can be eliminated by setting the frequency to 1 kHz to 3 kHz. Therefore, by reducing the laser energy density j under the above conditions, it is possible to form a portion where crystal defects remain.

[0079] Here, in the second embodiment, n + The intensity of the laser annealing for the region where the cathode region 82 is to be formed is set to p + The intensity of the laser annealing is weaker than that of the region where the p-type collector region 22 is formed. + A region with a low density of crystal defects is formed in the region where the n-type collector region 22 is formed, +A region with a high density of crystal defects is formed in the region where the mold cathode region 82 is to be formed. The state up to this point is shown in FIG.

[0080] Next, n - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + The mold FS layer 20 is formed (seventh step). - The amount of crystal defects varies on the rear surface of the n-type semiconductor substrate 18, and in the region with a high density of crystal defects, the n-type impurity + Therefore, in the IGBT region 70, the n-type cathode region 82 is more difficult to pass through than in the diode region 80. - At a deep position from the rear surface of the n-type semiconductor substrate 18 + The n-type FS layer 20 is formed. + The type FS layer 20 is formed in a wavy shape. Therefore, in the second embodiment, n ions are implanted deep into the IGBT region 70 by a single ion implantation. + The n-type FS layer 20 is formed at a shallow position in the diode region 80. + It is possible to form a mold FS layer 20. The state up to this point is illustrated in FIG.

[0081] Next, by photolithography, - A resist mask 101 having openings corresponding to the diode region 80 and the edge termination region 91 is formed on the rear surface of the semiconductor substrate 18. Next, using the resist mask 101 as a mask, n-type impurities such as phosphorus (P) are ion-implanted 100 to form n-type impurities. - The p-type semiconductor substrate 18 has a surface layer on the back surface thereof in the diode region 80 and the edge termination region 91. + The collector region 22 is inverted to n-type to form n + The n-type cathode region 82 is formed (eighth step). + Type domain and p + A Relaxed Field of Cathode (RFC) structure is formed with the mold regions arranged. The state up to this point is shown in Figure 12.

[0082] Next, the resist mask 101 is removed by ashing. + The ion species for forming the type FS layer 20 include phosphorus, hydrogen, arsenic (As), etc. Among them, phosphorus is preferable. The reason is that phosphorus is used to form n + By performing ion implantation to form the FS layer 20, the effect of forming a wavy shape due to the difference in the amount of crystal defects becomes significant, and the wavy n + This is because the FS layer 20 can be formed more easily. Hydrogen is a lighter element than phosphorus, so it can be implanted deeper, and a wavy n-type layer at a deeper position can be formed than when phosphorus is used. + Since arsenic is a heavier element than phosphorus, it is easy to form a wavy n layer 20 at a shallower position than when phosphorus is used. + It is necessary to implant with a large energy to form the n-type FS layer 20. Other ion species that may be used include selenium and sulfur, but they are prone to diffusion and are therefore not suitable for use in the n-type FS layer 20. + The mold FS layer 20 is less likely to be formed into a wavy shape.

[0083] Next, by heat treatment (annealing), n + type cathode region 82 and n + Activate the mold FS layer 20. + Since the temperature suitable for activating the type FS layer 20 is different from the temperature suitable for activating layers formed by other impurities, n + The activation of the type FS layer 20 is + This is done separately from the activation of the n-type cathode region 82. + Activation of the cathode region 82 may be achieved by heating with a laser. + The activation of the type FS layer 20 is + Activation of the mold cathode region 82 may be performed by heating with a laser under modified processing conditions, or by annealing in a furnace at a relatively low temperature of about 400° C. or less. Next, the entire front surface of the substrate is covered with a surface protection film (not shown) such as a polyimide film, and the surface protection film is then patterned to expose the front electrode 130 and each electrode pad.

[0084] Next, helium is irradiated from the rear surface of the substrate, and n is formed from the diode region 80 to the IGBT region 70 near the boundary with the diode region 80. - Lattice defects that act as lifetime killers are introduced into the semiconductor substrate 18 to form a lifetime control region 72.

[0085] Next, the lattice defects caused by helium irradiation are repaired by heat treatment (annealing) to adjust the amount of lattice defects in the semiconductor substrate, thereby adjusting the carrier lifetime.

[0086] Next, n + type cathode region 82 and p + A back electrode 24 is formed in contact with the collector region 22 (ninth step). Thereafter, the semiconductor wafer is cut (diced) into individual chips, thereby completing the RC-IGBT 150 shown in FIGS. 1 and 2.

[0087] As described above, according to the second embodiment, in the IGBT region, n is larger than that in the diode region, as in the first embodiment. - n type semiconductor substrate at a deep position from the back surface + A type FS layer is provided, which provides the same effects as those of the first embodiment.

[0088] (Embodiment 3) The structure of the semiconductor device according to the third embodiment is the same as that of the semiconductor device according to the first embodiment, and therefore a description thereof will be omitted.

[0089] (Method of manufacturing a semiconductor device according to the third embodiment) Next, a description will be given of a method for manufacturing the semiconductor device according to the third embodiment. Figures 13 and 14 are cross-sectional views showing the state of the active region 90 during the manufacturing process of the semiconductor device according to the third embodiment.

[0090] First, as in the first embodiment, the n-type drift layer - A front surface element structure is formed on the front surface side of the mold semiconductor substrate 18 (first to fourth steps).

[0091] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - A p-type impurity such as boron (B) is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18. - The surface layer of the entire back surface of the semiconductor substrate 18 is p + If there are any areas where the p-type impurity is not implanted due to particles or the like, this will result in poor breakdown voltage. - In order to prevent the process from proceeding with the rear surface of the p-type semiconductor substrate 18 exposed, p-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point is the same as that shown in FIG. 9 of the second embodiment.

[0092] Next, by photolithography, - A resist mask (not shown) is formed on the back surface of the semiconductor substrate 18, with openings in the areas corresponding to the diode region 80 and the edge termination region 91. Next, using this resist mask as a mask, n-type impurities such as phosphorus (P) are ion-implanted 100 to form n-type impurities. - The p-type semiconductor substrate 18 has a surface layer on the back surface thereof in the diode region 80 and the edge termination region 91. + The collector region 22 is inverted to n-type to form n + The n-type cathode region 82 is formed (sixth step). + Type domain and p + An RFC structure is formed with a series of type regions.

[0093] Next, the resist mask is removed by ashing. - By performing laser annealing 102 from the rear surface of the n-type semiconductor substrate 18, + type cathode region 82 and p +The p-type collector region 22 is activated (seventh step). A laser with higher energy than the band edge is irradiated and heated to activate the ion-implanted p-type impurities and n-type impurities. At this time, by changing the laser scanning speed, etc., regions with strong and weak laser annealing 102 intensity are created. In Figure 13, thin arrows indicate areas with weak laser annealing 102, and thick arrows indicate areas with strong laser annealing 102. When the laser annealing 102 is strong, many crystal defects are repaired by the heat, creating regions with a low density of crystal defects. On the other hand, when the laser annealing 102 is weak, many crystal defects are not repaired sufficiently by the heat, creating regions with a high density of crystal defects. In this way, depending on the strength of the laser annealing 102, the n-type impurities can be activated. - A difference in crystal defects is created on the back surface of the semiconductor substrate 18.

[0094] Here, in the third embodiment, n + The intensity of the laser annealing for the region where the cathode region 82 is to be formed is set to p + The intensity of the laser annealing is weaker than that of the region where the p-type collector region 22 is formed. + A region with a low density of crystal defects is formed in the region where the n-type collector region 22 is formed, + A region with a high density of crystal defects is formed in the region where the mold cathode region 82 is to be formed. The state up to this point is shown in FIG.

[0095] Next, n - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + The mold FS layer 20 is formed (eighth step). - The amount of crystal defects varies on the rear surface of the n-type semiconductor substrate 18, and in the region with a high density of crystal defects, the n-type impurity + Therefore, in the IGBT region 70, the n-type cathode region 82 is more difficult to pass through than in the diode region 80. - At a deep position from the rear surface of the n-type semiconductor substrate 18 + The n-type FS layer 20 is formed. +The type FS layer 20 is formed in a wavy shape. Therefore, in the third embodiment, n ions are implanted deep into the IGBT region 70 by a single ion implantation. + The n-type FS layer 20 is formed at a shallow position in the diode region 80. + It is possible to form a mold FS layer 20. The state up to this point is illustrated in FIG.

[0096] In the third embodiment, before the laser annealing 102, n + type cathode region 82 and p + Ion implantation is performed to form the p-type collector region 22. + The difference in crystal defects is greater than in the second embodiment, in which only ion implantation is performed to form the n-type collector region 22, and the difference in n-type collector region 22 between the IGBT region 70 and the diode region 80 is greater. + The difference in depth of the type FS layer 20 can be made larger. + By varying the intensity of the laser annealing 102 in the cathode region 82, the n-type + This allows the depth of the mold FS layer 20 to be adjusted.

[0097] Next, by heat treatment (annealing), n + Activate the mold FS layer 20. + The activation of the type FS layer 20 is + Activation of the mold cathode region 82 may be performed by heating with a laser under modified processing conditions, or by annealing in a furnace at a relatively low temperature of about 400° C. or less. Next, the entire front surface of the substrate is covered with a surface protection film (not shown) such as a polyimide film, and the surface protection film is then patterned to expose the front electrode 130 and each electrode pad.

[0098] Next, helium is irradiated from the rear surface of the substrate, and n is formed from the diode region 80 to the IGBT region 70 near the boundary with the diode region 80. - Lattice defects that act as lifetime killers are introduced into the semiconductor substrate 18 to form a lifetime control region 72.

[0099] Next, the lattice defects caused by helium irradiation are repaired by heat treatment (annealing) to adjust the amount of lattice defects in the semiconductor substrate, thereby adjusting the carrier lifetime.

[0100] Next, n + type cathode region 82 and p + A back electrode 24 is formed in contact with the collector region 22 (ninth step). Thereafter, the semiconductor wafer is cut (diced) into individual chips, thereby completing the RC-IGBT 150 shown in FIG.

[0101] As described above, according to the third embodiment, in the IGBT region, n is larger than that in the diode region, as in the first embodiment. - n type semiconductor substrate at a deep position from the back surface + In the third embodiment, the n-type FS layer is formed before laser annealing. + type cathode region and p + Ion implantation is performed to form the p-type collector region. + Compared to the second embodiment, in which only ion implantation is used to form the n-type collector region, there are more crystal defects, and the n-type collector region in the IGBT region and the diode region + The depth of the type FS layer can be made larger.

[0102] (Fourth embodiment) In the first to third embodiments, the RC-IGBT 150 is an IGBT having a trench gate structure and a diode connected in anti-parallel to the IGBT integrated on the same semiconductor substrate (semiconductor chip). However, the present invention is applicable not only to the RC-IGBT 150 but also to an IGBT alone or a diode alone.

[0103] The IGBT structure of the semiconductor device according to the fourth embodiment is configured from an IGBT region 70 and an edge termination region 91 in FIG. 2. That is, it is the configuration obtained by excluding the diode region 80 from FIG. 2. On the other hand, the diode structure of the semiconductor device according to the fourth embodiment is configured from a diode region 80 and an edge termination region 91 in FIG. 2. That is, it is the configuration obtained by excluding the IGBT region 70 from FIG. 2.

[0104] (Method of manufacturing a semiconductor device according to the fourth embodiment) Next, a method for manufacturing a semiconductor device according to the fourth embodiment will be described. Fig. 15 is a cross-sectional view showing the state of an active region 90 during the manufacturing of a semiconductor device according to the fourth embodiment. Fig. 15 shows the state of the active region 90 during the manufacturing process when an IGBT is formed, and the state of the active region 90 during the manufacturing process when a diode is formed is p + The part of the collector region 22 is n + This forms the cathode region 82.

[0105] First, as in the first embodiment, the n-type drift layer - A front surface element structure is formed on the front surface side of the semiconductor substrate 18 (first to fourth steps, first to third steps, in the order of an IGBT and a diode, and the same applies below).

[0106] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - The entire rear surface of the semiconductor substrate 18 is ion-implanted 100 with p-type impurities or n-type impurities such as boron (B) or phosphorus (P), - The surface layer of the entire back surface of the semiconductor substrate 18 is p + Type collector region 22 or n + The p-type cathode region 82 is formed (fifth step, fourth step). If there are any areas where the p-type impurities or n-type impurities are not implanted due to particles or the like, this will result in poor voltage resistance. -In order to prevent the process from proceeding with the rear surface of the semiconductor substrate 18 exposed, p-type or n-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point when an IGBT is formed is the same as that shown in FIG. 9 of the second embodiment. The state up to this point when a diode is formed is the same as that shown in FIG. 9 of the second embodiment, except that p-type or n-type impurities are ion-implanted. + The part of the collector region 22 is n + This forms the cathode region 82.

[0107] Next, n - Laser annealing 102 is performed from the backside of the semiconductor substrate 18 (sixth and fifth steps). A laser beam with higher energy than the band edge is irradiated and heated to activate the ion-implanted p-type impurities or n-type impurities. At this time, the p-type impurities or n-type impurities are activated by changing the scanning speed of the laser, etc. + Type collector region 22 or n + The intensity of the laser annealing for a given area of the cathode region 82 is defined as p + Type collector region 22 or n + The intensity of the laser annealing is made weaker than that for the region other than the predetermined region of the cathode region 82, thereby creating regions with strong and weak intensity of the laser annealing 102. + As a region where the type FS layer 20 is formed deep, a region with a low density of crystal defects is formed, and a region other than the predetermined region is formed as n + The region where the type FS layer 20 is formed shallowly is a region where the density of crystal defects is high.

[0108] Next, n - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + (6th and 5th steps) for forming the mold FS layer 20. - The amount of crystal defects varies on the rear surface of the n-type semiconductor substrate 18, and in the region with a high density of crystal defects, the n-type impurity + The electrons are less likely to pass through the n-type cathode region 82. +The FS layer 20 is formed in a wavy shape. Therefore, in the fourth embodiment, a wavy n-type FS layer is formed in the IGBT and the diode by one ion implantation. + It is possible to form a mold FS layer 20. The state up to this point is illustrated in FIG.

[0109] Thereafter, the steps from the heat treatment (annealing) in the first embodiment onwards are carried out to complete the IGBT or diode.

[0110] As described above, according to the fourth embodiment, the wavy n-type IGBT and the diode are + For example, in an IGBT or diode, n-type FS layers can be formed in the active area and edge termination region. + The depth of the type FS layer can be varied to provide different breakdown voltages in the active and edge termination regions.

[0111] (Embodiment 5) The structure of the semiconductor device according to the fifth embodiment is the same as the structure of the semiconductor device according to the fourth embodiment, that is, the structure of the IGBT alone and the diode alone.

[0112] (Method of manufacturing a semiconductor device according to the fifth embodiment) Next, a method for manufacturing a semiconductor device according to the fifth embodiment will be described. Figs. 16 to 18 are cross-sectional views showing the state of an active region 90 during the manufacturing process of a semiconductor device according to the fifth embodiment. Figs. 16 to 18 show the state of the active region 90 during the manufacturing process when an IGBT is formed, and the state of the active region 90 during the manufacturing process when a diode is formed is p + The part of the collector region 22 is n + This forms the cathode region 82.

[0113] First, as in the first embodiment, the n-type drift layer - A front surface element structure is formed on the front surface side of the mold semiconductor substrate 18 (first to fourth steps, first to third steps).

[0114] Next, n- The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - The entire rear surface of the semiconductor substrate 18 is ion-implanted 100 with p-type impurities or n-type impurities such as boron (B) or phosphorus (P), - The surface layer of the entire back surface of the semiconductor substrate 18 is p + Type collector region 22 or n + The p-type cathode region 82 is formed (fifth step, fourth step). If there are any areas where the p-type impurities or n-type impurities are not implanted due to particles or the like, this will result in poor voltage resistance. - In order to prevent the process from proceeding with the rear surface of the semiconductor substrate 18 exposed, p-type or n-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point when an IGBT is formed is the same as that shown in FIG. 9 of the second embodiment. The state up to this point when a diode is formed is the same as that shown in FIG. 9 of the second embodiment, except that p-type or n-type impurities are ion-implanted. + The part of the collector region 22 is n + This forms the cathode region 82.

[0115] Next, n - Laser annealing 102 is performed from the backside of the semiconductor substrate 18. The p-type impurity or n-type impurity ion implanted is activated by irradiating it with a laser having higher energy than the band edge and heating it (steps 6 and 5). At this time, the intensity of the laser annealing 102 is uniform. The state up to this point is shown in FIG. 16.

[0116] Next, by photolithography, - On the rear surface of the n-type semiconductor substrate 18, + A resist mask 101 is formed with openings in areas corresponding to the areas where the mold FS layer 20 will be shallowly formed. Next, argon (Ar) or Si ions are implanted 100 using this resist mask 101 as a mask. In the areas where argon (Ar) or Si is implanted, crystal defects are broken down, resulting in areas with a low density of crystal defects (seventh and sixth steps). The state up to this point is shown in FIG. 17.

[0117] Next, the resist mask 101 is removed by ashing. - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + The mold FS layer 20 is formed (8th step, 7th step). - The amount of crystal defects varies on the rear surface of the n-type semiconductor substrate 18, and in the region with a high density of crystal defects, the n-type impurity + The electrons are less likely to pass through the n-type cathode region 82. + The FS layer 20 is formed in a wavy shape. Therefore, in the fifth embodiment, a wavy n-type FS layer is formed in the IGBT and the diode by one ion implantation. + It is possible to form a mold FS layer 20. The state up to this point is illustrated in FIG.

[0118] Thereafter, the steps from the heat treatment (annealing) in the first embodiment onwards are carried out to complete the IGBT or diode.

[0119] As described above, according to the fifth embodiment, the IGBT and the diode are provided with wavy n-type contacts in the same manner as in the fourth embodiment. + A type FS layer can be formed, which provides the same effects as those of the fourth embodiment.

[0120] (Embodiment 6) The structure of the semiconductor device according to the sixth embodiment is the same as the structure of the semiconductor device according to the fourth embodiment, that is, the structure of the IGBT alone and the diode alone.

[0121] (Method of manufacturing a semiconductor device according to the sixth embodiment) Next, a method for manufacturing a semiconductor device according to the sixth embodiment will be described. Figs. 19 to 22 are cross-sectional views showing the state of an active region 90 during the manufacturing process of a semiconductor device according to the sixth embodiment. Figs. 19 to 22 show the state of the active region 90 during the manufacturing process when an IGBT is formed, and the state of the active region 90 during the manufacturing process when a diode is formed is p + The part of the collector region 22 is n+ This forms the cathode region 82.

[0122] First, as in the first embodiment, the n-type drift layer - A front surface element structure is formed on the front surface side of the mold semiconductor substrate 18 (first to fourth steps, first to third steps).

[0123] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness that corresponds to the thickness of the product to be used as a semiconductor device. - The entire rear surface of the semiconductor substrate 18 is ion-implanted 100 with p-type impurities or n-type impurities such as boron (B) or phosphorus (P), - The surface layer of the entire back surface of the semiconductor substrate 18 is p + Type collector region 22 or n + The p-type cathode region 82 is formed (fifth step, fourth step). If there are any areas where the p-type impurities or n-type impurities are not implanted due to particles or the like, this will result in poor voltage resistance. - In order to prevent the process from proceeding with the back surface of the semiconductor substrate 18 exposed, p-type or n-type impurities are ion-implanted immediately after the implantation surface is clean. The state up to this point is shown in FIG.

[0124] Next, by photolithography, - On the rear surface of the n-type semiconductor substrate 18, + A resist mask 101 is formed with openings in areas corresponding to the areas where the mold FS layer 20 is to be shallowly formed. Next, Ar or Si ions are implanted 100 using this resist mask 101 as a mask. In the areas where Ar or Si is implanted, crystal defects are broken down, and the areas become areas with a low density of crystal defects (seventh step, sixth step). The state up to this point is shown in FIG. 20.

[0125] Next, the resist mask 101 is removed by ashing. -Laser annealing 102 is performed from the backside of the semiconductor substrate 18. The p-type impurity or n-type impurity ion implanted is activated by irradiating it with a laser having higher energy than the band edge and heating it (steps 6 and 5). At this time, the intensity of the laser annealing 102 is uniform. The state up to this point is shown in FIG. 21.

[0126] Next, n - An n-type impurity such as phosphorus is ion-implanted 100 onto the entire rear surface of the n-type semiconductor substrate 18, - Inside the n-type semiconductor substrate 18 + The mold FS layer 20 is formed (8th step, 7th step). - Due to the influence of ion implantation 100, there is a difference in the amount of crystal defects on the rear surface of the n-type semiconductor substrate 18 even after laser annealing 102. In the region with a high density of crystal defects, the n-type impurities + The electrons are less likely to pass through the n-type cathode region 82. + The FS layer 20 is formed in a wavy shape. Therefore, in the fifth embodiment, a wavy n-type FS layer is formed in the IGBT and the diode by one ion implantation. + The state up to this point is shown in FIG. 22. In the sixth embodiment, the laser annealing 102 is performed after ion implantation of p-type impurities or n-type impurities, so the amount of crystal defects can be reduced compared to the fifth embodiment, and the n-type impurity layer 20 can be formed. + The difference in depth of the mold FS layer 20 can be made smaller than that in the fifth embodiment.

[0127] Thereafter, the steps from the heat treatment (annealing) in the first embodiment onwards are carried out to complete the IGBT or diode.

[0128] As described above, according to the sixth embodiment, the IGBT and the diode are provided with wavy n-type contacts in the same manner as in the fourth embodiment. + A type FS layer can be formed, which provides the same effects as those of the fourth embodiment.

[0129] Next, a method for creating regions with high and low laser annealing intensity will be described. FIGS. 23 to 25 are diagrams showing methods for creating regions with high and low laser annealing intensity. In FIG. 23, the laser scanning speed is changed during laser annealing. For example, by slowing the laser scanning speed as shown in FIG. 23A, the time the laser is irradiated per unit area can be increased, thereby forming regions with high laser annealing intensity. Furthermore, by increasing the laser scanning speed as shown in FIG. 23B, the time the laser is irradiated per unit area can be reduced, thereby forming regions with low laser annealing intensity. Furthermore, by keeping the laser scanning speed the same and thinning out the laser pulses using an electrical filter or the like, the amount of laser irradiated per unit area can be reduced, thereby forming regions with low laser annealing intensity.

[0130] In Figure 24, the overlap of the laser pulses is changed during laser annealing. For example, when shifting the scan line as shown in Figure 24A, the shift length is shortened to increase the overlap with adjacent scan lines, thereby increasing the number of laser irradiations per unit area and forming a region with high laser annealing intensity. Also, when shifting the scan line as shown in Figure 24B, the shift length is lengthened to reduce the overlap with adjacent scan lines, thereby reducing the number of laser irradiations per unit area and forming a region with low laser annealing intensity. For example, by irradiating the same location with the laser four times, a region with high laser annealing intensity is formed, and by irradiating the same location with the laser twice, a region with low laser annealing intensity is formed. This method can be applied to continuous wave lasers as well as pulsed lasers.

[0131] In Figure 25, the laser pulse energy is changed during laser annealing. For example, by increasing the laser pulse energy as shown in Figure 25A, the laser energy irradiated per unit area is increased, creating a region with high laser annealing intensity. Also, by decreasing the laser pulse energy as shown in Figure 25B, the laser energy irradiated per unit area is reduced, creating a region with low laser annealing intensity. For example, by irradiating the laser through a mask (shutter / filter), it is possible to create a laser intensity distribution with any desired pattern, thereby increasing the laser intensity at any desired position on the substrate. This method can also be applied to continuous wave lasers, not just pulsed lasers.

[0132] In addition, it is possible to create areas with strong and weak laser annealing intensity by changing the wavelength of the laser. Of these, since the pulsed laser spot is rectangular, it is preferable to change the overlap or thin out the laser pulses using a filter.

[0133] In the above, the present invention has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon substrate, but the present invention is not limited to this and various changes can be made to the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, etc. Furthermore, in the first embodiment of the present invention, a trench-type RC-IGBT has been described as an example, but the present invention is not limited to this and can be applied to semiconductor devices with various configurations, such as planar-type semiconductor devices. Furthermore, in each of the first embodiments of the present invention, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0134] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0135] 11 p + Mold well area 12n + Type emitter area 14 p-type base region 16 n-type storage layer 18, 118 n - semiconductor substrate 20, 120 n + type FS layer 22, 122 p. + Type Collector Region 24 Back electrode 30 Dummy Trench 38 Interlayer insulating film 40 Gate Trench 50 Gate insulating film 51 gate electrode 52 Emitter electrode 70 IGBT area 72 Lifetime Control Area 80 Diode Region 82, 182 n + Type cathode area 90 active area 91 Edge Termination Area 92 Guard Ring 94 Field plate electrode 100, 200 ion implantation 101, 201 resist mask 102 Laser annealing 130 Front electrode 150 RC-IGBT 174n + Type Channel Stopper

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate; a second semiconductor region of a first conductivity type selectively provided in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a gate insulating film in contact with the first semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a first semiconductor layer of a first conductivity type provided inside the semiconductor substrate; a third semiconductor region of a second conductivity type provided on a back surface side of the semiconductor substrate; a first electrode provided on the surface of the first semiconductor region and the second semiconductor region; a second electrode provided on a surface of the third semiconductor region; a transistor portion having the semiconductor substrate; the first semiconductor region; the first semiconductor layer; a fourth semiconductor region of the first conductivity type provided on the back surface side of the semiconductor substrate; the first electrode provided on a surface of the first semiconductor region; the second electrode provided on a surface of the fourth semiconductor region; a diode portion having Equipped with a first semiconductor layer in the transistor section having a depth from a rear surface of the semiconductor substrate that is greater than a depth from a rear surface of the semiconductor substrate that is greater than a depth from a rear surface of the semiconductor substrate that is greater than a depth from a rear surface of the semiconductor layer in the diode section;

2. a thickness of the first semiconductor layer in the transistor section is the same as a thickness of the first semiconductor layer in the diode section; 2. The semiconductor device according to claim 1, wherein in the transistor section, the semiconductor substrate is present between the first semiconductor layer and the third semiconductor region.

3. an active region including the transistor portion and the diode portion and through which a current flows; a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region; The termination structure includes: the semiconductor substrate; the first semiconductor layer; the fourth semiconductor region; the second electrode; and 3. The semiconductor device according to claim 1, wherein a depth of the first semiconductor layer of the diode portion from a back surface of the semiconductor substrate is the same as a depth of the first semiconductor layer of the termination structure portion from a back surface of the semiconductor substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the transistor portion and the diode portion, when viewed from above, comprise the transistor portion and the diode portion, and are arranged in parallel within an active region through which current flows.

5. A method for manufacturing a semiconductor device having a transistor portion and a diode portion, comprising: a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming, in the transistor portion, a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming first electrodes on surfaces of the first semiconductor region and the second semiconductor region of the transistor section and on a surface of the first semiconductor region of the diode section; a fifth step of increasing the amount of crystal defects in a back surface layer of the semiconductor substrate corresponding to the diode portion to be greater than the amount of crystal defects in a back surface layer of the semiconductor substrate corresponding to the transistor portion; a sixth step of implanting impurities of a first conductivity type into the back surface side of the semiconductor substrate after the fifth step and before performing an annealing treatment, to form a first semiconductor layer of the first conductivity type; a seventh step of forming a third semiconductor region of a second conductivity type on a back surface of the semiconductor substrate corresponding to the transistor portion; an eighth step of forming a fourth semiconductor region of the first conductivity type on a back surface of the semiconductor substrate corresponding to the diode portion; a ninth step of forming a second electrode on surfaces of the third semiconductor region and the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein phosphorus (P) is used to form the first semiconductor layer.

7. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the method is performed by ion implantation of argon (Ar), xenon (Xe), or silicon (Si) so that the amount of crystal defects in the back surface layer corresponding to the diode portion is greater than the amount of crystal defects in the back surface layer corresponding to the transistor portion.

8. A method for manufacturing a semiconductor device having a transistor portion and a diode portion, comprising: a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming, in the transistor portion, a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming first electrodes on surfaces of the first semiconductor region and the second semiconductor region of the transistor section and on a surface of the first semiconductor region of the diode section; a fifth step of injecting impurities of the second conductivity type into the back surface side of the semiconductor substrate to form a third semiconductor region of the second conductivity type; a sixth step of implanting an impurity of the first conductivity type into the third semiconductor region corresponding to the diode portion to form a fourth semiconductor region of the first conductivity type; a seventh step of implanting impurities of a first conductivity type into the back surface side of the semiconductor substrate after the sixth step and before performing an annealing treatment, to form a first semiconductor layer of the first conductivity type; an eighth step of forming a second electrode on the surfaces of the third semiconductor region and the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the impurity implanted in the fifth step is boron (B), and the impurity implanted in the sixth step is phosphorus (P) or arsenic (As).

10. A method for manufacturing a semiconductor device having a transistor portion and a diode portion, comprising: a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming, in the transistor portion, a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming first electrodes on surfaces of the first semiconductor region and the second semiconductor region of the transistor section and on a surface of the first semiconductor region of the diode section; a fifth step of injecting impurities of the second conductivity type into the back surface side of the semiconductor substrate to form a third semiconductor region of the second conductivity type; a sixth step of performing laser annealing for activating the third semiconductor region by setting the intensity of laser annealing for the third semiconductor region corresponding to the diode portion to be weaker than the intensity of laser annealing for the third semiconductor region corresponding to the transistor portion; a seventh step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; an eighth step of injecting an impurity of the first conductivity type into the third semiconductor region corresponding to the diode portion to form a fourth semiconductor region of the first conductivity type; a ninth step of forming a second electrode on surfaces of the third semiconductor region and the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

11. A method for manufacturing a semiconductor device having a transistor portion and a diode portion, comprising: a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming, in the transistor portion, a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming first electrodes on surfaces of the first semiconductor region and the second semiconductor region of the transistor section and on a surface of the first semiconductor region of the diode section; a fifth step of injecting impurities of the second conductivity type into the back surface side of the semiconductor substrate to form a third semiconductor region of the second conductivity type; a sixth step of implanting an impurity of the first conductivity type into the third semiconductor region corresponding to the diode portion to form a fourth semiconductor region of the first conductivity type; a seventh step of performing laser annealing for activating the third semiconductor region and the fourth semiconductor region, with the intensity of laser annealing for the fourth semiconductor region being weaker than the intensity of laser annealing for the third semiconductor region; an eighth step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; a ninth step of forming a second electrode on surfaces of the third semiconductor region and the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

12. a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate; a second semiconductor region of a first conductivity type selectively provided in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a gate insulating film in contact with the first semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a first semiconductor layer of a first conductivity type provided inside the semiconductor substrate; a third semiconductor region of a second conductivity type provided on a back surface side of the semiconductor substrate; a first electrode provided on the surface of the first semiconductor region and the second semiconductor region; a second electrode provided on a surface of the third semiconductor region; Equipped with a depth from the rear surface of the semiconductor substrate in a predetermined region of the first semiconductor layer is greater than a depth from the rear surface of the semiconductor substrate in a region other than the predetermined region of the first semiconductor layer; a third semiconductor region provided in the active region; a termination structure including the semiconductor substrate, the first semiconductor layer, and the second electrode; and a depth of the first semiconductor layer in the active region from a back surface of the semiconductor substrate that is greater than a depth of the first semiconductor layer in the termination structure from the back surface of the semiconductor substrate by a thickness of the third semiconductor region.

13. a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming a first electrode on surfaces of the first semiconductor region and the second semiconductor region; a fifth step of injecting impurities of the second conductivity type into the back surface side of the semiconductor substrate to form a third semiconductor region of the second conductivity type; a sixth step of performing laser annealing for activating the third semiconductor region with a laser annealing intensity for a predetermined region of the third semiconductor region being weaker than a laser annealing intensity for a region other than the predetermined region of the third semiconductor region; a seventh step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; an eighth step of forming a second electrode on a surface of the third semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

14. a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming a gate insulating film in contact with the first semiconductor region and a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; a fourth step of forming a first electrode on surfaces of the first semiconductor region and the second semiconductor region; a fifth step of injecting impurities of the second conductivity type into the back surface side of the semiconductor substrate to form a third semiconductor region of the second conductivity type; a sixth step of performing laser annealing for activating the third semiconductor region; a seventh step of ion-implanting Ar (argon) or silicon (Si) into a predetermined region of the third semiconductor region; an eighth step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; a ninth step of forming a second electrode on a surface of the third semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the sixth step is performed after the seventh step and before the eighth step.

16. a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate; a first semiconductor layer of a first conductivity type provided inside the semiconductor substrate; a fourth semiconductor region of the first conductivity type provided on the back surface side of the semiconductor substrate; a first electrode provided on a surface of the first semiconductor region; a second electrode provided on a surface of the fourth semiconductor region; Equipped with an active region through which a current flows; and a termination structure portion disposed outside the active region and having a breakdown voltage structure surrounding the active region; a depth from the back surface of the semiconductor substrate of a predetermined region of the active region of the first semiconductor layer is greater than a depth from the back surface of the semiconductor substrate of a region other than the predetermined region of the active region of the first semiconductor layer, and the termination structure has the semiconductor substrate, the first semiconductor layer, the fourth semiconductor region, and the second electrode, and a depth from the back surface of the semiconductor substrate of the first semiconductor layer in a region other than the predetermined region of the active region is the same as a depth of the termination structure of the first semiconductor layer from the back surface of the semiconductor substrate.

17. a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming a first electrode on a surface of the first semiconductor region; a fourth step of injecting impurities of the first conductivity type into the back surface side of the semiconductor substrate to form a fourth semiconductor region of the first conductivity type; a fifth step of performing laser annealing for activating the fourth semiconductor region with a laser annealing intensity for a predetermined region of the fourth semiconductor region being weaker than a laser annealing intensity for a region other than the predetermined region of the fourth semiconductor region; a sixth step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; an eighth step of forming a second electrode on a surface of the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

18. a first step of forming a first semiconductor region of a second conductivity type on a front surface side of a semiconductor substrate; a second step of selectively forming a second semiconductor region of the first conductivity type in a surface layer of the first semiconductor region on the opposite side to the semiconductor substrate; a third step of forming a first electrode on a surface of the first semiconductor region; a fourth step of injecting impurities of the first conductivity type into the back surface side of the semiconductor substrate to form a fourth semiconductor region of the first conductivity type; a fifth step of performing laser annealing for activating the fourth semiconductor region; a sixth step of ion-implanting Ar (argon) or silicon (Si) into a predetermined region of the fourth semiconductor region; a seventh step of injecting impurities of a first conductivity type into the back surface side of the semiconductor substrate to form a first semiconductor layer of the first conductivity type; an eighth step of forming a second electrode on a surface of the fourth semiconductor region; 10. A method for manufacturing a semiconductor device, comprising:

19. 19. The method for manufacturing a semiconductor device according to claim 18, wherein the fifth step is performed after the sixth step and before the seventh step.

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