Substrate processing apparatus and substrate processing method

Abstract

To provide a substrate processing device capable of enhancing throughput and saving space.SOLUTION: The substrate processing device includes: a loading / unloading block; a processing station, between which and the loading / unloading block, a substrate is transferred, and which is provided on either right or left side with respect to the loading / unloading block; a relay block which is provided on either right or left side with respect to the processing station, and between which and the processing station, the substrate is transferred; processing blocks which each comprise a processing module for performing processing on the substrate, and a main transfer mechanism for transferring the substrate to and from the processing module, and which are arranged in plurality respectively on right and left sides to constitute the processing station; and bypass transfer mechanisms which are provided independently of the main transfer mechanism, and each provided on each of the processing blocks arranged on the right and left sides. As transfer paths for the substrates transferred by the bypass transfer mechanisms, bypass transfer paths are provided, being mutually different in height, and partially overlapping each other in plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing apparatus and a substrate processing method. [Background technology]

[0002] In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as wafers) are transported between various processing modules to undergo various processes such as liquid processing and heat treatment. Patent Document 1 describes a coating and developing apparatus including processing blocks S2 and S4, each of which includes a plurality of unit blocks stacked on top of each other, each of which is provided with a plurality of processing modules, and a main arm provided for each unit block to transport wafers between the processing modules. The processing blocks S2 and S4 are sandwiched between a carrier block and an exposure device, and a block S3 is interposed between the processing blocks S2 and S4 to transport wafers up and down. Furthermore, the unit blocks below each processing block S2 and S4 are provided with a plurality of shuttle arms, which serve as a transport mechanism separate from the main arm and transport wafers without passing through the processing modules.

[0003] Wafers transferred to block S3 using the shuttle arm of processing block S2 are sorted to the upper unit blocks of processing blocks S2 and S4, then returned to block S3 and transferred to the exposure device using the shuttle arm of processing block S4. Thereafter, when processing is performed in one of processing blocks S2 and S4, the wafers are transferred to the carrier block side using the shuttle arm so as to bypass the processing modules of the block that is not performing processing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-258208 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a technique for increasing throughput and saving space in a substrate processing apparatus. [Means for solving the problem]

[0006] The substrate processing apparatus according to the present disclosure includes: a loading / unloading block for loading and unloading a substrate; a processing station provided on one of the left and right sides of the load-out block, through which the substrate is transported between the load-out block and the processing station; a relay block provided on one of the left and right sides of the processing station, through which the substrate is transported between the processing station and the relay block; a plurality of processing blocks arranged side by side to form the processing station, each of which includes a processing module for processing the substrate and a main transport mechanism for transferring the substrate to the processing module; a bypass transport mechanism provided for each of the processing blocks arranged on the left and right to transport substrates between the left and right blocks, separate from the main transport mechanism; The bypass transport paths, which are transport paths for substrates by the bypass transport mechanism, are different in height and partially overlap each other in plan view. the law of nature, The bypass transport mechanism includes a base body provided in the processing block; a movable body that moves left and right relative to the base body; a substrate support that supports the substrate and moves left and right relative to the moving body; Equipped with The processing modules are provided in plurality, arranged side by side, the main transport mechanism includes pillars provided between the plurality of processing modules in a plan view, The bypass transport path includes a transport path in the front-rear direction, and is a detour route for the substrate to bypass the pillar. The substrate processing apparatus according to the present disclosure includes: a loading / unloading block for loading and unloading a substrate; a processing station provided on one of the left and right sides of the load-out block, through which the substrate is transported between the load-out block and the processing station; a relay block provided on one of the left and right sides of the processing station, through which the substrate is transported between the processing station and the relay block; a plurality of processing blocks arranged side by side to form the processing station, each of which includes a processing module for processing the substrate and a main transport mechanism for transferring the substrate to the processing module; a bypass transport mechanism provided for each of the processing blocks arranged on the left and right to transport substrates between the left and right blocks, separate from the main transport mechanism; The bypass transport paths, which are transport paths for substrates by the bypass transport mechanism, are different in height and partially overlap each other in a plan view; At least three processing blocks are provided, in the order of a first processing block, a second processing block, and a third processing block, from one side to the other, and the bypass transport paths of the respective bypass transport mechanisms are designated as a first bypass transport path, a second bypass transport path, and a third bypass transport path, a left end of the second bypass conveying path overlaps with one of the first bypass conveying path and the third bypass conveying path in a plan view, and a right end of the second bypass conveying path overlaps with the other of the first bypass conveying path and the third bypass conveying path in a plan view, The first bypass transport path and the third bypass transport path are located above or below the second bypass transport path. [Effects of the Invention]

[0007] The present disclosure provides a substrate processing apparatus that can increase throughput and reduce space requirements. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional plan view of a substrate processing apparatus according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a vertical sectional front view of the substrate processing apparatus. [Figure 3] FIG. 2 is a vertical sectional front view of the substrate processing apparatus. [Figure 4] FIG. 2 is a vertical sectional side view of the substrate processing apparatus. [Figure 5] FIG. 2 is a cross-sectional plan view of a shuttle provided in the substrate processing apparatus. [Figure 6] FIG. [Figure 7] FIG. 2 is a top perspective view of a wafer transfer unit provided in the shuttle. [Figure 8] FIG. 2 is a perspective view of the bottom surface of the wafer transfer unit. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] FIG. 10 is a graph showing the speed of the shuttle moving in the left-right direction. [Figure 12] FIG. 4 is an explanatory view showing the position of the wafer transfer unit. [Figure 13] FIG. 2 is a plan view of a wafer transport path by the shuttle. [Figure 14] FIG. 2 is an explanatory view showing a wafer transfer path in the substrate processing apparatus. [Figure 15] FIG. 10 is a schematic front view showing a modified example of the substrate processing apparatus. [Figure 16] FIG. 10 is a schematic front view of a substrate processing apparatus according to a second embodiment. [Figure 17]FIG. 2 is an explanatory view showing a wafer transfer path in the substrate processing apparatus. DETAILED DESCRIPTION OF THE INVENTION

[0009] [First embodiment] A substrate processing apparatus 1 according to a first embodiment of the present disclosure will be described with reference to the cross-sectional plan view of FIG. 1 and the longitudinal front views of FIG. 2 and FIG. 3. FIGS. 2 and 3 show cross sections at different positions of the apparatus. The substrate processing apparatus 1 includes a carrier block D1, a first stacked processing block D2, a second stacked processing block D3, and an interface block D4, which are arranged in this order in a horizontal linear fashion. Adjacent blocks (carrier block, first and second stacked processing blocks, interface block) D1 to D4 are connected to each other. Each of the blocks D1 to D4 is partitioned by a housing, and a transport area for wafers W, which are circular substrates, is formed inside each housing.

[0010] The arrangement direction of the blocks D1 to D4 is the left-right direction, and for convenience of explanation, the carrier block D1 side is the left side and the interface block D4 is the right side. Furthermore, in the front-to-rear direction of the device, when the carrier block D1 is on the left, the front is the front and the back is the rear. The interface block D4, which is a relay block, is connected to the exposure machine 20 from the right side.

[0011] Before describing each of the blocks D1 to D4 in detail, we will describe the general configuration of the substrate processing apparatus 1. Wafers W are transported to the carrier block D1 while stored in carriers C, such as a FOUP (Front Opening Unify Pod), and a resist film is formed on the surface of the wafer W. The substrate processing apparatus 1 includes processing modules that perform various processes, such as a cleaning process and a development process, which are liquid processes, and a post-exposure bake (PEB) process for the wafer W after exposure and before development, and also transfers the wafer W to an exposure machine 20 to expose the resist film before the PEB process.

[0012] The first stacked processing block D2 and the second stacked processing block D3 constitute a processing station G where various processes, including liquid processing, are performed. The first stacked processing block D2 and the second stacked processing block D3 are each divided vertically into two sections, each of which constitutes a processing block equipped with a processing module and a main transport mechanism capable of transferring materials to and from the processing module. The lower and upper sections of the first stacked processing block D2, which is divided into two sections as described above, are designated processing block 2A and processing block 2B, respectively, and the lower and upper sections of the second stacked processing block D3, which is divided into two sections, are designated processing block 2C and processing block 2D, respectively.

[0013] Processing blocks 2A and 2C are adjacent to each other and may be collectively referred to as the lower processing blocks. Processing blocks 2B and 2D are adjacent to each other and may be collectively referred to as the upper processing blocks, and FIG. 1 shows these upper processing blocks. Each of these upper processing blocks, processing blocks 2B and 2D, is provided with a transfer mechanism (bypass transfer mechanism) separate from the main transfer mechanism. This separate transfer mechanism will hereinafter be referred to as a shuttle. This shuttle transfers wafers W to downstream blocks on the transfer path without passing through the processing modules.

[0014] The lower processing block forms an outgoing path for transporting wafers W from carrier block D1 to interface block D4. The upper processing block forms a return path for transporting wafers W that have been exposed in exposure machine 20 from interface block D4 to carrier block D1. On the return path, wafers W are transported to a processing module by a transfer mechanism in one of processing blocks 2B and 2D for processing, and then transported by a shuttle in the other processing block. In other words, there are two transfer paths on the return path, and wafers W are transported via one of these two paths. Note that a module is a location other than the transfer mechanism (including the shuttle) where wafers W are placed. A module that processes wafers W is referred to as a processing module as described above, but this processing also includes acquiring images for inspection.

[0015] Each block will be described below. Carrier block D1 is a load / unload block that loads and unloads wafers W into and from carriers C that store wafers W. Three support platforms for supporting carriers C are arranged vertically on the left side of the housing that constitutes carrier block D1, and are designated support platforms 11, 12, and 13 from bottom to top. Each of support platforms 11 to 13 has four stages for carriers C arranged front to back. The two stages in front of support platforms 11 and 12 are stages 14 on which carriers C are placed to load and unload wafers W into and from the apparatus. The other stages are designated as stages 15 and are configured as stages for loading and unloading carriers C into and from substrate processing apparatus 1, or as stages to which carriers C are temporarily retracted when they cannot be transferred to their destination. A transfer mechanism 16 is provided to transfer carriers C between stages 14 and 15.

[0016] Transport mechanisms 18 and 19 are provided on the front and rear sides of a transport region 17 within the housing of carrier block D1, and a module stack T1 is provided between the transport mechanisms 18 and 19 in plan view. The module stack T1 is configured by vertically stacking a transfer module TRS on which wafers W are temporarily placed, a temperature control module SCPL that adjusts the temperature of the placed wafers W, and other modules. Note that other module stacks described below also have a similar configuration. Note that in this specification, when modules overlap each other in plan view, they are considered to form a stack even if they are separated from each other.

[0017] The temperature control module SCPL can adjust the temperature of the wafer W placed thereon, and the wafer W is transferred by the lifting and lowering motion of the transfer mechanism. The transfer module TRS has, for example, multiple pins arranged horizontally, and the wafer W is transferred to and from these pins by the lifting and lowering motion of the transfer mechanism. TRSs and SCPLs are also provided in blocks other than the carrier block D1 to form module stacks, and some of the modules constituting each module stack have the role of transferring wafers W between blocks. The shuttle TRS, which transfers wafers W to and from the shuttle, differs from the above-mentioned configuration in that it can be raised and lowered, but will be described in detail together with the shuttle. In the following, the SCPLs and TRSs at each location are identified by numbers after the SCPLs and TRSs to distinguish them from one another. The modules constituting the module stack T1 are designated TRS1, TRS2, SCPL1, TRS3, and SCPL2 from bottom to top.

[0018] SCPL1 is located at the height of the lower processing block to form the outbound path, while TRS3 and SCPL2 are located at the height of the upper processing block to form the return path. TRS1 and TRS2 are used to transfer wafers W between transfer mechanisms 18 and 19. To transport wafers W along the transfer path shown in FIG. 14, transfer mechanism 18 can access TRS1 and TRS2, and transfer mechanism 19 can access TRS1 to TRS3, SCPL1, and shuttle TRS 12B. A pre-processing inspection module 29 is provided between the modules constituting module stack T1, and a portion of the pre-processing inspection module 29 protrudes outside the block housing. The pre-processing inspection module 29 acquires the above-mentioned images for inspection of wafers W before they are processed in the substrate processing apparatus 1. The transfer mechanism 18 can also access the inspection module 29.

[0019] Next, the first stacked processing block D2 (processing blocks 2A and 2B) will be described with reference to FIG. 4, which is a vertical cross-sectional side view. The front side of the first stacked processing block D2 is vertically partitioned to form eight stories, which are numbered E1 to E8 from bottom to top. The lower stories E1 to E4 are included in processing block 2A, and the upper stories E5 to E8 are included in processing block 2B. Each story is an area where a liquid processing module can be installed.

[0020] First, regarding the processing block 2B, each of the stories E5 to E8 is provided with a liquid processing module, a developing module 21 that supplies a developer to a wafer W. A transfer area 22 for wafers W is provided behind the stories E5 to E8. This transfer area 22 is linearly formed in a plan view, extending from the left end to the right end of the processing block 2B and from the height of story E5 to the height of story E8. Behind the transfer area 22, processing modules are stacked vertically in seven levels, forming a processing module stack 23. Two processing module stacks 23 are provided laterally, spaced apart. The two processing module stacks 23 include a heating module 24 that performs PEB and a post-processing inspection module 25. The post-processing inspection module 25 is similar to the pre-processing inspection module 29, except that the image of the post-processing inspection module 25 is acquired from a wafer W after processing in the apparatus.

[0021] The processing block 2B is provided with a main transfer mechanism 3B. The main transfer mechanism 3B includes a support column 31, a main body 32, and a holder 33 for holding a wafer W. The support column 31 supporting the main body 32 extends vertically from the lower end to the upper end of the processing block 2B at the center of the left and right sides of the processing block 2B, sandwiched between the two processing module stacks 23. More specifically, the support column 31 is located at the front end of the area between the two processing module stacks 23. The base end of the main body 32, which is an articulated arm, is supported by the front side of the support column 31 and provided in the transfer region 22, and moves up and down along the extension direction of the support column 31. A mechanism for raising and lowering the main body 32 in this manner is provided, for example, on the support column 31. The arm at the tip end of the main body 32 is configured as a base for independently moving the two holders 33 forward and backward.

[0022] The main transport mechanism 3B delivers wafers W to and from each processing module in the processing block 2B and to modules located at the same height as the processing block 2B in the module stacks (T1 and T2, described later) provided in blocks adjacent to the processing block 2B. The main transport mechanism 3B can also deliver wafers W to and from a shuttle TRS, described later, provided in the processing block 2B.

[0023] The lower side of the processing module stack 23 is configured as a partitioned, flat space 5B, which is provided from the left end to the right end of the processing block 2B. The support columns 31 are positioned so as to fit into the front ends of the left and right centers of this space 5B. Therefore, the front ends of the left and right centers of the space 5B are recessed toward the rear. A shuttle 4B and shuttle TRSs 12B and 12D are provided in this space 5B. These shuttles and shuttle TRSs will be described in detail later.

[0024] The processing blocks other than processing block 2B, which will be described below, are generally configured similarly to processing block 2B, except for differences that will be explained later. Each processing block is equipped with a main transport mechanism equivalent to main transport mechanism 3B, and the reference numerals for these main transport mechanisms are designated by the same alphabetic character as that of the processing block, instead of "B." Specifically, for processing block "2A," its main transport mechanism is designated as "3A." Furthermore, the other main transport mechanisms equivalent to main transport mechanism 3B are also configured to transfer wafers W to and from the processing modules and shuttle TRSs within the processing block in which the main transport mechanism is installed, as well as to the module stacks within the processing block or in blocks adjacent to the processing block in the horizontal direction.

[0025] Furthermore, the symbol for a space corresponding to the above-described space 5B where a shuttle can be installed is indicated by the same alphabetical character as that attached to the processing block instead of "B." Furthermore, if a shuttle is provided in a processing block, the symbol for that shuttle is also indicated by the same alphabetical character as that attached to the processing block. The shuttle TRS is indicated by the same alphabetical character as the processing block in which the shuttle is provided, with the source TRS indicated by "11" and the destination TRS indicated by "12." The transfer path for wafers W by the shuttle is indicated by the numeral "40" followed by the same alphabetical character as that attached to the shuttle. To give a specific example of the above symbol convention, the shuttle provided in the processing block 2D described below is indicated as 4D. The source and destination TRSs of this shuttle 4D are indicated as TRS11D and TRS12D, respectively, the transfer path for wafers W by shuttle 4D is indicated as 40D, and the space in which shuttle 4D is provided is indicated as 5D.

[0026] Returning to the explanation of the processing block configuration, processing block 2A below processing block 2B will be described using FIG. 4. Differences from processing block 2B include the provision of a backside cleaning module 26, which supplies a cleaning liquid to the backside of wafer W as a liquid processing module, on each of stories E1 to E4, and the provision of a transfer region 22 spanning the height of stories E1 to E4. Furthermore, the processing modules constituting the processing module stack 23 include an edge exposure module 27 for removing unnecessary resist film from the peripheral edge of wafer W during development. In processing block 2A, a space 5A is provided above, rather than below, the processing module stack 23; however, in this example, no shuttle is provided in this space 5A. While the vertical positional relationship between the space and the processing module stack 23 differs from that of processing block 2B, in processing block 2A, a support column 31 of a main transfer mechanism 3A is provided between the two processing module stacks 23. The layout of processing module stack 23, main transport mechanism 3A, transport area 22, and liquid processing modules in plan view is the same as the layout of processing block 2B.

[0027] Next, the second stacked processing block D3 (processing blocks 2C and 2D), which constitutes each processing block on the right side of the apparatus, will be described using Figures 1 to 3. The second stacked processing block D3 has a configuration substantially similar to that of the first stacked processing block D2, and differences from the first stacked processing block D2 will be mainly described. First, the upper processing block 2D is described. The positional relationship of the transfer region 22, processing module stack 23, main transport mechanism, and spaces for installing shuttles stacked on the processing modules is the same as that of the processing block 2B. The processing modules installed in the processing block 2D are the same as those in the processing block 2B. The shuttle space 5D in the processing block 2D is located at the same height as the space 5B and is connected to the space 5B. The shuttle 4D and shuttle TRSs 11B and 11D are provided in the space 5D.

[0028] The lower processing block 2C has substantially the same configuration as the lower processing block 2A, with the difference being that stories E1 to E4 are provided with post-exposure cleaning modules 28 that supply a cleaning liquid to the surface of the wafer W to clean it after exposure by the exposure machine 20. Furthermore, no processing other than the cleaning is performed in processing block 2C, and processing module stack 23 is not provided. Space 5C is located at the same height as space 5A and communicates with space 5A, but in this example, no shuttle is provided in this space 5C.

[0029] Meanwhile, a module stack T2 is provided at the left end of the transfer area 22 of the second stack processing block D3, and is positioned so that a portion of the module stack T2 overlaps the right end of the transfer area 22 of the first stack processing block D2 in plan view. The module stack T2 includes a TRS4 located at the height of the lower processing block and an SCPL3 located at the height of the upper processing block.

[0030] The interface block D4 will now be described. The interface block D4 has a module stack T3 in the center between the front and rear. This module stack T3 includes TRS5 to TRS8 and a temperature adjustment module ICPL, which are stacked on top of each other. The ICPL adjusts the temperature of the wafer W just before exposure by the exposure device 20, similar to the SCPL. TRS5 to TRS7 are located at the height of the lower processing block, and TRS8 is located at the height of the upper processing block. Transfer mechanisms 34 and 35 are located in front and behind the module stack T3, respectively. The transfer mechanism 34 transfers the wafer W between the exposure device 20, TRS5, and the ICPL, which is located near the bottom of the module stack T3. The transfer mechanism 35 transfers the wafer W between each module constituting the module stack T3 and the shuttle TRS11D in the processing block 2D.

[0031] Next, the shuttles 4B and 4D and the shuttle TRSs 11B, 12B, 11D, and 12D will be described. By using the shuttles 4B and 4D as described above, the return route of the wafer W includes two transfer paths. On one of the transfer paths, the wafer W is transferred from the interface block D4 to the processing block 2D, processed in the processing block 2D, and then transferred by the shuttle 4B from the TRS 11B to the TRS 12B in the processing block 2B and returned to the carrier block D1. On the other transfer path, the wafer W is transferred from the interface block D4 to the TRS 11D in the processing block 2D, transferred by the shuttle 4D to the TRS 12D in the processing block 2B, processed in the processing block 2B, and returned to the carrier block D1.

[0032] 1, of the TRSs 11B and 12B for the shuttle 4B, the destination TRS 12B is located at the left end of the space 5B, i.e., to the left of the support columns 31 of the main transport mechanism 3B, so that the wafer W can be transferred to and from the transport mechanism 19 in the carrier block D1. The source TRS 11B is located to the left of the support columns 31 of the main transport mechanism 3D and to the right of the module stack T2, so that the wafer W can be transferred to and from the main transport mechanism 3D while preventing the transport area of the shuttle 4B from becoming larger. Of the TRSs 11D and 12D for the shuttle 4D, the source TRS 11D is located at the right end of the space 5D, i.e., to the right of the support columns 31 of the main transport mechanism 3D, so that the wafer W can be transferred to and from the transport mechanism 35 in the interface block D4. The destination TRS12D is located to the right of the support pillar 31 of the main transport mechanism 3B and to the left of the module stack T2 so as to enable the transfer of wafer W between the main transport mechanism 3B and the shuttle 4D while preventing the transport area from becoming too large.

[0033] These shuttle TRSs 11B, 12B, 11D, and 12D are all located near the front of the space 5B or 5D so that transfer mechanisms other than the shuttle can receive and transfer wafers W. Therefore, in a plan view, the support pillar 31 of the main transfer mechanism 3B is located on the line connecting TRSs 11B and 12B, and the support pillar 31 of the main transfer mechanism 3D is located on the line connecting TRSs 11D and 12D.

[0034] Therefore, shuttle 4B is configured to transport wafers W from TRS11B to TRS12B so as to bypass support columns 31 of main transport mechanism 3B, and shuttle 4D is configured to transport wafers W from TRS11D to TRS12D so as to bypass support columns 31 of main transport mechanism 3D. Therefore, transport path 40B for wafers W by shuttle 4B and transport path 40D for wafers W by shuttle 4D form detour routes that include front and rear movement paths in addition to left and right movement paths. Note that these transport paths 40B and 40D are horizontal transport paths and are indicated in FIG. 1 by dotted arrows and two-dot chain arrows, respectively.

[0035] The above-mentioned transfer paths 40B and 40D are bypass transfer paths along which transfer is performed by shuttles 4B and 4D, which are bypass transfer mechanisms. The shuttle substrate rests TRS11B and 12B are located at one end and the other end of the transfer path 40B in the longitudinal direction because they serve to transfer wafers W to and from shuttle 4B. Similarly, the shuttle substrate rests TRS11D and 12D are located at one end and the other end of the transfer path 40D in the longitudinal direction because they serve to transfer wafers W to and from shuttle 4D.

[0036] The following is an overview of the configuration of the shuttle 4B. The shuttle 4B includes a base body 41, an intermediate movable body 61, and a wafer transport unit 71, and these three members move relative to each other in the left-right direction. The base body 41 is a long member extending left and right at a position near the rear of the space 5B, and is fixed in that position. Therefore, the position of the base body 41 is fixed relative to the processing module stack 23 and the liquid processing modules in the processing block 2B. The intermediate movable body 61 is a long member provided in front of the base body 41 and extending left and right. The wafer transport unit 71 is provided in front of the intermediate movable body 61, and supports and transports the wafer W.

[0037] The intermediate movable body 61 is a movable body that can move horizontally left and right relative to the base body 41. The wafer transfer unit 71 can move horizontally left and right and front and rear relative to the intermediate movable body 61. The intermediate movable body 61 and the wafer transfer unit 71 both move leftward and frontward, and the intermediate movable body 61 and the wafer transfer unit 71 both move rightward and frontward. The wafer W is transferred between the TRS11B and TRS12B as described above by changing the front and rear positions of the wafer transfer unit 71 depending on the left and right position relative to the wafer transfer unit 71. The movement of the intermediate movable body 61 and the movement of the wafer transfer unit 71 are both powered by a motor 42 provided on the base body 41.

[0038] The configuration of each part of the shuttle 4B will be described in detail below with reference to the plan view of FIG. 5 and the schematic perspective view of FIG. 6. In FIGS. 5 and 6, the upper sides of the base body 41 and the intermediate moving body 61 are cut away to show the interior. The base body 41 has a rectangular housing 43 that is long in the left-right direction, and a motor 42 is provided so as to protrude rearward from the left end of the housing 43. Pulleys 44 and 45 are provided at the left and right ends, respectively, of the rear end of the housing 43. The pulleys 44 and 45 are rotatable around horizontal axes extending forward and backward, and an endless belt 46 is looped around these pulleys 44 and 45. The pulley 44 is connected to the motor 42, and the motor 42 rotates the belt 46 via the pulleys 44 and 45.

[0039] Inside the housing 43, guide rails 47 and 48 are provided forward of the position where the belt 46 is provided, extending linearly from side to side. The guide rails 47 and 48 are provided parallel to each other with a gap between them in the front and rear, with the guide rail 47 provided in the center between the front and rear of the housing 43, and the guide rail 48 provided closer to the front of the housing 43. Inside the housing 43, a slider 51 is provided, and the slider 51 includes a main body 51A forming a rectangular base and a connecting portion 51B protruding rearward from the main body 51A. The main body 51A is connected to the guide rails 47 and 48, and the connecting portion 51B is connected to the belt 46. The rotation of the belt 46 causes the slider 51 to move horizontally left and right along the guide rails 47 and 48. The reason for providing two guide rails connected to the slider 51 at the positions described above is to ensure high rigidity for the base body 41 supporting the intermediate moving body 61 and the wafer transport section 71 on the front side, thereby reducing distortion and more reliably transporting the wafer W to the desired position.

[0040] A slit 49 extending laterally and opening into the housing 43 is formed on the front side of the housing 43, and the front side of the main body 51A of the slider 51 protrudes outside the housing 43 through the slit 49. Inside the housing 43, rollers 52 rotatable around vertical axes are provided at four locations: front and rear on the left end and front and rear on the right end. A seal belt 53 is looped around each roller 52, and one end and the other end of the seal belt 53 are connected to the left and right ends of the main body 51A, respectively. This allows the seal belt 53 to seal the slit 49 from the inside of the housing 43, except for the location where the main body 51A is located. In a plan view, the portion of the seal belt 53 extending laterally on the rear side inside the housing 43 overlaps with the connection portion 51B of the slider 51, but the connection portion 51B is positioned below the seal belt 53 so as not to interfere with each other.

[0041] Rollers 54 that can rotate around vertical axes are provided at the left and right ends of the housing 43. A belt 55 is hung from the front around these two rollers 54, and the belt 55 is parallel to the guide rails 47, 48 between the two rollers 54 and is positioned on the main body 51A of the slider 51. One end and the other end of the belt 55 are connected to fixing members 56 provided behind the rollers 54, and are thereby fixed inside the housing 43.

[0042] Pulleys 57 and 58, each rotatable about a vertical axis, are stacked in this order facing upward on the rear of main body 51A, and these pulleys 57 and 58 are interlocked. In other words, when one of pulleys 57 and 58 rotates, the other also rotates. Belt 55 is connected to pulley 58, and as slider 51 moves left and right as described above, pulley 58 rolls on belt 55, thereby rotating pulley 57. In addition, two pulleys 59, each rotatable about a vertical axis, are provided on the front of main body 51A, spaced apart from each other on the left and right, respectively, of pulleys 57 and 58. Pulleys 57 and 58 are provided inside housing 43, and pulley 59 is provided outside housing 43.

[0043] Next, the intermediate mover 61 will be described. The intermediate mover 61 has a rectangular housing 62, and the front side of the main body 51A of the slider 51 enters the housing 62 through an opening on the rear side of the housing 62 and is fixed to the housing 62. The front side of the housing 62 is open. This opening is formed so that when the wafer transfer unit 71 moves back and forth, the wafer W can enter the housing 62 and the opening prevents the housing 62 from interfering with the forward and backward movement.

[0044] A guide rail 69 extending linearly from side to side is provided at the front end of the housing 62, and a slider 63 is connected to the guide rail 69. Pulleys 60 that can rotate around a vertical axis are provided near the four corners of the housing 62. An endless belt 64 is looped around the pulley 60 and the pulleys 57 and 59 on the slider 51, and the rear side of the slider 63 is connected to the belt 64. With this configuration, when the pulley 57 on the slider 51 rotates as described above, the belt 64 rotates, and the slider 63 moves horizontally from side to side along the guide rail 69. A groove 65 extending from front to back is formed in the upper part of the slider 63, which is a movable body that can move from side to side. The groove 65 is a guide that pairs with a guide rail 74, which will be described later.

[0045] A curved rail 66 is provided behind the guide rail 69 within the housing 62, at a position surrounded by the belt 64 in a plan view. The curved rail 66 is a rail formed to extend laterally between the left and right ends within the housing 62, but by curving, a portion of the rail extends in the front-to-rear direction. More specifically, the left and right ends of the linear guide rail extending laterally are curved forward and to the left and right, respectively. The tip of the curved left end and the tip of the curved right end are further curved to the left and right, respectively. The curved rail 66, curved at a total of four points, has a bilaterally symmetrical shape. Furthermore, a guide groove 67 is formed on the top surface of the curved rail 66 along the extension direction of the curved rail 66.

[0046] Next, the wafer transfer unit 71 will be described with reference to the top perspective view of Fig. 7 and the bottom perspective view of Fig. 8. The wafer transfer unit 71 includes a horizontal, rectangular plate-shaped wafer support (substrate support) 72 and an arm 73 extending rearward from the rear surface of the wafer support 72. The front-to-rear width of the wafer support 72 is smaller than the diameter of the wafer W, and the wafer W is placed on the wafer support 72 so that the peripheral edge of the wafer W extends beyond the front and rear of the wafer support 72 (see Fig. 5).

[0047] A guide rail 74 and a roller 75 are provided on the back surface of the arm 73. The guide rail 74 is formed so as to extend linearly in the front-to-rear direction from the tip end (front end) of the arm 73 toward the base end. The roller 75 is located rearward away from the guide rail 74 and is rotatable around a vertical axis. The guide rail 74 is located in a groove 65 of the slider 63 and is slidable back and forth relative to the groove 65. The roller 75 is also located in a guide groove 67 of the curved rail 66 and is capable of rolling on the side wall of the guide groove 67. In this way, the arm 73 is configured as a connection part that is connected to the curved rail 66 via the roller 75.

[0048] With the above configuration, as the slider 63 moves left and right, the arm 73 moves left and right so that its base end is positioned on the curved rail 66. That is, the wafer support 72 that supports the wafer W moves via the arm 73 along the shape of the curved rail 66, and the wafer W can be transported along the transport path 40B shown in FIG.

[0049] Next, we will explain the TRS 12B, shown in Figures 5 and 6, to which the wafer W is transferred by the shuttle 4B. The TRS 12B includes a main body 77 and an elevator mechanism 78 (shown only in Figure 2). The elevator mechanism 78 moves the main body 77 vertically between an upper position and a lower position. The main body 77 includes a pin support 77A formed to form a recess that opens toward the right in a plan view, and three pins 77B provided on the pin support 77A. The pin support 77A is located below the transfer path 40B, and the pins 77B extend vertically and are spaced apart from one another. When the elevator mechanism 78 moves the main body 77 up and down relative to the transfer path 40B, the pins 77B support the peripheral portion of the wafer W that protrudes from the front and rear of the wafer support 72 of the shuttle 4B in a plan view, as described above, allowing the wafer W to be transferred between the wafer support 72 and the TRS 12B.

[0050] The lifting mechanism 78 includes, for example, a cylinder, a motor, etc., and is provided, for example, below the main body 77 of the TRS12B so as not to interfere with the intermediate moving body 61 and wafer transfer unit 71 of the shuttle 4B, or the main body 77 of the TRS12B. In this example, the TRS11B has the same configuration as the TRS12B, except that the opening of the recess formed in the main body 77 faces leftward in a plan view. As described above, the transfer path 40B of the shuttle 4B is horizontal, and therefore the TRS11B and TRS12B are provided at the same height.

[0051] The transfer of the wafer W by the shuttle 4B will be described in more detail with reference to FIGS. 9, 10, and the aforementioned FIG. 5. FIG. 9 shows the state immediately after the main body 77 of TRS 11B, which supports the wafer W, moves from the upper position to the lower position, and the wafer transfer unit 71 receives the wafer W, i.e., immediately before the transfer to TRS 12B. FIG. 10 shows the state during the transfer of the wafer W to TRS 12B. FIG. 5 shows the state immediately before the main body 77 of TRS 12B moves to the upper position and receives the wafer W, i.e., the state at the end of the transfer of the wafer W to TRS 12B.

[0052] The wafer W moves leftward from the position overlapping with TRS11B shown in FIG. 9 (which is the transfer position for TRS11B and the transfer start position), and during this movement, the wafer W moves backward while moving leftward. After that, the backward movement stops, and the wafer W moves only leftward, passing behind the support 31 (FIG. 10). As the wafer W moves further leftward, it moves forward while moving leftward, and then the forward movement stops, and the wafer W moves only leftward, and moves to a position overlapping with TRS12B (which is the transfer position for TRS12B and the transfer end position) (FIG. 5). After the wafer W is received by TRS12B due to the lifting and lowering operation of TRS12B, the wafer transfer unit 71 returns toward TRS11B along the path opposite to that taken toward TRS12B, and receives a new wafer W from TRS11B.

[0053] 9, when transferring a wafer W to or from TRS11B, the right end of intermediate mover 61 is located to the right of the right end of base body 41, and the right end of wafer transfer unit 71 is located to the right of the right end of intermediate mover 61. As shown in FIG. 5, when transferring a wafer W to or from TRS12B, the left end of intermediate mover 61 is located to the left of the left end of base body 41, and the left end of wafer transfer unit 71 is located to the left of the left end of intermediate mover 61. By moving intermediate mover 61 and wafer transfer unit 71 in this way, the left-right length of the area in which wafer W can be transferred is increased, and the shuttle 4B and therefore the substrate processing apparatus 1 are made smaller.

[0054] As described above, the transport of the wafer W by the shuttle 4B is achieved by changing the relative left-right positions of multiple components (base body 41, intermediate movable body 61, and wafer transport unit 71) arranged in the front-rear direction. By changing the relative left-right positions of the components in this way, interference between the TRS11B, TRS12B and the shuttle 4B is reduced. This contributes to a high degree of freedom in the arrangement and design of the TRS11B and TRS12B, and also a high degree of freedom in the arrangement of each pin 77B. Three or more pins 77B may be provided.

[0055] Next, an example of speed control of the wafer transfer unit 71 when it moves from the transfer start position to the transfer end position, i.e., an example of operation control of the motor 42 that moves the wafer transfer unit 71, will be described with reference to FIGS. 11 and 12. FIG. 11 is a graph showing the change in the lateral movement speed of the wafer transfer unit 71 during the above-mentioned movement. FIG. 12 shows the wafer transfer unit 71 at various positions on the curved rail 66 during its movement. However, in FIG. 12, the wafer transfer unit 71 is denoted by the same reference numerals as times t1 to t8 on the horizontal axis of the graph in FIG. 11 to correspond to these times. Note that in FIG. 12, the wafer transfer unit 71 at times t4 and t5 is not shown, and the wafer W supported by the wafer transfer unit 71 is also not shown. For ease of explanation, the four curved portions of the curved rail 66 from the transfer start position to the transfer end position are designated 66A, 66B, 66C, and 66D, respectively.

[0056] The wafer transfer unit 71 starts moving leftward from a stationary state at the transfer start position (time t1), and the speed of its movement to the left continues to increase. When the arm 73 of the wafer transfer unit 71 reaches the curved portion 66A, the increase in the movement speed stops (time t2), and the wafer transfer unit 71 moves leftward at a constant speed. When the arm 73 reaches the curved portion 66B, the speed of the wafer transfer unit 71 moving leftward begins to increase again (time t3), and then the increase in the movement speed stops and becomes constant (time t4). Thereafter, just before the arm 73 reaches the curved portion 66C, the speed of the wafer transfer unit 71 moving leftward decreases (time t5). When the arm 73 reaches the curved portion 66C, the decrease in the speed of the wafer transfer unit 71 moving leftward stops and becomes constant (time t6). Then, when the arm 73 reaches the curved portion 66D, the speed of the wafer transfer unit 71 moving leftward decreases, and the wafer transfer unit 71 reaches the transfer end position and stops moving (time t7).

[0057] In this way, the moving speed of the wafer transfer part 71 in the left-right direction is controlled in accordance with the positions of the curved portions 66A to 66D. More specifically, in the transfer path 40B for the wafer W, a region formed by the base end of the arm 73 moving from the curved portion 66A to the curved portion 66B and a region formed by the arm 73 moving from the curved portion 66C to the curved portion 66D (i.e., a region where the wafer W moves forward and backward as well as left and right) are defined as a first region. Further, in the transfer path 40B, a region formed by the base end of the arm 73 moving from the curved portion 66B to the curved portion 66C and sandwiched between the two first regions (i.e., a region where the wafer W moves only left and right) is defined as a second region.

[0058] As already described in detail, the horizontal movement speed of the wafer W is controlled to be smaller in each first region than in the second region. This is because, in the first region where forward / backward movement and left / right movement are performed, a vector resulting from the sum of the vectors of the movements in each direction acts on the wafer W. In other words, if the wafer W were moved at a constant speed in the first region and the second region, a greater force would be applied to the wafer W in the first region. Therefore, in the first region, the horizontal movement speed is set to be greater than the first region in order to more reliably prevent the wafer W from shifting or detaching from the wafer transfer unit 71. From another perspective, by increasing the horizontal speed of the wafer W in the second region, which does not include forward / backward movement, throughput is improved.

[0059] When the wafer transfer unit 71 returns to the transfer start position on the TRS11B side, since there is no wafer W to support, the moving speed in the left-right direction may be controlled to change stepwise, as when moving toward the transfer end position on the TRS12B side, but such control is not necessary. That is, after the speed is increased from the transfer end position where the wafer W is transferred to TRS12B, the speed increase is stopped and the wafer is moved at a constant speed, and then the speed is decelerated near the transfer start position where the wafer W is transferred to TRS11B. That is, if the speed change is represented by a graph as shown in FIG. 12, the speed is controlled to change so that the graph describes a trapezoid. That is, the number of steps of the speed change may be reduced compared to when transferring the wafer W to TRS12B, thereby improving throughput.

[0060] Next, shuttle 4D of processing block 2D will be described. Shuttle 4D has the same configuration as shuttle 4B, except that the connection position of intermediate movable body 61 to base body 41 in the left-right direction differs to match the arrangement of TRS11D and 12D, and is subject to the same speed control as shuttle 4B. TRS11D and TRS12D also have the same configuration as TRS11B and 12B, respectively, and a main body 77 equipped with pins 77B is raised and lowered by an elevating mechanism 78 relative to transport path 40D.

[0061] The positional relationship between the transport path 40B of the shuttle 4B and the transport path 40D of the shuttle 4D will be described with reference to the plan view of FIG. 13. As shown by the arrangement of the shuttle TRSs described above, both transport paths 40B and 40D are provided from the space 5B of the processing block 2B to the space 5D of the processing block 2D. To prevent interference between the transport paths 40B and 40D, the set of shuttle 4B, TRS11B, and TRS12B and the set of shuttle 4D, TRS11D, and TRS12D are provided at positions offset from each other in the longitudinal direction (vertical direction) (see FIGS. 2 and 4). That is, the transport paths 40B and 40D are at different heights. As shown in FIG. 13, the right end of the transport path 40B and the left end of the transport path 40D overlap in a plan view. In this example, the transport path 40B is on the upper side and the transport path 40D is on the lower side, but the arrangements may be reversed.

[0062] The substrate processing apparatus 1 includes a control unit 10 (see FIG. 1). The control unit 10 is configured by a computer and includes a program, a memory, and a CPU. The program incorporates steps that enable a series of operations in the substrate processing apparatus 1 to be performed. The program causes the control unit 10 to output control signals to each component of the substrate processing apparatus 1, thereby controlling the operation of each component. Specifically, the control unit 10 controls the operations of the main transport mechanisms 3A-3D, the shuttles 4B and 4D, and each processing module. This controls the transport and processing of wafers W, as described below. The control of the operation of the shuttles 4B and 4D also includes the speed control described in FIG. 12. The control of the module operations performed by the control unit 10 also includes the determination of anomalies based on image data transmitted from each inspection module. The above program is stored on a storage medium, such as a compact disc, hard disk, or DVD, and installed in the control unit 10.

[0063] Next, the processing and transport of wafers W in the substrate processing apparatus 1 will be described with reference to Fig. 14, which shows an outline of the transport path. In Fig. 14, the transport mechanisms used for the transport of wafers W between modules are shown on or near some of the arrows. In this example, it is assumed that wafers W are removed from carriers C on support base 11 and returned to carriers C on support base 12 after processing.

[0064] First, the wafer W is unloaded from the carrier C on the support stage 11 by the transfer mechanism 18 and transferred within the carrier block D1 in the following order: pre-processing inspection module 29 → transfer mechanism 18 → TRS1 → transfer mechanism 19 → SCPL1. The wafer W is then transferred within the lower processing block in the following order: main transfer mechanism 3A → backside cleaning module 26 → main transfer mechanism 3A → edge exposure module 27 → main transfer mechanism 3A → TRS4 → main transfer mechanism 3C, and transferred to TRS5 in the interface block D4. The wafer W is then transferred in the following order: transfer mechanism 35 → ICPL → transfer mechanism 34 → exposure machine 20 → transfer mechanism 35 → TRS6 → main transfer mechanism 3C → post-exposure cleaning module 28 → main transfer mechanism 3C → TRS7 → transfer mechanism 35, and is handed over between the interface block D4, exposure machine 20, and processing block 2C.

[0065] The transfer path of the wafer W thereafter is divided into a path (one transfer path) for processing in the processing block 2D and a path (the other transfer path) for processing in the processing block 2B, as described above. Regarding one transfer path, the transfer mechanism 35 in the interface block D4 transfers the wafer W to the TRS8, and the main transfer mechanism 3D takes the wafer W into the processing block 2D. The wafer W is then transferred in the following order: heating module 24 → SCPL3 → developing module 21 → post-processing inspection module 25 → main transfer mechanism 3D, where a pattern mask is formed and inspected according to the exposure pattern in the exposure tool 20. Thereafter, as described with reference to FIGS. 5, 9, and 10, the wafer W is transferred in the following order: TRS11B → shuttle 4B → TRS12B, and the transfer mechanism 19 in the carrier block D1 receives the wafer W and transfers it to TRS2 in the module stack T1.

[0066] Regarding the other transfer path, the wafer W is transferred in the order of transfer mechanism 35 → TRS11D → shuttle 4D → TRS12D → main transfer mechanism 3B, and the wafer W is taken into processing block 2B. The wafer W is then transferred by main transfer mechanism 3B in the order of heating module 24 → SCPL3 → developing module 21 → post-processing inspection module 25, and after being processed in the same manner as the wafer W transferred to processing block 2D, is transferred to TRS3 in carrier block D1. The wafer W is then transferred to TRS2 by transfer mechanism 19. In these two transfer paths, the wafer W transferred to TRS2 is transferred to carrier C on support table 12 by transfer mechanism 18.

[0067] As described above, the substrate processing apparatus 1 is configured and transported by the main transport mechanism 3B of the processing block 2B and the main transport mechanism 3D of the processing block 2D. Therefore, the main transport mechanism 3B of the processing block 2B and the main transport mechanism 3D of the processing block 2D do not need to transport wafers W that are not processed in the blocks where the main transport mechanisms 3B and 3D are installed toward the carrier block D1. This reduces the load on each of the main transport mechanisms 3B and 3D, specifically the number of transport processes required within the block. As described above, each of the processing blocks 2B and 2D is equipped with multiple modules. This reduced load allows the main transport mechanisms 3B and 3D to quickly access each module, receive wafers W, and transport the wafers W to downstream modules. This means that the substrate processing apparatus 1 can process wafers W in multiple processing modules and quickly transport wafers W between modules. Therefore, the substrate processing apparatus 1 can achieve high throughput.

[0068] To avoid the need for the main transport mechanisms 3B and 3D to move across adjacent blocks, shuttles 4B and 4D are provided in the processing blocks 2B and 2D, respectively, in addition to the main transport mechanisms 3B and 3D. The transport path 40B of the shuttle 4B extends to the processing block 2D, and the transport path 40D of the shuttle 4D extends to the processing block 2B. The transport paths 40B and 40D extending across adjacent blocks are offset in height and do not intersect, allowing the shuttles 4B and 4D to transport materials independently. More specifically, during transport by one of the shuttles 4A and 4B, there is no need to stop the other shuttle to avoid interference with the other shuttle. This further increases the throughput of the substrate processing apparatus 1. Furthermore, because the transport paths 40B and 40D, which are offset in height, overlap in plan view, the substrate processing apparatus 1 does not need to be enlarged in its longitudinal direction, reducing its footprint and saving space.

[0069] The height of the substrate processing apparatus 1 must be set so as not to interfere with the ceiling of the clean room. Meanwhile, liquid processing modules such as the developing module 21 are equipped with cups (not shown) for storing wafers W, making them relatively tall. However, in the substrate processing apparatus 1, shuttles 4B and 4D are provided on top of the processing module stack 23, which performs a type of processing other than the liquid processing, as described above. Therefore, within the limited height of the apparatus, the number of levels on which liquid processing modules are provided can be increased, and the height of the transfer region 22 can be sufficiently secured so that wafers W can be transferred between each level. Therefore, the substrate processing apparatus 1 can more reliably increase the throughput of wafers W.

[0070] Furthermore, the shuttles 4B and 4D are located below the processing module stack 23 in the upper processing block, i.e., at the height of the lower processing block. That is, the shuttles 4B and 4D are located at the block of the upper or lower processing block that is connected from below to the block in which the shuttle bypass transfer path is located. Suppose the shuttles 4B and 4D are located at a relatively high position in the upper processing block, and the TRSs for the shuttles 4B and 4D are also located at a relatively high position. In this case, the transfer mechanisms 19 and 35 that deliver wafers W to and from the TRSs 12B and 11D, respectively, may need to be moved to positions above the positions of the modules constituting the module stacks T1 and T3. That is, locating the shuttles 4B and 4D at the height of the lower processing block relative to the processing module stack 23 as described above reduces the amount of lift required by the transfer mechanisms 19 and 35. Therefore, the placement of the shuttles 4B and 4D contributes to a more reliable increase in throughput.

[0071] The transport path 40B of the shuttle 4B and the transport path 40D of the shuttle 4D bypass the support pillars 31 of the main transport mechanisms 3B and 3D, respectively, as described above. Instead of bypassing the transport paths 40B and 40D, it is possible to provide them linearly so as to pass behind the support pillars 31, and increase the lateral movement of the transport mechanisms other than the shuttles so that wafers W can be transferred between the shuttles 4B and 4D. However, such a configuration would increase the footprint of the substrate processing apparatus 1. Therefore, by providing the transport paths 40B and 40D as bypasses around the support pillars 31 as described above, the substrate processing apparatus 1 is prevented from becoming larger. From another perspective, by having the shuttles 4B and 4D form a bypass around the support pillars 31 in this manner, it is not necessary to shift the front-to-rear positions of the support pillars 31 and the processing module stack 23. This prevents the substrate processing apparatus 1 from becoming larger in size, thereby preventing the substrate processing apparatus 1 from becoming larger in size.

[0072] Furthermore, as described above, the shuttles 4B and 4D are configured such that the relative positions of the base body 41, intermediate mover 61, and wafer transport unit 71 change. This change in relative positions allows the shuttles 4B and 4D to accommodate these components (base body 41, intermediate mover 61, and wafer transport unit 71) in the processing blocks 2B and 2D, respectively. Therefore, after the processing blocks 2B and 2D are assembled in the equipment manufacturing factory, the widths of the processing blocks 2B and 2D can be reduced when transporting them to the clean room where the substrate processing apparatus 1 will be installed. This simplifies the labor and equipment required for transportation. Furthermore, transporting the shuttles 4B and 4D accommodated in the processing blocks 2B and 2D contributes to quickly assembling the apparatus and making it operational at the destination.

[0073] The intermediate movable body 61 and the wafer transport unit 71 are moved using a common drive source, the motor 42 provided on the base body 41. This common drive source reduces manufacturing costs and simplifies the device configuration. The shuttles 4B and 4D are configured such that the arm 73 of the wafer transport unit 71 moves along the curved rail 66, as described above. This configuration allows the arm 73 to move left and right and back and forth by transmitting the driving force of the motor 42, which is the drive source, to the arm 73, without providing separate drive sources for left and right movement and for front and back movement. This also advantageously avoids a complex device configuration and prevents an increase in manufacturing costs.

[0074] A slider 63 is provided on the front side (the side where the wafer support 72 is located) of a curved rail 66 for controlling the movement trajectory of the arm 73, and the arm 73 moves along a guide rail 74 for the arm 73 while being supported by the slider 63, so that the arm 73 is supported near the wafer support 72. This prevents an increase in the load on the arm 73 due to its own weight or the weight of the wafer W, thereby suppressing deterioration of the components that make up the shuttles 4B, 4D and also suppressing fluctuations in the operation of the arm 73. Therefore, with this configuration, the wafer W can be transported to the desired destination position with high precision.

[0075] The shuttle TRS 11D may be disposed in the interface block D4, and the shuttle 4D may be transported from the interface block D4 to the TRS 11D in the processing block 2B, passing through the processing block 2D. The shuttle TRS 12B may be disposed in the carrier block D1, and the shuttle 4B may be transported from the TRS 11B in the processing block 2D to the TRS 11B, passing through the processing block 2B. In other words, the shuttle TRSs are not limited to being provided in the processing blocks. The shuttle transports the wafer W between adjacent blocks on one side and the other side of the wafer W transfer path, and is not limited to the configuration in which the wafer W is transferred between adjacent blocks on the left and right, as shown in the substrate processing apparatus 1.

[0076] [Modification of the first embodiment] Although an example in which a shuttle and a shuttle TRS are provided on the return path has been shown, an apparatus configuration in which a shuttle and a shuttle TRS are provided on the forward path may also be used. Figure 15 shows a schematic front view of substrate processing apparatus 1A in which shuttles and shuttle TRSs are provided on the return path and the forward path. The following will focus on the differences from substrate processing apparatus 1. Lower processing blocks 2A and 2C of substrate processing apparatus 1A are equipped with similar processing modules, including, for example, a resist film forming module as a liquid processing module, and module stack 23 includes a heating module for use after resist film formation.

[0077] Shuttles 4A, TRS11A, and TRS11C are provided in a front position in space 5A of processing block 2A, and shuttles 4C, TRS12A, and TRS12C are provided in a front position in space 5C of processing block 2C. In space 5A, TRS11A and TRS11C are provided in order toward the right side, sandwiching support column 31 of main transport mechanism 3A therebetween, and in space 5C, TRS12A and TRS12C are provided in order toward the right side, sandwiching support column 31 of main transport mechanism 3C therebetween. The set of shuttles 4A, TRS11A, and TRS12A and the set of shuttles 4C, TRS11C, and TRS12C are offset in height from each other.

[0078] Due to the layout of each component as described above, the transport path 40A for shuttle 4A and the transport path 40C for shuttle 4C have the same positional relationship as the transport paths 40B and 40D described in Figure 13. That is, the transport paths 40A and 40C are at different heights, and their ends overlap in a plan view. Note that in the lower processing blocks 2A and 2C, the shuttle and shuttle TRS are provided above the processing module stack 23 for the same reason as in the upper processing blocks 2B and 2D, where the shuttle and shuttle TRS are provided below the processing module stack 23, in order to prevent an increase in the movement range of the transport mechanisms 19 and 35.

[0079] The two outward transfer paths in this substrate processing apparatus 1B will be described. On one transfer path, a wafer W unloaded from a carrier C and transferred to the module stack T1 in the carrier block D1 is received by the main transfer mechanism 3A, processed in the processing block 2A, and then transferred in the order of TRS11C, shuttle 4C, TRS12C, and interface block D4. On the other transfer path, a wafer W unloaded from a carrier C is transferred in the order of the transfer mechanism 19 in the carrier block D1, TRS11A, shuttle 4A, TRS12A, and main transfer mechanism 3C, processed in the processing block 2C, and then transferred to the interface block D4. The transfer of wafers W by shuttles 4A and 4C on these outward paths bypasses the supports 31 of the main transfer mechanism 3B and the supports 31 of the main transfer mechanism 3D, respectively, just as wafers W on shuttles 4B and 4D on the return paths do.

[0080] Second Embodiment The number of laterally adjacent processing blocks equipped with shuttles may be three or more, and as a second embodiment, a schematic front view of a substrate processing apparatus 1B equipped with three such processing blocks is shown in Fig. 16. This substrate processing apparatus 1B performs processing similar to that of the substrate processing apparatus 1 of the first embodiment, for example, and the following description will focus on the differences from the substrate processing apparatus 1.

[0081] In the substrate processing apparatus 1B, a third stacked processing block D5 is provided adjacent to the second stacked processing block D3 and the interface block D4, and these first to third stacked processing blocks D2, D3, and D5 form a processing station G. The third stacked processing block D5 has a configuration similar to that of the first stacked processing block D3 and is composed of a lower processing block 2E and an upper processing block 2F. On the return path, the wafer W is processed in one of the processing blocks 2B, 2D, and 2F. The processing blocks 2B, 2D, and 2F are the first processing block, the second processing block, and the third processing block, respectively. The shuttles 4B, 4D, and 4F are the first bypass transfer mechanism, the second bypass transfer mechanism, and the third bypass transfer mechanism, respectively. The transfer paths 40B, 40D, and 40F are the first bypass transfer path, the second bypass transfer path, and the third bypass transfer path, respectively.

[0082] In the space 5F for installing the shuttle 4F in the processing block 2F, TRSs 11F and 11D are provided on the right and left sides of the support pillar 31 of the main transport mechanism 3F, respectively, and the TRS 11F is accessible to the transport mechanism 35 of the interface block D4. Furthermore, in the space 5D, a TRS 12F is provided on the right side of the support pillar 31 of the main transport mechanism 3D.

[0083] Regarding the set of shuttle 4B, TRS11B, and TRS12B (referred to as the first set), the set of shuttle 4D, TRS11D, and TRS12D (referred to as the second set), and the set of shuttle 4F, TRS11F, and TRS12F (referred to as the third set), the second set is located higher than the first and third sets, and the first and third sets are located at the same height. Therefore, transport paths 40B and 40F are located at the same height, and transport path 40D is located higher than transport paths 40B and 40F. As shown in FIG. 17 , in a plan view, the right end of transport path 40B overlaps with the left end of transport path 40D, and the right end of transport path 40D overlaps with the left end of transport path 40F.

[0084] An example of a return transfer path will be described. When a wafer W is processed in the processing block 2F, the wafer W is transferred in the order of module stack T3 in the interface block D4, then to the main transfer mechanism 3F, and after being processed in each processing module in the processing block 2F, is transferred to the TRS11D. The wafer W is then transferred in the order of shuttle 4D, then to the TRS12D, then to the main transfer mechanism 3B, and then to the module stack T1 in the carrier block D1.

[0085] When a wafer W is processed in processing block 2D, the wafer W is transferred in the order of transfer mechanism 35 in interface block D4 → TRS11F → shuttle 4F → TRS12F → main transfer mechanism 3D, and after being processed in each processing module in processing block 2D, it is transferred in the order of TRS11B → shuttle 4B → TRS12B and transferred to carrier block D1. When a wafer W is processed in processing block 2B, the wafer W is transferred in the order of module stack T3 → main transfer mechanism 3F → TRS11D → shuttle 4D → TRS12D → main transfer mechanism 3B, and after being processed in each processing module in processing block 2B, it is transferred to module stack T1.

[0086] In the substrate processing apparatus 1B, a module stack corresponding to the module stack T2 is provided across the second and third processing blocks D3 and D5. By utilizing each module stack, the wafer W can be freely transported between the lower processing blocks 2A, 2C, and 2E, and an outbound route is formed by the processing blocks 2A, 2C, and 2E.

[0087] In the substrate processing apparatus 1B, as described above, the ends of the transfer path 40D overlap with the transfer paths 40B and 40F in a plan view in order to transfer wafers W between the upper processing blocks. By locating the transfer path 40D at a higher position than the transfer paths 40B and 40F, as described above, the height required to install the transfer paths 40B, 40D, and 40F is reduced compared to when the transfer paths 40B, 40D, and 40F are arranged in a vertical direction, thereby preventing the substrate processing apparatus 1B from becoming larger. The transfer path 40D may also be located below the transfer paths 40B and 40F. Whether the transfer path 40D is located above or below the transfer paths 40B and 40F, it is preferable that the transfer paths 40B and 40F be at the same or approximately the same height in order to reduce the height of the apparatus.

[0088] In this substrate processing apparatus 1B, shuttles may be provided in the lower processing blocks 2A, 2C, and 2E, and wafers W may be transported to a desired processing block among 2A, 2C, and 2E, similar to the transport between the upper processing blocks 2B, 2D, and 2F, so that wafers W can be processed in the desired processing block among 2A, 2C, and 2E. Even in this case, it is preferable that the transport paths 40A, 40C, and 40E of the shuttles in the lower processing blocks have the same positional relationship as the transport paths 40B, 40D, and 40F of the shuttles in the upper processing blocks. In other words, it is preferable that the central transport path 40D on the left and right is located above or below the transport paths 40B and 40F, and it is more preferable that 40B and 40F are at the same height.

[0089] Although the configuration examples of each apparatus described above are provided with a shuttle TRS, the apparatus may be configured without the shuttle TRS, and wafers W may be transferred directly between each transfer mechanism and the shuttle. However, if a shuttle TRS is not provided, each transfer mechanism and shuttle will wait while still supporting the wafer W. Therefore, it is preferable to provide a shuttle TRS to improve throughput.

[0090] Furthermore, while the liquid processing modules are located in the front and the processing module stack 23 is located in the rear in each of the above-described apparatuses, this layout may be reversed. The left-right layout of the apparatus may also be reversed from the examples described above. Furthermore, the interface block D4 may not transport wafers W to or from the exposure device 20, but may instead only lift and lower wafers W between the height of the lower processing block and the height of the upper processing block. Furthermore, the upper and lower processing blocks may not be directly connected to the carrier block D1, which loads and unloads wafers W into and out of the apparatus. For example, a block for lifting and lowering wafers W may be interposed between the carrier block D1 and the upper and lower processing blocks. Furthermore, the processing blocks are not limited to a vertically stacked structure. For example, one of the forward and return paths may be formed by transport using a main transport mechanism, and the other may be formed by transport using a shuttle.

[0091] In each shuttle, for example, the curved rail 66, guide rail 69, and slider 63 are provided on the base body 41 instead of the intermediate mover 61. An arm corresponding to the arm 73 is connected to the curved rail 66 and slider 63, and the arm is connected to the belt 46 driven by the motor 42. Furthermore, the intermediate mover 61 may be connected to the front end of the arm, and the intermediate mover 61 may move along the curved rail 66 together with the wafer support body 72 connected to the front side of the arm. In this case, a power transmission mechanism consisting of a pulley, belt, gearbox, etc. may be provided to the slider 63, the arm, and the intermediate mover 61, so that the lateral position of the wafer support body 72 relative to the intermediate mover 61 changes in response to a change in the lateral position of the slider 63. As described above, the shuttle is not limited to the configuration in which the curved rail 66 is provided on the intermediate mover 61 as shown in FIG. 5 etc.

[0092] In the shuttle shown in FIG. 5 and other figures, instead of providing the groove 65 on the slider 63 of the intermediate mover 61 and the guide rail 74 on the arm 73, the slider 63 may be provided with the guide rail 74 and the arm 73 with the groove 65. Furthermore, with respect to the roller 75 of the arm 73 that fits into the guide groove 67 of the curved rail 66, a circular protrusion formed of a material with a sufficiently low coefficient of friction with the curved rail 66 may be provided instead of the roller 75. Furthermore, a thick plate with the guide groove 67 formed on its upper surface may be used instead of the curved rail 66, and the guide member that guides the wafer transport unit 71 is not limited to a rail. In addition, in the above-described configuration example, the wafer support 72 is connected to the curved rail 66 via the arm 73 and moves following the arm 73, but a member corresponding to the arm 73 need not be provided. That is, the wafer support 72 may be directly connected to the curved rail 66, and the wafer support 72 may also serve as a connecting portion. In this case, the guide rails 74 provided on the arm 73 may be provided on the wafer support 72. In this way, the structure of the shuttle described above can be modified as appropriate.

[0093] Incidentally, in FIG. 5, when shuttle 4B transfers wafer W to TRS12B, two of the three pins 77B of TRS11B are shown sandwiching arm 73 in a plan view. However, both of these pins 77B may be located on the left side of arm 73. The arrangement of the pins 77B and the recessed shape of main body 77 that opens to the right allow the wafer transfer unit 71 of shuttle 4B to begin moving toward TRS11B after the main body 77 of TRS11B moves to the upper position and the pins 77B support the wafer W, but before returning to the lower position. In other words, when TRS11B receives the wafer W, the TRS11B is configured so that its components are not positioned in the direction of travel (to the right in this case) from the wafer transfer unit 71, preventing interference between them. This allows the timing at which the wafer transfer unit 71 begins to move to be advanced, thereby improving the throughput of the device. Similarly, when the wafer W is transferred to the TRS 11B in FIG. 9, two of the three pins 77B of the TRS 11B are shown to sandwich the arm 73 in a plan view, but these pins 77B may be provided on the right side of the arm 73.

[0094] The liquid processing performed in the substrate processing apparatus is not limited to the above examples, and may include, for example, forming an insulating film by applying a chemical solution, or applying an adhesive to bond wafers W to each other. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The above embodiments may be omitted, substituted, modified, and / or combined in various ways without departing from the scope and spirit of the appended claims. [Explanation of symbols]

[0095] C Carrier D1 Carrier Block D3 Interface Block G Processing Station 24 Heating Module 2A~2D Processing Blocks 4A~4D Shuttle 40A~40D Conveyor path

Claims

1. a carry-in / out block for carrying in and out the substrate; a processing station provided on one of the left and right sides of the load-out block, through which the substrate is transported between the load-out block and the processing station; a relay block provided on one of the left and right sides of the processing station, through which the substrate is transported between the processing station and the relay block; a plurality of processing blocks arranged side by side to form the processing station, each of which includes a processing module for processing the substrate and a main transport mechanism for transferring the substrate to the processing module; a bypass transport mechanism provided for each of the processing blocks arranged on the left and right to transport substrates between the left and right blocks, separate from the main transport mechanism; The bypass transport paths, which are transport paths for substrates by the bypass transport mechanism, are different in height and partially overlap each other in a plan view; The bypass transport mechanism includes a base body provided in the processing block; a movable body that moves left and right relative to the base body; a substrate support that supports the substrate and moves left and right relative to the moving body; Equipped with The processing modules are provided in plural and arranged side by side, the main transport mechanism includes pillars provided between the plurality of processing modules in a plan view, The bypass transport path includes a transport path in the front-rear direction, and is a bypass route for the substrate to bypass the pillar.

2. a loading / unloading block for loading and unloading substrates; a processing station provided on one of the left and right sides of the load-out block, through which the substrate is transported between the load-out block and the processing station; a relay block provided on one of the left and right sides of the processing station, through which the substrate is transported between the processing station and the relay block; a plurality of processing blocks arranged side by side to form the processing station, each of which includes a processing module for processing the substrate and a main transport mechanism for transferring the substrate to the processing module; a bypass transport mechanism provided for each of the processing blocks arranged on the left and right to transport substrates between the left and right blocks, separate from the main transport mechanism; The bypass transport paths, which are transport paths for substrates by the bypass transport mechanism, are different in height and partially overlap each other in a plan view; At least three processing blocks are provided, from left to right in the order of a first processing block, a second processing block, and a third processing block, and the bypass transport paths of the respective bypass transport mechanisms are designated as a first bypass transport path, a second bypass transport path, and a third bypass transport path, a left end of the second bypass transport path overlaps with one of the first bypass transport path and the third bypass transport path in a plan view, and a right end of the second bypass transport path overlaps with the other of the first bypass transport path and the third bypass transport path in a plan view, The substrate processing apparatus, wherein the first bypass transport path and the third bypass transport path are located above or below the second bypass transport path.

3. 3. The substrate processing apparatus according to claim 1, further comprising a substrate placement section that moves up and down relative to an end of the bypass transport path to transfer the substrate to the bypass transport mechanism and on which the substrate is placed.

4. 2. The substrate processing apparatus according to claim 1, wherein one of the base body and the movable body is provided with a guide member for guiding the movement of the substrate support in the front-rear direction and the left-right direction.

5. the guide member is a curved rail, The substrate processing apparatus of claim 4 , wherein the substrate support moves along the curved rail to form the bypass path.

6. On the side of the base body and the movable body where the guide member is provided, a connecting portion connected to the guide member and movable together with the substrate support in the left-right and front-rear directions; a movable body connected to the connection portion and movable in the left-right direction, 6. The substrate processing apparatus according to claim 5, wherein one of the connecting portion and the moving body is provided with a rail extending in the front-rear direction for sliding the one of the connecting portion and the moving body back and forth relative to the other.

7. The substrate processing apparatus according to claim 6 , wherein the rail extending in the front-rear direction is provided at the connection portion.

8. The bypass conveying path is two first regions for transporting the substrate in left-right and front-rear directions; a second region sandwiched between the first regions and transporting the substrate only in the left-right direction; 8. The substrate processing apparatus according to claim 1, wherein a moving speed of the substrate in the left-right direction in the first area is slower than a moving speed of the substrate in the left-right direction in the second area.

9. a step of loading and unloading the substrate in a loading / unloading block; transporting the substrate between a processing station provided on one of the left and right sides of the load-out block and the load-out block; a step of transporting the substrate between a relay block provided on one of the left and right sides of the processing station and the processing station; in a processing block where a plurality of processing stations are provided side by side to form the processing station, each including a processing module, a main transport mechanism, and a bypass transport mechanism that transports the substrate separately from the main transport mechanism, transferring the substrate to the processing module by the main transport mechanism and processing the substrate in the processing module; transporting the substrate between the left and right blocks using bypass transport paths which are transport paths for the substrate by the bypass transport mechanisms, which have different heights and which partially overlap each other in a plan view; a step of moving a movable body of the bypass transport mechanism left and right relative to a base body of the bypass transport mechanism provided in the processing block; a step of moving a substrate support member provided in the bypass transport mechanism and supporting the substrate left and right relative to the moving body, The processing modules are provided in plural and arranged side by side, the main transport mechanism includes pillars provided between the plurality of processing modules in a plan view, The bypass transport path is a detour route including a transport path in a forward and backward direction, and the substrate processing method includes a step of causing the substrate to detour around the pillar.

10. a step of loading and unloading the substrate in a loading / unloading block; transporting the substrate between a processing station provided on one of the left and right sides of the load-out block and the load-out block; a step of transporting the substrate between a relay block provided on one of the left and right sides of the processing station and the processing station; in a processing block where a plurality of processing stations are provided side by side to form the processing station, each including a processing module, a main transport mechanism, and a bypass transport mechanism that transports the substrate separately from the main transport mechanism, transferring the substrate to the processing module by the main transport mechanism and processing the substrate in the processing module; transporting the substrate between the left and right blocks using bypass transport paths which are transport paths for the substrate by the bypass transport mechanisms, which have different heights and which partially overlap each other in a plan view; Equipped with At least three processing blocks are provided, from left to right in the order of a first processing block, a second processing block, and a third processing block, and the bypass transport paths of the respective bypass transport mechanisms are designated as a first bypass transport path, a second bypass transport path, and a third bypass transport path, a left end of the second bypass transport path overlaps with one of the first bypass transport path and the third bypass transport path in a plan view, and a right end of the second bypass transport path overlaps with the other of the first bypass transport path and the third bypass transport path in a plan view, A substrate processing method, wherein the first bypass transport path and the third bypass transport path are positioned above or below the second bypass transport path.

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