Semiconductor Module

Abstract

To provide a semiconductor module with protective layers that have high adhesion with electrode portions.SOLUTION: A semiconductor module has a semiconductor device 11, junction layers 14a and 14b that contain nickel or copper and are disposed on the semiconductor device 11 and electrically connected to the semiconductor device 11, solder sections 17a and 17b that are disposed on the junction layers 14a and 14b and contain gold, and a protective layer 16 that is directly disposed on the junction layers 14a and 14b and covers the outer edge of the junction layers 14a and 14b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. [Background technology]

[0002] Conventionally, semiconductor modules including semiconductor devices have been used. The semiconductor modules include a semiconductor device and an insulating substrate that supports the semiconductor device, and wiring that connects the semiconductor device to an external device is soldered to electrodes of the semiconductor device.

[0003] The semiconductor module includes, as semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), or free wheeling diodes (FWDs).

[0004] Therefore, semiconductor modules are subjected to a thermal cycle test that simulates the environment in which they are used, and their reliability is evaluated.

[0005] In a semiconductor module, one of the parts that is subject to stress due to thermal cycles is a protective layer that protects electrodes to which wiring that connects the semiconductor device to the outside is soldered.

[0006] The electrodes of the semiconductor device are connected to the wiring by soldering. The electrodes are then covered with a protective layer. The protective layer is made of resin, and the electrodes to which the protective layer is attached are made of metal, so the two have different degrees of thermal expansion.

[0007] An electrode of a semiconductor device has a bonding layer that connects to a circuit of the semiconductor device, and an anti-oxidation layer that is disposed on the bonding layer and prevents the bonding layer from being oxidized.

[0008] For example, the bonding layer is made of nickel, the anti-oxidation layer is made of gold, and the protective layer is made of polyimide. In the electrode soldered to the wiring, the portion of the anti-oxidation layer is covered with the protective layer.

[0009] The polyimide used as the protective layer has weak adhesion to the gold antioxidant layer. Therefore, when a thermal cycle test of the semiconductor device is performed, stress acts on the adhesive surface between the antioxidant layer and the protective layer, which may cause the protective layer to peel off from the antioxidant layer and reduce the insulating properties.

[0010] Therefore, for example, Patent Document 1 proposes to improve the adhesive strength between the polyimide and the aluminum film by interposing an amorphous silicon film, which has strong adhesive strength with the polyimide, between the polyimide protective layer and the aluminum film serving as the electrode.

[0011] Furthermore, Patent Document 2 proposes improving the adhesion between the polyimide and the aluminum film by interposing a hexamethyldisilane film, which has strong adhesion to polyimide, between the polyimide protective layer and the aluminum film electrode. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-277512 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-189309 Summary of the Invention [Problem to be solved by the invention]

[0013] The techniques proposed in the above-mentioned Patent Documents 1 and 2 may result in a decrease in the adhesion of polyimide in the electrodes of a semiconductor device if the material that adheres to the polyimide is other than aluminum.

[0014] An object of the present specification is to provide a semiconductor module including a protective layer that has high bonding strength with the electrode portion. [Means for solving the problem]

[0015] According to one embodiment of the semiconductor module disclosed in this specification, the semiconductor module comprises a semiconductor device, a bonding layer disposed on the semiconductor device, containing nickel or copper and electrically connecting to the semiconductor device, a solder portion disposed on the bonding layer and containing gold, and a protective layer disposed directly on the bonding layer and covering the outer periphery of the bonding layer.

[0016] In this semiconductor module, the outer peripheral edge of the solder portion preferably contacts the inner peripheral edge of the protective layer.

[0017] In this semiconductor module, the outer peripheral edge of the solder portion is preferably located inside the inner peripheral edge of the protective layer.

[0018] In particular, in this semiconductor module, it is preferable that the bonding layer be exposed between the outer peripheral edge of the solder portion and the inner peripheral edge of the protective layer.

[0019] In this semiconductor module, the arithmetic mean roughness of the surface of the portion of the bonding layer where the protective film is disposed is preferably 1 μm or more and 6 μm or less.

[0020] In this semiconductor module, the protective layer preferably includes polyimide or polyamide.

[0021] Furthermore, according to one embodiment of the method for manufacturing a semiconductor module disclosed in this specification, the method includes the steps of forming a bonding layer on the semiconductor device, the bonding layer containing nickel or copper and electrically connecting to the semiconductor device; forming an anti-oxidation layer containing gold on the bonding layer except for the outer periphery of the bonding layer; forming a protective layer on the outer periphery of the bonding layer; and joining the bonding layer region where the anti-oxidation layer is located to wiring using solder.

[0022] In this method for manufacturing a semiconductor module, the step of forming an antioxidant layer preferably includes the steps of forming an antioxidant layer on the entire surface of the bonding layer and removing the antioxidant layer on the outer peripheral edge of the bonding layer.

[0023] In this method of manufacturing a semiconductor module, the step of forming the anti-oxidation layer preferably includes forming the outer peripheral edge of the anti-oxidation layer at the same position as the inner peripheral edge of the protective layer. [Effects of the Invention]

[0024] The semiconductor module disclosed in the present specification described above includes a protective layer that has high bonding strength with the electrode portion.

[0025] Furthermore, according to the method for manufacturing a semiconductor module disclosed in the present specification, a semiconductor module having a protective layer with high bonding strength to the electrode portion can be obtained. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1A is a plan view of one embodiment of a semiconductor module disclosed in this specification, and FIG. 1B is a cross-sectional view taken along line XX'. [Figure 2] 1A and 1B are diagrams illustrating a bonding layer. [Figure 3] 10A and 10B are diagrams illustrating a modified example of the semiconductor module disclosed in this specification. [Figure 4] 1A to 1C are diagrams (part 1) illustrating steps in one embodiment of a method for manufacturing a semiconductor module disclosed in this specification. [Figure 5] 10A to 10C are diagrams (part 2) illustrating steps in one embodiment of the method for manufacturing a semiconductor module disclosed in this specification. [Figure 6] 10A to 10C are views (part 3) illustrating steps in one embodiment of the method for manufacturing a semiconductor module disclosed in this specification. [Figure 7] 10A to 10C are views (part 4) illustrating steps in one embodiment of the method for manufacturing a semiconductor module disclosed in this specification. [Figure 8]5 is a diagram (part 5) showing a process of an embodiment of the method for manufacturing a semiconductor module disclosed in this specification. [Figure 9] 6 is a diagram (part 6) showing a process of an embodiment of the method for manufacturing a semiconductor module disclosed in this specification. [Figure 10] 7 is a diagram (part 7) showing a process of an embodiment of the method for manufacturing a semiconductor module disclosed in this specification. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0027] A preferred embodiment of the semiconductor module disclosed in this specification will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to the embodiment, but extends to the inventions set forth in the claims and their equivalents.

[0028] FIG. 1A is a plan view of one embodiment of a semiconductor module disclosed in this specification, and FIG. 1B is a cross-sectional view taken along line XX'.

[0029] The semiconductor module 10 includes a semiconductor device 11 and an insulating substrate 12 that supports the semiconductor device 11. The semiconductor module 10 has a MOSFET as the semiconductor device 11. Wiring 20a, 20b that electrically connects the semiconductor device 11 to the outside are soldered to the semiconductor device 11. The semiconductor module 10 may be housed in a housing (not shown). Note that the wiring is not shown in FIG. 1(A).

[0030] The semiconductor device 11 has a device body 11a, a source electrode 11b, a gate electrode 11c, and a drain electrode 11d. The source electrode 11b and the gate electrode 11c are disposed on a first surface s1 of the device body 11a, and the drain electrode 11d is disposed on a second surface s2 of the device body 11a.

[0031] The semiconductor module 10 also has a first protective layer 15 that covers the first surface s1 except for the areas where the source electrode 11b and the gate electrode 11c are arranged. The first protective layer 15 has electrical insulation properties and is made of, for example, polyimide or polyamide.

[0032] The insulating substrate 12 supports the semiconductor device 11 and dissipates heat generated by the semiconductor device 11. The insulating substrate 12 has a substrate body 12a, a circuit board 12b, and a metal plate 12c.

[0033] The substrate body 12a has electrical insulation and thermal conductivity as well as mechanical strength to support the semiconductor device 11. The substrate body 12a is made of ceramics such as aluminum nitride, for example.

[0034] The circuit board 12b is electrically connected to the drain electrode 11d via the solder layer 12d, and also joins the semiconductor device 11 to the insulating substrate 12. The circuit board 12b may be a copper plate that electrically connects the drain electrode 11d to wiring (not shown). The circuit board 12b is electrically connected to the outside of the semiconductor device 11 via wiring (not shown).

[0035] The metal plate 12c is joined to a housing (not shown) or the like to fix the semiconductor module 10 to the housing and to conduct heat generated in the semiconductor module 10 to the housing. The metal plate 12c is formed using a metal with high thermal conductivity, such as copper.

[0036] The dimensions of the substrate body 12a can be determined appropriately depending on the dimensions of the semiconductor device 11. For example, if the dimensions of the semiconductor device 11 are 10 mm long x 10 mm wide x 1 mm thick, the dimensions of the substrate body 12a may be 30 mm long x 30 mm wide x 0.5 mm thick, and the dimensions of the metal plate 12c may be 25 mm long x 25 mm wide x 1 mm thick.

[0037] The semiconductor module 10 includes a first electrode structure 10a electrically connecting a source electrode 11b of the semiconductor device 11 to a wiring 20a, and a second electrode structure 10b electrically connecting a gate electrode 11c of the semiconductor device 11 to a wiring 20b. The source electrode 11b has an outer periphery covered with a protective film 15, and the inner periphery not covered by the protective film 15 is recessed. The gate electrode 11c is also disposed in a recess surrounded by the protective film 15. The outer periphery of the source electrode 11b and the gate electrode 11c may or may not be covered by the protective film 15. The contour of the recess may have any shape, including a circular shape, but is preferably rectangular in a planar view for practical use. The following description will be given assuming that the contour of the recess is rectangular in a planar view. Similarly, the bonding layers 14a and 14b described below may have any shape, including a circular shape, but are preferably rectangular in a planar view for practical use, and will therefore be described assuming that they are rectangular in a planar view for practical use.

[0038] Next, the first electrode structure 10a will be described in detail below. The first electrode structure 10a has a bonding layer 14a and a solder portion 17a. The bonding layer 14a is electrically conductive and electrically connected to the inside of the semiconductor device 11 via the source electrode 11b. The bonding layer 14a has a rectangular shape in a plan view and is disposed above and near the center of the source electrode 11b. The source electrode 11b is formed using, for example, aluminum or an aluminum alloy.

[0039] The thickness of the source electrode 11b is preferably in the range of 3 μm to 6 μm. When the thickness of the source electrode 11b is 3 μm or more, the electrical characteristics and mechanical strength of the conductive layer can be ensured. Furthermore, if the thickness of the source electrode 11b is 6 μm or more, there is a risk that the source electrode 11b may apply stress to the device body 11a if it is warped.

[0040] The bonding layer 14a of the first electrode structure 10a is disposed on the source electrode 11b and electrically connected to the source electrode 11b. The bonding layer 14a mediates solder bonding between the source electrode 11b and the solder portion 17a. The bonding layer 14a has a rectangular shape in a plan view, and its outer periphery is covered with a protective film 15. The bonding layer 14a is formed using nickel, a nickel alloy, copper, or a copper alloy.

[0041] 2, the bonding layer 14a has a first region 14a1 arranged along the outer periphery and a second region 14a2 arranged inside the first region 14a1. In the semiconductor module 10, the first region 14a1 and the second region 14a2 are in contact with each other. That is, the first region 14a1 is an area arranged along the outer periphery of the bonding layer 14a, and the second region 14a2 is an area inside the first region 14a1.

[0042] The first region 14a1 is an area that is covered with a protective layer 16, which will be described later. The second region 14a2 is an area where the solder portion 17a is disposed.

[0043] The first region 14a1 has a predetermined width and is disposed along the outer periphery of the bonding layer 14a. The width of the first region 14a1 is preferably 30 μm or more from the viewpoint of bonding the second protective layer 16 to the bonding layer 14a with sufficient bonding strength. The upper limit of the width of the first region 14a1 can be determined appropriately depending on the dimensions of the bonding layer 14a or the solder portion 17a.

[0044] Furthermore, it is preferable that the arithmetic mean roughness of the surface of the first region 14a1 be 1 μm or more and 6 μm or less, from the viewpoint that the second protective layer 16 described later fits into the irregularities on the surface of the first region 14a1 and is bonded to the bonding layer 14a with sufficient bonding strength.

[0045] The thickness of the bonding layer 14a is preferably in the range of 3 μm to 6 μm. When the thickness of the bonding layer 14a is 3 μm or more, the electrical characteristics and mechanical strength of the conductive layer can be ensured. Furthermore, when the thickness of the bonding layer 14a is 6 μm or more, if the bonding layer 14a is warped, stress may be applied to the semiconductor device 11.

[0046] The solder portion 17a of the first electrode structure 10a is disposed on the second region 14a2 of the bonding layer 14a and electrically connects to the bonding layer 14a. The solder portion 17a also electrically connects the bonding layer 14a and the wiring 20a. The solder portion 17a is formed using a solder containing gold. When soldered to the bonding layer 14a, the solder portion 17a may be an alloy containing the material that forms the bonding layer 14a.

[0047] Next, the second electrode structure 10b will be described in detail below. The second electrode structure 10b has a bonding layer 14b and a solder portion 17b. The bonding layer 14b is electrically conductive and electrically connected to the semiconductor device 11 via the gate electrode 11c. The bonding layer 14b has a rectangular shape in a plan view and has the same contour as the gate electrode 11c. The gate electrode 11c is formed using, for example, aluminum or an aluminum alloy. The above description of the thickness of the first electrode structure 10a relative to the source electrode 11b also applies, as appropriate, to the gate electrode 11c.

[0048] The bonding layer 14b of the second electrode structure 10b is disposed on the gate electrode 11c and electrically connected to the gate electrode 11c. The bonding layer 14b mediates solder bonding between the gate electrode 11c and the solder portion 17b. The bonding layer 14b has a rectangular shape in a plan view and has the same outline as the gate electrode 11c. The bonding layer 14b is formed using nickel, a nickel alloy, copper, or a copper alloy.

[0049] As shown in FIG. 2, the bonding layer 14b has a first region 14b1 arranged along the outer periphery and a second region 14b2 arranged inside the first region 14b1.

[0050] The first region 14b1 is an area covered with the protective layer 16. The second region 14b2 is an area where the solder portion 17b is disposed.

[0051] The above description of the first region 14a1 and the second region 14a2 of the bonding layer 14a in the first electrode structure 10a is also applied to the first region 14b1 and the second region 14b2 of the second electrode structure 10b as appropriate.

[0052] Moreover, the above description of the thickness of the bonding layer 14a of the first electrode structure 10a also applies appropriately to the bonding layer 14b of the second electrode structure 10b.

[0053] The solder portion 17b of the second electrode structure 10b is disposed on the second region 14b2 of the bonding layer 14b and electrically connects to the bonding layer 14b. The solder portion 17b also electrically connects the bonding layer 14b to the wiring 20b. The solder portion 17b is formed using a solder containing gold. When soldered to the bonding layer 14b, the solder portion 17b may be an alloy containing the material that forms the bonding layer 14b.

[0054] The semiconductor module 10 includes a second protective layer 16 that covers the first surface s1 of the semiconductor device 11 except for the solder portions 17a and 17b.

[0055] The second protective layer 16 is disposed directly on the first region 14a1 of the bonding layer 14a of the first electrode structure 10a and covers the outer peripheral edge of the bonding layer 14a. The edge 16a of the second protective layer 16 on the second region 14a2 side is disposed on the first region 14a1 and contacts the edge 17a1 of the solder portion 17a. In other words, the inner peripheral edge of the second protective layer 16 contacts the outer peripheral edge of the solder portion 17a. As shown by hatching in FIG. 1(A), the second protective layer 16 is bonded (adhered) to the surface of the first region 14a1 via the bonding surface 16a1 with the first region 14a1. The bonding surface 16a1 has an annular shape surrounding the solder portion 17a.

[0056] The second protective layer 16 is disposed directly on the first region 14b1 of the bonding layer 14b of the second electrode structure 10b, covering the outer peripheral edge of the bonding layer 14b. The edge 16b of the second protective layer 16 on the second region 14b2 side is disposed on the first region 14b1 and contacts the edge 17b1 of the solder portion 17b. In other words, the inner peripheral edge of the second protective layer 16 contacts the outer peripheral edge of the solder portion 17b. As shown by hatching in FIG. 1(A), the second protective layer 16 is bonded (adhered) to the surface of the first region 14b1 via the bonding surface 16b1 with the first region 14b1. The bonding surface 16b1 has an annular shape surrounding the solder portion 17b.

[0057] The second protective layer 16 has electrical insulating properties and is made of, for example, polyimide or polyamide.

[0058] According to the semiconductor module of the present embodiment, the bonding strength between the bonding layers of the first electrode structure and the second electrode structure and the second protective layer is high, preventing the second protective layer from peeling off from the bonding layer. This protects the first electrode structure and the second electrode structure by the second protective layer and ensures electrical insulation, improving the reliability of the semiconductor module.

[0059] For example, when warping occurs in the semiconductor device due to a temperature change or the like in the semiconductor module 10, shear stress may act between the surface of the first region of the bonding layer and the second protective layer. Because the second protective layer is bonded (adhered) to the surface of the first region by the bonding surface with the first region, the shear force acting per unit area of the bonding surface between the second protective layer and the first region of the bonding layer is small, and therefore the second protective layer is unlikely to peel off from the first region of the bonding layer.

[0060] Next, a modified example of the semiconductor module of the above-described embodiment will be described below with reference to FIG.

[0061] 3 is a diagram showing a modified example of the semiconductor module disclosed in this specification. In the semiconductor module 10 of this modified example, in the first electrode structure 10a, the edge 16a of the second protective layer 16 on the second region 14a2 side is spaced apart from the edge 17a1 of the solder portion 17a, and the bonding layer 14a is exposed between both edges. In other words, the inner peripheral edge of the second protective layer 16 is spaced apart from the outer peripheral edge of the solder portion 17a, and the bonding layer 14a is exposed between both edges. In other words, the first region 14a1 and the second region 14a2 are spaced apart. At this time, the solder does not wet and spread in the region where the bonding layer 14a is exposed because the bonding layer 14a is exposed to the air and oxidized.

[0062] In manufacturing the semiconductor module 10, spacing the edge 16a of the second protective layer 16 on the second region 14a2 side from the edge 17a1 of the solder portion 17a, i.e., spacing the inner peripheral edge of the second protective layer 16 from the outer peripheral edge of the solder portion 17a, allows for more flexibility in the positional accuracy when forming the second protective layer 16 and / or the solder portion 17a, thereby reducing the time and cost of the manufacturing process.

[0063] In the second electrode structure 10b, the edge 16b of the second protective layer 16 on the second region 14b2 side is spaced apart from the edge 17b1 of the solder portion 17b, and the bonding layer 14b is exposed between both edges. In other words, the inner peripheral edge of the second protective layer 16 and the outer peripheral edge of the solder portion 17b are spaced apart, thereby achieving the same effect as described above. The other configurations of this variation are the same as those of the above-described embodiment.

[0064] Next, a preferred embodiment of a method for manufacturing the above-mentioned semiconductor module will be described below with reference to FIGS.

[0065] First, as shown in FIG. 4, a semiconductor device 11 is prepared, which includes a source electrode 11b, a gate electrode 11c, and a drain electrode 11d. The source electrode 11b and the gate electrode 11c may be made of, for example, aluminum or an aluminum alloy. The source electrode 11b and the gate electrode 11c may have a thickness of, for example, 5 μm. Although FIG. 4 shows only one semiconductor device 11, multiple semiconductor devices 11 are prepared on a single wafer. The following process description is for one semiconductor device 11; similar processes are also performed for other semiconductor devices.

[0066] Next, as shown in FIG. 5 , a first protective layer 15 is formed on the semiconductor device 11 to obtain a semiconductor structure 30. The first protective layer 15 is formed on the first surface s1 of the semiconductor device 11 so as to expose the source electrode 11b and the gate electrode 11c. The first protective layer 15 may cover the outer peripheries of the source electrode 11b and the gate electrode 11c. Whether the first protective layer 15 covers the outer peripheries of the source electrode 11b and the gate electrode 11c or not may be appropriately selected taking into account the sizes of the source electrode 11b and the gate electrode 11c. Hereinafter, the case where the outer periphery of the source electrode 11b is covered with the first protective layer 15 and the outer periphery of the gate electrode is not covered with the first protective layer 15 will be described. For example, the first protective layer 15 is formed by applying liquid polyimide or polyamide to the first surface s1 of the semiconductor device 11 so as to expose the source electrode 11b and the gate electrode 11c, and then heating and curing the applied liquid.

[0067] Next, as shown in FIG. 6, a bonding layer 14a is formed on the source electrode 11b, and a bonding layer 14b is formed on the gate electrode 11c. The bonding layers 14a and 14b are formed using a plating technique such as electroless plating. The bonding layers 14a and 14b are preferably formed using nickel, a nickel alloy, copper, or a copper alloy. Specifically, the bonding layers 14a and 14b may be formed as nickel-phosphorus films using an electroless plating technique. The thickness of the bonding layers 14a and 14b may be, for example, 5 μm.

[0068] Next, as shown in FIG. 7, an antioxidant layer 18a is formed on the bonding layer 14a, and an antioxidant layer 18b is formed on the bonding layer 14b. The antioxidant layers 18a and 18b prevent the bonding layers 14a and 14b from oxidizing. The antioxidant layers 18a and 18b are formed as gold or gold alloy films using a plating technique such as electroless plating. The thickness of the antioxidant layers 18a and 18b is preferably in the range of 0.025 μm to 0.1 μm. A thickness of 0.025 μm ensures a thickness that prevents the bonding layers 14a and 14b from oxidizing. Furthermore, a thickness of 0.1 μm or less reduces material costs and ensures thickness uniformity.

[0069] Next, as shown in FIG. 8 , the antioxidant layer 18a on the first region 14a1 of the bonding layer 14a is removed to expose the first region 14a1 of the bonding layer 14a. The antioxidant layer 18b on the first region 14b1 of the bonding layer 14b is also removed to expose the first region 14b1 of the bonding layer 14b. Specifically, a first mask (not shown) is formed on the first surface s1 of the semiconductor device 11 so as to expose only the first region 14a1 of the bonding layer 14a and the first region 14b1 of the bonding layer 14b, and the portions of the bonding layer 14a and the bonding layer 14b exposed by the first mask are etched and removed. Dry etching, such as plasma etching, or wet etching can be used for the etching. Alternatively, blasting may be used to remove the portions of the bonding layer 14a and the bonding layer 14b exposed by the mask. Alternatively, the portion of the antioxidant layer 18a on the first region 14a1 of the bonding layer 14a and the portion of the antioxidant layer 18b on the first region 14b1 of the bonding layer 14b may be removed by scanning with a laser.

[0070] It is preferable to set the arithmetic mean roughness of the surface of first region 14a1 or first region 14b1 to 1 μm or less and 6 μm or less by adjusting the above-mentioned etching conditions, the particle size of particles used in the blasting treatment, the laser irradiation conditions, etc. This allows second protective layer 16 to fit into the irregularities formed on the surface of first region 14a1 or first region 14b1, thereby increasing the bonding strength with second protective layer 16.

[0071] Next, as shown in FIG. 9 , a second protective layer 16 is formed on the first region 14a1 of the bonding layer 14a so as to cover the outer periphery of the bonding layer 14a, and a second protective layer 16 is formed on the first region 14b1 of the bonding layer 14b so as to cover the outer periphery of the bonding layer 14b. The second protective layer 16 is formed on the first surface s1 of the semiconductor device 11 so as to cover the first protective layer 15, leaving only the second region 14a2 of the bonding layer 14a and the second region 14b2 of the bonding layer 14b exposed. Here, the second protective layer 16 is preferably formed so as not to cover the antioxidant layers 18a and 18b. This is because if the second protective layer 16 covers the antioxidant layer 18a or the antioxidant layer 18b, it will be difficult for the solder portions 17a and 17b, described below, to bond to the second regions 14a2 and 14b2 of the bonding layers 14a and 14b.

[0072] The second protective layer 16 may be formed, for example, as follows. In a first method, a second mask (not shown) is formed to cover the first mask on the antioxidant layer 18a and the antioxidant layer 18b. The second mask is formed to cover a portion of the first region 14a1 of the bonding layer 14a on the second region 14a2 side and a portion of the first region 14b1 of the bonding layer 14b on the second region 14b2. The first mask not covered by the second mask is then removed. With the second region 14a2 of the antioxidant layer 18a and the second region 14b2 of the antioxidant layer 18b covered by the first mask, liquid polyimide or polyamide may be applied to the first surface s1 of the semiconductor device 11 by spin coating, and then heated and cured to form the second protective layer 16. Heating conditions may be, for example, 350°C for one hour. The first mask is then removed from the antioxidant layer 18a and the antioxidant layer 18b.

[0073] 9 is removed, and then photosensitive polyimide or polyamide is applied onto the first surface s1 of the semiconductor device 11 and then patterned to form a provisionally cured second protective layer 16 on the first surface s1 of the semiconductor device 11. The provisionally cured second protective layer 16 may then be heated and fully cured to form the second protective layer 16.

[0074] 9 is removed, liquid polyimide or polyamide may be applied to predetermined regions on the first surface s1 of the semiconductor device 11 using an inkjet method, and then heated and fully cured to form the second protective layer 16. Then, the multiple semiconductor structures 30 formed on one wafer are cut into individual semiconductor structures 30.

[0075] Next, as shown in FIG. 10, the drain electrode 11d of the semiconductor device 11 in the semiconductor structure 30 is joined onto the circuit board 12b of the insulating substrate 12 with a solder layer 12d interposed therebetween.

[0076] Next, as shown in FIGS. 1A and 1B, the second region 14a2 of the bonding layer 14a, on which the antioxidant layer 18a is disposed, is electrically joined to the wiring 20a using solder to form the solder portion 17a. The antioxidant layer 18a melts with the solder and becomes part of the solder portion 17a. That is, the solder portion 17a contains gold. Similarly, the second region 14b2 of the bonding layer 14b, on which the antioxidant layer 18b is disposed, is electrically joined to the wiring 20b using solder to form the solder portion 17b. The antioxidant layer 18b melts with the solder and becomes part of the solder portion 17b. Through the above-described process, the semiconductor module 10 is obtained. Furthermore, when the bonding layer 14a and the wiring 20a are joined using the solder portion 17a, if a portion of the bonding layer 14a is exposed to the surface, the surface of the bonding layer 14a is exposed to the air and oxidized, preventing the solder from spreading. In this case, the outer peripheral edge of the solder portion 17a and the outer peripheral edge of the antioxidant layer 18a are aligned. In the above-described modified example of the semiconductor module of this embodiment, the part of the bonding layer 14a exposed to the surface is the area sandwiched between the outer peripheral edge of the solder portion 17a or the outer peripheral edge of the antioxidant layer 18a and the inner peripheral edge of the protective layer 16.

[0077] According to the manufacturing method of the semiconductor module of this embodiment described above, the second protective layer 16 is formed directly on the first regions 14a1, 14b1 of the bonding layers 14a, 14b, and is not formed on the second regions 14a2, 14b2 of the bonding layers 14a, 14b, so that the second protective layer 16 has high bonding strength with the bonding layers 14a, 14b.

[0078] In the present invention, the semiconductor module and the method for manufacturing the semiconductor module according to the above-described embodiments can be modified as appropriate without departing from the spirit of the present invention.

[0079] For example, although the semiconductor modules in the above-described embodiments have MOSFETs as semiconductor devices, the semiconductor devices are not limited to this. The semiconductor modules may have semiconductor devices such as IGBTs or FWDs as semiconductor devices.

[0080] Furthermore, in the semiconductor module of the above-described embodiment, a bonding layer is disposed on the source electrode of the semiconductor device, but an electrode layer formed of a conductor may be disposed between the source electrode and the bonding layer. The material and thickness of this conductor may be the same as those of the source electrode. Similarly, an electrode layer formed of a conductor may be disposed between the gate electrode of the semiconductor device and the bonding layer. The material and thickness of this conductor may be the same as those of the gate electrode.

[0081] Furthermore, in the semiconductor module of the above-described embodiment, the second protective layer that protects the first electrode structure and the second electrode structure is common, but the protective layer that protects the first electrode structure and the second electrode structure may be made of different materials.

[0082] In addition, in the manufacturing method of the semiconductor module of the above-mentioned embodiment, a protective layer is formed on the first region of the bonding layer so as to cover the outer edge of the bonding layer, and then the second region of the bonding layer on which the anti-oxidation layer is arranged is electrically joined to the wiring using solder, but the order of these steps may be reversed. [Explanation of symbols]

[0083] 10 Semiconductor Module 10a 1st electrode structure 10b Second electrode structure 11 Semiconductor devices 11a Device body 11b Source electrode 11c Gate electrode 11d Drain electrode 12 Insulating substrate 12a Board body 12b Circuit board 12c metal plate 12d solder layer 14a, 14b bonding layer 15 1st protective layer 16 Second protective layer 17a, 17b Solder part 18a, 18b Antioxidant layer 20a, 20b wiring 30 Substrate structure

Claims

1. a semiconductor device having a first electrode formed containing aluminum and a second electrode formed containing aluminum; a first bonding layer formed by containing nickel or copper and disposed on the semiconductor device and having a back surface connected to the first electrode; a second bonding layer formed by containing nickel or copper and disposed on the semiconductor device and having a rear surface connected to the second electrode; a protective layer in contact with a side surface of the first electrode, a side surface of the first bonding layer, a side surface of the second electrode, and a side surface of the second bonding layer, and covering an outer periphery of the first bonding layer and an outer periphery of the second bonding layer; a first solder portion including gold and disposed on the first bonding layer and inside the protective layer; a second solder portion including gold and disposed on the second bonding layer and inside the protective layer; the protective layer includes: a first protective layer formed containing polyimide or polyamide and in direct contact with a side surface of the first electrode, a side surface of the first bonding layer, and a side surface of the second electrode, and a side surface of the second bonding layer; and a second protective layer formed containing polyimide or polyamide and disposed on the first protective layer, covering an outer periphery of the first bonding layer and an outer periphery of the second bonding layer; A semiconductor module, wherein the surfaces of the first bonding layer and the second bonding layer in the areas covered by the second protective layer are rougher than the surfaces of the first bonding layer and the second bonding layer in the areas not covered by the second protective layer.

2. The semiconductor module according to claim 1 , wherein the protective layer is provided from an outer periphery on the first bonding layer to an outer periphery on the second bonding layer.

3. The semiconductor module according to claim 1 , wherein the protective layer covers an outer periphery of an upper surface of the first electrode.

4. The semiconductor module according to claim 1 , wherein an outer peripheral edge of the first solder portion and an outer peripheral edge of the second solder portion are in contact with an inner peripheral edge of the protective layer.

5. 4. The semiconductor module according to claim 1, wherein an outer peripheral edge of the first solder portion and an outer peripheral edge of the second solder portion are located inside an inner peripheral edge of the protective layer.

6. 6. The semiconductor module according to claim 1, wherein the semiconductor device is a transistor, the first electrode is a source electrode, and the second electrode is a gate electrode.

7. The semiconductor module according to claim 1 , wherein the outer periphery of the first bonding layer and the outer periphery of the second bonding layer have a surface with an arithmetic mean roughness of 1 μm or more and 6 μm or less.

8. The semiconductor module according to claim 1 , wherein the first electrode surrounds the second electrode in a U-shape in plan view.

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