Semiconductor laminate and method for manufacturing semiconductor laminate

Abstract

To provide a high-quality semiconductor laminate with a p-type layer.SOLUTION: A semiconductor laminate comprises a substrate, and a p-type layer provided above the substrate including a group III nitride containing Mg. C concentration in the p-type layer is less than 5×1015 cm-3, and O concentration in the p-type layer is less than 5×1015 cm-3. Si concentration in the p-type layer is less than 1×1015 cm-3, and F concentration in the p-type layer is greater than or equal to 1×1014 cm-3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor laminate and a method for manufacturing the semiconductor laminate. [Background technology]

[0002] Various methods have been disclosed as manufacturing methods for obtaining p-type Group III nitride crystals (for example, Patent Documents 1 and 2, and Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2008 / 117750 [Patent Document 2] International Publication No. 2004 / 061923 [Non-patent literature]

[0004] [Non-Patent Document 1] Y.Mori et al.:Japanese Journal of Applied Physics 58, SC0803 (2019) Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to obtain a high-quality semiconductor laminate having a p-type layer. [Means for solving the problem]

[0006] According to one aspect of the present invention, A substrate; a p-type layer provided above the substrate and having a group III nitride containing Mg; Equipped with The C concentration in the p-type layer is 5×10 15 cm -3 is less than The O concentration in the p-type layer is 5×10 15 cm -3 is less than The Si concentration in the p-type layer is 1×10 15 cm -3 is less than The F concentration in the p-type layer is 1×10 14 cm -3 That's all A semiconductor stack is provided.

[0007] According to another aspect of the present invention, A substrate; an underlayer provided on the substrate and including a group III nitride; a p-type layer provided on the underlayer and having a group III nitride containing Mg; Equipped with The C concentration in each of the underlayer and the p-type layer is 5×10 15 cm -3 is less than The O concentration in each of the underlayer and the p-type layer is 5×10 15 cm -3 is less than The Si concentration in the p-type layer is 1×10 15 cm -3 is less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. A semiconductor stack is provided.

[0008] According to yet another aspect of the present invention, preparing a substrate and a hydride vapor phase growth apparatus containing the substrate; growing a p-type layer having a group III nitride containing Mg above the substrate using the hydride vapor phase epitaxy apparatus; Equipped with In the step of growing the p-type layer, Mg is doped into the p-type layer by transporting MgF2 while etching it with a halogen-containing gas. A method for manufacturing a semiconductor stack is provided. [Effects of the Invention]

[0009] According to the present invention, a high-quality semiconductor laminate having a p-type layer can be obtained. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor laminate according to a first embodiment of the present invention. [Figure 2] This is a schematic diagram of an HVPE device, showing the crystal growth process being carried out inside the reaction vessel. [Figure 3] FIG. 1 is a schematic diagram of an HVPE apparatus, showing the reactor chamber with its furnace opening open. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a semiconductor laminate according to a second embodiment of the present invention. [Figure 5] FIG. 10 is a diagram showing SIMS depth profiles in the semiconductor stacks of Sample A and Sample B1. [Figure 6] FIG. 1 is a graph showing hole concentrations relative to Mg concentrations in semiconductor laminates of Sample A and Samples B1 to B3. [Figure 7] FIG. 1 is a diagram showing the activation rate of Mg relative to the Mg concentration in the semiconductor laminates of Sample A and Samples B1 to B3. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Insights gained by the inventor> Conventionally, metalorganic chemical vapor deposition (MOCVD) has been the main method used for growing p-type Group III nitride semiconductors industrially.

[0012] In the MOCVD method, for example, biscyclopentadienyl magnesium (Cp2Mg) is used as a dopant. This allows the Mg concentration to be controlled relatively easily. In addition, the MOCVD method allows n-type impurities such as silicon (Si) or oxygen (O), which compensate for the acceptor, to be controlled to a low concentration. As a result, p-type nitride semiconductors grown by the MOCVD method can be grown at a low concentration of 10 15 ~10 18 cm -3 This makes it possible to realize a wide range of hole concentrations.

[0013] However, in the MOCVD method, it is difficult to prevent carbon (C) from being mixed into the p-type layer due to various organic source gases. 15 Although it was possible to achieve a hole concentration of about 1000 nm, it was difficult to control a low hole concentration due to the effect of carrier compensation by C.

[0014] On the other hand, other growth methods have had the following problems:

[0015] For example, Patent Document 2 discloses an ammonothermal method that suppresses the incorporation of impurities such as O, which acts as a compensating donor. However, the ammonothermal method is primarily a technique for obtaining bulk crystals, and it has been difficult to grow thin films. This is because the phenomenon known as meltback, in which GaN dissolves in a Ga solution, and growth during the temperature and pressure increase process cannot be ignored. For this reason, it has been difficult to manufacture a stacked structure having a thin p-type layer using the ammonothermal method. Furthermore, for the same reasons as those mentioned above, it has been difficult to manufacture a stacked structure having multiple layers.

[0016] Furthermore, the ammonothermal method involves the incorporation of high concentrations of O, which acts as a compensating donor, making it extremely difficult to achieve p-type nitride semiconductors with particularly low hole concentrations.

[0017] Furthermore, for example, Non-Patent Document 1 discloses a flux method for growing a stacked layer having a p-type layer. However, even in the flux method, the process results in the incorporation of a high concentration of O as a compensating donor. This makes it extremely difficult to realize a p-type nitride semiconductor with a particularly low hole concentration.

[0018] Furthermore, for example, in conventional hydride vapor phase epitaxy (HVPE), quartz has been used for the main parts of the growth equipment. As a result, conventional HVPE methods have resulted in high concentrations of Si or O contaminated from the quartz. Even if p-type nitride semiconductors are obtained using HVPE, the inclusion of Si or O as compensating donors makes it difficult to realize p-type nitride semiconductors with particularly low hole concentrations.

[0019] Furthermore, conventional HVPE methods can also cause problems due to dopants.

[0020] For example, when using metallic Mg as a dopant, the metallic Mg is placed in a region of the reaction vessel that is heated to about 800°C, and then transported in vapor form to the growth region. However, the metallic Mg reacts with the quartz that constitutes the high-temperature reaction region, making it difficult to transport the dopant.

[0021] For example, when magnesium oxide (MgO) is used as a dopant, Mg can be transported relatively easily. However, because O, a compensating donor contained in the dopant, is mixed into the crystal, it has been difficult to realize a p-type nitride semiconductor with a particularly low hole concentration.

[0022] For example, when magnesium nitride (Mg3N2) is used as a dopant, Mg can be transported relatively easily. However, because Mg-containing gas is constantly supplied from the Mg3N2 placed in the reaction vessel, a certain amount of Mg is also taken in when growing the non-p-type layer.

[0023] Therefore, the present inventors conducted extensive research to solve the above-mentioned problems with growing p-type nitride semiconductors using conventional manufacturing methods. As a result, they discovered that by using magnesium fluoride (MgF2) as a dopant in addition to the HVPE technology (JP 2018-070405 A) invented by the present inventors to obtain high-purity nitride semiconductors, it is possible to stably control the hole concentration over a wide range.

[0024] The following embodiments are based on the above findings made by the present inventors.

[0025] <First embodiment of the present invention> A first embodiment of the present invention will be described below with reference to the drawings.

[0026] (1) Semiconductor laminate A semiconductor laminate 1 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic cross-sectional view showing the semiconductor laminate according to this embodiment.

[0027] 1, the semiconductor laminate 1 of this embodiment is configured as a disc-shaped laminate used in manufacturing a semiconductor device. Specifically, the semiconductor laminate 1 is configured as a laminate for manufacturing, for example, a pn junction diode as a semiconductor device.

[0028] Specifically, the semiconductor laminate 1 includes, for example, a substrate 10, an underlayer 20, and a p-type layer 30.

[0029] [substrate] The substrate 10 is made of a single crystal of a group III nitride semiconductor, for example, a single crystal of gallium nitride (GaN).

[0030] The plane orientation of the primary surface (upper surface) of substrate 10 is, for example, the (0001) plane (+c plane, Ga polarity plane). The GaN crystal constituting substrate 10 may have a predetermined off-angle with respect to the primary surface of substrate 10. The off-angle refers to the angle between the normal direction to the primary surface of substrate 10 and the main axis (c-axis) of the GaN crystal constituting substrate 10. Specifically, the off-angle of substrate 10 is, for example, not less than 0° and not more than 1.2°.

[0031] The main surface of the substrate 10 is an epi-ready surface, and the root mean square roughness (RMS) of the main surface of the substrate 10 is, for example, 10 nm or less, and preferably 1 nm or less. Note that "RMS" here refers to the RMS measured over a 20 μm square area with an atomic force microscope (AFM).

[0032] The diameter of the substrate 10 is not particularly limited, but is, for example, 25 mm or more, preferably 50 mm or more, and more preferably 100 mm or more. By making the diameter of the substrate 10 25 mm or more, preferably 50 mm or more, and more preferably 100 mm or more, the productivity of the semiconductor device can be improved.

[0033] The thickness of the substrate 10 is, for example, 150 μm or more and 2 mm or less. When the thickness of the substrate 10 is 150 μm or more, the mechanical strength of the substrate 10 is ensured, and the substrate 10 can stand on its own.

[0034] The conductivity type of the substrate 10 is not particularly limited, but is, for example, n-type. Examples of n-type impurities in the substrate 10 include silicon (Si) and germanium (Ge). In this embodiment, for example, the n-type impurity in the substrate 10 is Si, and the Si concentration in the substrate 10 is 1×10 18 cm -3 3x10 or more 20 cm -3 The following is the result.

[0035] [Base layer] The base layer 20 is preferably provided on the substrate 10, has a group III nitride semiconductor, and is made of a single crystal of the group III nitride semiconductor. The base layer 20 of this embodiment is preferably made of a single crystal of GaN epitaxially grown by a manufacturing method described below.

[0036] The conductivity type of the underlayer 20 is not particularly limited, but is, for example, n-type. Examples of n-type impurities in the underlayer 20 include Si and Ge. In this embodiment, the n-type impurity in the underlayer 20 is, for example, Si, and the Si concentration in the underlayer 20 is, for example, 5×10 14 cm -3 3x10 or more 19 cm -3 As described above, in the MOCVD method, the inclusion of C as an impurity is unavoidable, making it difficult to obtain a low free electron concentration. In contrast, in this embodiment, the HVPE method described below can be used to stably reduce the free electron concentration while reducing the Si concentration in the underlayer 20. This makes it possible to stably manufacture semiconductor devices with high breakdown voltage.

[0037] In this embodiment, the concentration of each impurity other than the n-type impurity in the underlayer 20 is below the measurement limit (lower detection limit) of SIMS by a manufacturing method described later.

[0038] Specifically, the C concentration and the O concentration in the underlayer 20 measured by the SIMS depth profile analysis were 5×10 15 cm -3 is less than.

[0039] The iron (Fe) concentration and boron (B) concentration in the underlayer 20 measured by SIMS depth profile analysis were 1×10 15 cm -3 is less than.

[0040] Furthermore, the underlayer 20 of this embodiment is grown by the HVPE method described below, and is not grown by a flux method using an alkali metal such as sodium (Na) or lithium (Li) as a flux, and therefore does not substantially contain alkali metal elements such as Na or Li.

[0041] Furthermore, none of the following elements is detected in the underlayer 20 of this embodiment: arsenic (As), chlorine (Cl), phosphorus (P), fluorine (F), Na, Li, potassium (K), tin (Sn), titanium (Ti), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), and nickel (Ni).

[0042] That is, the concentrations of these impurities in the underlayer 20 are below the lower detection limit of SIMS. The current lower detection limit of each element in SIMS is as follows:

[0043] As:5×10 12 cm -3 , Cl: 1×10 14 cm -3 , P:2×10 15 cm -3 , F:4×10 13 cm -3 , Na: 5 × 10 11 cm -3 , K:2×10 12 cm -3 , Sn: 1×10 13 cm -3 , Ti: 1×10 12 cm -3 , Mn: 5 × 10 12 cm -3 , Cr:7×10 13 cm -3 , Mo: 1×10 15 cm -3 , W:3×10 16 cm -3 , Ni: 1×10 14 cm -3 .

[0044] The thickness of the underlayer 20 is not particularly limited, but is, for example, 5 μm or more and 200 μm or less. For example, when a practical GaN vertical device is manufactured using the semiconductor laminate 1, the lower the carrier concentration of the underlayer 20, the higher the breakdown voltage of the device that can be manufactured. However, the lower the carrier concentration of the underlayer 20, the lower the breakdown voltage of the device will be due to a phenomenon called punch-through, which is lower than the breakdown voltage predicted from the carrier concentration. For this reason, the lower the carrier concentration of the underlayer 20, the thicker the underlayer 20 needs to be. For example, when the carrier concentration (=Si concentration) of the underlayer 20 is less than the above-mentioned lower limit of 5×10 14 cm -3 In this case, the thickness of the underlayer 20 needs to be 200 μm.

[0045] [p-type layer] The p-type layer 30 is provided, for example, on the base layer 20 (i.e., above the substrate 10), and preferably includes a group III nitride semiconductor and is made of a single crystal of the group III nitride semiconductor. The p-type layer 30 of this embodiment is made of a single crystal of GaN epitaxially grown by the same manufacturing method as the base layer 20, except that it is doped with a p-type impurity.

[0046] The p-type layer 30 contains Mg as a p-type impurity. The Mg concentration in the p-type layer 30 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0047] In this embodiment, the concentration of each impurity other than Mg and fluorine (F) in the p-type layer 30, which will be described later, is below the measurement limit (lower detection limit) of SIMS, due to the manufacturing method described later.

[0048] Specifically, the C concentration, O concentration, and Si concentration in the p-type layer 30 measured by SIMS depth profile analysis were 5×10 15 cm -3 Less than 5 x 10 15 cm -3 Less than, and 1 × 10 15 cm -3 is less than.

[0049] The Fe concentration and B concentration in the p-type layer 30 measured by SIMS depth profile analysis were, for example, 1×10 15 cm -3 is less than.

[0050] Similarly to the underlayer 20, the p-type layer 30 of this embodiment does not substantially contain alkali metal elements such as Na and Li. Furthermore, none of the elements As, Cl, P, Na, Li, K, Sn, Ti, Mn, Cr, Mo, W, and Ni is detected in the p-type layer 30 of this embodiment.

[0051] That is, the concentrations of these impurities in the p-type layer 30 are below the lower detection limit of SIMS. The current lower detection limit of each element in SIMS is as follows:

[0052] As:5×10 12 cm -3 , Cl: 1×10 14 cm -3 , P:2×10 15 cm -3 , Na: 5 × 10 11 cm -3 , K:2×10 12 cm -3 , Sn: 1×10 13 cm -3 , Ti: 1×10 12 cm -3 , Mn: 5 × 10 12 cm -3 , Cr:7×10 13 cm -3 , Mo: 1×10 15 cm -3 , W:3×10 16 cm -3 , Ni: 1×10 14 cm -3 .

[0053] In this way, the unintended incorporation of these impurities into the p-type layer 30 is suppressed, thereby suppressing crystal distortion in the p-type layer 30. Furthermore, the incorporation of the above-described compensating donors such as Si or O into the p-type layer 30 is suppressed, thereby enabling a particularly low hole concentration in the p-type layer 30 to be stably achieved.

[0054] On the other hand, the p-type layer 30 of this embodiment contains fluorine (F) due to the Mg dopant used in the manufacturing method described below.

[0055] Specifically, the F concentration in the p-type layer 30 of this embodiment is, for example, 1×10 14 cm -3 As described above, when the p-type layer 30 contains a small amount of F, the activation rate of Mg in the p-type layer 30 can be improved.

[0056] The F concentration in the p-type layer 30 of this embodiment is, for example, 1×10 16 cm -3 It is preferable that the content of F is not more than 100%. This makes it possible to suppress carrier passivation caused by excessive F contamination.

[0057] As described above, in this embodiment, the p-type layer 30 does not contain any unnecessary impurities other than Mg, and contains a trace amount of F, so that the activation rate of Mg in the p-type layer 30 is equal to or higher than the activation rate of Mg obtained by the MOCVD method. Note that the "activation rate of Mg" here refers to the ratio of the hole concentration in the p-type layer 30 at room temperature (23°C) to the Mg concentration in the p-type layer 30.

[0058] Specifically, in this embodiment, the Mg concentration in the p-type layer 30 is 1×10 18 cm -3 When the concentration is less than 1000 ppm, the activation rate of Mg in the p-type layer 30 is, for example, 11% or more.

[0059] On the other hand, in this embodiment, the Mg concentration in the p-type layer 30 is 1×10 18 cm -3 In the above cases, the p-type layer 30 satisfies the following formula (1). Y≧-5.5logX+110 (1)

[0060] where X is in cm -3 is the Mg concentration in the p-type layer 30 expressed in m / s. Y is the activation rate of Mg in the p-type layer 30 expressed in %.

[0061] In this way, in this embodiment, the p-type layer 30 exhibits a high Mg activation rate, thereby realizing a wide range of hole concentration. Specifically, the hole concentration in the p-type layer 30 of this embodiment can be set to, for example, 1×10 15 cm -3 5x10 or more 18 cm -3 It can be as follows:

[0062] Furthermore, in this embodiment, the supply of Mg-containing gas is appropriately switched from the base layer growth process S20 to the p-type layer growth process S30 by the manufacturing method described below, so that the Mg concentration changes sharply near the interface between the base layer 20 and the p-type layer 30.

[0063] Specifically, the ratio B / A of the Mg concentrations between the underlayer 20 and the p-type layer 30 near the interface is 100 or more.

[0064] where A is the Mg concentration at a position 100 nm from the interface between the underlayer 20 and the p-type layer 30 toward the underlayer 20 in the thickness direction, and B is the Mg concentration at a position 100 nm from the interface between the underlayer 20 and the p-type layer 30 toward the p-type layer 30 in the thickness direction. Note that the "interface" here refers to the maximum Mg concentration in the underlayer 20 and the p-type layer 30, expressed as N Max The minimum value of Mg concentration is N min When the Mg concentration is 10^{(logN Max +logN min ) / 2}.

[0065] In this way, by setting the ratio B / A of the Mg concentration near the interface between the underlayer 20 and the p-type layer 30 to 100 or more, that is, by changing the Mg concentration sharply, the depletion layer width in the pn junction diode can be narrowed.

[0066] Furthermore, in this embodiment, the thickness of the p-type layer 30 obtained by the manufacturing method described below can be thinner than the crystal obtained by the ammonothermal method. Specifically, the thickness of the p-type layer 30 is, for example, 10 nm to 5 μm, preferably 10 nm to 3 μm. When the thickness of the p-type layer 30 is 10 nm or more, the p-type layer 30 can function as a p-type contact layer. On the other hand, when the thickness of the p-type layer 30 is 5 μm or less, inactivation of the p-type layer 30 due to a thick film can be suppressed. This allows a vertical device having the p-type layer 30 to function optimally.

[0067] In this embodiment, as will be described later, the base layer 20 and the p-type layer 30 are grown continuously in the same HVPE apparatus 200. As a result, no unintended high concentration region of Si or O, etc., derived from impurities in the atmosphere, is formed at the interface between the base layer 20 and the p-type layer 30.

[0068] Specifically, in the SIMS depth profile, no spike-like peak is formed between the underlayer 20 and the p-type layer 30, with a Si concentration that is 10 times or more higher than the Si concentration at a position 100 nm from the interface between the underlayer 20 and the p-type layer 30 toward the underlayer 20 in the thickness direction.

[0069] Furthermore, in the SIMS depth profile, a spike-like O concentration peak that is 10 times or more higher than the O concentration at a position 100 nm from the interface between the underlayer 20 and the p-type layer 30 toward the underlayer 20 in the thickness direction is not formed between the underlayer 20 and the p-type layer 30.

[0070] (2) Manufacturing method of semiconductor laminate The method for producing the semiconductor laminate 1 in this embodiment will be specifically described below.

[0071] The method for manufacturing the semiconductor laminate 1 of this embodiment includes, for example, a preparation step S10, a base layer growth step S20, a p-type layer growth step S30, and a carry-out step S40. Note that, hereinafter, the base layer growth step S20 and the p-type layer growth step S30 are also collectively referred to as the "crystal growth step."

[0072] [S10: Preparation process] First, a substrate 10 is prepared, and an HVPE apparatus 200 that accommodates the substrate 10 is prepared. The preparation process S10 of this embodiment includes, for example, an apparatus preparation step S12, a high-temperature bake step S14, and a substrate placement step S18. Note that, as described below, in some cases, the high-temperature bake step S14 may be replaced with a normal bake step S16.

[0073] (S12: Equipment preparation step) The following HVPE apparatus 200 is prepared.

[0074] The configuration of an HVPE apparatus 200 used for growing GaN crystals will be described in detail with reference to FIG. 2 . The HVPE apparatus 200 includes a reaction vessel 203, which is configured, for example, as a cylinder. The reaction vessel 203 has a sealed structure to prevent the outside atmosphere and gases in a glove box 220 (described later) from entering the interior. A reaction chamber 201 in which crystal growth takes place is formed inside the reaction vessel 203. A susceptor 208 is provided in the reaction chamber 201 to hold a substrate 10 made of a GaN single crystal. The susceptor 208 is connected to a rotation shaft 215 of a rotation mechanism 216 and is configured to be freely rotatable. The susceptor 208 also includes an internal heater 210. The temperature of the internal heater 210 can be controlled separately from the zone heater 207 (described later). Furthermore, the upstream side and surrounding area of the susceptor 208 are covered by a heat shield wall 211. By providing the heat insulating wall 211, gases other than those supplied from the nozzles 249a to 249c and 249e, which will be described later, are not supplied to the substrate 10.

[0075] The reaction vessel 203 is connected to the glove box 220 via a cylindrical metal flange 219 made of stainless steel or the like. The glove box 220 also has an airtight structure to prevent atmospheric air from entering the interior. The exchange chamber 202 provided inside the glove box 220 is continuously purged with high-purity nitrogen (hereinafter simply referred to as N2 gas) to maintain low oxygen and moisture concentrations. The glove box 220 includes a transparent acrylic wall, multiple rubber gloves connected to holes penetrating the wall, and a pass box for transferring materials between the inside and outside of the glove box 220. The pass box is equipped with a vacuum mechanism and an N2 purge mechanism, and is configured to replace the atmosphere inside with N2 gas, thereby allowing materials to be transferred between the inside and outside of the glove box 220 without drawing oxygen-containing atmosphere into the glove box 220. 3, when the crystal substrate is put into or taken out of the reaction vessel 203, the opening of the metal flange 219, i.e., the furnace port 221, is opened. This prevents the surfaces of the components inside the reaction vessel 203 that have been cleaned and modified by the high-temperature bake step described below from being contaminated again, and prevents the surfaces of these components from being exposed to air or gases containing the various impurities described above.

[0076] One end of the reaction vessel 203 is connected to a gas supply pipe 232a that supplies hydrogen chloride (HCl) gas into a gas generator 233a (described later), a gas supply pipe 232b that supplies ammonia (NH) gas into the reaction chamber 201, a gas supply pipe 232c that supplies HCl gas for high-temperature baking and normal baking into the reaction chamber 201, and a gas supply pipe 232d that supplies nitrogen (N) gas into the reaction chamber 201. The gas supply pipes 232a-232c are configured to supply hydrogen (H) gas and N gas as carrier gases in addition to HCl gas and NH. The gas supply pipes 232a-232c and 232e are each equipped with a flow rate controller and a valve (neither of which is shown) for each type of gas, allowing flow rate control and supply start / stop of each gas to be performed individually for each type of gas. The gas supply pipe 232d is also equipped with a flow rate controller and a valve (neither of which is shown). The N2 gas supplied from the gas supply pipe 232d is used to purge the upstream side of the heat insulating wall 211 and the surrounding area in the reaction chamber 201, thereby maintaining the cleanliness of the atmosphere in these areas.

[0077] The HCl gas supplied from the gas supply pipe 232c and the H2 gas supplied from the gas supply pipes 232a-232c act as cleaning gases that clean the surfaces of components inside the reaction chamber 201 (particularly the inside of the heat insulating wall 211) and as modifying gases that modify these surfaces to have a low probability of releasing impurities in the high-temperature bake step and normal bake step described below. The N2 gas supplied from the gas supply pipes 232a-232c acts to appropriately adjust the blowing flow rate of the HCl gas and H2 gas ejected from the tips of the nozzles 249a-249c so that desired locations inside the reaction chamber 201 (particularly the inside of the heat insulating wall 211) are properly cleaned in each bake step.

[0078] The HCl gas introduced from gas supply pipe 232a acts as a reactive gas that reacts with the Ga source material to produce GaCl gas, a Ga halide, i.e., Ga source gas, in the crystal growth process described below. Furthermore, the NH gas supplied from gas supply pipe 232b acts as a nitriding agent, i.e., N source gas, that reacts with GaCl gas to grow GaN, a Ga nitride, on substrate 10 in the crystal growth process described below. Hereinafter, GaCl gas and NH gas may be collectively referred to as source gases. Furthermore, the H gas and N gas supplied from gas supply pipes 232a-232c act to appropriately adjust the flow rate of the source gases ejected from the tips of nozzles 249a-249c in the crystal growth process described below, thereby directing the source gases toward substrate 10.

[0079] As described above, the gas generator 233a that accommodates the Ga melt as a Ga raw material is provided downstream of the gas supply pipe 232a. The gas generator 233a is provided with a nozzle 249a that supplies GaCl gas, generated by a reaction between HCl gas and the Ga melt, toward the main surface of the substrate 10 held on the susceptor 208. The gas supply pipes 232b and 232c are provided downstream with nozzles 249b and 249c that supply various gases supplied from these gas supply pipes toward the main surface of the substrate 10 held on the susceptor 208. The nozzles 249a to 249c are each configured to penetrate the upstream side of the heat insulating wall 211.

[0080] The gas supply pipe 232c is configured to be able to supply HCl gas, H2 gas, N2 gas, and also Si-containing gas such as silane (SiH4) gas or dichlorosilane (SiH2Cl2) as a dopant gas.

[0081] Furthermore, in this embodiment, a gas supply pipe 232e is connected to one end of the reaction vessel 203, which supplies a halogen-containing gas into a gas generator 233e (described later). The halogen-containing gas is a gas capable of etching MgF2 (described later), and examples thereof include HCl gas, HF gas, and CH3F. The gas supply pipe 232e is configured to be able to supply H2 gas and N2 gas as carrier gases in addition to the halogen-containing gas. The gas supply pipe 232e is provided with a flow rate controller and a valve (neither of which is shown) for each type of gas, and is configured to be able to individually control the flow rate and start / stop supply of each gas for each type of gas.

[0082] A gas generator 233e containing MgF2 as an Mg dopant is provided downstream of the gas supply pipe 232e. The halogen-containing gas introduced from the gas supply pipe 232e into the gas generator 233e acts to transport and etch MgF2 in the p-type layer growth step S30 described below. On the other hand, even if the gas generator 233e is heated, if no halogen-containing gas is supplied, almost no Mg-containing gas is generated.

[0083] The gas generator 233e is provided with a nozzle 249e that supplies the Mg-containing gas, which is transported while etching MgF2 with the halogen-containing gas, toward the main surface of the substrate 10 held on the susceptor 208. The nozzle 249e is configured to penetrate the upstream side of the heat insulating wall 211.

[0084] The H2 gas supplied from the gas supply pipe 232e acts to appropriately adjust the blowing flow rate of the source gas ejected from the tip of the nozzle 249e in the p-type layer growth step S30 described below, and to direct the source gas toward the substrate 10. Note that the H2 gas supplied from the gas supply pipe 232e can also act as a cleaning gas and a modifying gas in the high-temperature bake step and normal bake step described below, similar to the H2 gas supplied from the gas supply pipes 232a to 232c described above.

[0085] An exhaust pipe 230 for exhausting the inside of the reaction chamber 201 is provided on a metal flange 219 provided on the other end of the reaction vessel 203. An APC valve 244 as a pressure regulator and a pump 231 are provided in this order from the upstream side on the exhaust pipe 230. Note that instead of the APC valve 244 and the pump 231, a blower including a pressure adjustment mechanism can also be used.

[0086] A zone heater 207 that heats the inside of the reaction chamber 201 to a desired temperature is provided on the outer periphery of the reaction vessel 203. The zone heater 207 is composed of at least two heaters: an upstream portion including the gas generators 233a and 233e, and a downstream portion including the susceptor 208. Each heater has a temperature sensor and a temperature regulator (neither of which are shown) so that the temperature can be individually adjusted in the range from room temperature to 1200°C.

[0087] Furthermore, as described above, the susceptor 208 that holds the substrate 10 is equipped with an internal heater 210, a temperature sensor 209, and a temperature regulator (not shown), separate from the zone heater 207, so as to be able to adjust the temperature at least in the range of room temperature to 1600°C. Furthermore, as described above, the upstream side and periphery of the susceptor 208 are surrounded by a heat insulating wall 211. At least the surface (inner peripheral surface) of the heat insulating wall 211 facing the susceptor 208 must be made of a limited material that does not generate impurities, as described below. However, for the other surfaces (outer peripheral surfaces), there are no limitations on the materials used, as long as they can withstand temperatures of 1600°C or higher. The heat insulating wall 211, excluding at least the inner peripheral surface, can be made of, for example, a highly heat-resistant non-metallic material such as carbon or silicon carbide (SiC), or a highly heat-resistant metallic material such as Mo or W, and can also have a structure in which plate-shaped reflectors are stacked. By using such a configuration, even when the temperature of the susceptor 208 is set to 1600°C, the temperature outside the heat insulating wall 211 can be kept at 1200°C or less. Since this temperature is below the softening point of quartz, in this configuration, quartz can be used for each of the members constituting the reaction vessel 203, the gas generator 233a, the gas generator 233e, and the upstream portions of the gas supply pipes 232a to 232e.

[0088] Here, the reaction chamber 201 is heated to the crystal growth temperature (900° C. or higher) of the group III nitride in the crystal growth step described below, and has a high-temperature reaction region 201a with which the gas supplied to the substrate 10 comes into contact.

[0089] In this embodiment, at least the surface of the member that constitutes the high temperature reaction region 201a is made of, for example, a material that does not contain quartz (SiO2) and does not contain B, and has heat resistance of at least 1600°C or more.

[0090] Specifically, the inner wall of the heat shield wall 211 upstream of the susceptor 208, the portions of the nozzles 249a-249c, 249e penetrating into the heat shield wall 211, the portions of the outer portion of the heat shield wall 211 that are heated to 900°C or higher during the crystal growth process, and the surface of the susceptor 208 are made of heat-resistant materials such as alumina (Al2O3), SiC, graphite, and pyrolytic graphite. Although not included in the high-temperature reaction region 201a, the portion around the internal heater 210 is also required to be heat-resistant to at least 1600°C or higher. The reason why such high heat resistance is required for the components constituting the high-temperature reaction region 201a, etc., is that a high-temperature bake step is performed before the crystal growth process, as will be described later.

[0091] Each component of the HVPE apparatus 200, such as various valves and flow rate controllers provided in the gas supply pipes 232a to 232e, the pump 231, the APC valve 244, the zone heater 207, the internal heater 210, the temperature sensor 209, etc., is connected to a controller 280 configured as a computer.

[0092] Next, an example of processing using the above-mentioned HVPE apparatus 200 will be described in detail with reference to Fig. 2. In the following description, the operation of each component constituting the HVPE apparatus 200 is controlled by a controller 280.

[0093] (S14: High temperature bake step) This step is performed when the reaction chamber 201 or the exchange chamber 202 is exposed to the atmosphere due to maintenance of the HVPE apparatus 200, the introduction of Ga source material into the gas generator 233a, the introduction of MgF2 into the gas generator 233e, or the like. Before performing this step, it is confirmed that the reaction chamber 201 and the exchange chamber 202 are airtight. After confirming that they are airtight, the reaction chamber 201 and the exchange chamber 202 are purged with N2 gas to create a low-oxygen and low-moisture state. Then, with the reaction vessel 203 in a predetermined atmosphere, the surfaces of the various components constituting the reaction chamber 201 are heat-treated. This treatment is performed before the substrate 10 is loaded into the reaction vessel 203, and after the introduction of Ga source material into the gas generator 233a and the introduction of MgF2 into the gas generator 233e.

[0094] In this step, the temperature of the zone heater 207 is adjusted to a temperature similar to that in the crystal growth process. Specifically, the temperature of the upstream heater including the gas generators 233a and 233e is set to a temperature of 700 to 900°C, and the temperature of the downstream heater including the susceptor 208 is set to a temperature of 1000 to 1200°C. Furthermore, the temperature of the internal heater 210 is set to a predetermined temperature of 1500°C or higher. As will be described later, in the crystal growth process, the internal heater 210 is either off or set to a temperature of 1200°C or lower, so the temperature of the high-temperature reaction region 201a is 900°C or higher but lower than 1200°C. On the other hand, during the high-temperature bake step, by setting the temperature of the internal heater 210 to 1500°C or higher, the temperature of the high-temperature reaction region 201a reaches 1000-1500°C or higher, resulting in a high temperature of 1500°C or higher near the susceptor 208 on which the substrate 10 is placed, and temperatures at other locations are at least 100°C higher than the temperature during the crystal growth process. The area of the high-temperature reaction region 201a where the temperature reaches the lowest temperature of 900°C during the crystal growth process—specifically, the area inside the thermal barrier 211, upstream of the nozzles 249a-249c, 249e—is the area where adhering impurity gas is least easily removed. By setting the temperature of the internal heater 210 to 1500°C or higher so that the temperature of this area reaches at least 1000°C or higher, the effects of the cleaning and modification processes described below, i.e., the effect of reducing impurities in the GaN crystal being grown, can be fully achieved. If the temperature of the internal heater 210 is set to a temperature below 1500°C, the temperature at any point within the high-temperature reaction region 201a cannot be sufficiently increased, and it becomes difficult to obtain the effects of the cleaning and modification treatment described below, i.e., the effect of reducing impurities in the GaN crystal.

[0095] The upper limit of the temperature of the internal heater 210 in this step depends on the capacity of the thermal barrier 211. That is, as long as the temperature of the quartz parts and the like outside the thermal barrier 211 can be kept within a range that does not exceed their heat resistance temperature, the higher the temperature of the internal heater 210, the more likely it is that the cleaning and modification treatment effects described below will be achieved. If the temperature of the quartz parts and the like outside the thermal barrier 211 exceeds their heat resistance temperature, the frequency and cost of maintenance of the HVPE apparatus 200 may increase.

[0096] In this step, after the temperatures of the zone heater 207 and the internal heater 210 reach the predetermined temperatures, H gas is supplied from each of the gas supply pipes 232a, 232b, and 232e at a flow rate of, for example, about 3 slm. Note that HCl gas is not supplied from the gas supply pipe 232a, and no halogen-containing gas is supplied from the gas supply pipe 232e. HCl gas is supplied from the gas supply pipe 232c at a flow rate of, for example, about 2 slm, and H gas is supplied at a flow rate of, for example, about 1 slm. N gas is supplied from the gas supply pipe 232d at a flow rate of, for example, about 10 slm. This state is maintained for a predetermined time to bake the reaction chamber 201. By starting the supply of H gas and HCl gas at the above-described timing, i.e., after the temperature inside the reaction chamber 201 has been raised, the amount of gas that flows uselessly without contributing to the cleaning and modification processes described below can be reduced, thereby reducing the processing costs for crystal growth.

[0097] This step is performed with the pump 231 operating, and the pressure inside the reaction vessel 203 is maintained at, for example, 0.5 atmospheres or more and 2 atmospheres or less by adjusting the opening of the APC valve 244. By performing this step while the reaction vessel 203 is being evacuated, it becomes possible to efficiently remove impurities from inside the reaction vessel 203, i.e., to efficiently clean the inside of the reaction vessel 203. If the pressure inside the reaction vessel 203 is less than 0.5 atmospheres, it becomes difficult to obtain the effects of the cleaning and modification processes described below. If the pressure inside the reaction vessel 203 exceeds 2 atmospheres, etching damage to components inside the reaction chamber 201 becomes excessive.

[0098] In this step, the partial pressure ratio of HCl gas to H2 gas (HCl partial pressure / H2 partial pressure) in the reaction vessel 203 is set to, for example, 1 / 50 to 1 / 2. If the partial pressure ratio is less than 1 / 50, it becomes difficult to obtain the effects of the cleaning and modification processes described below. If the partial pressure ratio is greater than 1 / 2, etching damage to components in the reaction chamber 201 becomes excessive. This partial pressure control can be performed by adjusting the flow rates of flow rate controllers provided in the gas supply pipes 232a to 232e.

[0099] By performing this step for, for example, 30 to 300 minutes, the surfaces of various components constituting at least the high-temperature reaction region 201a of the reaction chamber 201 can be cleaned and foreign matter adhering to these surfaces can be removed. Furthermore, by maintaining the surfaces of these components at a temperature at least 100°C higher than the temperature in the crystal growth process described below, the release of impurity gases from these surfaces can be promoted, and the surfaces can be modified to be less susceptible to the release of impurities such as Si, B, Fe, O, and C under the temperature and pressure conditions in the crystal growth process. Note that if this step is performed for less than 30 minutes, the effects of the cleaning and modification process described herein may be insufficient. Furthermore, if this step is performed for more than 300 minutes, excessive damage to the components constituting the high-temperature reaction region 201a can occur.

[0100] When H2 gas and HCl gas are supplied into the reaction vessel 203, NH3 gas is not supplied into the reaction vessel 203. If NH3 gas is supplied into the reaction vessel 203 in this step, it becomes difficult to obtain the effects of the above-mentioned cleaning and reforming treatments, especially the effect of the reforming treatment.

[0101] Furthermore, when H2 gas and HCl gas are supplied into the reaction vessel 203, a halogen-based gas such as chlorine (Cl2) gas may be supplied instead of HCl gas. In this case, the effects of the above-described cleaning and modification processes can be similarly obtained.

[0102] Furthermore, when H2 gas and HCl gas are supplied into the reaction vessel 203, N2 gas may be added as a carrier gas from the gas supply pipes 232a to 232c. By adjusting the flow rate of the gas blown out from the nozzles 249a to 249c by adding N2 gas, it is possible to prevent the above-mentioned cleaning and modification processes from being incomplete in some areas. Note that a rare gas such as Ar gas or He gas may be supplied instead of N2 gas.

[0103] Once the above-described cleaning and modification processes are complete, the output of the zone heater 207 is reduced to lower the temperature inside the reaction vessel 203 to, for example, 200°C or below, that is, to a temperature at which the substrate 10 can be loaded into the reaction vessel 203. The supply of H2 gas and HCl gas into the reaction vessel 203 is stopped, and the reaction vessel 203 is purged with N2 gas. Once purging of the reaction vessel 203 is complete, the supply of N2 gas into the reaction vessel 203 is maintained, and the aperture of the APC valve 244 is adjusted so that the pressure inside the reaction vessel 203 becomes atmospheric pressure or slightly higher than atmospheric pressure.

[0104] (S16: Normal bake step) The high-temperature bake step S14 is performed when the reaction chamber 201 or the exchange chamber 202 is exposed to the atmosphere. However, during the crystal growth process, the reaction chamber 201 or the exchange chamber 202 is not usually exposed to the atmosphere, including before and after the process, so the high-temperature bake step S14 is unnecessary. However, the crystal growth process causes GaN polycrystals to adhere to the surfaces of the nozzles 249a-249c and 249e, the surface of the susceptor 208, the inner wall of the heat shield wall 211, and the like. If the subsequent crystal growth process is performed while GaN polycrystals remain, GaN polycrystal powder and Ga droplets that have separated from the polycrystals and scattered will adhere to the substrate 10, hindering good crystal growth. For this reason, a normal bake step S16 is performed after the crystal growth process to remove the GaN polycrystals. The procedure and conditions of the normal bake step can be the same as those of the high-temperature bake step S14, except that the internal heater 210 is turned off and the temperature around the susceptor 208 is set to 1000 to 1200° C. By performing the normal bake step S16, the GaN polycrystal can be removed from inside the reaction chamber 201.

[0105] (S18: Substrate placement step) After the high-temperature bake step S14 or the normal bake step S16 is performed, once the temperature inside the reaction vessel 203 has been lowered and purging has been completed, a substrate placement step S18 is performed in which the substrate 10 is placed inside the reaction vessel 203.

[0106] As shown in FIG. 3, the furnace port 221 of the reaction vessel 203 is opened, and the substrate 10 is placed on the susceptor 208. The furnace port 221 is isolated from the atmosphere and connected to the glove box 220, which is continuously purged with N2 gas. As described above, the glove box 220 includes a transparent acrylic wall, multiple rubber gloves connected to holes penetrating the wall, and a pass box for transferring materials between the inside and outside of the glove box 220. By replacing the atmosphere inside the pass box with N2 gas, materials can be transferred between the inside and outside of the glove box 220 without drawing air into the glove box 220. Using this mechanism to place the substrate 10 can prevent recontamination of components in the reaction vessel 203 that have been cleaned and modified by the high-temperature bake step S14, as well as reattachment of impurity gases to these components. The surface of the substrate 10 placed on the susceptor 208, i.e., the main surface (crystal growth surface, base surface) facing the nozzles 249a to 249c, is set to be, for example, the (0001) plane of a GaN crystal, i.e., the +c plane (Ga polarity plane).

[0107] [S20: Base layer growth process] After the substrate 10 has been placed in the reaction chamber 201, the HVPE apparatus 200 is used to perform the following base layer growth step S20.

[0108] After the substrate 10 is loaded into the reaction chamber 201, the furnace port 221 is closed, and while the reaction chamber 201 is heated and evacuated, the supply of H gas or H gas and N gas into the reaction chamber 201 is initiated. Then, once the reaction chamber 201 reaches the desired processing temperature and processing pressure and the atmosphere within the reaction chamber 201 is adjusted to the desired level, the supply of HCl gas and NH gas from the gas supply pipes 232a and 232b is initiated, and GaCl gas and NH gas are respectively supplied to the surface of the substrate 10. At this time, SiH2Cl2 is supplied to the surface of the substrate 10 from the gas supply pipe 232c. Note that no halogen-containing gas is supplied from the gas supply pipe 232e to prevent the generation of Mg-containing gas. In this manner, the underlayer 20 made of n-type GaN single crystal can be grown on the substrate 10.

[0109] In this step, in order to prevent thermal decomposition of the GaN crystal constituting the substrate 10, it is preferable to start supplying NH3 gas into the reaction chamber 201 when the temperature of the substrate 10 reaches 500°C or before that. In order to improve the in-plane film thickness uniformity of the underlayer 20 and the p-type layer 30, it is preferable to perform the crystal growth process, including the p-type layer growth process S30 described below, while the susceptor 208 is rotating.

[0110] In this step, it is preferable that the temperature of the zone heater 207 is set to, for example, 700 to 900°C for the upstream heater including the gas generator 233a, and set to, for example, 1000 to 1200°C for the downstream heater including the susceptor 208. This adjusts the temperature of the susceptor 208 to a predetermined crystal growth temperature of 1000 to 1200°C. In this step, the internal heater 210 may be used in an off state, but temperature control using the internal heater 210 may be performed as long as the temperature of the susceptor 208 is in the above-mentioned range of 1000 to 1200°C.

[0111] Other processing conditions for this step include the following: Processing pressure: 0.5 to 2 atmospheres GaCl gas partial pressure: 0.1 to 20 kPa Partial pressure of NH3 gas / partial pressure of GaCl gas: 1 to 100 Partial pressure of H2 gas / partial pressure of GaCl gas: 0 to 100 Partial pressure of SiH2Cl2 gas: 0.1 to 10 Pa

[0112] When the growth of the underlayer 20 is completed, the supply of SiH2Cl2 from the gas supply pipe 232c is stopped.

[0113] [S30: p-type layer growth process] After the base layer growing step S20 is completed, the HVPE apparatus 200 is continued to be used to grow the p-type layer 30 made of single crystal GaN containing Mg on the base layer 20.

[0114] Specifically, the supply of HCl gas and NH 3 gas from the gas supply pipes 232a and 232b continues, and GaCl gas and NH 3 gas are supplied to the surface of the substrate 10, respectively.

[0115] At this time, in this embodiment, HCl gas as a halogen-containing gas is supplied from the gas supply pipe 232e, and MgF2 in the gas generator 233e is transported while being etched, thereby doping Mg into the p-type layer 30.

[0116] At this time, the partial pressure of the HCl gas as the halogen-containing gas from the gas supply pipe 232e is set to, for example, 1 Pa or more and 1 kPa or less. In the p-type layer growth step S30, the conditions other than the partial pressure of the halogen-containing gas from the gas supply pipe 232e are the same as those in the base layer growth step S20.

[0117] In this way, by growing the p-type layer 30 using the above-described HVPE apparatus 200, it is possible to incorporate a predetermined amount of Mg and a trace amount of F into the p-type layer 30 while suppressing the incorporation of impurities other than Mg and F into the p-type layer 30. Furthermore, by using MgF2 as a dopant, it is possible to selectively dope only the p-type layer 30 with Mg.

[0118] The above-described steps from the base layer growth step S20 to the p-type layer growth step S30 are performed consecutively in the same HVPE apparatus 200 without exposing the substrate 10 to the atmosphere. This makes it possible to prevent the formation of an unintended high concentration region of Si or O, etc. (a region having a relatively higher Si concentration or O concentration than the base layer 20 and the p-type layer 30) at the interface between the base layer 20 and the p-type layer 30, which is derived from impurities in the atmosphere.

[0119] [S40: Unloading process] After growing the base layer 20 and the p-type layer 30 in this order on the substrate 10, NH3 gas and N2 gas are supplied into the reaction chamber 201. While the reaction chamber 201 is evacuated, the supply of HCl gas and H2 gas into the reaction chamber 201 and the heating by the zone heater 207 are stopped. When the temperature inside the reaction chamber 201 drops to 500°C or below, the supply of NH3 gas is stopped, and the atmosphere inside the reaction chamber 201 is replaced with N2 gas and returned to atmospheric pressure. The temperature inside the reaction chamber 201 is then lowered to, for example, 200°C or below, i.e., to a temperature at which the semiconductor laminate 1 can be removed from the reaction vessel 203. The semiconductor laminate 1 is then removed from the reaction chamber 201 via the glove box 220 and the pass box.

[0120] In this manner, the semiconductor laminate 1 of this embodiment is manufactured.

[0121] When manufacturing multiple (n) semiconductor laminates 1, it is preferable to perform the steps in the following order, for example: exposing the reaction chamber 201 and the exchange chamber 202 to the atmosphere → high-temperature bake step S14 → crystal growth process → carry-out process S40 → (normal bake step S16 → crystal growth process → carry-out process S40) × (n-1).

[0122] (3) Effects Obtained by the Present Embodiment According to this embodiment, one or more of the following effects can be obtained.

[0123] (a) In this embodiment, the p-type layer 30 is grown in the high-temperature reaction region 201a that has been cleaned and modified by the above-described manufacturing method while suppressing the release of impurities such as C, Si, and O from the high-temperature reaction region 201a, thereby suppressing the unintended incorporation of these impurities into the p-type layer 30. This suppresses crystal distortion in the p-type layer 30. Furthermore, suppressing the incorporation of compensating impurities such as C, Si, or O into the p-type layer 30 makes it possible to achieve a particularly low hole concentration in the p-type layer 30.

[0124] (b) In this embodiment, in the p-type layer growth step S30, MgF2 is used as a dopant by the HVPE method, and the MgF2 is transported while being etched by a halogen-containing gas, thereby doping Mg into the p-type layer 30.

[0125] By using the HVPE method without using organic source gases, it is possible to suppress the incorporation of C into the p-type layer 30. This suppresses carrier compensation due to the C impurity. As a result, it is possible to achieve a high Mg activation rate at a low Mg concentration that could not be achieved by the MOCVD method. In other words, it is possible to stably control a low hole concentration.

[0126] Furthermore, by using O-free MgF as the Mg dopant, it is possible to suppress the incorporation of O as a compensating donor into the p-type layer 30. This has a synergistic effect with the effect of suppressing the compensating donor caused by the device. That is, even when the HVPE method is used, a low hole concentration can be stably achieved in the p-type layer 30.

[0127] Furthermore, by using MgF2 as a dopant, it is possible to dope the p-type layer 30 with Mg while incorporating a trace amount of F derived from the dopant into the p-type layer 30. This improves the activation rate of Mg in the p-type layer 30. Although the detailed mechanism of this effect is not known, it is believed that the inclusion of F in the p-type layer 30 can alleviate the crystal distortion of the p-type layer 30. This makes it possible to achieve a high activation rate of Mg at a high Mg concentration that could not be achieved by conventional manufacturing methods. As a result, it is possible to obtain a p-type layer 30 with a high hole concentration.

[0128] In this way, by incorporating a predetermined amount of Mg and a small amount of F into the p-type layer 30 while suppressing the incorporation of compensating donors into the p-type layer 30, it is possible to obtain a wide range of hole concentration in the p-type layer 30. In other words, it is possible to obtain a high-quality semiconductor laminate 1 including the p-type layer 30.

[0129] (c) In this embodiment, MgF2 is used as the dopant, and Mg doping is controlled by supplying a halogen-containing gas that has an etching effect on MgF2. This Mg doping control allows Mg to be selectively doped only into the p-type layer 30 while suppressing the incorporation of Mg into the underlayer 20, which serves as a non-p-type layer. This allows the Mg concentration to change sharply near the interface between the underlayer 20 and the p-type layer 30. Specifically, the ratio B / A of the Mg concentrations on both sides near the interface between the underlayer 20 and the p-type layer 30 can be set to 100 or greater.

[0130] In this way, by changing the Mg concentration sharply, the depletion layer width in the pn junction diode can be narrowed, which reduces the recombination probability during current diffusion in the on-state. As a result, it becomes possible to reduce the loss in the pn junction diode.

[0131] Furthermore, it is possible to achieve a Mg doping profile as designed, which allows for greater freedom in device design.

[0132] <Second embodiment of the present invention> Next, a second embodiment of the present invention will be described. In the first embodiment described above, the semiconductor laminate 1 has an underlayer 20 and a p-type layer 30 in this order on a substrate 10. However, the configuration of the semiconductor laminate 1 may be changed as in the following embodiment.

[0133] Hereinafter, only elements different from the above-described embodiment will be described, and elements that are substantially the same as the elements described in the above-described embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0134] (1) Semiconductor laminate The semiconductor laminate 1 according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a schematic cross-sectional view showing the semiconductor laminate according to this embodiment.

[0135] 4, the semiconductor laminate 1 of this embodiment is configured as a laminate for manufacturing, for example, a vertical field effect transistor (FET) having a trench gate structure (npn structure). Specifically, the semiconductor laminate 1 includes, for example, a substrate 10, an underlayer 20, a p-type layer 30, and an upper layer 40.

[0136] [Upper layer] The upper layer 40 is preferably provided on the p-type layer 30, has a group III nitride semiconductor, and is made of a single crystal of the group III nitride semiconductor. The upper layer 40 of this embodiment is preferably made of a single crystal of GaN epitaxially grown by the same manufacturing method as the base layer 20 described above.

[0137] The conductivity type of the upper layer 40 is, for example, n-type, and the Si concentration in the upper layer 40 is, for example, the same as the Si concentration in the underlying layer 20.

[0138] In this embodiment, the concentration of each impurity other than the n-type impurity in the upper layer 40 is below the measurement limit (lower detection limit) of SIMS, similar to the underlying layer 20, by the above-described manufacturing method.

[0139] Specifically, the C concentration and the O concentration in the underlayer 20 measured by the SIMS depth profile analysis were 5×10 15 cm -3 The Fe concentration and B concentration in the underlayer 20 measured by SIMS depth profile analysis were each less than 1×10 15 cm -3 Furthermore, the concentrations of As, Cl, P, Na, Li, K, Sn, Ti, Mn, Cr, Mo, W, and Ni in the upper layer 40 are also equivalent to those in the underlayer 20.

[0140] Furthermore, in this embodiment, the supply of Mg-containing gas is appropriately stopped from the p-type layer growth step S30 to the upper layer growth step, so that the Mg concentration changes sharply near the interface between the p-type layer 30 and the upper layer 40.

[0141] Specifically, the ratio D / E of the Mg concentrations between the p-type layer 30 and the upper layer 40 near the interface is 100 or more.

[0142] where D is the Mg concentration at a position 100 nm from the interface between the p-type layer 30 and the upper layer 40 toward the p-type layer 30 in the thickness direction, and E is the Mg concentration at a position 100 nm from the interface between the p-type layer 30 and the upper layer 40 toward the upper layer 40 in the thickness direction. The definition of the interface is the same as that described above, except that the underlayer 20 is replaced with the upper layer 40.

[0143] The thickness of the upper layer 40 is not limited, but is, for example, 10 nm or more and 1 μm or less.

[0144] In the method for manufacturing the semiconductor laminate 1 of this embodiment, for example, after the p-type layer growth step S30, the upper layer growth step may be performed in the same manner as the base layer growth step S20.

[0145] (2) Effects of this embodiment In this embodiment, the above-described Mg doping control can suppress the incorporation of Mg into the upper layer 40 serving as a non-p-type layer. This allows the ratio D / E of the Mg concentrations near the interface between the p-type layer 30 and the upper layer 40 to be 100 or more, i.e., the Mg concentration can be changed sharply. As a result, the gate region in the trench gate structure can be clearly defined, and the gate length can be made equal to the thickness of the p-type layer 30.

[0146] <Other Embodiments of the Present Invention> Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit and scope of the present invention.

[0147] In the above embodiment, the substrate 10 is a freestanding GaN substrate, but the substrate 10 may be made of other materials. Specifically, the substrate 10 may be made of silicon carbide (SiC), Si, Si, or sapphire (Al2O3).

[0148] In the above embodiment, the semiconductor layers of the underlayer 20, p-type layer 30, and upper layer 40 are each made of a single crystal of GaN, but the present invention is not limited to this. Each semiconductor layer is not limited to a single crystal of GaN, and may be made of a group III nitride crystal such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN), i.e., In x Al y Ga 1-x-y It may be made of a single crystal represented by the composition formula N (where 0≦x≦1, 0≦y≦1, 0≦x+y≦1).

[0149] In the above embodiment, the semiconductor laminate 1 has the base layer 20, the p-type layer 30, and the upper layer 40 in this order on the substrate 10, but the present invention is not limited to this. For example, the semiconductor laminate 1 may not have the base layer 20, but may have the p-type layer 30 and the upper layer 40 in this order on the substrate 10.

[0150] In the above-described embodiments, a vertical pn junction diode or a vertical trench gate structure FET is described as a semiconductor device manufactured using the semiconductor laminate 1, but the semiconductor laminate 1 may be used to manufacture other semiconductor devices. For example, the semiconductor laminate 1 may be configured to manufacture a lateral device. For example, the semiconductor laminate 1 may be manufactured for manufacturing a lateral power device by growing the underlayer 20 and the p-type layer 30 and then ion-implanting n-type impurities such as Si into the p-type layer 30. [Example]

[0151] The following describes experimental results that support the effects of the above-described embodiment.

[0152] (1) Semiconductor laminates The semiconductor laminates of Sample A and Samples B1 to B3 were fabricated as follows.

[0153] [Common conditions] The following conditions are the same for Sample A and Samples B1 to B3.

[0154] Substrate: GaN freestanding substrate Orientation of the main surface of the substrate: +c plane Board diameter: 2 inches (50.8 mm) Substrate thickness: 500 μm

[0155] [Sample A: HVPE method of the present disclosure] For Sample A, the HVPE apparatus used was one in which at least the surfaces of the components constituting the high-temperature reaction zone were made of SiC. After the Ga source material and MgF2 were introduced, a high-temperature bake step was carried out before the crystal growth process. The pressure conditions were 1 atmosphere, and the temperature of the high-temperature reaction zone was 1500°C. After the high-temperature bake step, the substrate was placed in the reaction chamber via a glove box.

[0156] Next, in the underlayer growth step, an underlayer made of GaN was grown on the substrate. In this sample A, the underlayer was undoped. The temperatures of the downstream zone heater and susceptor were set to 1050°C, and the thickness of the underlayer was set to 5 μm.

[0157] After the underlayer growth process, the p-type layer growth process was carried out without opening the reaction chamber to the atmosphere. MgF2 was etched using HCl gas while being transported, and Mg was doped into the p-type layer made of GaN. During this process, the temperatures of the downstream zone heater and susceptor were maintained at the same levels as in the underlayer growth process, and the thickness of the p-type layer was set to 3 μm.

[0158] In sample A, a plurality of semiconductor laminates with different Mg concentrations were manufactured by changing the partial pressure of the HCl gas supplied to the MgF2 line.

[0159] [Sample B1: HVPE method using Mg3N2] For sample B1, a semiconductor device was manufactured in the same manner as sample A, except that Mg3N2 was used as the Mg dopant in the p-type layer growth process. H2 gas was supplied as a carrier gas for Mg3N2.

[0160] [Sample B2: Conventional HVPE method] For sample B2, a conventional HVPE reactor with a high-temperature reaction region made of quartz was used, and no high-temperature bake step was performed. Metallic Mg was used as the Mg dopant in the p-type layer growth process. Other conditions for sample B2 were the same as for sample B1.

[0161] [Sample B3: MOCVD method] For Sample B3, a semiconductor laminate was manufactured by MOCVD. Cp2Mg gas was supplied as the Mg dopant gas in the p-type layer growth process. The layer structure of the semiconductor laminate for Sample B3 was the same as for Sample B1. Other conditions for Sample B3 were set to standard conditions for conventional MOCVD.

[0162] In addition, for samples B1 to B3, a plurality of semiconductor laminates with different Mg concentrations were also manufactured.

[0163] (2) Evaluation The semiconductor laminates of Sample A and Samples B1 to B3 were evaluated as follows.

[0164] [SIMS] The concentrations of Mg, C, O, Si, B, Fe, and the like in the p-type layer of each of Sample A and Samples B1 to B3 were measured by SIMS depth profile analysis.

[0165] [Hole concentration] The hole concentration in the p-type layer of the semiconductor laminate was measured at a temperature of 23° C. by Hall effect measurement.

[0166] (3) Results The evaluation results will be explained with reference to Table 1 and Figures 5 to 7. The impurity concentrations in Table 1 indicate the concentrations in the p-type layer. Note that the "(lower limit)" in Table 1 indicates the lower limit of detection in each evaluation, and results below the lower limit of detection are indicated as "DL."

[0167] [Table 1]

[0168] [Sample B3: MOCVD method] As shown in Table 1, in sample B3, the concentrations of impurities other than Mg and C in the p-type layer were low, and the Mg concentration was obtained over a wide range. The F concentration in the p-type layer was below the lower limit of detection.

[0169] As shown in Figures 6 and 7, in sample B3, an activation rate of 1% or more of Mg was obtained over a wide range of Mg concentrations. 17 cm -3 and the range where the Mg concentration is 2×10 18 cm -3 In the above range, the activation rate of Mg was low.

[0170] In MOCVD sample B3, the Mg concentration was relatively easy to control by using Cp2Mg gas as a dopant. However, sample B3 contained C as an impurity, which compensated for the Mg. As a result, the Mg activation rate was low in the low Mg concentration range. Furthermore, sample B3 did not contain F, so the Mg activation rate tended to decrease slightly as the Mg concentration increased.

[0171] [Sample B2: Conventional HVPE method] As shown in Table 1, the concentration of impurities other than Mg was high in Sample B2. As shown in Figures 6 and 7, Sample B2 had a low hole concentration despite a high Mg concentration, and a sufficient Mg activation rate was not obtained.

[0172] In sample B2, which was grown using the conventional HVPE method, the metallic Mg dopant reacted with the quartz that made up the high-temperature reaction region, making it difficult to transport the dopant. Furthermore, high concentrations of Si or O, which act as compensating donors, were mixed in from the quartz that made up the high-temperature reaction region. As a result, the hole concentration was low, and a sufficient Mg activation rate could not be achieved.

[0173] [Sample B1: HVPE method using Mg3N2] As shown in Table 1, in sample B1, the concentrations of impurities other than Mg in the p-type layer were low and the Mg concentration was obtained over a wide range, but the F concentration in the p-type layer was below the lower limit of detection.

[0174] As shown in Figures 6 and 7, Sample B1 had a higher Mg activation rate than Sample B2. However, when the Mg concentration was 2 × 10 18 cm -3 In the above range, the hole concentration decreased, and the activation rate of Mg decreased sharply.

[0175] Furthermore, in sample B1, Mg was also detected in the underlayer, as shown in Figure 5. The Mg concentration changed gradually between the underlayer and the p-type layer.

[0176] In sample B1 grown by the Mg3N2-based HVPE method, the Mg dopant did not contain F, so F was not incorporated into the p-type layer. As a result, a sufficient Mg activation rate was not obtained in the high Mg concentration range.

[0177] In addition, in sample B1, a constant amount of Mg was incorporated into the underlayer because Mg-containing gas was constantly supplied from Mg3N2 placed in the reaction vessel.

[0178] [Sample A] As shown in Table 1, in sample A, the impurity concentrations other than Mg and F in the p-type layer were low, and the Mg concentration was obtained over a wide range. On the other hand, the F concentration in the p-type layer was 1×10 14 cm-3 That was all.

[0179] 6 and 7, Sample A exhibited a higher hole concentration and Mg activation rate than Sample B1 obtained by the MOCVD method over a wide range of Mg concentrations. That is, when the Mg concentration in the p-type layer of Sample A was 1×10 18 cm -3 In addition, when the Mg concentration in the p-type layer of sample A was in the range of 1×10 18 cm -3 Within the above range, the p-type layer satisfied the above-mentioned formula (1) (Y≧−5.5 log X+110) regarding the activation rate.

[0180] Furthermore, as shown in Figure 5, the Mg concentration in sample A changed sharply between the underlayer and the p-type layer. Specifically, the ratio B / A of the Mg concentrations between the underlayer and the p-type layer near the interface was 100 or more.

[0181] In addition, in sample A, no spike-like peak was formed between the underlayer and the p-type layer in the SIMS depth profile, with a Si concentration that was 10 times or more higher than the Si concentration at a position 100 nm from the interface between the underlayer and the p-type layer toward the underlayer in the thickness direction.

[0182] In Sample A according to the present disclosure, it was confirmed that a wide range of hole concentrations could be obtained in the p-type layer by incorporating a predetermined amount of Mg and a trace amount of F into the p-type layer while suppressing the incorporation of compensating impurities into the p-type layer.

[0183] Furthermore, in sample A, it was confirmed that by controlling Mg doping by supplying a halogen-containing gas that has the etching effect of MgF2, it was possible to rapidly change the Mg concentration near the interface between the underlayer and the p-type layer.

[0184] <Preferred embodiment of the present invention> Preferred embodiments of the present invention will be described below.

[0185] (Appendix 1) A substrate; a p-type layer provided above the substrate and having a group III nitride containing Mg; Equipped with The C concentration in the p-type layer is 5×10 15 cm -3 is less than The O concentration in the p-type layer is 5×10 15 cm -3 is less than The Si concentration in the p-type layer is 1×10 15 cm -3 is less than The F concentration in the p-type layer is 1×10 14 cm -3 That's all Semiconductor laminate.

[0186] (Appendix 2) The F concentration in the p-type layer is 1×10 16 cm -3 is 2. The semiconductor laminate of claim 1.

[0187] (Appendix 3) an underlayer having a Group III nitride and provided between the substrate and the p-type layer; The carbon concentration in the underlayer is 5×10 15 cm -3 is less than The O concentration in the underlayer is 5×10 15 cm -3 is less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. 3. The semiconductor laminate according to claim 1 or 2.

[0188] (Appendix 4) A substrate; an underlayer provided on the substrate and including a group III nitride; a p-type layer provided on the underlayer and having a group III nitride containing Mg; Equipped with The C concentration in each of the underlayer and the p-type layer is 5×10 15 cm -3 is less than The O concentration in each of the underlayer and the p-type layer is 5×10 15 cm -3 is less than The Si concentration in the p-type layer is 1×10 15 cm -3 is less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. Semiconductor laminate.

[0189] (Appendix 5) The thickness of the p-type layer is 10 nm or more and 5 μm or less. 5. The semiconductor laminate according to any one of claims 1 to 4.

[0190] (Appendix 6) The B concentration and the Fe concentration in the p-type layer are each 1×10 15 cm -3 is less than 6. The semiconductor laminate according to any one of appendices 1 to 5.

[0191] (Appendix 7) an upper layer provided on the p-type layer and having a Group III nitride; The C concentration in the upper layer is 5×10 15 cm -3 is less than The O concentration in the upper layer is 5×10 15 cm -3 is less than a ratio D / E of Mg concentrations between the upper layer and the p-type layer near the interface is 100 or more; however, D is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction, The E is the Mg concentration at a position 100 nm from the interface toward the upper layer in the thickness direction. 7. The semiconductor laminate according to any one of claims 1 to 6.

[0192] (Appendix 8) The Mg concentration in the p-type layer is 1×10 18 cm -3 is less than The activation rate of Mg, determined by the hole concentration in the p-type layer at 23°C relative to the Mg concentration in the p-type layer, is 11% or more. 8. The semiconductor laminate according to any one of claims 1 to 7.

[0193] (Appendix 9) The Mg concentration in the p-type layer is 1×10 18 cm -3 That's all, The p-type layer satisfies formula (1): Y≧-5.5logX+110 (1) however, X is cm -3 is the Mg concentration in the p-type layer, expressed as Y is the ratio of the hole concentration in the p-type layer at 23°C to the Mg concentration in the p-type layer, and is the activation rate of Mg expressed in %. 8. The semiconductor laminate according to any one of claims 1 to 7.

[0194] (Appendix 10) The hole concentration in the p-type layer at 23°C is 10 15 cm -3 5x10 or more 18 cm -3 is 10. The semiconductor laminate according to any one of claims 1 to 9.

[0195] (Appendix 11) preparing a substrate and a hydride vapor phase growth apparatus containing the substrate; growing a p-type layer having a group III nitride containing Mg above the substrate using the hydride vapor phase epitaxy apparatus; Equipped with In the step of growing the p-type layer, Mg is doped into the p-type layer by transporting MgF2 while etching it with a halogen-containing gas. A method for manufacturing a semiconductor laminate.

[0196] (Appendix 12) The preparing step includes: preparing a reaction vessel for the hydride vapor phase epitaxy apparatus, the reaction vessel having a high-temperature reaction zone that is heated to a crystal growth temperature of a Group III nitride and that comes into contact with a gas supplied to the substrate, the high-temperature reaction zone having at least a surface made of a material that does not contain quartz and does not contain boron; a high-temperature baking step in which the temperature of the high-temperature reaction zone is heated to a temperature of 1500°C or higher, the supply of the nitrogen source gas into the reaction vessel is stopped, and hydrogen gas and a halogen-containing gas are supplied into the reaction vessel, thereby cleaning and modifying the surfaces of the members constituting the high-temperature reaction zone; placing the substrate in the reaction vessel; have 12. A method for producing a semiconductor laminate according to claim 11.

[0197] (Appendix 13) In the step of growing the p-type layer, The C concentration in the p-type layer is 5×10 15 cm -3 Less than The O concentration in the p-type layer is set to 5×10 15 cm -3 Less than The Si concentration in the p-type layer is 1×1015 cm -3 Less than The F concentration in the p-type layer is 1×10 14 cm -3 That's all 13. A method for producing a semiconductor laminate according to claim 11 or 12.

[0198] (Appendix 14) a step of growing an underlayer having a Group III nitride on the substrate after the preparing step and before the growing step of the p-type layer; In the step of growing the underlayer, The carbon concentration in the underlayer is 5×10 15 cm -3 Less than The O concentration in the underlayer is 5×10 15 cm -3 Less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. 14. A method for producing a semiconductor laminate according to any one of claims 11 to 13. [Explanation of symbols]

[0199] 10 Substrate 20 Base layer 30 p-type layer 40 upper layer

Claims

1. A substrate; a p-type layer provided above the substrate and having a group III nitride containing Mg; Equipped with The C concentration in the p-type layer is 5×10 １５ cm －３ is less than The O concentration in the p-type layer is 5×10 １５ cm －３ is less than The Si concentration in the p-type layer is 1×10 １５ cm －３ is less than The F concentration in the p-type layer is 1×10 １４ cm －３ That's all Semiconductor laminate.

2. an underlayer provided between the substrate and the p-type layer and including a Group III nitride; The carbon concentration in the underlayer is 5×10 １５ cm －３ is less than The O concentration in the underlayer is 5×10 １５ cm －３ is less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. The semiconductor laminate according to claim 1 .

3. A substrate; an underlayer provided on the substrate and including a Group III nitride; a p-type layer provided on the underlayer and having a group III nitride containing Mg; Equipped with The C concentration in each of the underlayer and the p-type layer is 5×10 １５ cm －３ is less than The O concentration in each of the underlayer and the p-type layer is 5×10 １５ cm －３ is less than The Si concentration in the p-type layer is 1×10 １５ cm －３ is less than a ratio B / A of Mg concentrations between the underlayer and the p-type layer near the interface is 100 or more; however, A is the Mg concentration at a position 100 nm from the interface toward the underlayer in the thickness direction, The B is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction. Semiconductor laminate.

4. The thickness of the p-type layer is 10 nm or more and 5 μm or less. The semiconductor laminate according to any one of claims 1 to 3.

5. The B concentration and the Fe concentration in the p-type layer are each 1×10 １５ cm －３ is less than The semiconductor laminate according to any one of claims 1 to 4.

6. an upper layer disposed on the p-type layer and having a Group III nitride; The C concentration in the upper layer is 5×10 １５ cm －３ is less than The O concentration in the upper layer is 5×10 １５ cm －３ is less than a ratio D / E of Mg concentrations between the upper layer and the p-type layer near the interface is 100 or more; however, D is the Mg concentration at a position 100 nm from the interface toward the p-type layer in the thickness direction, The E is the Mg concentration at a position 100 nm from the interface toward the upper layer in the thickness direction. The semiconductor laminate according to any one of claims 1 to 5.

7. The Mg concentration in the p-type layer is 1×10 １８ cm －３ is less than The activation rate of Mg, determined by the hole concentration in the p-type layer at 23° C. relative to the Mg concentration in the p-type layer, is 11% or more. The semiconductor laminate according to any one of claims 1 to 6.

8. The Mg concentration in the p-type layer is 1×10 １８ cm －３ That's all, The p-type layer satisfies formula (1): Y≧-5.5logX+110...(1) however, X is cm －３ is the Mg concentration in the p-type layer, expressed as Y is the ratio of the hole concentration in the p-type layer at 23° C. to the Mg concentration in the p-type layer, and is the activation rate of Mg expressed in %. The semiconductor laminate according to any one of claims 1 to 6.

9. preparing a substrate and a hydride vapor phase growth apparatus containing the substrate; growing a p-type layer having a Group III nitride containing Mg above the substrate using the hydride vapor phase epitaxy apparatus; Equipped with In the step of growing the p-type layer, Halogen-containing gas ２ Mg is doped into the p-type layer by transporting the A method for manufacturing a semiconductor laminate.

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