Semiconductor device package with die stackup and connection platform

Abstract

To provide semiconductor device packages configured to reduce the noise in electrical signals transmitted to and from stacked dies and to reduce the risk of electrical shorts.SOLUTION: A semiconductor device package 100 includes a substrate 102, and a stack 104 of semiconductor dies positioned on the substrate and including semiconductor dies 104a-104l. Platforms 106, 108 are positioned on the substrate such that the stack of semiconductor dies is positioned therebetween. Multiple through-vias 112 are electrically connected to the substrate and extend through the respective platforms. Multiple bond wires 116 respectively electrically connects the through-vias and substrate bond pads 118 to the respective semiconductor dies. The through-vias reduce the required length of the bond wires thereby reducing signal noise, and the platforms vertically space the bond wires to prevent electrical short circuits.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 503,381, entitled "Semiconductor Device Package with Die Stackup and Connection Platform," filed May 19, 2023, which is incorporated herein by reference in its entirety. [Background technology]

[0002] The present disclosure relates generally to semiconductor device packages having a stack of dies, and more particularly to semiconductor device packages including a die stackup and a platform for routing electrical signals to the die stackup.

[0003] A semiconductor package may include multiple stacked dies. For example, a semiconductor memory package may include multiple semiconductor memory dies and a controller packaged together on a substrate and encapsulated in a molding compound. The memory dies may be stacked, with each memory die in the stack electrically coupled to the substrate with a respective plurality of bond wires. The die stack may include multiple different sub-stacks arranged on top of each other in a center-stacked manner. The substrate includes communication lines or traces that route electrical signals (e.g., power, ground, input / output (IO) signals) between the bond wires and the controller, and to external connections. Traditionally, continuous bond wires directly connected to the substrate transmit power and ground signals to each memory die included in the die stack. However, as the length of the bond wires increases, so does the undesired disturbance of the electrical signals, commonly referred to as noise, transmitted to and from the memory dies. Additionally, as the length of the bond wires increases, inductance increases, resulting in a voltage drop in the electrical signals. Furthermore, as the pitch between adjacent bond pads on the memory dies decreases, the risk of electrical shorts occurring due to bond wires contacting each other also increases. Therefore, there is a need to provide a semiconductor device package that is configured to reduce noise in electrical signals transmitted to and from stacked dies and to reduce the risk of electrical shorts. Summary of the Invention

[0004] In one embodiment, there is a semiconductor device package including: a substrate; a semiconductor die stack positioned on the substrate and including a first semiconductor die and a second semiconductor die; a first platform positioned on the substrate; a second platform positioned on the substrate opposite the first platform, with the semiconductor die stack positioned between the first platform and the second platform; a first through via electrically connected to the substrate and extending through the first platform; a second through via electrically connected to the substrate and extending through the second platform; a first bond wire electrically connecting the first through via to the first semiconductor die; and a second bond wire electrically connecting the second through via to the second semiconductor die.

[0005] In some embodiments, the first platform includes a first stepped surface, a second stepped surface vertically offset from the first stepped surface, and a first bond pad exposed at the first stepped surface and electrically connected to the first through via, the first through via extending through the first platform from the first bond pad to the substrate. In some embodiments, the first platform includes a second bond pad exposed at the second stepped surface, and a third through via electrically connected to the substrate and the second bond pad, the third through via extending through the first platform from the second bond pad to the substrate. In some embodiments, the semiconductor device package further includes a third semiconductor die included in the stack of semiconductor dies, the third semiconductor die positioned above the first and second semiconductor dies, and a third bond wire electrically connecting the third semiconductor die to the third through via.

[0006] In some embodiments, at least a portion of the third bond wire is positioned vertically above the first bond wire and does not directly contact the first bond wire. In some embodiments, the first and second platforms include a series of sections stacked on top of each other, each section including a conductive layer and a dielectric layer. In some embodiments, the semiconductor device package further includes a bond pad exposed on a surface of the first platform, with the first bond wire electrically connected to the bond pad, and two or more through vias electrically connected to the bond pad and the substrate. In some embodiments, the first platform has an overall height greater than that of the second platform.

[0007] In some embodiments, the first platform and the second platform are constructed from the same material as the substrate. In some embodiments, the stack of semiconductor dies includes a memory die. In some embodiments, the semiconductor device package further includes a substrate bond pad electrically connected to the substrate and positioned between the stack of semiconductor dies and the first platform, and a bond wire electrically connecting the substrate bond pad to a bottom semiconductor die included in the stack of semiconductor dies. In some embodiments, the first bond wire is electrically connected to the first semiconductor die and another semiconductor die adjacent to the first semiconductor die. In some embodiments, the first bond wire is electrically connected to the first semiconductor die and at least two adjacent semiconductor dies.

[0008] In another embodiment, there is a semiconductor device package including: a substrate including a top surface and bond pads exposed on the top surface; a stack of semiconductor dies positioned on the top surface of the substrate; a first platform positioned on the top surface of the substrate, the first platform electrically connected to the substrate and including a plurality of through vias extending through the first platform; a second platform positioned opposite the first platform on the top surface of the substrate such that the stack of semiconductor dies is positioned between the first and second platforms, the second platform electrically connected to the substrate and including a plurality of through vias extending through the second platform; a first bond wire connecting the first semiconductor die of the stack to the at least one through via of the first platform; and a second bond wire connecting a second semiconductor die of the stack to the at least one through via of the second platform.

[0009] In some embodiments, the first platform includes at least two stepped surfaces vertically offset from one another, each of the stepped surfaces including a bond pad electrically connected to one or more of the plurality of through vias of the first platform. In some embodiments, at least one of the bond pads is connected to two or more of the plurality of through vias of the first platform. In some embodiments, the first and second platforms include a series of sections stacked on top of one another, each section including a conductive layer and a dielectric layer. In some embodiments, each through via of the plurality of through vias has a diameter of about 10 microns. In some embodiments, the first platform and the second platform are constructed from the same material as the substrate.

[0010] In another embodiment, there is a semiconductor device package comprising: substrate means for providing electrical interconnections between electrical components coupled to the substrate means; first platform means for providing a first set of raised electrical contacts spaced from the substrate means, the first platform means including first conductive means extending through the first platform means for electrically connecting the first set of raised electrical contacts to the substrate means; second platform means for providing a second set of raised electrical contacts spaced from the substrate means, the second platform means including second conductive means extending through the second platform means for electrically connecting the second set of raised electrical contacts to the substrate means; and a stack of storage means each for storing a quantity of data, the stack of storage means being positioned on the substrate means between the first platform means and the second platform means, the stack including a first storage means electrically connected to the first set of raised electrical contacts and a second storage means electrically connected to the second set of raised electrical contacts. [Brief explanation of the drawings]

[0011] The foregoing summary, as well as the following detailed description, will be better understood when read in conjunction with the accompanying drawings. For purposes of illustrating the present disclosure, presently preferred embodiments are shown in the drawings, in which like reference numerals refer to like elements throughout. It should be noted, however, that aspects of the present disclosure may be embodied in different forms and therefore should not be construed as limited to the illustrated embodiments set forth herein. The elements shown in the accompanying drawings are not necessarily drawn to scale, but rather may be exaggerated to emphasize important features of the subject matter therein. Additionally, the drawings may be simplified by omitting elements not necessary for an understanding of the disclosed embodiments.

[0012] The drawings are as follows: [Figure 1A]1 is a cross-sectional side view of a portion of a semiconductor device package having a die stackup and a platform according to an exemplary embodiment of the present disclosure. [Figure 1B] FIG. 1B is a perspective view of the semiconductor device package of FIG. 1A. [Figure 2] FIG. 10 is a cross-sectional side view of a portion of a semiconductor device package having a die stackup and a platform according to another exemplary embodiment of the present disclosure. [Figure 3] FIG. 10 is a cross-sectional side view of a portion of a semiconductor device package having a die stackup and a platform according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present subject matter will now be described more fully hereinafter with reference to the accompanying figures, in which exemplary embodiments are shown. However, the present subject matter may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to illustrate and enable one of skill in the art.

[0014] Numerous details are described herein to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without any of the specific details, and the claims are limited only by the features and aspects specifically recited in the claims. Additionally, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure relevant aspects of the embodiments described herein.

[0015] 1A-1B , a portion of a semiconductor device package generally designated 100 is shown in accordance with an exemplary embodiment of the present disclosure. Semiconductor device package 100, or package 100 for short, may include a substrate 102, a stack of semiconductor dies 104, a first platform 106, and a second platform 108. Package 100 may be any type of semiconductor device package, such as, but not limited to, a system-in-package (SiP), a storage device (e.g., a Secure Digital (SD) card or a Multimedia Card (MMC)), or the like. In some embodiments, stack of semiconductor dies 104 may be a stack of memory dies. The memory dies included in stack of memory dies 104 may be NAND memory dies. The memory dies included in stack 104 may generally be storage means configured to store a quantity of electrical charge (e.g., provide data storage). In some embodiments, package 100 may include a controller (not shown) configured to control the routing of signals (e.g., power, ground, IO signals) to and from the semiconductor dies included in stack 104. In some embodiments, the controller (not shown) may be an application specific integrated circuit (ASIC) or any other type of controller. The controller may be electrically connected to the substrate 102. In some embodiments, a molding compound (not shown) may encapsulate at least the die stack 104, the first platform 106, and the second platform 108. The molding compound may include, for example, epoxy molding compound (EMC) or other encapsulating materials known in the art.

[0016] The substrate 102 may be the mechanical base support for the package 100 and / or the electrical interface that provides access to the stack of semiconductor dies 104 housed within the package. The electrical interface may include multiple metal layers within the substrate 102, including at least one layer for routing data using conductive (e.g., copper) traces, ground layers, and / or power layers. The stack of semiconductor dies 104 and the platforms 106, 108 may be mounted on a top planar surface 110 of the substrate 102. In some embodiments, the stack of semiconductor dies 104, the first platform 106, and the second platform 108 may extend from the top planar surface 110 of the substrate 102 (e.g., upward as shown in the drawings). The stack of semiconductor dies 104 may be positioned on the substrate 102 between the first platform 106 and the second platform 108. For example, in some embodiments, a first platform 106 may be positioned on the substrate 102 and spaced apart from the stack 104, and a second platform 108 may be positioned on the substrate 102 opposite the first platform 106 and spaced apart from the stack 104. In this manner, there may be platforms (e.g., platform 106, platform 108) spaced apart from opposite sides of the stack 104.

[0017] The semiconductor die stack 104 may include multiple semiconductor dies, including a first (bottom) die on the substrate 102, with each subsequent die stacked on top of an adjacent die. For example, as shown in FIGS. 1A-1B, the stack 104 includes twelve semiconductor dies 104a-104l stacked on top of one another. In some embodiments, each memory die included in the stack 104 is vertically offset from an adjacent memory die. For example, the stack 104 may be a staggered memory die stack, where the memory dies included in the stack 104 form a staggered staircase pattern in which the sidewalls of each memory die are offset from the corresponding sidewalls of an adjacent memory die. Thus, each memory die included in the stack 104 may have an exposed top surface not covered by an adjacent memory die, on which a corresponding set of die bond pads 110 is located.

[0018] In some embodiments, the semiconductor dies 104a-104l are arranged in a center-stacked pattern or a side-by-side stacked pattern. In some embodiments, the semiconductor dies 104a-104l may form substacks aligned along different axes (axes not shown). These axes may be oriented obliquely with respect to the top planar surface 110 of the substrate 102. For example, the semiconductor dies 104a-104d may form a first substack of dies, the semiconductor dies 104e-104h may form a second substack of dies, and the semiconductor dies 104i-104l may form a third substack thereof. The center points of each die included in each substack may be generally positioned along an axis (not shown). The axis of the second substack may intersect the axes of the first and third substacks. The axes of the first and third substacks may be generally parallel and offset from one another. While the axes are not shown to avoid cluttering the illustration, it should be understood that each axis may be illustrated as extending approximately through the center points of each die included in the substack. In some embodiments, different sub-stacks of semiconductor dies 104a-104l may alternatively be referred to as different memory channels (e.g., first, second, and third memory channels). In some embodiments, the semiconductor dies of the sub-stacks may be electrically connected to each other, but the semiconductor dies of one sub-stack may be electrically isolated from the semiconductor dies of a different sub-stack. In other embodiments, the semiconductor dies of one sub-stack may be electrically connected to the semiconductor dies of a different sub-stack. In some embodiments, each sub-stack of semiconductor dies may include, for example, at least four semiconductor dies. In some embodiments, semiconductor die stack 104 may include eight or more semiconductor dies. In some embodiments, semiconductor die stack 104 includes at least 12 semiconductor dies. In some embodiments, semiconductor die stack 104 includes at least 16 semiconductor dies.

[0019] The first platform 106 and the second platform 108 may each be configured to provide one or more raised surfaces spaced apart from the top planar surface 110 of the substrate 102 to facilitate electrical connection between one or more of the semiconductor dies 104a-104l and the substrate 102. As described further below, in some embodiments, the first platform 106 and / or the second platform 108 may include two or more levels or "steps," each step providing a separate raised surface (a "step surface") spaced a predetermined distance from the top planar surface 110 of the substrate 102. In some embodiments, the first platform 106 and the second platform 108 may have different numbers of steps or the same number of steps. According to some embodiments, each step surface of a single platform may have a different height, measured from the top planar surface 110 of the substrate 102. Thus, in some embodiments, the step surfaces of the platforms may be vertically offset from one another. Furthermore, the step surfaces may also be horizontally offset from one another. For example, in some embodiments, the higher step planes may be spaced horizontally further from the semiconductor stack 104 compared to the lower step planes. In some embodiments, the first platform 106 and the second platform 108 may each have one or more steps at the same height as measured from the top planar surface 110 of the substrate 102. The step planes may be approximately parallel to each other and to the top planar surface 110 of the substrate 102 in some embodiments.

[0020] In some embodiments, there are a plurality of through vias 112 extending through each of the first and second platforms 106, 108. In some embodiments, each through via 112 may extend from one of the stepped surfaces to the substrate 102 to provide a conductive path through one of the platforms 106, 108, and each through via 112 may be oriented approximately perpendicular to the top planar surface 110 of the substrate 102. In some embodiments, a step of one of the platforms 106, 108 may include a plurality of through vias 112. The through vias 112 may be configured to establish electrical communication between one or more of the semiconductor dies 104a-104l and the substrate 102. The through vias 112 may be electrically connected to the substrate 102. In some embodiments, the through vias 112 are embedded within the respective platforms 106, 108 and are exposed at one end so that they can be electrically connected to the substrate 102.

[0021] In some embodiments, the platforms 106, 108 are configured to minimize and / or reduce the required diameter of the through vias 112 extending therethrough. Each platform 106, 108 may be formed from one or more sections stacked on top of one another. Each section of the platform 106, 108 may be composed of a conductive layer 109 and a dielectric layer 111. According to some embodiments, the dielectric layer 111 may be made of, for example, an organic material, the same material as the substrate 102, and / or a ceramic material. The conductive layer 109 and dielectric layer 111 of each section may be fixedly coupled to one another via an adhesive or any other fastening means known to those skilled in the art. In this manner, each platform 106, 108 may be formed from a series of alternating conductive layers 109 and dielectric layers 111. For example, each platform 106, 108 may be formed from a first conductive layer 109, a dielectric layer 111 attached on top of the first conductive layer 109, a second conductive layer 109 attached directly on top of the dielectric layer 111, etc. In some embodiments, the conductive layers 109 allow for signal redistribution between layers and connect vias 112. In some embodiments, the conductive layers 109 may be comprised of multiple conductive traces that are electrically isolated and / or spaced apart from one another. In some embodiments, the vias 112 may include a series of electrically connected sub-vias, each sub-via extending between adjacent conductive layers 109. The series of electrically connected sub-vias may be arranged in a staggered manner, a generally linear manner, or a combination thereof. In some embodiments, one or more passive components (e.g., resistors, capacitors, inductors) may be mounted on the platforms 106, 108 and electrically connected to the substrate 102 by through vias 112.

[0022] In some embodiments, the number of sections included in each platform 106, 108 may depend on the desired height of the platform 106, 108. For example, the first platform 106 may be formed from five sections stacked on top of each other, and the second platform 108 may be formed from three sections, such that the overall height of the first platform 106 is greater than the overall height of the second platform 108. In some embodiments, the vertical thickness of each conductive layer 109 may be approximately the same, and the vertical thickness of each dielectric layer 111 may also be approximately the same. In some embodiments, the topmost dielectric layer 111 may have a vertical thickness that is less than or greater than the vertical thickness of the dielectric layer 111 positioned immediately below it. By providing a series of sections composed of conductive layers 109 and dielectric layers 111, the required diameter of the through via 1112 extending therethrough may be minimized and / or reduced. For example, if the platforms 106, 108 are formed from a continuous piece of dielectric material, the required diameter of the through vias 112 passing therethrough may be larger than if there is a conductive layer 109 between adjacent dielectric layers 111. In some embodiments, the diameter of the through vias 112 may be from about 2 microns to about 20 microns. In some embodiments, the diameter of the through vias 112 may be about 10 microns.

[0023] There may be one or more bond pads 114 coupled to each of the first and second platforms 106, 108 and configured to facilitate electrical communication between the semiconductor die stack 104 and the through vias 112. In some embodiments, the bond pads 114 are exposed on the surfaces of the first and second platforms 106, 108, with each bond pad 114 electrically connected to one or more of the through vias 112. Each bond pad 114 may be exposed on a stepped surface of the respective first and second platforms 106, 108. For example, the first platform 106 may include a first stepped surface 106a, a second stepped surface 106b, and a third stepped surface 106c. There may be bond pads 114 exposed on one or more of the first, second, and third stepped surfaces 106a-106c, with at least one through via 112 electrically connected to each of the bond pads 114. In some embodiments, there are one or more bond pads 114 exposed on the first, second, and third stepped surfaces 106a-106c. In some embodiments, the first, second, and / or third stepped surfaces 106a-106c include sets of bond pads 114 arranged in one or more rows on their respective stepped surfaces. The second platform 108 may include a first stepped surface 108a, a second stepped surface 108b, and a third stepped surface 108c. There may be additional bond pads 114 exposed on one or more of the first, second, and third stepped surfaces 108a-108c, with at least one through via 112 electrically connected thereto. In some embodiments, there are bond pads 114 exposed on the second and third stepped surfaces 108b-108c. In some embodiments, the first stepped surface 108a may be omitted. The bond pads 114 exposed on each of the stepped surfaces 106a-106c and / or stepped surfaces 108a-108c may be substantially aligned with one another in at least one direction. For example, the bond pads 114 exposed on the third stepped surface 106c may be arranged along a substantially straight line or a single row. In other embodiments, the bond pads 114 may be arranged along two parallel lines or two rows.

[0024] In some embodiments, there may be more than one through via 112 electrically connected to a single bond pad 114. For example, as shown in FIG. 1B , there are three through vias 112 electrically and mechanically connected to a single bond pad 114 exposed on the third stepped surface 106c of the first platform 106. In some embodiments, one or more bond pads 114 may have a different number of through vias 112 electrically connected to it than one or more other bond pads 114. For example, a bond pad 114 exposed on the third stepped surface 108c of the second platform 108 may have a single through via 112 electrically connected to it, while a bond pad 114 exposed on the third stepped surface 106c of the first platform 106 has three through vias 112 electrically connected to it.

[0025] There may be a plurality of bond wires 116 electrically connecting one or more of the semiconductor dies included in the stack 104 to through vias 112 extending through the first and second platforms 106, 108, respectively. For example, there may be a first set of bond wires 116 electrically connecting semiconductor dies 104c-104d and 104i-104l to the through vias 112 extending through the first platform 106, and there may be a second set of bond wires 116 electrically connecting semiconductor dies 104e-104h to the through vias 112 extending through the second platform 108. The bond wires 116 may be electrically connected to and extend between respective bond pads 114 and die bond pads 115 exposed on the surface of each semiconductor die. In this manner, bond wires 116 may electrically connect a respective semiconductor die (e.g., at least one of semiconductor dies 104a-104l) to one or more through vias 112 electrically connected to a respective bond pad 114. Bond pads 114 and die bond pads 115 may be composed of a conductive material. In some embodiments, pitch P1 of bond pads 114 may be smaller than pitch P2 of die bond pads 115. In some embodiments, pitch P1 is at least half of pitch P2. In some embodiments, pitch P2 is between about 80 microns and about 120 microns. In some embodiments, pitch P1 is between about 80 microns and about 120 microns.

[0026] In some embodiments, a semiconductor die may be electrically connected via bond wires 116 to bond pads 114 located on the step plane that is closest in height to the position of the semiconductor die relative to the substrate 102. In some embodiments, die bond pads 115 from different semiconductor dies in the stack 104 may be connected via bond wires 116 to different bond pads 114 on the same step plane. In some embodiments, a particular step plane may include bond pads 114 that connect to two adjacent semiconductor dies in the stack 104. 1A and 1B, die bond pads 115 from semiconductor dies 104c and 104d may connect to bond pads 114 on the first stepped surface 106a, die bond pads from semiconductor dies 104i and 104j may connect to bond pads 114 on the second stepped surface 106b, and die bond pads 115 from semiconductor dies 104k and 104l may connect to bond pads 114 on the third stepped surface 106c. Meanwhile, continuing with this illustrated example, die bond pads from semiconductor dies 104e and 104f may connect to bond pads 114 on the second stepped surface 108b of the second platform 108, and die bond pads from semiconductor dies 104g and 104h may connect to bond pads 114 on the third stepped surface 108c of the second platform 108.

[0027] In some embodiments, a particular semiconductor die positioned at or near the bottom of the stack 104 may be directly connected to bond pads on the substrate 102 rather than on the first and second platforms 106, 108. For example, in some embodiments, there are one or more substrate bond pads 118 electrically connected to the substrate 102. The substrate bond pads 118 may be electrically connected to an electrical interface of the substrate 102. Thus, the substrate bond pads 118 may function as a set of electrical contact means for transmitting and receiving multiple electrical signals. In some embodiments, the substrate bond pads 118 are electrically connected to the substrate 102 and are mounted directly on the top surface 110 of the substrate 102. In some such embodiments, unlike the bond pads 114, the substrate bond pads 118 are not located on the first or second platforms 106, 108, and the substrate bond pads 118 are not connected to through vias 112. In some embodiments, the substrate bond pads 118 are positioned between the platform (e.g., the first platform 106) and the stack of memory dies 104. There may be bond wires 116 electrically connecting the substrate bond pads 118 to at least one semiconductor die included in the stack 104. For example, in some embodiments, there are bond wires 116 electrically connecting the bottom semiconductor die (e.g., semiconductor die 104a) of the stack 104 to a respective substrate bond pad 118. In some embodiments, the two bottom semiconductor dies included in the stack 104 are electrically connected to the substrate bond pads 118 by corresponding bond wires 116. For example, each of the semiconductor dies 104a and 104b may be electrically connected to a respective substrate bond pad 118 by a bond wire 116 extending therebetween.

[0028] In some embodiments, the total number of different step surfaces included in the platforms 106, 108 may be half the number of semiconductor dies in the stack 104. In some embodiments, the total number of different step surfaces included in the platforms 106, 108 may be at least half the number of semiconductor dies in the stack 104. In some embodiments, the total number of different step surfaces included in the platforms 106, 108 may be half or at least half the number of semiconductor dies in the stack 104 minus one. In some embodiments, the total number of different step surfaces included in the platforms 106, 108 may be equal to or less than the number of substacks included in the die stack 104. For example, in FIGS. 1A-1B, there are three substacks, and the total number of step surfaces on each platform 106, 108 is three.

[0029] In some embodiments, by providing platforms 106, 108 with stepped surfaces spaced apart at different heights above substrate 102, the length of bond wires 116 extending between each stepped surface and the semiconductor die included in stack 104 can be reduced or minimized and / or shortened. For example, there can be first and second bond wires 116a, 116b electrically connecting one or more of the semiconductor die included in stack 104 to first and second through vias 112a, 112b. The first bond wire 116a can be electrically connected to the first through via 112a and to the first semiconductor die, which in this example is semiconductor die 104c. Further to this example, the second bond wire 116b can be electrically connected to the second through via 112b and to the second semiconductor die, which in this example is semiconductor die 104e. In this manner, semiconductor dies 104c and 104e may be in electrical communication with substrate 102 via bond wires 116a, 116b and through vias 112a, 112b. Thus, the length of first and second bond wires 116a, 116b is shorter than the length of bond wires required to directly connect the semiconductor dies to substrate 102.

[0030] The inductance of a bond wire increases with the length of the wire (e.g., the longer the bond wire, the greater the inductance of the wire). As inductance increases, noise in electrical signals (e.g., power signals, ground signals, I / O signals) also increases. However, a through via 112 having approximately the same length as a bond wire 116 may have a lower inductance than the inductance of the bond wire 116. Therefore, by electrically connecting the bond wire 116 to a through via 112 that extends upward from the substrate 102 through the platforms 106, 108, the required length of the bond wire 116 is minimized and / or reduced, thereby reducing the total inductance and improving signal integrity (e.g., reducing signal noise).

[0031] In some embodiments, the minimum required length of the bond wire 116 may be directly related to the height of the platform 106, 108 or its stepped surfaces 106a-106c, 108a-108c. For example, the length of the first bond wire 116a may be directly related to the height H1 of the first stepped surface 106a (e.g., the distance from the top surface 110 of the substrate 102 to the stepped surface 106a). Accordingly, the height H1 of the first stepped surface 106a may be selected such that the length of the first bond wire 116a is minimized and / or reduced. In some embodiments, the height of the stepped surfaces 106a-106c, 108a-108c is equal to or less than the height of the corresponding lowermost semiconductor die on the stack 104 to which the corresponding bond wire 116 is connected. For example, the first bond wire 116a extends between the first stepped surface 106a and the first semiconductor die 104c. There is also another bond wire 116 extending from the first step surface 106a to the semiconductor die 104d, which is mounted directly on top of the semiconductor die 104c. Thus, with respect to the first step surface 106a, the lowest die on the stack is, in this example, the first semiconductor die 104c to which a corresponding bond wire (e.g., bond wire 116a) is connected. As a further example, with respect to the second step surface 106b, the semiconductor die 104i may be the lowest semiconductor die 104 on the stack to which a corresponding bond wire 116 is connected. The first step surface 106a may have a height H1 that is equal to or less than the height H2 of the semiconductor die 104c. In other embodiments, the height H1 may be + / - about 10% of the height H2. In some embodiments, the height H1 is about 0.75 * H2 ~ approx. 0.95 * It is H2.

[0032] In some embodiments, the semiconductor device package 100 of the present disclosure is configured to reduce the risk of electrical short circuits occurring. For example, there may be a third through-hole via 112c electrically connected to the substrate 102 and extending through the first platform 106. The third through-hole via 112c may be electrically connected to a bond pad 114 exposed on the second stepped surface 106b. The third through-hole via 112c may be electrically connected to a third bond wire 116c, which may be electrically connected to a third semiconductor die on the stack 104 (semiconductor die 104i in this example). At least a portion of the third bond wire 116c may be spaced apart (e.g., vertically above) the first bond wire 116a and / or the second bond wire 116b. In some embodiments, the entire third bond wire 116c is positioned above the first bond wire 116a. Thus, the distance between the first step surface 106 a and the second step surface 106 b of the first platform 106 may provide a vertical offset between the first bond wire 116 a and the third bond wire 116 c. In this manner, the bond wires 116 a, 116 c may not be in direct contact with each other, which may reduce the risk of an electrical short between the bond wires 116 a, 116 c.

[0033] In some embodiments, the semiconductor device package 100 of the present disclosure is configured to reduce the amount of load (e.g., power, amperes) on the top die included in the die stack 104 or any sub-stack thereof. For example, as shown in FIGS. 1A-1B , there is a single set of bond wires 116 connected to each semiconductor die 104a-104l. The bond wires 116 may not include wire loops connecting to one or more adjacent semiconductor die on the stack 104. In this manner, the increase in inductance caused by the increased length of bond wires electrically connected to multiple dies on the stack is reduced, thereby eliminating or at least reducing the load experienced by the top die connected to that bond wire. For example, each die 104a-104l may have a bond wire 116 connected only to the corresponding die 104a-104l, such that each bond wire 116 carries only the load of the corresponding die 104a-104l, as opposed to bond wires in a conventional die stack that carry loads to multiple dies (e.g., 2-8 dies).

[0034] By providing first and second platforms 106, 108, through vias 112 extending therethrough, and bond wires 116 electrically connected thereto, the semiconductor device package 100 of the present disclosure can be configured to improve power and signal integrity, reduce loading on the top die of the stack 104, and reduce the risk of electrical short circuits occurring, as described above.

[0035] 2, another embodiment of a semiconductor device package, generally designated 200, is shown in accordance with an exemplary embodiment of the present disclosure. Semiconductor device package 200 may be generally similar to package 100 described above with respect to FIGS. 1A-1B, except that package 200 may include a bond wire 216 electrically connecting two adjacent semiconductor dies on stack 204. Semiconductor device package 200 may include a substrate 202 that is generally similar to substrate 102, a stack 204 of semiconductor dies 204a-204l that is generally similar to stack 104, a first platform 206 that is generally similar to platform 106, and a second platform that is generally similar to platform 106. There may be a first bond wire 216a electrically connected to through via 212. The first bond wire 216a may differ from the first bond wire 116a in that the bond wire 216a in the package 200 is electrically connected to the first semiconductor die 204c and to the adjacent semiconductor die 204d. In this manner, the package 200 may include fewer through vias 212 than the package 100. For example, each through via 212 may be electrically connected to a corresponding bond wire 216 that is electrically connected to two adjacent semiconductor dies (e.g., dies 204c and 204d, dies 204e and 204f, dies 204g and 204h, dies 204i and 204j, and dies 204k and 204l). Thus, the number of required through vias 212 may be reduced compared to the package 100.

[0036] Referring to FIG. 3, another embodiment of a semiconductor device package, generally designated 300, is shown in accordance with an exemplary embodiment of the present disclosure. The semiconductor device package 300 may be generally similar to the package 100 described above with respect to FIGS. 1A-1B, except that the package 300 may include a bond wire 316 electrically connected to at least two adjacent semiconductor dies on the stack 304. The semiconductor device package 300 may include a substrate 302 that is generally similar to the substrate 102. The semiconductor device package 300 may include a stack 304 of semiconductor dies 304a-304p that is generally similar to the stack 104, except that the stack 304 includes more dies than the stack 104 (e.g., 16 dies). There may be a first bond wire 316a electrically connecting a first semiconductor die, in this example semiconductor die 304i, to a through via 312 extending through the first platform 306. The first platform 306 may be similar to the first platform 106, except that it may include fewer step surfaces. For example, the first platform 306 includes a single step surface. The first bond wire 316a may be electrically connected to the first semiconductor die 304i and at least two adjacent semiconductor dies. For example, as shown in FIG. 3, the first bond wire 316a is electrically connected to the dies 304i-304l. In some embodiments, the first bond wire 316a is electrically connected to sub-stacks of the semiconductor dies included in the stack 304. For example, the semiconductor dies 304a-304d may form a first sub-stack, the dies 304e-304h may form a second sub-stack, the dies 304i-304l may form a third sub-stack, and the dies 304m-304p may form a fourth sub-stack. The semiconductor dies within each sub-stack may be electrically connected to each other. Each of the first, second, third, and fourth substacks may be electrically connected to a corresponding bond wire 316 that is electrically connected to a corresponding through via 312. In this manner, semiconductor device package 300 may include fewer through vias 312 than package 100 and / or package 200.In some embodiments, the bottom first substack including semiconductor dies 304a-304d may be directly connected to the substrate via bond wires rather than through vias 312 in platforms 306 or 308. In some embodiments, the total number of different step planes included in platforms 306, 308 may be equal to or at least equal to the number of substacks of semiconductor dies in stack 304. In some embodiments, the total number of different step planes included in platforms 306, 308 may be equal to or at least equal to the number of substacks of semiconductor dies in stack 304 minus one.

[0037] Those skilled in the art will understand that changes can be made to the exemplary embodiments shown and described above without departing from the broad inventive concept thereof. It is therefore understood that the present invention is not limited to the exemplary embodiments shown and described, but is intended to cover modifications within the spirit and scope of the present invention as defined by the claims. For example, certain features of the exemplary embodiments may or may not be part of the claimed invention, and various features of the disclosed embodiments may be combined. The words "right," "left," "bottom," and "top" designate directions in the drawings to which reference is made. Unless specifically stated herein, the terms "a," "an," and "the" are not limited to one element and should instead be read to mean "at least one." As used herein, the term "about" may refer to + / - 10% of the referenced value. For example, "about 9" is understood to encompass 8.1 and 9.9.

[0038] It should be understood that at least some of the figures and descriptions of the invention have been simplified to focus on elements relevant to a clear understanding of the invention, while the omission of other elements that one skilled in the art would understand for the sake of clarity may also comprise part of the invention. However, because such elements are well known in the art, and because they do not necessarily facilitate a better understanding of the invention, descriptions of such elements are not provided herein.

[0039] Furthermore, to the extent that the methods of the present invention do not rely on a particular order of steps set forth herein, the particular order of steps should not be construed as limiting the scope of the claims. Any claims directed to the methods of the present invention should not be limited to the performance of those steps in the order written, and one of ordinary skill in the art can readily appreciate that steps can be varied and still remain within the spirit and scope of the present invention.

Claims

1. 1. A semiconductor device package comprising: A substrate; a stack of semiconductor dies positioned on the substrate, the stack including a first semiconductor die and a second semiconductor die; a first platform positioned on the substrate; a second platform positioned on the substrate opposite the first platform, the stack of semiconductor dies being positioned between the first platform and the second platform; a first through via electrically connected to the substrate and extending through the first platform; a second through via electrically connected to the substrate and extending through the second platform; a first bond wire electrically connecting the first through via to the first semiconductor die; a second bond wire electrically connecting the second through via to the second semiconductor die; the first platform includes a first step surface, a second step surface vertically offset from the first step surface, and a first bond pad exposed on the first step surface and electrically connected to the first through via; The semiconductor device package, wherein the first through via extends through the first platform from the first bond pad to the substrate.

2. the first platform includes a second bond pad exposed at the second stepped surface and a third through via electrically connected to the substrate and the second bond pad; 2. The semiconductor device package of claim 1, wherein the third through via extends through the first platform from the second bond pad to the substrate.

3. a third semiconductor die included in the stack of semiconductor dies, the third semiconductor die being positioned above the first and second semiconductor dies; 3. The semiconductor device package of claim 2, further comprising: a third bond wire electrically connecting said third semiconductor die to said third through via.

4. 4. The semiconductor device package of claim 3, wherein at least a portion of the third bond wire is positioned vertically above the first bond wire and does not directly contact the first bond wire.

5. 10. The semiconductor device package of claim 1, wherein the first and second platforms comprise a series of sections stacked on top of one another, each section comprising a conductive layer and a dielectric layer.

6. A semiconductor device package, comprising: A substrate; a stack of semiconductor dies positioned on the substrate, the stack including a first semiconductor die and a second semiconductor die; a first platform positioned on the substrate; a second platform positioned on the substrate opposite the first platform, the stack of semiconductor dies being positioned between the first platform and the second platform; a first through via electrically connected to the substrate and extending through the first platform; a second through via electrically connected to the substrate and extending through the second platform; a first bond wire electrically connecting the first through via to the first semiconductor die; a second bond wire electrically connecting the second through via to the second semiconductor die; a bond pad exposed on a surface of the first platform, the first bond wire electrically connected to the bond pad; The semiconductor device package, wherein the first through via is electrically connected to the bond pad and the substrate and extends through the first platform from the bond pad to the substrate.

7. The semiconductor device package of claim 1 , wherein the first platform has an overall height greater than the second platform.

8. 10. The semiconductor device package of claim 1, wherein the first platform and the second platform are constructed from the same material as the substrate.

9. The semiconductor device package of claim 1 , wherein the stack of semiconductor dies includes a memory die.

10. a substrate bond pad electrically connected to the substrate and positioned between the stack of semiconductor dies and the first platform; a bond wire electrically connecting the substrate bond pad to a bottom semiconductor die in the stack of semiconductor dies; The semiconductor device package of claim 1 further comprising:

11. 10. The semiconductor device package of claim 1, wherein the first bond wire is electrically connected to the first semiconductor die and another semiconductor die adjacent to the first semiconductor die.

12. The semiconductor device package of claim 1 , wherein the first bond wires are electrically connected to the first semiconductor die and at least two adjacent semiconductor dies.

13. 1. A semiconductor device package comprising: a substrate including a top surface and a substrate bond pad exposed on the top surface; a stack of semiconductor dies positioned on the top surface of the substrate; a first platform positioned on the top surface of the substrate, the first platform being electrically connected to the substrate and including a plurality of through vias extending through the first platform; a second platform positioned on the top surface of the substrate opposite the first platform such that the stack of semiconductor dies is positioned between the first platform and the second platform, the second platform being electrically connected to the substrate and including a plurality of through vias extending through the second platform; a first bond wire connecting a first semiconductor die of the stack to at least one through via of the plurality of through vias of the first platform, and a second bond wire connecting a second semiconductor die of the stack to at least one through via of the plurality of through vias of the second platform; a bond pad exposed on a surface of the first platform, the first bond wire electrically connected to the bond pad; a semiconductor device package, wherein the at least one through via of the plurality of through vias of the first platform is electrically connected to the bond pad and the substrate and extends through the first platform from the bond pad to the substrate.

14. 14. The semiconductor device package of claim 13, wherein the first platform includes at least two stepped surfaces vertically offset from one another, the bond pads being exposed on each of the stepped surfaces and electrically connected to one or more of the plurality of through vias of the first platform.

15. The semiconductor device package of claim 14 , wherein at least one of the bond pads is connected to two or more of the plurality of through vias of the first platform.

16. 14. The semiconductor device package of claim 13, wherein the first and second platforms include a series of sections stacked on top of one another, each section including a conductive layer and a dielectric layer.

17. 14. The semiconductor device package of claim 13, wherein each through via of the plurality of through vias has a diameter of approximately 10 microns.

18. 14. The semiconductor device package of claim 13, wherein the first platform and the second platform are constructed from the same material as the substrate.

19. 1. A semiconductor device package comprising: substrate means for providing electrical interconnections between electrical components coupled to said substrate means; first platform means for providing a first set of raised electrical contacts spaced from said substrate means, said first platform means including first conductive means extending through said first platform means to said substrate means for electrically connecting said first set of raised electrical contacts to said substrate means; second platform means providing a second set of raised electrical contacts spaced from said substrate means, said second platform means including second conductive means extending through said second platform means to said substrate means for electrically connecting said second set of raised electrical contacts to said substrate means; a stack of storage means each for storing a quantity of data, the stack of storage means being positioned on said substrate means between said first platform means and said second platform means and including a first storage means electrically connected to said first set of raised electrical contacts and a second storage means electrically connected to said second set of raised electrical contacts.

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