Fabrication of semiconductor structures
The method of selective epitaxy in photonic crystal structures addresses the challenges of electrical actuation and active material placement, resulting in improved semiconductor devices with enhanced light-matter interactions and modulation rates.
Patent Information
- Application Number
- JP2022561381
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2020-05-04
- Filing Date
- 2021-04-20
- Publication Date
- 2025-08-06
- Estimated Expiration
- 2041-04-20
AI Technical Summary
The challenge in fabricating photonic crystal cavities for semiconductor devices lies in efficient electrical actuation and precise placement of active materials within the cavity, which can lead to excessive absorption losses and compromised optical performance.
A method involving selective epitaxy to replace a first material in a predetermined portion of a photonic crystal structure with one or more second materials, enabling efficient carrier confinement and improved device performance by forming lateral heterojunctions and pin structures.
This approach allows for efficient manufacturing of photonic crystal structures with optimized material properties, enhancing light-matter interactions and modulation rates, and facilitating electrical actuation without compromising optical cavity integrity.
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Abstract
Description
[Technical Field]
[0001] Embodiments of the present invention relate generally to methods for fabricating semiconductor structures, and in particular to methods for fabricating semiconductor structures for optical applications such as laser applications. Embodiments of the present invention further relate to semiconductor devices, in particular resonators or more particularly lasers, that may be fabricated by such methods. [Background technology]
[0002] Optical interconnects for next-generation computing require semiconductor light sources. Photonic crystal nanocavities are an ideal platform for such sources because they offer strong light-matter interactions, high Q / V ratios, thresholdless laser behavior, and high modulation rates.
[0003] A challenge in devices based on photonic cavities is electrical actuation, i.e., efficient injection of carriers into the active region without compromising the optical cavity.
[0004] When a photonic cavity is implemented in an active material, excessive absorption losses can occur because light is absorbed outside the cavity.
[0005] On the other hand, precise placement of the active substance within the central portion of the cavity remains a difficult challenge. Summary of the Invention
[0006] According to a first aspect, the present invention is embodied in a method for fabricating a semiconductor structure. The method includes fabricating a photonic crystal structure of a first material, in particular a first semiconductor material, and selectively removing the first material within a predetermined portion of the photonic crystal structure. The method further includes replacing the first material within the predetermined portion of the photonic crystal structure with one or more second materials by selective epitaxy.
[0007] Such methods according to embodiments of the present invention provide an efficient way to fabricate photonic crystal structures comprising two different materials in an efficient manner.
[0008] According to embodiments, the properties of the first and second materials may be independently improved or optimized to improve the efficiency of the device.
[0009] According to one embodiment, the predetermined portion of the photonic crystal structure is a central portion of the photonic crystal structure. According to such an embodiment, the second material may be disposed in the central portion of the photonic crystal structure. This can enable efficient carrier confinement in the central portion or center of the photonic crystal structure, thereby improving device performance.
[0010] The first material may be, in particular, silicon, while the second material may be, in particular, an optically active material. This may, for example, enable the use of current photonic crystal cavity designs, in particular Si photonic designs, with suitable or compatible geometries, and the replacement of silicon with an optically active material, for example, a III-V material. Embodiments of the present invention may, in particular, enable the placement of the optically active material as a gain material in the portion of the photonic crystal structure where the optically active material boosts efficiency.
[0011] According to one embodiment, fabricating a photonic crystal structure includes providing a wafer including a layer of a first material and patterning the layer of first material, thereby fabricating a photonic crystal structure of the first material, which allows for efficient manufacturing.
[0012] According to one embodiment, the wafer is a silicon-on-insulator wafer comprising a silicon layer on an insulating layer, and the method further comprises patterning the silicon layer, thereby producing a photonic crystal structure comprising silicon as the first material, which allows for efficient manufacturing.
[0013] According to one embodiment, replacing the first material with one or more second materials includes growing the one or more second materials laterally across the wafer, which allows for advantageous device designs.
[0014] According to one embodiment, the method further comprises growing one or more second materials with a predetermined doping profile laterally across the wafer, which allows for more advantageous device designs. In particular, methods according to embodiments of the invention can enable the fabrication of pin structures with lateral doping in the epitaxial plane, i.e., aligned parallel to the substrate of the wafer.
[0015] According to one embodiment, the method further comprises growing two different second materials laterally across the wafer, thereby forming a lateral heterojunction. According to such an embodiment, in a first step, a first one of the second materials, e.g., a first III-V material such as AlGaAs or InP, is epitaxially grown, and in a second step, another one of the second materials, e.g., another III-V material such as InGaAs, is epitaxially grown, thereby producing a lateral heterojunction.
[0016] According to one embodiment, the method further comprises providing electrical contacts to the one or more second materials, which can be particularly easy to follow for embodiments having a lateral doping profile.
[0017] According to embodiments, several different material combinations of a first material and multiple second materials may be implemented on the same wafer by repeating growth runs, which may be possible due to the local integration of the gain material.
[0018] According to one embodiment, selectively removing the first material within a predetermined portion of the photonic crystal structure includes encapsulating the photonic crystal structure of the first material with a third material, particularly an oxide material. Further steps include selectively removing a portion of the third material within the predetermined portion of the photonic crystal structure to provide a window in the first material and selectively removing a portion of the first material through the window. This creates a template structure of the third material. The template structure may also be referred to as a cavity structure. To facilitate the growth of one or more second materials in the template structure, the remaining portion of the first material forms a seed structure for one or more second materials.
[0019] According to one embodiment, selectively removing portions of the first material through the window includes performing a selective etch of the first material, in other words, the etch is performed such that only the first material is etched but not the third material of the template structure.
[0020] According to one embodiment, replacing the first material with one or more second materials includes growing the one or more second materials from a seed structure within a template structure of a third material, which is an efficient and accurate method for placing a second material within a photonic crystal structure.
[0021] According to one embodiment, the method further comprises removing the seed structure of the first material after growing one or more second materials within the template structure, which in particular facilitates electrical contacting of the second materials.
[0022] According to one embodiment, growing the one or more second materials is performed by one of metalorganic chemical vapor deposition (MOCVD), atmospheric pressure CVD, low pressure or reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy (MBE), atomic layer deposition (ALD) or hybrid vapor phase epitaxy.
[0023] According to an embodiment of a further aspect of the present invention there is provided a semiconductor device obtainable by a method according to the first aspect.
[0024] According to an embodiment of a further aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, and a photonic crystal structure on the insulating layer, wherein the photonic crystal structure comprises a first material in an outer portion of the photonic crystal structure and one or more second materials in a central portion or region thereof, the one or more second materials being epitaxially grown semiconductor materials forming a gain structure extending laterally of the substrate.
[0025] According to one embodiment, the photonic crystal structure is a one-dimensional, two-dimensional, or three-dimensional photonic crystal lattice.
[0026] According to further embodiments, the semiconductor device may be embodied as an optical cavity or a laser.The gain structure may comprise one or more quantum wells according to embodiments.
[0027] The steps of different aspects of the invention may be performed in different orders as appropriate. Furthermore, multiple steps may also be combined as appropriate, i.e., for example, two or more steps may be performed together.
[0028] An advantage of a feature of one aspect of the invention may apply to a corresponding feature of another aspect of the invention.
[0029] Embodiments of the invention are described in more detail below, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]
[0030] [Figure 1a] FIG. 2 is a three-dimensional view of an initial structure including a layer of a first material. [Figure 1b] FIG. 1 is a three-dimensional diagram including a photonic crystal structure formed from a layer of a first material by patterning. [Figure 1c] FIG. 10 is a three-dimensional view of the photonic crystal structure after encapsulation with a third material, for example, an oxide. [Figure 1d] FIG. 3D view of the structure after windows have been formed in the oxide. [Figure 1e] FIG. 2 is a three-dimensional view of the structure after a portion of the first material has been selectively removed through the window. [Figure 1f] FIG. 3D view after the second material has been grown from the seed structure of the first material. [Figure 1g] FIG. 3D is a three-dimensional view of the structure after the second material forms electrical contact. [Figure 2a] FIG. 1b is a top view corresponding to FIG. 1a. [Figure 2b] FIG. 1B is a top view corresponding to FIG. [Figure 2c] FIG. 1C is a top view corresponding to FIG. [Figure 2d] FIG. 1D is a top view corresponding to FIG. [Figure 2e] FIG. 1c is a top view corresponding to FIG. 1e. [Figure 2f] FIG. 1f is a top view corresponding to FIG. [Figure 2g] FIG. 1g is a top view corresponding to FIG. [Figure 3] 1 is an exemplary top view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1 is a scanning electron microscope image showing an exemplary device structure fabricated using a method according to one embodiment of the present invention. [Figure 5] 1 is a flowchart of method steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0031] Figures 1a-1g show enlarged three-dimensional views of initial, intermediate and final structures formed during stages of a manufacturing method according to an embodiment of the present invention, and Figures 2a-2g show corresponding enlarged top views of the structures corresponding to Figures 1a-1g.
[0032] In some or all of the figures, dimensions may not be drawn to scale and may be shown in a simplified and schematic manner to illustrate features and principles of embodiments of the present invention.
[0033] The terms "on" and "above" are used in this context as is conventional to indicate an orientation or relative position in a direction normal or perpendicular to the surface of the substrate, particularly in the vertical z-direction.
[0034] The terms "lateral" or "laterally" are used in this context to denote an orientation generally parallel to the plane of the substrate, as opposed to generally perpendicular or outward from the substrate surface, as is customary.
[0035] The term "disposed on a semiconductor substrate" should be understood broadly and should include certain embodiments according to which an intermediate layer, e.g., an insulating layer, is disposed between the substrate and the photonic crystal structure. Thus, the term "disposed on a substrate" should include the meaning "above the substrate."
[0036] FIG. 1a shows a three-dimensional view of the initial structure 100, and FIG. 2a shows the corresponding top view. The initial structure 100 includes a substrate 110. The substrate 110, depicted by diagonally upward stripes, includes a semiconductor material and may be, for example, a bulk semiconductor substrate. The substrate 110 may be embodied as a large-diameter crystalline semiconductor wafer or a compound semiconductor wafer. The substrate may include, for example, a material from Group IV of the periodic table as the semiconductor material. Group IV materials include, for example, silicon, germanium, alloys of silicon and germanium, alloys of silicon and carbon, alloys of silicon, germanium, and carbon, etc. For example, the substrate 110 may be a crystalline silicon wafer used in the semiconductor industry.
[0037] The structure 100 further includes an insulating layer 111 on the substrate 110, depicted by diagonally downward stripes. The insulating layer 111 may be embodied as, for example, a dielectric layer. The insulating layer 111 may be formed by known methods such as, for example, thermal oxidation, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, chemical solution deposition, MOCVD, evaporation, sputtering, and other deposition processes. Examples of such dielectric materials include, but are not limited to, SiO2, Si3N4, Al2O3, AlON, Ta2O5, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, YO3, Gd2O3, MgO, MgNO, Hf-based materials, and combinations thereof, including multilayers.
[0038] The structure 100 further includes a layer of a first material 112 embodied as a semiconductor material on the insulating layer 111. The first material may be silicon in particular. The layer of first material 112 is illustrated with a 30% dot pattern.
[0039] The thickness of substrate 110, insulating layer 111 and layer 112 may be any suitable thickness.
[0040] The structure 100 may be particularly embodied as a silicon-on-insulator wafer.
[0041] FIG. 1b shows a three-dimensional view of the structure 101, and FIG. 2b shows the corresponding top view. The structure 101 includes a photonic crystal structure 113 of a first material, e.g., silicon. The structure 101 is formed by patterning a layer 112 of the first material. This may be performed, for example, by lithography and subsequent etching. According to one embodiment, the patterning of the layer 112 may be performed by etching based on HBr chemistry. The photonic crystal structure 113 includes a plurality of rods 114 of the first material. The rods 114 are arranged successively next to each other at a predetermined regular distance d. The plurality of rods extends laterally across the substrate 110, more specifically, parallel to the xy-plane of the substrate 110. FIG. 1c shows a three-dimensional view of the structure 102, and FIG. 2c shows the corresponding top view. The structure 102 includes an encapsulation layer 115 that encapsulates the photonic crystal structure 113 of the first material. The encapsulation layer 115 comprises a third material, particularly a dielectric material, particularly an oxide. The encapsulation layer 115 is used as a template structure, as will be further explained below. The encapsulation layer 115 completely covers the rods 114. For ease of illustration, the encapsulation layer 115 is shown in a transparent format in Figures 1c to 1h.
[0042] FIG. 1d shows a three-dimensional view of the structure 103, and FIG. 2d shows the corresponding top view. The structure 103 includes a window 116 formed by selectively removing a portion of the third material of the encapsulation layer 115 within a predetermined portion 120 of the photonic crystal structure 113, as shown in FIG. 2d. The window 116 forms a window to the first material of the photonic crystal structure 113. In other words, the window 116 provides an opening to the photonic crystal structure 113 within the predetermined portion 120. The predetermined portion 120 is disposed in a central portion of the photonic crystal structure 113. More specifically, the predetermined portion 120 is disposed symmetrically with respect to a symmetry axis 121 of the photonic crystal structure, as shown in FIG. 2d. The window 116 may be fabricated, for example, by lithography and etching. The central portion 120 of the photonic crystal structure is surrounded or surrounded by an outer portion 122 of the photonic crystal structure 113, as shown in FIG. 2d.
[0043] It should be noted that the rods 114 can generally have any desired shape and geometric dimensions as appropriate for a particular application. The rods 114 may also be referred to as bars. According to an embodiment, the geometric dimensions of the rods 114 in the outer portions 122 may differ from the geometric dimensions of the rods 114 in the central portion 120. By way of example, the rods 114 in the outer portions 122 may have a different length and width than the rods 114 in the central portion 120.
[0044] FIG. 1e shows a three-dimensional view of structure 104, and FIG. 2e shows the corresponding top view. In structure 104, portions of the first material of rods 114 within central portion 120 have been removed through windows 116. Rods 114 have created hollow cavities or template structures 117 within the third material. However, rods 114 are not completely removed; the remaining portions of rods 114 form seed structures 118 within template structures 117 for subsequent growth of one or more second materials. Selective removal of the first material through windows 116 may be performed by selective etching of the first material, i.e., etching that etches the first material but not the third material. Suitable etching techniques may depend on the first and third materials, respectively. Generally, the etching technique is selected to etch only the first material but not the third material of the encapsulation layer. Selective removal may be performed by dry or wet etching of the first material in particular.
[0045] FIG. 1f shows a three-dimensional view of the structure 105, and FIG. 2f shows the corresponding top view. In the structure 105, the removed first material has been replaced within a predetermined portion 120 of the photonic crystal structure 113 with one or more second materials by selective epitaxy. Specifically, the one or more second materials are grown from a seed structure 118 within a template structure 117 of a third material. The growth of the one or more second materials is performed laterally across the substrate 110. The one or more second materials form rods 119 of the second material that replace previous rods 114 of the first material within the central portion 120 of the photonic crystal structure 113. The rods 119 of the second material are illustrated with a 70% dot pattern.
[0046] Growing the rods 119 of the second material may be performed, for example, by metalorganic chemical vapor deposition (MOCVD), atmospheric pressure CVD, low pressure or reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy (MBE), atomic layer deposition (ALD) or hybrid vapor phase epitaxy.
[0047] The second material of the rods 119 may in particular be an optically active material, for example InP, InGaAs, AlGaAs, GaAs, GaN, InGaN, AlGaN, any other ternary or quaternary alloy thereof, a II-VI semiconductor or a group IV semiconductor.
[0048] In general, the versatility of methods according to embodiments of the present invention can enable any combination of III-V semiconductor materials within the template structure 117, including buried quantum wells, quantum dots, quantum wires, doped or intrinsic semiconductor layers, and heterojunctions.
[0049] Figure 1g shows a three-dimensional view of structure 106, and Figure 2g shows the corresponding top view. Structure 106 is provided with electrical contacts 130 that contact one or more second materials of rods 119. Rods 119 are shown in a wave pattern.
[0050] According to further embodiments, depending on the respective application and post-processing, there may be an additional step of removing the seed structure 118 of the first material before the step of providing the electrical contact.
[0051] Rods 114 (as described above) and therefore rods 119 can generally have any desired shape and geometric dimensions as appropriate for the respective application. Thus, according to an embodiment, the geometric dimensions of the structures of the first material and the geometric dimensions of the structures of the second material may be different. By way of example, rods 119 of the second material may have a different length and width than rods 114 of the first material.
[0052] 3 shows an exemplary top view of a semiconductor device 300 according to an embodiment of the present invention. The semiconductor device 300 includes a photonic crystal structure 313 disposed on an insulating layer 311 of, for example, an SOI wafer. The semiconductor device 300 may be fabricated using a method according to an embodiment of the present invention as described above.
[0053] The photonic crystal structure 313 includes a plurality of rods 314 of Si arranged in an outer region 322 of the photonic crystal structure 313 and a plurality of rods 319 of one or more second materials, in particular III-V materials, in a central region 320 of the photonic crystal structure 313.
[0054] A plurality of rods 319 in the central region 320 form a gain structure. The rods 319 are embodied as pin structures. The rods 319 are epitaxially grown and extend laterally through the substrate and photonic crystal structure, specifically in the y direction of the xy plane. The xy plane is aligned parallel to the underlying substrate (not shown in FIG. 3 ). Thus, the rods 319 have an exemplary pin doping profile. The rods 319 are laterally contacted by electrical contacts 330, also designated by “c” in FIG. 3 . The photonic crystal structure 313 is embodied as a one-dimensional photonic crystal lattice and forms the gain structure and photonic mirror in the central portion, or in other words, central region 320.
[0055] Therefore, the embodied gain structure may include a doping profile that forms a pin structure, which facilitates electrical pumping. A pin structure is a structure having an intrinsic region disposed between p-doped and n-doped regions.
[0056] In this context, doping should be understood as the intentional introduction of impurities into an intrinsic semiconductor with the purpose of altering its electrical, optical, and structural properties. Doping a semiconductor introduces allowed energy states within the bandgap but very close to the energy band corresponding to the dopant type. Positive, or p-type, doping introduces free holes into the valence band, while negative, or n-type, doping introduces free electrons into the conduction band.
[0057] The introduction of dopants has the effect of shifting the energy band relative to the Fermi level. In n-type semiconductors, the Fermi level is close to the conduction band, or in degenerate n-type semiconductors, it is within the conduction band. For p-type, the Fermi level is close to or within the valence band. Typically, the doping concentration in doped semiconductors is in the range of 5 x 10, depending on the material and the density of states. 18 cm -3 From 10 20 cm -3 Semiconductors are rarely completely intrinsic, but intrinsic in the electrical sense means that the semiconductor is not conductive. Typically, doping levels are in the 10 15 ~10 16 cm -3 It is nearby.
[0058] The pin structures may be grown within a template structure formed by an encapsulating oxide as follows.
[0059] In a first sub-step, an n-doped semiconductor layer 351 of a second semiconductor material is grown within the template structure. In a second sub-step, an intrinsic layer 352 of the second semiconductor material is grown. And in a third sub-step, a p-doped semiconductor layer 353 of the second semiconductor material is grown. Semiconductor layers 351, 352, and 353 collectively form the gain structure of photonic crystal structure 313.
[0060] According to other embodiments, multiple quantum wells may be grown in the central portion of the photonic crystal structure by sequentially growing multiple semiconductor layers of different semiconductor materials in an alternating manner within the template structure, where the different semiconductor materials may have different bandgaps to facilitate the formation of the quantum wells.
[0061] 4 is a scanning electron microscope image showing an exemplary device structure 400 being fabricated using a method according to one embodiment of the present invention. Device structure 400 comprises a photonic crystal structure 413 that includes a plurality of Si rods 414 in an outer region 422 of photonic crystal structure 413 and a plurality of InP rods 419 in a central region 420 of photonic crystal structure 413. The plurality of InP rods 419 are fabricated by replacing the Si rods in central region 420 of photonic crystal structure 413.
[0062] Because an oxide layer covers the photonic crystal structure 413, the rods 414 and 419 can only be seen in shadow.
[0063] FIG. 5 shows a flow chart of method steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
[0064] In step 510, a wafer, particularly a silicon-on-insulator wafer, containing a layer of a first material is provided.
[0065] In step 520, the layer of first material is patterned, for example, by lithography and etching, thereby forming a photonic crystal structure.
[0066] In step 530, the photonic crystal structure of the first material is encapsulated with a third material, in particular an oxide.
[0067] In step 540, a portion of the third material is selectively removed in the central portion of the photonic crystal structure, forming a window, or in other words, an opening, through the oxide to the first material.
[0068] In step 550, the first material is partially and selectively removed through a window in the central portion or central region of the photonic crystal structure. This creates a hollow template or cavity structure of a third material. However, the first material is not completely removed; a portion of the first material remains within the template structure and forms a seed structure for subsequent growth of one or more second materials.
[0069] In step 560, one or more second materials are grown within the template structure from seeds of the first material by selective epitaxy, resulting in the first material being replaced within a central portion of the photonic crystal structure with one or more of the second materials.
[0070] In step 570, the seed structure of the first material may be removed, for example by etching. Whether this step is useful depends on the respective design of the semiconductor structure and the respective post-processing.
[0071] In step 580, electrical contacts are provided to the structures of the second material formed within the template structures of the third material.
[0072] It should be noted that step 580 may be followed by further processing steps as necessary to obtain the final device structure as desired.
[0073] While illustrative examples are given above, it will be recognized that the basic fabrication steps described above may be used to produce semiconductor structures of other materials, shapes, and sizes. Materials and processing techniques may be selected as needed for a given embodiment, and appropriate choices will be readily apparent to those skilled in the art.
[0074] Although specific examples have been described above, numerous other embodiments are conceivable. The seed surface for growing the semiconductor structure may preferably be a crystalline seed surface, but may also be provided by an amorphous surface according to other embodiments. If the seed has a well-defined crystal orientation, and if the seed's crystal structure reasonably matches the crystal orientation of the growing crystal (e.g., a III-V compound semiconductor), the growing crystal can adopt this orientation. If the seed is amorphous or has no well-defined crystal orientation, the growing crystal will be single crystalline, but its crystal orientation will be random.
[0075] The disclosed semiconductor structures and circuits may be part of a semiconductor chip. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with surface interconnects or buried interconnects, or both). In either case, the chips may be integrated with other chips or discrete circuit elements or other signal processing devices, or a combination thereof, as part of an intermediate product such as a motherboard, or as part of a final product. The final product may be any product that includes integrated circuit chips.
[0076] The following definitions and abbreviations should be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a component, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or inherent to such component, mixture, process, method, article, or device.
[0077] As used herein, the articles "a" and "an" preceding an element or component are not intended to be limiting with respect to the number of instances (i.e., frequency of occurrence) of the element or component. Thus, "a" or "an" should be read to include one or at least one, and the singular form of an element or component also includes the plural unless the number is clearly intended to be singular.
[0078] As used herein, the term "quantum well" is a non-limiting term and does not refer exclusively to quantum well embodiments, but can encompass all possible quantum light-emitting systems such as quantum dots and quantum wires.
[0079] As used herein, the term "invention" or "present invention" is an open-ended term and does not refer to any single embodiment of a particular invention, but encompasses all possible embodiments as described in the specification and claims.
[0080] The descriptions of various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. 1. A method for fabricating a semiconductor structure, comprising: Fabricating a photonic crystal structure of a first material; selectively removing the first material within a central portion of the photonic crystal structure; encapsulating the photonic crystal structure of the first material with a third material; selectively removing a portion of the third material in the central portion of the photonic crystal structure to provide a window in the first material; selectively removing portions of the first material through the windows, thereby creating template structures of the third material, with remaining portions of the first material forming seed structures for the one or more second materials; selectively removing the first material in the central portion of the photonic crystal structure, replacing the first material in the central portion of the photonic crystal structure with one or more second materials by selective epitaxy; replacing the first material with the one or more second materials, including growing the one or more second materials from the seed structure within the template structure of the third material; A method comprising:
2. manufacturing the photonic crystal structure, providing a wafer including a layer of the first material; patterning the layer of the first material, thereby producing the photonic crystal structure of the first material; The method of claim 1 , comprising:
3. 3. The method of claim 2, wherein the wafer is a silicon-on-insulator wafer comprising a silicon layer on an insulating layer.
4. 3. The method of claim 2, wherein replacing the first material with the one or more second materials comprises growing the one or more second materials laterally across the wafer.
5. 5. The method of claim 4, further comprising growing the one or more second materials with a predetermined doping profile in the lateral direction of the wafer.
6. 5. The method of claim 4, further comprising growing two different second materials laterally across the wafer, thereby forming one or more lateral heterojunctions.
7. The method of claim 1 , wherein selectively removing the central portion of the first material through the window comprises performing a selective etch of the first material.
8. The method of claim 1 , wherein the photonic crystal structure of the first material comprises a plurality of rods of the first material.
9. The method of claim 1 , further comprising removing the seed structure of the first material after growing the one or more second materials within the template structure.
10. The method of claim 1 further comprising providing an electrical contact to the one or more second materials.
11. The method of claim 2 , wherein patterning the first material comprises performing an etch based on HBr chemistry.
12. 10. The method of claim 1, wherein growing the one or more second materials is performed by one of metalorganic chemical vapor deposition (MOCVD), atmospheric pressure CVD, low pressure or reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy (MBE), atomic layer deposition (ALD), and hybrid vapor phase epitaxy.
13. The method of claim 1 , wherein the one or more second materials are optically active materials.
14. 10. The method of claim 1, wherein the one or more second materials are selected from the group consisting of InP, InGaAs, AlGaAs, GaAs, GaN, InGaN, AlGaN, ternary or quaternary alloys thereof, Group II-VI semiconductors, and Group IV semiconductors.
15. The method of claim 1 , wherein the first material is silicon.
16. The method of claim 1 , wherein the third material from the seed structure is a dielectric material, an oxide.
17. An optical resonator, a semiconductor substrate; an insulating layer on the semiconductor substrate; a photonic crystal structure on the insulating layer, the photonic crystal structure forming a gain structure and a photonic mirror, the photonic crystal structure including a first material in an outer portion of the photonic crystal structure and one or more second materials in a central portion, the one or more second materials being epitaxial semiconductor materials forming the gain structure disposed in a plane parallel to a surface of the substrate; An optical resonator comprising:
18. 18. The optical resonator of claim 17, wherein the first material is silicon and the one or more second materials are selected from the group consisting of InP, InGaAs, AlGaAs, GaAs, GaN, InGaN, AlGaN, ternary or quaternary alloys thereof, II-VI semiconductors, and Group IV semiconductors.
19. 20. The optical resonator of claim 17, wherein the one or more second materials comprise a predetermined doping profile laterally across the substrate.
20. 18. The optical resonator of claim 17, wherein the central portion comprises two different semiconductor materials that form a heterojunction in a plane parallel to a surface of the substrate.
21. 18. The optical resonator of claim 17, wherein the photonic crystal structure is a one-dimensional, two-dimensional, or three-dimensional photonic crystal lattice.
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