III-nitride devices with depletion layers

Abstract

This specification describes a lateral III-N (e.g., GaN) device having a III-N depletion layer in which the III-N material is formed with an N-polar orientation. The III-N device has a III-N layer structure including a III-N channel layer between a III-N barrier layer and a p-type III-N depletion layer. A 2DEG channel is formed in the III-N channel layer. The III-N element includes source and drain electrodes electrically connected to the 2DEG channel and a gate electrode between the source and drain electrodes, with the gate overlying the III-N layer structure. The p-type III-N depletion layer includes a first layer between the gate and drain electrodes, and the p-type III-N depletion layer is electrically connected to the gate electrode and electrically insulated from the source and drain electrodes.

Description

[Technical Field]

[0001] The disclosed technology relates to semiconductor devices, particularly III-nitride transistors and switches. [Background technology]

[0002] Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs, and insulated gate bipolar transistors (IGBTs), are fabricated using silicon (Si) semiconductor materials. More recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their superior properties. III-nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying large currents, supporting high voltages, and offering very low on-resistance and fast switching times. The term device is used generically for any transistor, switch, or diode when there is no need to distinguish between them.

[0003] FIG. 1 shows a cross-sectional view of a group III-polar (i.e., Ga-polar) lateral III-N device 100. The device 100 has a source contact 21, a drain contact 22, a gate contact 23, and access regions 82 and 83. As used herein, the "access region" of the device refers to the two regions between the source and gate contacts and between the gate and drain contacts of the device, i.e., regions 82 and 83 in FIG. 1. Region 82, the access region on the source side of the gate, is typically referred to as the source-side access region, and region 83, the access region on the drain side of the gate, is typically referred to as the drain-side access region. As used herein, the "gate region" 81 of the device refers to the portion of the transistor between the two access regions 82 and 83 in FIG. 1. The gate region of the device refers to the portion of the device's layers and materials within or adjacent to the gate region 81 of the device, in which the electric field is modulated by the application of a gate voltage to modulate the channel conductivity in the gate region of the device. The device channel refers to the conductive region that serves as the device's current path between the source and drain contacts when the device is biased in the on-state. The source contact 21 and the drain contact 22 are electrically connected to a lateral two-dimensional electron gas (2DEG) channel 19 (shown by a dashed line in FIG. 1 ) induced in the III-N channel layer 12 adjacent to the interface between the III-N barrier layer 13 and the III-N channel layer 12, which serves as the device channel. The III-N material structure of the device 100 includes a III-N buffer layer 11 formed on a suitable substrate 10. The III-N channel layer 12 is formed on the III-N buffer layer, and the III-N barrier layer 13 is formed on the III-N channel layer 12. The III-N barrier layer 13 has a bandgap larger than that of the III-N channel layer 12. The source contact 21, the drain contact 22, and the gate contact 23 are all formed on the surface of the III-N material structure opposite the substrate. An insulating layer 18 is formed on the surface of the III-N material structure between the source 21 and the drain 22.If device 100 is a depletion-mode device, a portion of insulator layer 18 can be formed between gate contact 23 and the top of the III-N material structure, as shown in FIG. 1 . Device 100 includes a field plate 26 that extends over insulator layer 18 toward drain 22 in drain-side access region 83 and is connected to gate 23. The field plate 26 can help manage the electric field profile within the drain-side access region during device operation. However, when field plate 26 is the primary method used to control the electric field, high electric field peaks can occur at the corners of the field plate, resulting in poor electric field uniformity across the entire drain-side access region. As a result, a large gate-drain spacing is required to fabricate a reliable III-N transistor such as device 100.

[0004] High-voltage Ga-polar III-N transistors, such as device 100 in Figure 1, are beginning to be commercialized, but thus far, designing and fabricating III-N transistors with a figure of merit has proven challenging. To accelerate market adoption, design improvements are needed to improve device size, efficiency, and power characteristics. Summary of the Invention

[0005] Described herein are lateral III-N (e.g., GaN) devices having a III-N depletion layer (also called a charge compensation layer) in which the III-N material is formed in an N-polar orientation. The device structure can be configured to have a stable threshold voltage, low leakage current, and high breakdown voltage, while maintaining a small gap between the gate and drain, ensuring low device on-resistance. Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will be apparent from the description, drawings, and claims.

[0006] In a first embodiment, a III-N device has a III-N layer structure including a III-N channel layer between a III-N barrier layer and a p-type III-N depletion layer. The III-N channel layer includes a 2DEG therein. The III-N device includes source and drain electrodes, each electrically connected to the 2DEG channel, and a gate electrode between the source and drain electrodes, the gate being above the III-N layer structure. The p-type III-N depletion layer has a first portion between the gate and drain electrodes, the p-type III-N depletion layer being electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.

[0007] In a second embodiment, a transistor has an N-polar III-N layer structure. The N-polar layer structure has a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor has a source electrode, a drain electrode, and a gate electrode between the source and drain, where the gate is on the III-N layer structure and the p-type III-N layer is electrically connected to the gate electrode. The transistor further has a 2DEG channel in the III-N channel layer, and the N-polar III-N layer structure is configured so that the 2DEG channel extends continuously from the source electrode to the drain electrode when the gate is biased at 0 V relative to the source.

[0008] In a third embodiment, a transistor has a III-N layer structure including a III-N channel layer between a III-N barrier layer and a p-type III-N depletion layer, the III-N channel layer having a 2DEG channel formed therein. The transistor has source and drain electrodes electrically connected to the 2DEG channel, and a gate electrode between the source and drain, the gate being on the III-N layer structure. A first portion of the p-type III-N depletion layer is electrically connected to the gate electrode, and a second portion of the p-type III-N depletion layer is electrically connected to the drain electrode, with the first and second portions being electrically isolated from each other.

[0009] In a fourth embodiment, a III-N device includes a III-N layer structure including a III-N channel layer and a 2DEG channel therein, a III-N barrier layer below the III-N channel layer, and a p-type III-N layer above the III-N channel layer. The device further includes a source electrode, a drain electrode, and a gate electrode between the source and drain, the gate being above the III-N layer structure and electrically connected to the p-type III-N layer. The p-type III-N layer has a first portion between the gate and drain electrode. The III-N device has a negative threshold voltage, and the III-N device is configured such that when the gate is biased with respect to the source electrode at a negative voltage greater than a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode, and when the gate is biased with respect to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer depletes holes in the device region between the gate and drain electrode.

[0010] Each of the electronic devices and transistors described herein can include one or more of the following features: The device can be an N-polar device with a III-N barrier layer between the III-N channel layer and the III-N buffer layer; The device can have a dopant concentration in the p-type III-N depletion layer such that the p-type doping areal density in the p-type III-N layer is in the range of 10-120% of the sheet charge areal density of mobile charges in the 2DEG channel; The device can have an Al layer between the p-type III-N depletion layer and the III-N channel layer; x Ga 1-x N layer, x is 0.5 to 1, and Al x Ga 1-x The thickness of the N layer is 0.5 nm to 5 nm. The device can have an n-type GaN layer between the gate electrode and the p-type III-N depletion layer. The device can have a second Al layer between the n-type GaN layer and the p-type III-N depletion layer. x Ga 1-x N layer, x is 0.5 to 1, and Al x Ga 1-xThe N layer has a thickness of 0.5 nm to 5 nm. The gate electrode can have a field plate, and the field plate can extend at least partially over a first portion of the p-type III-N depletion layer. The drain electrode can have a field plate, and a portion of the field plate can extend at least partially over the first portion of the p-type III-N depletion layer. The device can include multiple p-type layers above the III-N channel layer, each layer being Al. x Ga 1-x Separated by N layers, x is 0.5 to 1, and Al x Ga 1-x The N layer has a thickness of 0.5 nm to 5 nm. The device can be configured such that when the gate is biased above a first minimum voltage and the drain electrode is biased above a second minimum voltage, the p-type III-N layer depletes holes in a region of the device between the gate and drain electrodes. The first minimum voltage can be less than -5 V and the second minimum voltage can be greater than 5 V.

[0011] As used herein, the term Group III nitride or Group III-N materials, layers, devices, etc. refers to materials having the stoichiometric formula B w Al x In y Ga z III-N refers to a material or element composed of a III-N compound semiconductor material, where w+x+y+z is approximately 1 and 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1. III-N materials, layers, or devices can be formed or prepared either by direct growth on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growing them on a suitable substrate, peeling them off from the original substrate, and bonding them to another substrate.

[0012] As used herein, two or more contacts or other items, e.g., conductive channels or components, are said to be "electrically connected" when they are connected by a material that is sufficiently conductive to ensure that the electrical potential at each of the contacts or other items is the same, e.g., intended to always be approximately the same under any bias conditions.

[0013] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent significant current, such as a current greater than 0.001 times the operating current during normal conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component is blocking a voltage applied to it, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices with off-currents greater than this value exhibit high losses and low efficiency and are typically unsuitable for many applications, particularly power switching applications.

[0014] As used herein, a "high voltage device," e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300 V or more, about 600 V or more, or about 1200 V or more, and when the device is on, it has an on-resistance (R) that is sufficiently low for the application in which the device is used. ON ), e.g., have sufficiently low conduction losses when substantial current passes through the device. A high-voltage device is capable of blocking voltages at least equal to the high-voltage source or maximum voltage in the circuit in which it is used. A high-voltage device may block 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltages required by the application. In other words, a high-voltage device is capable of blocking voltages between 0V and at least V max It can block all voltage between max is the highest voltage that can be supplied by the circuit or power supply, and V maxis, for example, 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltage as required by the application. For bidirectional or four-quadrant switches, the blocking voltage can be any polarity less than some maximum value when the switch is off (±V max , e.g., ±300V, ±600V, ±1200V, etc.), current can be in either direction when the switch is on.

[0015] As used herein, a "III-N device" refers to a device based on or essentially consisting of III-N materials, including III-N heterostructures. III-N devices can be designed to operate as transistors or switches, with the state of the device controlled by a gate terminal, or as two-terminal devices that block current in one direction and conduct current in the other direction without a gate terminal. III-N devices can be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., when the voltage on the gate relative to the source is less than the device threshold voltage), the device can support at least all source-drain voltages up to the high voltage in the application in which the device is used, such as 100 V, 300 V, 600 V, 1200 V, 1700 V, 2500 V, or more. When the high-voltage device is biased on (e.g., when the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), it can conduct substantial current at low on-voltages (i.e., low voltages between the source and drain terminals, or between opposing power terminals). The maximum allowable on-state voltage is the maximum on-state voltage that the device can sustain in the application in which it is used.

[0016] As used herein, a "III-polar" or "group III-polar" III-N material is a III-N material in which the group III plane (i.e., the [0 0 0 1] plane) is opposite the substrate on which the material is grown. In a "III-polar" or "group III-polar" lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the [0 0 0 1] plane (e.g., opposite the [0 0 0 -1] plane) of the III-N material.

[0017] As used herein, an "N-polar" III-N material is a III-N material whose nitrogen face (i.e., the [0 0 0 -1] face) is opposite the substrate on which the material is grown. In an "N-polar" lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the [0 0 0 -1] face (e.g., opposite the [0 0 0 1] face) of the III-N material.

[0018] As used herein, a "regrowth" III-N layer structure or III-N material structure refers to an additional material deposition process performed after a previous material deposition process. Between the subsequent growth and regrowth processes, the device can be removed from the deposition tool and the vacuum environment can be interrupted. Thus, a regrown III-N material structure may require a separate insertion into the III-N material structure deposition apparatus from the initial insertion of the III-N material structure. For example, a regrown III-N layer can be deposited after removal of at least a portion of the initial III-N material structure. Removal of the portion of the initial III-N material structure is typically performed in an environment external to the main III-N material structure deposition apparatus.

[0019] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer with respect to another layer. Thus, for example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to another layer is provided assuming that operations are performed with respect to the substrate without regard to the absolute orientation of the substrate.

[0020] The details of one or more disclosed implementations of the subject matter described herein are set forth in the accompanying drawings and the description below. Additional features and variations may also be included in the implementations. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a cross-sectional view of a prior art Ga-polar III-N device.

[0022] [Figure 2] FIG. 1 is a cross-sectional view of a depletion-mode N-polar III-N device with a III-N depletion layer.

[0023] [Figure 3A] FIG. 10 is a detailed cross-sectional view of the III-N material layer structure forming the gate connection. [Figure 3B] FIG. 10 is a detailed cross-sectional view of the III-N material layer structure forming the gate connection.

[0024] [Figure 4A] 3 is an alternative embodiment of the III-N device of FIG. 2. [Figure 4B] 3 is an alternative embodiment of the III-N device of FIG. 2. [Figure 4C] 3 is an alternative embodiment of the III-N device of FIG. 2. [Figure 4D] 3 is an alternative embodiment of the III-N device of FIG. 2. [Figure 4E] 3 is an alternative embodiment of the III-N device of FIG. 2. [Figure 4F] 3 is an alternative embodiment of the III-N device of FIG. 2.

[0025] [Figure 5A] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5B] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5C] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5D] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5E] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5F] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer. [Figure 5G] FIG. 1C is a cross-sectional view of an N-polar III-N device with a III-N depletion layer below the III-N channel layer.

[0026] [Figure 6] FIG. 1C shows a cross section of an enhancement mode N-polar III-N device with a III-N depletion layer.

[0027] [Figure 7] FIG. 1C is a cross-sectional view of a bidirectional III-N device with a III-N depletion layer. DETAILED DESCRIPTION OF THE INVENTION

[0028] Described herein are lateral III-N devices with a III-N layer used as a channel charge depletion layer (also called a charge compensation layer), where the III-N material structure of the device is grown with an N-polar (i.e., N-face) orientation, such as the [0 0 0 -1] orientation, where the bracket notation indicates the Miller index orientation of the material lattice structure. Specifically, the III-N depletion layer can partially or completely deplete some (or all) of the 2DEG channel charge in the access region of the transistor when the transistor's gate is biased relative to the source at a voltage below a certain value (e.g., -5 V, -10 V, or -20 V), but not partially or completely deplete while the transistor is biased on (e.g., when the transistor's gate is biased relative to the source at a similar voltage above 0 V). Such a structure can realize compact transistors with very high breakdown voltages while maintaining low on-resistance.

[0029] Typical III-N high electron mobility transistors (HEMTs) and related devices, such as device 100 of FIG. 1, are formed on III-nitride material grown in a III-polar (e.g., Ga-polar) orientation, such as the [0 0 0 1] (C-face) orientation, as shown in FIG. 1. That is, the source, gate, and drain contacts of the HEMT are formed on the group III face (e.g., the [0 0 0 1] face) of the III-N material layer, which is typically on the opposite side of the III-N material layer from the substrate on which the III-N layer is formed. Alternatively, III-N HEMTs can be formed on III-nitride material grown in an N-polar (i.e., N-face) orientation, such as the [0 0 0 -1] orientation. In this case, the source, gate, and drain contacts of the HEMT are formed on the N face (e.g., the [0 0 0 -1] face) of the III-N material layer. N-polar III-N materials have a polarization field in the opposite direction to group-III-polar III-N materials, thus enabling the implementation of III-N devices that cannot be fabricated using group-III-polar structures. Additionally, N-polar III-N devices have demonstrated superior electrical properties when compared to similarly sized group-III-polar devices, with lower static and dynamic on-resistances, higher current densities, and higher power densities.

[0030] III-N devices with charge depletion layers can be advantageous over N-polar III-N materials over Ga-polar III-N materials for at least the following reasons. First, when used in N-polar III-N devices, the channel depletion layer does not significantly affect the mobility and charge density of the 2DEG channel between the source and drain electrodes compared to Ga-polar III-N devices. Therefore, the 2DEG sheet resistance of N-polar III-N devices can be reduced even with the channel depletion layer formed above the 2DEG channel (e.g., less than 450 Ω / sq or less than 300 Ω / sq), which is necessary for improving device on-resistance. Second, N-polar III-N materials have high dopant ionization efficiency (e.g., the ratio between the hole concentration and the acceptor concentration in the p-type layer is 10% or more or 50% or more), which are essential for fast transient times (turn-on and turn-off) and small switching losses, as described in the following figure. 2 / Vs) and low contact resistance (e.g., 1 Ω cm 2 Less than or equal to 10 -3 Ωcm 2 Furthermore, the N-polarity material structure offers the possibility to integrate a high-voltage charge depletion module with a normally-off enhancement-mode gate module with a p-type body (as depicted in FIG. 6).

[0031] Referring to FIG. 2, an N-polar depletion-mode III-N device 200 is shown. The III-N device 200 has a III-N buffer layer 11, e.g., GaN or AlGaN, grown on a suitable substrate 10, e.g., silicon (Si), silicon carbide (SiC), sapphire, AlN, or GaN. The substrate can be, for example, electrically conductive (e.g., p-type Si), electrically semi-insulating (e.g., SiC), or electrically insulating (e.g., sapphire). The substrate can be thinned, e.g., less than 200 μm, to improve heat dissipation. The substrate can have a lattice constant and / or thermal expansion coefficient similar (e.g., within 10%) or different from that of any material layer in the III-N structure. If the lattice constants and / or thermal expansion coefficients between the substrate and the III-N layer are different, a nucleation and / or stress relaxation management layer (not shown) can be introduced between the substrate 10 and the buffer layer 11. The substrate 10 can be either floating (i.e., no fixed potential) or grounded (i.e., the substrate potential is fixed at the same voltage as the source). In some implementations, the substrate 10 can be omitted.

[0032] The buffer layer 11 can be made insulating or substantially free of unintended n-type mobile carriers by including dislocations or point defects within the layer or by doping the layer with compensating elements such as Fe, C, and / or Mg. The buffer layer can have a substantially uniform composition throughout, or the composition may vary. For example, in some implementations, the buffer layer is compositionally graded, such as by grading the aluminum composition along a vertical axis within the buffer layer. The buffer layer 11 can be substantially thicker than any of the other III-nitride layers in the structure. For example, the buffer layer 11 can have a thickness that is at least five times, and typically at least ten times, the total thickness of the III-N layers between the buffer layer 11 and the gate 23. N-polar III-N devices can allow for thinner buffer layers 11 than Ga-polar III-N devices due to growth conditions that may result in a higher-quality nucleation layer and better dislocation management in the buffer layer 11 on a foreign substrate.

[0033] The III-N device 200 further includes a layer of, for example, Al on the III-N buffer layer 11. x Ga 1-xThe III-N back barrier layer 14 is made of GaN, and a III-N channel layer 15, for example, unintentionally doped (UID) GaN, is placed on top of the III-N back barrier layer 14. The bandgap of the III-N back barrier layer 14 is larger than that of the III-N channel layer 15. The III-N channel layer 15 has a different composition from the III-N back barrier layer 14, and the thickness and composition of the III-N back barrier layer 14 and the III-N channel layer 15 are selected so that an electron conductive layer is induced in the III-N channel layer 15. The interface between the III-N back barrier layer 14 and the III-N channel layer 15 may be abrupt. In this case, a conductive two-dimensional electron gas (2DEG) channel 19 (shown by the dashed line in FIG. 2 ) is induced in the III-N channel layer 15 adjacent to the interface between the layers 14 and 15. The compositions of the III-N back barrier layer 14 and the III-N channel layer 15 may be constant or may vary throughout. For example, layer 14 can have a first portion that is a graded AlGaN portion with increasing Al concentration (e.g., with the lowest Al concentration closest to the substrate) and a second AlGaN portion with a constant Al concentration. In another example, the III-N back barrier layer has a first portion that is n-type GaN or AlGaN and a second portion that is undoped AlGaN. The III-N back barrier layer 14 can have a first portion (near the substrate) that is an n-type III-N portion, a second portion above the first portion that is a graded III-N portion (e.g., with a graded aluminum composition), and a third portion above the second portion with a constant composition. Furthermore, the graded or n-type portion of the III-N back barrier layer 14 can be doped with Si or any other dopant to prevent hole formation. The doping concentration can be 1e11 donors / cm. 2 ~1e14 donors / cm 2 Preferably, the doping concentration is expressed as an equivalent areal density (cm -2 ) is chosen to be similar (e.g., within ±50%) to the surface charge density in the 2DEG channel.

[0034] Another portion of the III-N back barrier layer 14 can act to prevent the formation of a parasitic two-dimensional hole gas near the bottom of the back barrier layer. For example, if holes accumulate near the bottom of the back barrier, the device may suffer from parasitic leakage current and threshold voltage instability due to hole trapping. If the doping of the layer is too low, parasitic hole accumulation can occur, while if the doping is too high, parasitic electron accumulation can occur near the bottom of the back barrier layer 14. Mobile carriers (either holes and / or electrons) can accumulate near the Fermi level (e.g., E) in the band gap that is far enough away from both the valence band and the conduction band to trap excess mobile carriers. V +0.5 eV, E V +0.9 eV, E C The reduction can be achieved in the back barrier layer 14 and / or buffer layer 11 by adding impurities (e.g., carbon, other amphoteric dopants, or deep level traps) that can fix the potential (such as −0.6 eV) of the back barrier layer 14 and / or buffer layer 11 .

[0035] The back barrier layer 14 may have a thickness of 5 nm to 50 nm. The back barrier layer 14 may have a thickness of more than 15 nm. The channel layer 15 may have a thickness of 2 nm to 300 nm. The channel layer 15 may have a thickness of more than 15 nm. The thickness of the channel layer 15 is determined by the threshold voltage (V TH ) can be determined. For example, a channel layer 15 thickness less than 30 nm can result in a threshold voltage greater than -10 V. Minimizing the negative threshold voltage of a depletion-mode device is useful when used in a cascode configuration with low-voltage enhancement-mode FETs, preventing the enhancement-mode FET from entering avalanche mode or being biased outside its safe operating area during the off-state, and therefore from suffering thermal runaway during a short-circuit event. Additionally, 0.5 to 5 nm of Al X Ga 1-x An N intermediate layer (x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15. X Ga1-x The N intermediate layer can help increase polarization charge and reduce electron scattering at the interface between the III-N back barrier layer 14 and the III-N channel layer 15, improving the 2DEG channel sheet resistance. For example, the 2DEG channel sheet resistance can be between 500 Ω / sq and 150 Ω / sq. Preferably, the 2DEG channel sheet resistance is less than 400 Ω / sq.

[0036] In another example, a portion of the III-N channel layer 15 can have bulk n-type conductivity created by either impurity doping (e.g., silicon incorporation) and / or polarization doping. To achieve polarization doped n-type conductivity, the III-N channel layer 15 is compositionally graded so that the gradient of the polarization field is negative in the [000-1] direction. For example, the III-N channel layer 15 of the III-N device 200 is composed of Al y Ga 1-y In the III-N channel layer 15, y is equal to the y of the III-N back barrier layer 14 on the side adjacent to the III-N back barrier layer 14, and y decreases (e.g., continuously decreases) from the side adjacent to the III-N back barrier layer 14 toward the side opposite to the III-N back barrier layer 14. Alternatively, the III-N channel layer 15 may be formed of In y Ga 1-y N (0≦y≦1), where y increases (e.g., continuously increases) from the side closest to the III-N back barrier layer 14 to the side facing the III-N back barrier layer 14.

[0037] The III-N depletion layer 16 is formed on at least a portion of the III-N channel layer 15. Specifically, the III-N depletion layer is formed when the gate of the transistor is biased to a negative value (e.g., V GS When biased with respect to the source at a voltage lower than V = -5V, -10V, or -20V), some (or all) of the 2DEG channel charge in the access region of the transistor can be partially or fully depleted, but the transistor will not deplete beyond a certain value (e.g., V GSThe III-N depletion layer can be partially or completely undepleted while biased above 0V (=-1V, 0V, or higher than 0V). The III-N depletion layer can act as a charge compensation layer, compensating some or all of the ionized positive charge in the channel layer 15 and the AlGaN back barrier layer 14 with ionized negatively charged acceptors when the device is biased off, so that it does not affect the 2DEG charge when the device is biased on.

[0038] As shown in FIG. 2 , the III-N depletion layer 16 may overlie the channel layer in the gate region 81 and extend laterally into the drain-side access region 83 between the gate contact 23 and the drain contact 22. The III-N depletion layer includes a first end and a second end, the first end adjacent to the source contact 21, and the second end adjacent to the drain contact 22. The III-N depletion layer 16 is electrically isolated from the drain contact 22 via a lateral isolation 25. The distance from the second end of the depletion layer 16 to the drain contact 22 may be between 0.5 μm and 10 μm, preferably less than 5 μm. Optionally, a portion of the III-N depletion layer 16 may extend into the source-side access region 82. The III-N depletion layer 16 is electrically isolated from the source contact 21 via a lateral isolation 27. The distance from the first end of the depletion layer 16 to the source contact 21 may be between 0.5 μm and 10 μm, preferably less than 5 μm. The lateral isolation 25 may be the same as or different from the lateral isolation 27. For example, the lateral isolation 25 may be used to withstand a higher drain-to-gate voltage (V DG ), which can be larger than the lateral isolation 27 to support the gate-source voltage (V GS) may require a larger isolation than that required to support the III-N channel layer. The III-N depletion layer 16 may be formed across the III-N channel layer and then removed (e.g., by dry and / or wet etching) in a portion of the source-side access region 82 adjacent to the source contact 21 and in a portion of the drain-side access region 83 adjacent to the drain contact 22.

[0039] The III-N depletion layer 16 can be realized by a single III-N layer or by multiple III-N layers with varying Al compositions. The III-N depletion layer 16 can be p-type. The p-type doping can be provided by impurity incorporation (e.g., magnesium) or by polarization (e.g., a positive polarization field gradient in the [000-1] direction). The p-type doping distribution across the depletion layer 16 can have a uniform or graded profile. The depletion layer 16 can have a box profile or a delta function profile. The depletion layer 16 can have multiple repetitions of any of the above profiles.

[0040] The p-type doped III-N depletion layer 16 is 1×10 16 cm -3 Larger than 2 x 10 20 cm -3 smaller than, for example, 1×10 18 / cm -3 . The acceptor concentration can be doped with an active acceptor concentration greater than 3×10 19 cm -3 The thickness of the III-N depletion layer 16 can be lower, thereby avoiding excessive incorporation of impurities (such as carbon and hydrogen) that are detrimental to the ionization rate and hole mobility. If the III-N depletion layer 16 is p-doped with Mg, the device can be treated with a high-temperature anneal to electrically activate the Mg dopant. The III-N depletion layer 16 can have a thickness of 1 nm to 1 μm. For example, the III-N depletion layer 16 can have a thickness greater than 4 nm and less than 80 nm.

[0041] The depletion layer 16 can be designed so that when operating in the off state, the area density of ionized negative charges in the depletion layer 16 is in the range of 10% to 150% of the area density of ionized positive charges in the channel layer 15 and the AlGaN back barrier layer 14. (The ionized negative and positive charges can result in ionized acceptors, ionized donors, spontaneous and piezoelectric polarization charges, ionized deep levels, and ionized interface states.) In some embodiments, the ratio between the ionized negative charges and the ionized positive charges can be 90% to 110%. However, due to process variations and difficulties in controlling the doping density of the charge depletion layer 16, the ionized negative charges in the depletion layer 16 can be significantly smaller (e.g., less than 70% or less than 40%) or larger (e.g., more than 120%) than the ionized positive charges in the channel layer 15 and the AlGaN back barrier layer 14. The mismatch between the ionized positive and negative charges can be taken into account in the device design. Device embodiments for improving field uniformity in the case of a mismatch between ionized positive and negative charges are described below. The depletion layer 16 is connected to the source (V GS ) is sufficiently negative than a minimum value (e.g., −5 V, −10 V, or −20 V) that is less than, similar to, or greater than the device's threshold voltage. Furthermore, when the gate is biased ON (above the device's threshold voltage, e.g., 0 V) and the drain voltage exceeds a second minimum voltage (e.g., 10 V, 20 V, 30 V, 100 V, etc.), the depletion layer 16 can be partially or substantially fully ionized (depleted) in the drain-side access region 83. When the device operates in the ON-state saturation regime (linear mode), the depletion layer 16 can be partially or substantially fully ionized (depleted) in the drain-side access region 83.

[0042] A fully ionized (depleted) depletion layer 16 can block high voltages while improving the electric field uniformity within the device. The depletion layer 16 can be designed so that, when operating in the on-state, the ionized acceptors in the depletion layer 16 are neutralized by positive carriers (holes), allowing drain-source current to flow. The depletion layer 16 can be designed so that the neutralization and ionization of the depletion layer 16 is sufficiently rapid during turn-on and turn-off transitions to ensure sufficiently fast device switching times (e.g., less than 20 ns) and sufficiently low switching losses. The ionization and neutralization of the depletion layer 16 can be improved by reducing the resistivity of the depletion layer 16 and / or by reducing the contact resistance between the depletion layer 16 and the gate contact 23.

[0043] A low resistivity of the depletion layer 16 can be achieved by improving the hole mobility and by increasing the acceptor ionization efficiency (e.g., more holes for the same number of acceptors). For example, the ionization efficiency may be higher than 1%, or higher than 10%, or higher than 50%, and the hole mobility may be higher than 5 cm. 2 / Vs or 10 cm 2 High hole mobility and / or high acceptor ionization efficiency can be achieved in p-type modulation doped III-N heterostructures, e.g., the depletion layer 16 can be Al x Ga 1-x In another example, the depletion layer 16 may be formed of a thin AlN layer (where x can be high enough so that the valence band discontinuity between the III-N depletion layer 16 and the channel layer 15 is greater than the ionization energy of the p-type acceptor). x Ga 1-x N layer (0.5 to 5 nm, x may be higher than 50%, x is the thickness of the thin GaN layer 16 and the thin Al x Ga 1-xIn another example, the depletion layer 16 can be formed by a thin GaN layer (0.5-5 nm) deposited on a thin AlN layer (which can be made high enough so that the valence band discontinuity between the AlN layer and the depletion layer is greater than the ionization energy of the p-type acceptor). x Ga 1-x The III-N heterostructure can be formed by periodically repeating a thin GaN layer deposited on an N layer (superlattice), where x can be higher than 50%. The p-type doping distribution in the III-N heterostructure can have a uniform profile, a box profile, or a delta function profile. Each III-N layer comprising the p-type modulation doping superlattice can have a thickness of 0.1 nm to 10 nm. Preferably, the Al in the p-type modulation doping superlattice x Ga 1-x The N portion can have a thickness of less than 3 nm or less than 2 nm. For example, a p-type modulation doped III-N heterostructure can have a thin Al x Ga 1-x A thin Al layer is deposited on the N layer, a thin p-type GaN layer, and the III-N channel layer 15. x Ga 1-x A two-dimensional hole gas (2DHG) is formed at the interface between the III-N channel 15 and the first thin AlGaN layer, and p-type GaN has a high ionization efficiency (higher than 90%).

[0044] Additionally, a 0.5-5 nm AlGaN or AlN intermediate layer (shown as layer 34 in FIG. 3A) can be disposed between the III-N depletion layer 16 and the channel layer 15. This AlGaN or AlN intermediate layer can help prevent unwanted Mg diffusion from the Mg doping of the p-type III-N depletion layer into the III-N channel layer 15. This AlGaN or AlN intermediate layer can also function as a selective etch stop layer to improve the control and precision of the etching process used to remove the III-N depletion layer 16 in the drain-side and source-side access regions.

[0045] Alternatively, returning to FIG. 2 , the p-type of the III-N depletion layer 16 can be achieved by polarization-induced doping (e.g., by grading the bandgap of the layer without introducing dopant impurities). In this case, the aluminum or indium composition of the III-N depletion layer 16 is graded to induce a bulk negative polarization charge that can attract holes, making the III-N depletion layer 16 p-type. The graded III-N depletion layer 16 has a composition that grades (e.g., continuously grades) from the side adjacent to the III-N channel layer 15 to the opposite side of the III-N channel layer 15. The composition of the graded p-type III-N depletion layer 16 is selected so that the gradient of the polarization field is positive in the [000-1] direction. For example, the III-N depletion layer 16 of the III-N device 200 is Al y Ga 1-y N (0≦y≦1), where y is equal to the y of the III-N channel layer 15 on the side adjacent to the III-N channel layer 15, and y increases (e.g., continuously increases) from the side adjacent to the III-N channel layer 15 toward the side opposite to the III-N channel layer 15. Alternatively, the III-N depletion layer 16 may be formed of In y Ga 1-y N (0≦y≦1), where y decreases (for example, continuously decreases) from the side close to the III-N channel layer 15 toward the side facing the III-N channel layer 15.

[0046] The gate contact 23 can be in direct contact with the III-N depletion layer 16. Alternatively, to improve the electrical connection between the gate contact 23 and the III-N depletion layer 16, an optional III-N contact layer 17 can be used, e.g., an n-type GaN layer formed at least on the III-N depletion layer 16 in the gate region 81 of the device 200 between the gate 23 and the III-N depletion layer 16. The III-N contact layer 17 can have a thickness of 10 nm to 1 μm. The III-N contact layer 17 can be doped with a donor, e.g., silicon. The doping concentration of the III-N contact layer can be 1×10 16 cm -3The thickness and net n-type doping of the III-N contact layer 17 can be high enough so that the layer 17 is not completely depleted of free electrons by the III-N depletion layer 16; for example, the thickness can be greater than 50 nm and the average n-type doping can be greater than 1×10. 18 cm -3 The n-type doping can be as high as 1×10 19 cm -3 It can be made larger.

[0047] Alternatively, for ease of manufacturability, the III-N contact layer 17 can be, for example, a p-type GaN layer. The thickness of the p-type III-N contact layer 17 can be 10 nm to 1 μm. The III-N contact layer 17 can be doped with a donor, for example, magnesium. The doping concentration of the III-N contact layer can be 1×10 16 cm -3 The thickness and net p-type doping of III-N contact layer 17 can be high enough to result in a hole concentration greater than 1×10. The thickness and net p-type doping of III-N contact layer 17 can be high enough so that layer 17 has a p-type doping density greater than the p-type doping density of III-N depletion layer 16. For example, the thickness of film 17 can be greater than 50 nm, with an average p-type doping of 1×10. 18 cm -3 The p-type doping can be greater than 1×10 19 cm -3 It can be made larger.

[0048] The III-N contact layer 17 is removed in portions of the source-side and drain-side access regions. The III-N contact layer can be left in place within the gate region 81. The length of the gate region 81 can be 10 nm to 10 μm, e.g., 0.5 μm to 3 μm. The gate aspect ratio can be defined as the ratio between the length of the gate region 81 and the thickness of the III-N channel 15. The gate aspect ratio can be sufficiently large, e.g., greater than 5, to prevent the drain-induced barrier reduction (DIBL) parasitic effect under high drain bias conditions. The process for removing the III-N contact layer 17 can be selected to substantially minimize damage to the exposed surfaces of the III-N depletion layer 16 in the source-side and drain-side access regions 82 and 83. The removal process can be performed by means of dry etching techniques, wet etching techniques, or a combination of dry and wet etching techniques. The removal process can be non-selective or selective. Thin Al x Ga 1-x The N portion can be inserted as an etch stop layer between the III-N contact layer 17 and the III-N depletion layer 16. After removing the III-N contact layer 17, chemical and thermal surface treatments can be performed to recover the surface of the III-N depletion layer 16.

[0049] The III-N depletion layer 16 is removed in portions of the source-side and drain-side access regions. The process for removing the III-N depletion layer 16 can be selected to substantially minimize damage to the surface of the exposed III-N material in the source-side and drain-side access regions 82 and 83. The removal process can be performed by means of dry etching techniques, wet etching techniques, or a combination of dry and wet etching techniques. For example, a low-power dry etch can be used to remove the bulk of the III-N contact layer 17 and the III-N depletion layer 16, followed by an acid wet etch process to remove the remaining portion of the III-N depletion layer 16. The removal process can be non-selective or selective. Thin Al x Ga 1-x The N layer can be inserted between the III-N depletion layer 16 and the III-N channel layer 15 as an etch stop layer.

[0050] Alternatively, the process of removing the III-N depletion layer 16 can include partial removal of the III-N channel layer 15. Partial removal of the III-N channel layer 15 can be performed by overetching the III-N depletion layer 16 in successive dry etching steps or by a combination of multiple dry and wet etching steps. The etching rate of the III-N depletion layer 16 can be less than that of the III-N channel layer 15, and the process of removing the III-N depletion layer 16 can result in substantial removal of the III-N channel layer in portions of the source-side and drain-side access regions due to insufficient overetching control. For example, before the etching process, the III-N channel layer 15 can have a thickness of 50 nm, and in the region where the III-N depletion layer 16 has been removed, the overetching of the III-N channel layer 15 can be 10 to 30 nm. In the region where the III-N depletion layer has been removed, the thickness of the remaining III-N channel layer 15 can exceed 20 nm. More than 50% of the thickness of the III-N channel layer can be removed during the over-etching process of the III-N depletion layer 16.

[0051] Alternatively, the III-N depletion layer 16 and III-N contact layer 17 can be selectively regrown by means of selective area regrowth, which can avoid the need for a removal process.

[0052] In the gate region 81, a gate contact 23 (gate electrode) is formed on the III-N contact layer 17. The gate contact 23 can be formed from a suitable conductive material, such as a metal stack (Al, Ti / Al, Ti / Al / Ni / Au, Ni / Au, etc.), to achieve ohmic contact with the III-N contact layer 17. It can be deposited by metal evaporation, sputtering, chemical vapor deposition, or various atomic layer deposition (ALD) techniques. After depositing the gate contact 23, a post-gate deposition annealing process can be optionally performed. The post-gate deposition annealing can be performed in a gas atmosphere containing oxygen or forming gas (H2+N2). The post-gate deposition annealing temperature can be higher than 300°C or even higher than 400°C. Finally, the gate contact 23 can be used as an etching mask to etch the III-N contact layer 17, so that the III-N contact layer 17 remains directly under the gate contact 23 but is etched away.

[0053] The detailed III-N material structure of region 30, indicated by the dashed line region in FIG. 2, is explained in more detail in FIGS. 3A and 3B. This region illustrates alternative methods and material structures that can be used to implement the electrical connection of the gate contact 23 to the III-N depletion layer 16. A first method of forming the electrical connection of the gate contact 23 to the III-N depletion layer 16 can be implemented using a tunnel junction contact between the III-N depletion layer 16 and the III-N contact layer 17, and an ohmic contact between the III-N layer 17 and the gate contact 23, as shown in FIG. 3A. The tunnel junction contact is implemented by forming a highly doped p-type GaN region 31 (i.e., p++ GaN) (e.g., 5×10 ) on top of the III-n depletion layer 16. 19 cm -3 a thickness of 2 nm to 1 μm having a doping density of more than 5×10 19 cm -3By introducing a thickness of 2 nm to 50 nm having a doping density exceeding [the reference value], it can be formed. The doping density in the highly doped region should be such that the depletion width in the junction formed between the III-N contact layer 17 and the III-N depletion layer 16 is several nanometers or less (for example, less than 10 nm), and thus, it should be comparable to the electron tunneling distance. Here, electrons can tunnel from the conduction band of the III-N contact layer 174 and recombine with holes in the valence band of the III-N depletion layer 16, creating an electrical connection between the gate contact 23 and the III-N depletion layer 16.

[0054] As shown in FIG. 3A, the quality of the tunnel junction in the N-polarity III-N material can be further improved, for example, by inserting a thin Al y Ga 1-y N (0 < y ≤ 1) layer 32 (such that the interface region becomes p++ GaN / Al y Ga 1-y N / N++ GaN). In the N-polarity III-N material, the polarization charges of the inserted thin Al y Ga 1-y N layer 32 further increase the accumulation of holes at the interface with the III-N depletion layer 16 and the accumulation of electrons at the interface with the III-N contact layer 17, facilitating the tunneling and recombination processes. The thickness of the thin Al y Ga 1-y N layer 32 can be 0.5 nm to 5 nm, preferably 0.5 nm to 2 nm, to facilitate tunneling. The thin Al y Ga 1-y N layer 32 can also act to suppress the diffusion of Mg (p-type dopant) in the III-N depletion layer 16 into the III-N contact layer 17. As a result, a sharper doping profile is obtained, and the junction between the III-N depletion layer 16 and the III-N contact layer 17 is improved. Preferably, Al y Ga 1-yThe AlN film 32 has a high aluminum composition, which improves (i) the Mg diffusion barrier, (ii) increases the polarization charge and carrier accumulation at the tunnel junction, resulting in better tunnel junction contact resistance. The aluminum composition (y) may be greater than 50% (i.e., y > 0.5), for example greater than 75%, for example greater than 90%, for example greater than 95%. The aluminum composition may be approximately 100% (i.e., y = 1) such that the layer is AlN (e.g., unintentionally doped with Ga). Further, an In z Ga 1-z N (0 < z ≦ 1) thin layer can be inserted between the Al y Ga 1-y N layer and the N++ layer at the bottom of the III-N contact layer 17 and can be used to further improve the electron accumulation at the tunnel junction interface. An In z Ga 1-z compound in the N (0 < z ≦ 1) layer can exceed 5% (i.e., z > 0.05). The source contact metal stack can be Al, Ti / Al, Ti / Al / Ni / Au, etc.

[0055] Another method for forming the electrical connection of the gate contact 23 to the III-N depletion layer 16 can be achieved by omitting the deposition of the III-N contact layer 17 and allowing the gate contact 23 to directly contact the III-N depletion layer 16 (as shown in Figure 3B). Wet etching and surface cleaning techniques can be used to ensure that the surface of the III-N depletion layer 16 is smooth and damage-free. High-temperature annealing can be performed to improve the surface morphology and composition. High-temperature annealing can be performed in nitrogen / oxygen (N2 / O2), nitrogen / ammonia (N2 / NH3), or forming gas (N2 / H2). The temperature ranges from 300°C to 1000°C, preferably 700°C to 900°C. A gate metal stack can be deposited to form a physical ohmic contact to the III-N depletion layer 16. The gate metal stack can be a high work function metal to ensure ohmic contact to the III-N depletion layer 16 (e.g., Al, Ti / Al, Pd, Pt, Ni / Au, etc.). The contact between the gate metal and the III-N depletion layer 16 can be achieved by a thin highly doped p-type layer (e.g., 5×10) on top of the III-N depletion layer 16. 19 cm -3 This can be improved by introducing a layer (2 nm to 50 nm thick) with a doping density greater than 1000 nm.

[0056] Source and drain contacts 21 and 22 (i.e., source and drain electrodes) are located on either side of the gate contact 23. The source 21 and drain 22 form ohmic contacts with the device 2DEG channel 19 formed in layer 15. The source and drain contacts 21 and 22 can be formed by metal stacks (Al, Ti / Al, Ti / Al / Ni / Au, Ni / Au, etc.) and / or n-type semiconductor regrowth. The source and drain contact the channel layer 15. The III-N channel layer 15 can be at least partially recessed to improve the contact of the source and drain electrodes to the 2DEG channel 19. Portions of the channel layer 15 below the source and drain contacts can be doped n-type, or additional n-type layers can be inserted between the source and drain contacts and the channel layer 15 to improve the electrical contact of the source and drain metals to the 2DEG. The n-type semiconductor layer below the source and drain contacts can be selectively regrown. The regrown n-type semiconductor can be 1×10 17 cm -3 Larger, preferably 1 x 10 19 cm -3 The metal stack can be Al, Ti / Al, Ti / Al / Ni / Au, etc. The contacts can be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact processes can also be used, including sputtering and dry etching processes.

[0057] An insulator layer 18 (e.g., a SiN layer) can be grown or deposited conformally over the top surfaces of the III-N contact layer 17 and the III-N depletion layer 16, at least in the source-side access region 82 and the drain-side access region 83. The insulator 18 can be, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon nitride (Si x N y ), Al 1-x Si x N, Al 1-x Si x O, Al1-x Si x The insulator 16 may be formed from or include N, Nb, NbO, or any other wide-bandgap insulator. The insulator 16 can be deposited either ex-situ (e.g., using a tool different from that used for the growth of the underlying III-N material) or in-situ (i.e., using the same tool and during the same growth session used for the growth of the underlying III-N material). In the case of in-situ deposition, the device surface is not exposed to air and, therefore, is not exposed to oxidizing elements (e.g., oxygen) and undesirable impurities / contaminants. Therefore, in-situ deposition can result in superior interface quality (e.g., lower interface states, lower fixed charges, and / or lower trapped charges) compared to ex-situ deposition, resulting in superior electrical performance and a better electric field profile. In the case of ex-situ deposition, the III-N material structure surface can be treated with chemical and thermal processes to improve surface quality (e.g., lower interface states, lower fixed charges, and / or lower trapped charges) before deposition of the insulator layer 18. The insulator layer 18 may perform the functions of passivation, neutralizing active trap states or fixed charges, and / or preventing charge trapping and / or current leakage in surface states, and / or increasing lateral breakdown between the gate and drain contacts.

[0058] The method for forming the device 200 of FIG. 2 is as follows. An N-polar III-N material structure is formed. Forming the N-polar III-N material structure includes forming a III-N buffer layer 11 on a suitable substrate 10, such as a miscut sapphire substrate. The III-N buffer layer 11 can consist of forming a thin N-polar GaN nucleation layer on the substrate and a carbon-doped GaN buffer layer on the nucleation layer. Next, a III-N back barrier layer 14 is formed on the buffer layer. A III-N channel layer 15 is formed on the III-N back barrier layer 14, and a two-dimensional electron gas (i.e., a 2DEG layer) 19 is induced at the interface between layers 14 and 15. Next, a p-type III-N depletion layer 16 is formed on the III-N channel layer 15, and an n-type III-N contact layer 17 is formed on the III-N depletion layer 16. The interface between the III-N depletion layer 16 and the III-N contact layer 17 can be formed via a tunnel junction. Forming the tunnel junction is achieved by forming a p++ / AlN / n++ material layer structure on top of the III-N depletion layer 16, e.g., a 20 nm thick p++ layer (e.g., 2×10 19 cm -3 ) doped with magnesium at a concentration of 1.5 nm; forming a thin AlN or AlGaN intermediate layer (e.g., 1.5 nm thick) on the p++ layer; forming an n++ layer (e.g., 2×10 19 cm -3Next, forming the device 200 includes removing the III-N contact layer 17 to define the gate region 81 and removing the III-N depletion layer 16 in portions of the drain-side access region 83 and the source-side access region 82 of the device, for example, by dry etching, to expose the surface of the III-N material structure. Next, forming the device includes annealing the device at high temperature to electrically activate the p-type III-N depletion layer 16. Next, ohmic contacts are formed for the source 21 and drain 22 by depositing a metal stack including aluminum (Al), Ti / Al, etc. A gate metal stack 23 (e.g., Ti / Al) is formed in the gate region 81 of the device to form a transistor. Finally, an insulator layer 18 can be formed on the surface of the III-N layer.

[0059] 2 operates as follows: when the gate 23 is biased relative to the source 21 at a voltage greater than the threshold voltage of the device (e.g., 0 V), there is 2DEG charge below the gate 23 in the gate region, and therefore there is a continuous 2DEG from the source 21 to the drain 22. When a positive voltage is applied to the drain 22, electrons flow from the source 21 through the continuous 2DEG channel 19 to the drain 22. Conventional current flows from the drain to the source, and the device is considered to be on.

[0060] When the gate 23 is biased relative to the source 21 at a voltage higher than the device's threshold voltage, the III-N depletion layer remains at substantially the same potential as the gate contact 23. As the voltage on the gate-source voltage gradually decreases to a negative voltage, a positive electric field is generated from the portion of the 2DEG immediately below the III-N depletion layer 16. Holes are gradually drawn out of the depletion layer 16, and the ionized negative charges in the III-N depletion layer 16 gradually deplete electrons from the 2DEG. When the gate 23 is biased relative to the source 21 at a voltage lower than a certain value (e.g., −5 V, −10 V, −20 V), the depletion layer 16 is fully ionized (fully depleted). When the gate 23 is biased relative to the source 21 at a voltage lower than the device's threshold voltage, there is no 2DEG below the charge depletion layer 16 (including the region 81 below the gate), and therefore the 2DEG is discontinuous between the source 21 and the drain 22. As mentioned above, the doping levels, Al composition, and layer thicknesses are selected to achieve the desired full p-type ionization voltage and desired threshold voltage of the device. When the device is used in a cascode configuration, the device's threshold voltage can be designed to be lower, in absolute value, than the breakdown voltage of a low-voltage normally-off common-source device. For example, the threshold voltage can be higher than -30 V (i.e., close to 0 V), higher than -20 V, or higher than -10 V. When the gate voltage relative to the source is lower than the full ionization voltage relative to layer 16 and lower than the device's threshold voltage, a subsequent increase in the drain voltage causes charge imaging from regions in or near the drain 22 to the gate 23. Because the III-N depletion layer 16 is fully depleted, it no longer remains at the gate potential and can withstand the voltage gradient. Therefore, there is a smooth transition of potential from the drain 22 to the gate 23. This results in a larger, more uniform electric field before breakdown occurs, and therefore a larger breakdown voltage than conventional HEMTs without a charge depletion layer.

[0061] In addition to improving field management and increasing breakdown voltage, N-polar III-N devices with junction-based channel depletion layers, such as device 200, can have additional advantages over conventional III-N devices, such as device 100, fabricated with industry-standard dielectric-based field plates (e.g., field plate 26). For example, III-N device 200 with channel depletion layers 16 can have a more stable threshold voltage than III-N device 100 with dielectric-based field plates. Device 200 does not contain dielectric bulk and interface traps formed during the field plate process, and in device 200, holes generated in depletion layer 16 by impact ionization can be efficiently removed by the junction gate terminal. Furthermore, when device 200 is switched in a cascode configuration and exposed to high dv / dt and / or di / dt transients, the junction gate terminal formed by junction-based III-N channel depletion layer 16 can turn on (i.e., forward bias) and clamp the gate voltage to a relatively low value (e.g., less than 4 V), thus preventing gate failure during high transients. On the other hand, in III-N device 100 with a dielectric-based field plate, when switched in a cascode configuration, exposure to high dv / dt and / or di / dt transients can cause the gate voltage to increase uncontrollably and reach relatively high values (e.g., greater than 15 V), potentially causing gate dielectric degradation such as charge trapping, leakage, and premature failure. III-N device 200 with a channel depletion layer 16 can also enable substantial improvements in electrostatic discharge (ESD) protection that cannot be easily designed into dielectric-based field plate devices such as device 100. Furthermore, III-N devices with a junction-based channel depletion layer such as device 200 can enable the design of lateral devices with very high breakdown voltages (e.g., greater than 1.2 kV, greater than 1.7 kV, greater than 3.3 kV, or greater than 6.6 kV).This is very difficult to implement in practice using lateral III-N devices with dielectric-based field plates, because the field plate structure to accommodate such a high breakdown voltage would be very long with many field plate steps.

[0062] The electric field profile within device 200 may need to be further refined. One reason for scaling is the potential for electric field peaks at abrupt discontinuities in the device structure. For example, the electric field may need to be optimized on the drain side of gate region 81. The electric field may also need to be optimized on the side of depletion layer 16 in region 83 adjacent to drain 22, where the electric field tends to be higher due to the abrupt discontinuities in the device structure. Another reason for optimization is when the area density of ionized negative charges in p-type III-N depletion layer 16 is different (e.g., lower or higher) than the area density of ionized positive charges in channel layer 15 and back barrier layer 14. Several solutions for improving the electric field profile of device 200 are described below.

[0063] The electric field profile of device 200 can be improved by adding a field plate structure. A cross-sectional view of device 400 is shown in FIG. 4A. Device 400 is an N-polarity depletion-mode III-N transistor similar to device 200 of FIG. 2, and shows the additional feature of a gate-connected field plate 26. Field plate 26 includes a metal portion that extends over insulator layer 18 and within drain-side access region 83 toward drain contact 22. Field plate 26 can be a single field plate, or field plate 26 can include multiple stacked field plates (as shown in FIG. 4A), each including a metal portion of different lengths extending toward the drain electrode.

[0064] Additionally, a drain-connected field plate 27 can be used to control the electric field in the drain-side access region 83. The field plate 27 is connected to the drain contact, which has a first end extending onto the insulator layer 18 toward the gate region 81. The length of the drain-connected field plate 27 can be selected so that the first end of the field plate extends across a portion of the III-N depletion layer 16 (e.g., the length of the field plate 27 can be greater than the distance 25 between the III-N depletion layer 16 and the drain contact 22). The field plate 27 can be a single field plate (as shown in FIG. 4A ), or the field plate 27 can include multiple field plates, each including a metal portion of a different length extending toward the gate electrode. Any excess mobile charge present at the end of the III-N depletion layer 16 adjacent to the drain contact 22 can be depleted by the drain-connected field plate 27. Incorporating a gate field plate 26 and / or a drain-connected field plate 27 can further help manage the electric field within the gate region 81 and drain-side access region 83, improving not only device breakdown characteristics but also short circuit withstand time (SCWT). A more uniform electric field can result in a more uniform power density across the drain-side access region 83, thus improving short circuit energy dissipation and increasing the time required to reach the critical temperature to failure.

[0065] FIG. 4B shows a cross-sectional view of a device 410 similar to device 200 of FIG. 2. Device 410 includes a III-N depletion layer 16' coupled to drain contact 22 and a III-N contact layer 17' used to enhance the electrical connection between layer 16' and drain contact 22. III-N depletion layer 16' is electrically isolated from layer 16' via a separation 25'. The separation from the second end of depletion layer 16' to the first end of depletion layer 16' can be greater than 0.5 μm. For example, separation 25' between the second end of III-N depletion layer 16 and the first end of depletion layer 16' can be between 0.5 μm and 10 μm. Also, as shown in device 410, the second end of III-N depletion layer 16, extending toward drain contact 22, can terminate at an angle α<90°. For example, angle α can be between 10° and 80°. The tapered shape can help manage the electric field near the edge of the III-N depletion layer 16 in the drain-side access region 83 and improve breakdown voltage.

[0066] Alternatively, the graded profile at the second end of III-N depletion layer 16 can be formed with a step profile, as seen in device 420 of Figure 4C. Device 420 includes a III-N depletion layer formed from multiple discrete p-type layers, for example, layers 16a, 16b, and 16c. Each layer has an AlN barrier formed between layers 16a and 16b, and between layers 16b and 16c. x Ga 1-x N intermediate layers, where x is between 0.5 and 1, and Al x Ga 1-xThe thickness of the N layer is between 0.5 nm and 5 nm. An AlGaN intermediate layer can be used as an etch stop layer to fabricate the step profile. The compositions and thicknesses of layers 16a, 16b, and 16c can be similar or different. For example, the p-type dopant concentration can decrease continuously from the first discrete layer 16a proximal to the III-N channel layer to the final discrete layer distal to the III-N channel layer toward the gate electrode. Alternatively, the first and final discrete layers can have higher dopant concentrations than the layers formed between the first and final discrete layers. The p-type layers can include a first end adjacent to the drain electrode, and the separation of the first end relative to the drain electrode increases from the discrete layer proximal to the III-N channel layer toward the gate electrode to the discrete layer distal to the III-N channel layer. The step profile can be used to mimic the sloped shape of Figure 4B, thus reducing the electric field at the second end of the depletion layer 16.

[0067] FIG. 4D is a cross-sectional view of device 430. Device 430 is similar to device 200 of FIG. 2, except that III-N depletion layer 16 can extend continuously from source contact 21 to drain contact 22. Here, rectifying contacts are formed between layer 16 and the source and drain contacts. The rectifying contacts can be Schottky barriers, pn barriers, or pn barriers. The rectifying contacts prevent shorts between gate 23 and drain 22 and between gate 23 and source 21. If the drain and source contacts are formed of a low work function metal (such as Ti or Al), a rectifying Schottky barrier can be formed between p-type depletion layer 16 and the low work function metal used for the drain and source ohmic contacts. Alternatively, the drain and source contacts can be formed with n-type III-N regrowth layer 31 below the source and drain contacts. Here, a rectifying pn barrier is formed between p-type depletion layer 16 and n-type ohmic regrowth layer 31. Additionally, the source and drain contacts can be formed by a III-N regrowth process, including a III-N stack with an unintentionally doped (UID) GaN layer 32 and an n-type layer 31 formed below the source and drain contacts 21 / 22 (as seen in FIG. 4D ). In this embodiment, a rectifying pin barrier is formed between the III-N depletion layer 16 and the drain / source contacts 21 / 22. Advantageously, the device in FIG. 4D does not have a selective removal process for the depletion layer 16, and therefore the channel layer 15 does not have exposed etched surfaces that can cause current leakage, charge trapping, and the presence of parasitic fixed and / or trapped charges that can degrade the electric field profile.

[0068] In another embodiment, in the device 440 shown in FIG. 4E, the III-N depletion layer 16 can be formed through magnesium implantation into a portion of the top of the III-N channel layer 15. The use of implantation can eliminate the need for a separate III-N depletion layer formed above the channel layer 15. This can result in a more planar device without the need to selectively remove the depletion layer in the source and drain side access regions. However, other fabrication aspects can become more challenging, such as the need for crystal damage recovery and dopant activation, which involves very high temperature and very high pressure processing, and the associated need to control Mg diffusion caused by high temperature exposure.

[0069] In another embodiment, device 450 of FIG. 4F is shown. Device 450 is similar to device 200 of FIG. 2, except that the III-N depletion layer 16 is not removed in a portion of source-side access region 82 and a portion of drain-side access region 83. Instead, the lattice structure of the III-N depletion layer 16 in a portion of source-side access region 82 and a portion of drain-side access region 83 is intentionally damaged by ion implantation (indicated by downward arrows in FIG. 4F). This ion implantation damage makes the charge depletion layer 16 semi-insulating in isolation region 25 and region 27, thus avoiding any short circuit between the gate and source terminals or between the gate and drain terminals.

[0070] FIG. 5A is a cross-sectional view of a device 500 including similar features to the device 200 of FIG. 2. However, the device 500 of FIG. 5A incorporates a buried III-N depletion layer 516 formed between the III-N buffer layer 11 and the III-N back barrier layer 14. The III-N depletion layer 516 contacts and electrically connects to the metal of the gate contact 23 via connection metal 523 in a manner similar to the connection of layer 16 to the gate 23, as described above with respect to FIGS. 2 and 3A / 3B. As shown in FIG. 5A, the region 26 where the buried depletion layer 561 connects to the metal 523 can be formed in a region outside the source and drain access regions so as not to affect the 2DEG channel 19. The buried III-N depletion layer 516 can further improve the uniformity of the electric field profile. In this case, the 2DEG channel charge can be partially or fully depleted across the entire device length between the source and drain contacts when the gate-source voltage is below a minimum value (e.g., −5 V, −10 V, −20 V) or below the device threshold voltage.

[0071] Optionally, when forming device 500 with buried III-N depletion layer 516, III-N depletion layer 16 can be omitted. However, when both III-N depletion layer 16 and buried III-N depletion layer 516 are present, the electron density in the 2DEG charge can be increased (e.g., 1.3×10) to achieve an even lower specific on-resistance compared to device 200 of FIG. 13 cm -2 , 1.5×10 13 cm -2 , 2 × 10 13 cm -2 The thickness and doping of the III-N depletion layer 16 and the buried III-N depletion layer 516 are designed to fully deplete when the gate-source voltage is lower than the threshold voltage. The gate voltage relative to the source when the buried III-N depletion layer 516 is fully depleted can be less negative or more negative than the gate voltage relative to the source when the III-N depletion layer 16 is fully depleted.

[0072] FIG. 5B is a plan view of a device 510 including similar features to device 500 of FIG. 5A. FIG. 5B includes device cross section AA′ shown in FIG. 5C and device cross section BB′ shown in FIG. 5D. Device 510 includes multiple 2DEG channels (e.g., two or more channels) (shown as 19, 19′, and 19″) and multiple buried III-N depletion layers (shown as layers 516, 516′, and 516″). The buried III-N depletion layers can be interleaved between 2DEG channels 19, 19′, and 19″. The buried III-N depletion layers can be connected to each other by forming trenches in portions of gate region 81. Trenches are formed in the III-N material structure, and the trenches extend through buried III-N layers 516, 516′, and 516″. The trench formation is followed by a p-type GaN regrowth step, which forms p-type III-N plugs 518 and 518' that connect to the buried III-N depletion layer, as shown in FIG. 5D. The III-N contact layer 17 and gate contact 23 are formed above the p-type III-N plugs 518 and 518' and connect the gate 523 to the buried III-N depletion layers 516, 516', and 516''. As can be seen in cross section BB' of FIG. 5D, the gate contact 523 is discontinuous, and an isolation 583 is formed between the p-type III-N plug 518 and the p-type III-N plug 518'. The separation 583 between the III-N plugs can be designed to maximize the surface of the contact between the III-N plugs 518 and 518′ and the buried III-N depletion layers 516, 516′ and 516″ and / or to take into account manufacturing limitations and lithography process resolution, for example, the separation 583 can be between 0.5 μm and 5 μm. Cross section AA′ in FIG. 5C is in a region of the device 510 where the gate contact 23 is discontinuous. The device 510 with multiple 2DEG channels allows for a reduction in device on-resistance. In addition, high charge mobility (a device with a single 2DEG channel charge is, for example, 2×10 13 cm -2(exceeding 2×10 may result in degradation) and maintain a low vertical electric field (single 2DEG channel charge is, for example, 2×10 13 cm -2 To maintain a standard 2DEG charge density (e.g., 1 × 10) coupled with multiple buried III-N depletion layers, the critical breakdown field must be exceeded. 13 cm -2 Devices with multiple 2DEG channels containing ultra-high 2DEG charges (e.g., 2 × 10 13 cm -2 This is preferable to a single channel (such as device 500) having a larger

[0073] In another embodiment, a multichannel device with a charge depletion layer can be implemented as shown in device 520, a plan view of which is shown in FIG. 5E. FIG. 5E includes device cross section CC' shown in FIG. 5F and device cross section DD' shown in FIG. 5G. Device 520 is similar to device 510 of FIGS. 5B-5C, but is formed without buried III-N depletion layers 516, 516', and 516''. Instead, the charge depletion layers are implemented by forming trenches in gate region 81 and drain-side access region 83. Trenches are formed in the III-N material structure, and the trenches extend through the multiple 2DEG channels 19, 19', and 19''. Following trench formation, a p-type GaN regrowth step is performed to form p-type III-N depletion layers 520 and 520', as shown in cross section DD' of FIG. 5G. The charge depletion layers 520 and 520' can be formed by regrowing p-type GaN. The charge depletion layer can be contacted in gate region 81 by gate contact 523 and an optional III-N contact layer, such as layer 17. As seen in FIG. 5E, gate contact 523 is discontinuous, forming cross section CC' in FIG. 5F. As shown in cross section DD' in FIG. 5G, isolation 585 is formed between p-type III-N depletion layers 520 and 520'. Isolation 585 determines the threshold voltage of 2DEG channels 19, 19', and 19''. When device 520 is used in a cascode configuration, isolation 585 can be designed so that the absolute value of the threshold voltage of device 520 is lower than the breakdown voltage of a low-voltage normally-off common-source device. For example, isolation 585 can be designed so that the absolute value of the threshold voltage of device 520 is less than 30 V, or less than 20 V, or less than 10 V. Cross section CC' in FIG. 5F is within the region of device 520 where gate contact 523 is discontinuous. The width and length of the trenches forming the III-N depletion layers 520 and 520′, as well as the doping of the III-N depletion layers 520 and 520′, can be optimized to achieve a desired electric field uniformity in the drain-side access region 83.

[0074] While devices 200-500 in Figures 2-5A illustrate depletion-mode devices, the properties of the N-polar material structure also allow for the fabrication of enhancement-mode devices with III-N depletion layers. Figure 6 shows a cross-sectional view of an enhancement-mode device 600 fabricated in an N-polar orientation. Device 600 has a substrate 610, a III-N buffer layer 611, a III-N back barrier layer 614, and a III-N channel layer 615, which have properties similar to those described with reference to the substrate 10, III-N buffer layer 11, III-N back barrier layer 14, and III-N channel layer 15 in device 200 of Figure 2. The thicknesses and compositions of the III-N back barrier layer 614 and III-N channel layer 615, respectively, are selected to induce a two-dimensional electron gas layer 619 (2DEG) in the III-N channel layer 615.

[0075] Device 600 has a gate contact 623 formed in gate region 681, a drain contact 622, and a source contact 621 formed on the same side of the device opposite substrate 610. As shown in Figure 6, the source contact 621 is formed between the gate contact 623 and the drain contact 622 such that the device contacts are arranged in a gate-source-drain (GSD) configuration. A drain-side access region 683 is formed between the source contact 621 and the drain contact 622. A source-side access region 682 is formed between the source contact 621 and the gate contact 623.

[0076] A III-N depletion layer 616 is formed over at least a portion of the III-N channel layer 615 and can have characteristics similar to the III-N depletion layer 16 of FIG. 2. As shown in FIG. 6, the III-N depletion layer 616 can include at least a first portion within the gate layer 681, a second portion within the source-side access layer 682, and a third portion extending laterally toward the drain-side access layer 683 between the source contact 621 and the drain contact 622. The III-N depletion layer 616 includes a first end and a second end, the first end adjacent to the gate contact 623, and the second end adjacent to the drain contact 622. The III-N depletion layer 616 is electrically isolated from the drain contact 622 via an isolation 625. The distance between the second end of the depletion layer 616 and the drain contact 622 can be 0.5 μm to 10 μm. Alternatively, the III-N depletion layer 616 can be in contact with a drain contact 625 having a rectifying barrier (i.e., no isolation 625) as described in device 430 of FIG. 4D.

[0077] A III-N body layer 630 and a III-N capping layer 617 are formed between the source contact 621 and the III-N depletion layer 616. The III-N body layer 630 and the III-N capping layer 617 are formed at least directly below the source contact 622, extending across the source-side access region 682 and partially into the gate region 681. The layers 630 and 617 are electrically isolated from the drain contact 622 via an isolation 628, which is greater than the isolation 625. The isolation 628 can affect the maximum rated blocking voltage of the device. For example, for a device with a maximum blocking voltage of 650 V, the isolation 628 can be 5 μm to 15 μm. For a device with a maximum blocking voltage of 1200 V, the isolation 628 can be 10 μm to 25 μm. This feature can be scaled to even greater isolations for higher maximum blocking voltages.

[0078] The III-N body layer 630 can be a p-type doped III-N layer (e.g., p-GaN). The p-type doped III-N body layer 630 can be 1×10 16 cm -3 Larger than 2 x 10 20 Active acceptor concentrations less than 1 × 10 cm, e.g., 18 / cm -3 The III-N body layer 630 can be doped with an active acceptor concentration greater than 2×10, so that it is not fully depleted when the drain is biased below the maximum voltage rating of the device. If the III-N body layer 630 is p-type GaN doped with Mg, the device is treated with a high temperature anneal to electrically activate the Mg dopants and to avoid excessive incorporation of impurities (e.g., carbon and hydrogen) and reduce electron scattering. 19 centimeters -3 The III-N body layer 630 may have a p-type doping concentration lower than that of the III-N body layer 630. Additionally, a 0.5-5 nm AlGaN or AlN interlayer (not shown) may be disposed between the III-N body layer 630 and the III-N depletion layer 616. This AlGaN or AlN interlayer may act as a selective etch stop, improving the control and precision of the etching process used to remove the III-N body layer 630 in the drain-side access region and protect the III-N depletion layer 616 from over-etching. The III-N body layer 630 may have a thickness of 20 nm-5 μm. The III-N body layer 630 may have a thickness greater than 50 nm. The III-N body layer 630 may have a thickness greater than 200 nm.

[0079] Furthermore, in some cases, the entire layer 630 is p-doped, while in other cases, only a portion of the layer is p-doped. For example, layer 630 can include a vertical series of p-doped portions, each separated by an undoped portion. When III-N body layer 630 is p-doped, the body layer depletes electrons in the vertical channel in gate region 81, thus making the device threshold voltage positive. To connect the source contact to the 2DEG channel, a positive voltage (relative to the source contact) must be applied to the gate contact, thereby achieving the E-mode operating mode. Additionally, when the p-doped body layer is electrically connected to source contact 621, the source potential (i.e., ground plane) can be very close (e.g., less than 20 nm) to the vertical channel. In this way, the body layer 630 functions as a buried source-connected field plate structure, shielding the gate region from high-voltage stress, mitigating short-channel effects such as drain-induced barrier lowering (DIBL), and reducing V TH The p-type body can collect holes generated in the high-voltage part of the III-N device, preventing them from being trapped under the gate, and V TH The normally-off gate with a p-type body reduces the on-state saturation current (I D, SAT ) and can therefore be used to control short circuit withstand time (SC-WT). The p-body can also enable the design and integration of electrostatic discharge (ESD) protection structures, improving device reliability.

[0080] Alternatively, the p-type of the III-N body layer 630 can be achieved by polarization-induced doping (e.g., by grading the bandgap of the layer without dopant impurities). In this case, the aluminum or indium composition of the III-N body layer 630 is graded to induce a bulk negative polarization charge that can attract holes, making the III-N body layer 630 p-type. The graded III-N body layer 630 has a composition that grades (e.g., continuously grades) from the side adjacent to the III-N channel layer 615 to the opposite side of the III-N channel layer 615. The composition of the graded p-type III-N body layer 630 is selected so that the gradient of the polarization field is positive in the [000-1] direction. For example, the III-N body layer 630 in the III-N device 600 is Al y Ga 1-y N (0≦y≦1), where y on the side of the III-N body layer 630 adjacent to the III-N channel layer is equal to y on the III-N channel layer 615 and increases (e.g., continuously increases) from the side adjacent to the III-N channel layer 615 toward the side facing the III-N channel layer 615. Alternatively, the III-N body layer 630 may be formed of In y Ga 1-y N (0≦y≦1), where y decreases (eg, continuously decreases) from the side close to the III-N channel layer 615 to the side facing the III-N channel layer 615.

[0081] Alternatively, the III-N body layer 630 can be formed using a semi-insulating or insulating GaN layer (e.g., i-GaN). The i-GaN layer can be made semi-insulating, insulating, or substantially free of n-type mobile carriers by including dislocations or point defects in the layer or by doping the layer with compensating elements such as Fe and / or C. Implementing an i-GaN body layer instead of a p-type GaN body layer can simplify the fabrication process because it is not necessary to control the Mg doping profile and Mg activation or grading profile of the p-type GaN body layer. However, due to the insulating nature of the i-GaN body, an electrical connection to a source contact cannot be used to control the voltage potential of the body layer 617, and therefore, an i-GaN body cannot offer the same advantages in terms of threshold voltage and field plating when compared to implementing a p-type III-N body layer.

[0082] A III-N capping layer 617, e.g., an n-type GaN layer, is formed on the III-N body layer 630 between the gate 623 and the source 621. The III-N capping layer provides a current path in the source-side access region 682 between the source contact 621 and the gate region 681. The III-N capping layer can have a thickness between 10 nm and 1 μm. The III-N capping layer can have a thickness greater than 10 nm. The III-N capping layer 617 can be doped with a donor (e.g., silicon). The doping concentration of the III-N capping layer can be greater than 1×10 16 centimeters -3 The thickness and net n-type doping of III-N capping layer 617 can be high enough so that layer 617 is not completely depleted of free electrons by III-N body layer 630, e.g., the thickness can be greater than 50 nm and the average n-type doping can be greater than 1×10 18 cm -3 The n-type doping can be as high as 1×10 19 centimeters -3It can be made larger.

[0083] The thickness and n-type doping of the III-N capping layer 617 can be high enough to provide a very low sheet resistance. The sheet resistance of the III-N capping layer 617 can be less than 100-200 Ω / □. The sheet resistance of the III-N capping layer 617 can be lower than the sheet resistance of the III-N channel layer 615. This represents a significant advantage of this device architecture, in that the source-side access layer 682 is realized on a completely separate layer relative to the drain-side access layer 683. Therefore, the III-N capping layer 617 in the source-side access region 682 can be designed to achieve a very low source access resistance.

[0084] The III-N capping layer 617 and III-N body layer 630 are removed in portions of the gate region 681 to form vertical (or semi-vertical or sloped) gate modules. The removal of the III-N material structures in these regions can be referred to herein as "trench recesses." The process for forming the trench recesses can be optimized to minimize damage to the surface of the exposed III-N channel layer 615 in the gate region 681. The selective removal process can be performed by means of dry etching techniques, wet etching techniques, or a combination of dry and wet etching techniques. For example, a low-power dry etch can be used to remove the bulk of the III-N capping layer 617 and III-N body layer 630 in the gate region 681, followed by an acid wet etch process to remove the remaining portions of layer 630.

[0085] The process of removing the III-N body layer 630 can include partial removal of the III-N channel layer 615 in the gate region 681. The partial removal of the III-N channel layer 615 can be performed by overetching the III-N body layer in successive dry etching steps or by a combination of multiple dry and wet etching steps. The remaining thickness of the III-N channel layer 615 determines the capacitance between the channel (e.g., 2DEG) and the gate contact 623. Before the trench etching process, the III-N channel layer 615 can be thicker than 150 nm, for example. In the region where the III-N body layer 630 has been removed, the overetch of the III-N channel layer can be 20-100 nm. In the region where the III-N body layer 630 has been removed, the thickness of the remaining III-N channel layer 615 can be greater than 50 nm. More than 50% of the III-N channel layer thickness can be removed during the overetch of the trench process.

[0086] A gate insulator layer 634 (e.g., a gate dielectric layer) is conformally grown or deposited on the vertical sidewalls of the III-N body layer 630, at least in the gate region 681. The gate insulator layer 634 may be above an upper surface of the III-N capping layer 617 and can have a first portion extending toward the source 21. The gate insulator 34 can be above an upper surface of the III-N channel layer 16 and can have a second portion between the channel layer 615 and the gate contact 623. The gate insulator layer 634 can have similar or different properties to the insulator 18 of FIG. 2 .

[0087] A gate contact 623 (i.e., a gate electrode) is conformally formed above the vertical sidewall portions of the gate insulating layer 634 and the III-N body layer 630 in the gate region 681. The gate contact 623 is above the top surface of the III-N capping layer 617 and can have a first portion that extends toward the source 621. The gate contact 623 can have material properties similar to the gate contact 23 of FIG. 2 or the gate contact 23 of FIG. 3B.

[0088] An insulating layer 618 is formed over the device between the gate, source, and drain contacts to passivate the top surface of the device. Insulating layer 618 can be similar to insulating layer 18 of FIG.

[0089] The source contact 621 is electrically connected to the III-N body layer 630. This connection can be made via direct contact or a tunnel junction. These contact methods can be similar to those described in Figures 3A and 3B used to connect the gate contact 23 of the device 200 to the III-N depletion layer 16.

[0090] 6 operates as follows: when the gate contact 623 is biased with respect to the source 621 at a voltage higher than the device's threshold voltage, an inversion channel forms at the vertical interface between the gate insulator layer 634 and the III-N body layer 630 in the device's gate region 681, thereby electrically connecting the source contact 621 to the 2DEG channel 619. When a positive voltage is applied to the drain 622, electrons flow from the source 621 through the source-side access region 682, through the inversion channel formed near the vertical interface between the gate insulator layer 634 and the III-N body layer 630 in the gate region 681, toward the 2DEG channel 619, and toward the drain 622, forming a continuous device channel between the source contact 621 and the drain contact 622. Conventional current flows from the drain 622 to the source 621, and the device is considered to be on.

[0091] When the gate 623 is biased relative to the source 621 at a voltage lower than the device's threshold voltage, the p-type dopants in the III-N body layer 630 completely deplete charge across the vertical interface between the gate insulator layer 634 and the III-N body layer 630. As a result, no inversion channel is formed in the gate region 681. Thus, the device channel is discontinuous between the source contact 261 and the 2DEG channel 619. Furthermore, when a positive voltage is applied relative to the drain 622, the III-N channel layer 615 and the III-N depletion layer 616 gradually deplete mobile charge. When the drain voltage is higher than a minimum value (e.g., 5 V, 10 V, 20 V), the III-N channel layer 615 and the III-N depletion layer 616 are completely depleted (i.e., pinched off) in the drain-side access region 683, and thus, similar to the device 200 of FIG. 2, the device can withstand high-voltage operation. The drain-side access region 683, the charge depletion layer 616, and the lateral portion of the channel within the passivation insulating layer 618 can be configured to withstand high voltages, for example, greater than 200V, greater than 300V, greater than 600V, greater than 900V, greater than 1200V, greater than 3300V, or greater than 10kV.

[0092] The III-N device 600 can be a transistor, a bidirectional switch, or a four-quadrant switch (FQS), and / or any suitable semiconductor device. Conventional III-N devices with lateral 2DEG gate regions typically exhibit a threshold voltage (Vth) shift after stress under continuous use, as previously described. However, in the device 600 of FIG. 6, the use of the III-N body layer 630 reduces the Vth of the device compared to conventional lateral III-N devices without a III-N body layer. TH The deviation can be brought closer to 0V.

[0093] Furthermore, when the gate 623 is biased with respect to the source 621 at a voltage less than the threshold voltage of the device and a sufficient reverse (i.e., positive) voltage bias is applied to the source contact with respect to the drain contact, a body diode is formed between the III-N body layer 630 and the III-N channel layer 615, and current can flow through the body diode in the reverse direction from the source contact 621 to the drain contact 622. This is referred to as the reverse conduction mode.

[0094] Another implementation of III-N device 700 is shown in FIG. 7. Device 700 is configured to operate as a bidirectional switch, sometimes referred to as a four-quadrant switch (i.e., FQS). Similar to the other devices described herein, device 700 includes a substrate 10 (although the substrate is optional), a III-N material structure including III-N layers 11 and 14 on the substrate 10, a 2DEG channel 19 within the III-N material structure, and an insulator layer 18 on the III-nitride material structure. Device 700 also includes a first source contact 21, a second source contact 721, a first gate electrode 23 formed on the first p-type III-N depletion layer 16, and a second gate electrode 723 formed on the second p-type III-N depletion layer 716. The first source contact 21 and the second source contact 721 each electrically contact the 2DEG channel 19. As with the previous embodiment, device 700 may also include gate- and / or source-connected field plates (not shown) to further assist with electric field management. The first III-N depletion layer 16 can be easily designed to be conductive when a gate bias relative to the first source contact 21 that is lower than the threshold voltage of the device is applied to the first gate electrode 23 and the second source contact 721 is biased at a voltage higher than the first source contact 124, so that the charge in the device channel in the gate region corresponding to gate 23 is depleted and the bidirectional switch is in the off state, but the device channel in the gate region corresponding to gate 23 is depleted when 0V is applied to the first gate electrode 23 relative to the first source contact 21 and the second source contact 721 is still biased at a voltage higher than the first source contact 21.The III-N depletion layer 716 can be designed such that when a gate bias is applied to the second gate electrode 723 relative to the second source contact 721, and the second source contact 721 is biased at a lower voltage than the first source contact 21, the device channel in the gate region corresponding to gate 723 is depleted of charge and the bidirectional switch is in an off state, but when 0V is applied to the second gate electrode 38 relative to the second source contact 721, the device channel in the gate region corresponding to gate 723 readily conducts while the second source contact 721 is still biased at a lower voltage than the first source contact 21. When gate 23 is biased off (i.e., below its threshold voltage relative to contact 21) and gate 723 is biased off (i.e., below its threshold voltage relative to contact 721), device 700 blocks voltages between contacts 21 and 721 of either polarity (i.e., both when the voltage at contact 21 is greater than the voltage at contact 721 and when the voltage at contact 721 is greater than the voltage at contact 21). When gate 35 is biased on (i.e., above its threshold voltage relative to contact 21) and gate 738 is biased on (i.e., above its threshold voltage relative to contact 721), device 700 can conduct current in either direction.

[0095] Having described several implementations, it will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein.

Claims

1. A III-N device, a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depletion layer, the III-N channel layer having a 2DEG channel formed therein; a source electrode and a drain electrode, each electrically connected to the 2DEG channel; a gate electrode between the source electrode and the drain electrode, the gate electrode being disposed on the III-N layer structure; Equipped with the p-type III-N depletion layer has a first layer between the gate electrode and the drain electrode; the p-type III-N depletion layer is electrically connected to the gate electrode and electrically insulated from the source electrode and the drain electrode; A device characterized by:

2. The device of claim 1 , wherein the III-N layer structure is grown with an N-polar orientation.

3. 10. The device of claim 1, wherein the dopant concentration in the p-type III-N depletion layer is such that the p-type doping areal density in the p-type III-N depletion layer is in the range of 10 to 150% of the sheet charge areal density of mobile charges in the 2DEG channel.

4. The device further comprises a first AlN layer between the p-type III-N depletion layer and the III-N channel layer. x Ga 1－x N layer, x is 0.5 to 1, x Ga 1－x The device of claim 1 , wherein the N layer has a thickness of 0.5 nm to 5 nm.

5. The device of claim 4 , wherein the device further comprises a first n-type GaN layer between the gate electrode and the p-type III-N depletion layer.

6. The device further comprises a second AlN layer between the first n-type GaN layer and the p-type III-N depletion layer. x Ga 1－x N layer, wherein x is 0.5 to 1, and the second Al x Ga 1－x The device of claim 5, wherein the N layer has a thickness of 0.5 nm to 5 nm.

7. 7. The device of claim 6, further comprising: a second n-type GaN layer between the first n-type GaN layer and the second AlxGa1-xN layer; and a second p-type GaN layer between the p-type III-N depletion layer and the second AlxGa1-xN layer, the second n-type GaN layer and the second p-type GaN layer having a doping density greater than the first n-type GaN layer and the p-type III-n depletion layer.

8. 2. The device of claim 1, wherein the p-type III-N depletion layer has a first end adjacent the drain electrode, the first end being spaced from the drain electrode by 0.5 μm to 5 μm.

9. 9. The device of claim 8, wherein the gate electrode comprises a field plate, the field plate extending at least partially above the first end of the p-type III-N depletion layer.

10. 9. The device of claim 8, wherein the drain electrode comprises a field plate, a portion of the field plate extending at least partially above the first end of the p-type III-N depletion layer.

11. The device of claim 8 , wherein a sidewall angle of the first end relative to a bottom surface of the p-type III-N depletion layer is between 10 and 80 degrees.

12. The p-type III-N depletion layer includes a plurality of p-type layers above the III-N channel layer, each layer being Al x Ga 1－x N layers, x is 0.5 to 1, and the Al x Ga 1－x The device of claim 1 , wherein the N layer has a thickness of 0.5 nm to 5 nm.

13. 13. The device of claim 12, wherein each of the plurality of p-type layers includes a first end adjacent the drain electrode, and wherein the separation from the first end to the drain electrode increases from the p-type layer proximate the III-N channel layer to the p-type layer distal to the III-N channel layer.

14. A transistor, an N-polar III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer; source and drain electrodes; a gate electrode between the source electrode and the drain electrode, the gate electrode being disposed above the N-polar III-N layer structure, the p-type III-N layer being electrically connected to the gate electrode; a 2DEG channel in the III-N channel layer, wherein the N-polar III-N layer structure is configured such that when the gate electrode is biased at 0 V with respect to the source electrode, the 2DEG channel extends continuously from the source electrode toward the drain electrode; A transistor comprising:

15. The transistor of claim 14 , wherein the p-type III-N layer has at least a first layer between the gate electrode and the drain electrode.

16. A transistor, a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depletion layer, the III-N channel layer having a 2DEG channel formed therein; a source electrode and a drain electrode, each electrically connected to the 2DEG channel; a gate electrode between the source electrode and the drain electrode, the gate electrode being disposed above the III-N layer structure; Equipped with a first portion of the p-type III-N depletion layer electrically connected to the gate electrode; a second portion of the p-type III-N depletion layer electrically connected to the drain electrode; The first portion and the second portion are electrically insulated from each other. Transistor.

17. 17. The transistor of claim 16, wherein a separation between the first portion of the p-type III-N depletion layer and the second portion of the p-type III-N depletion layer is between 0.5 μm and 5 μm.

18. 18. The transistor of claim 17, further comprising: a first n-type GaN layer between the gate electrode and the first portion of the p-type III-N depletion layer; and a second n-type GaN layer between the drain electrode and the second portion of the p-type III-N depletion layer.

19. 19. The transistor of claim 18, wherein the gate electrode is electrically connected to the first portion of the p-type III-N depletion layer by a tunnel junction, and the drain electrode is electrically connected to the second portion of the p-type III-N depletion layer by a tunnel junction.

20. A III-N device, a III-N layer structure comprising: a III-N channel layer and a III-N layer structure having a 2DEG channel therein; a III-N barrier layer below the III-N channel layer; and a p-type III-N layer above the III-N channel layer; source and drain electrodes; a gate electrode between the source electrode and the drain electrode, the gate electrode being above the III-N layer structure and electrically connected to the p-type III-N layer; Equipped with the p-type III-N layer has a first portion between the gate electrode and the drain electrode; the III-N device has a negative threshold voltage; The III-N device when the gate electrode is biased with respect to the source electrode at a negative voltage exceeding a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; when the gate electrode is biased relative to the source electrode below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in a device region between the gate electrode and the drain electrode. It is configured as follows: III-N device.

21. The III-N device of claim 20 , wherein the first minimum voltage is less than −5V.

22. 21. The III-N device of claim 20, wherein the p-type III-N layer is configured to deplete holes in the device region between the gate electrode and the drain electrode when the gate electrode is biased above the first minimum voltage and the drain electrode is biased above a second minimum voltage.

23. The III-N device of claim 22 , wherein the second minimum voltage is greater than 5V.

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