Method for manufacturing SiC electronic device with reduced processing steps and SiC electronic device

Abstract

To provide an improved method for manufacturing a SiC-based electronic device (50) and an electronic device manufactured thereby.SOLUTION: A method includes the steps of preparing a SiC substrate (53), forming a SiC structural layer (52) on the front portion of the substrate, forming an active region having a role in the generation and / or conduction of an electric current in the structural layer (52) during the period of use of an electronic device (50), forming a first electrical terminal (58) on the structural layer (52), forming a titanium intermediate layer (72) on the rear part of the substrate, heating an intermediate layer (72) by a laser beam (82) to generate local heating for the formation of ohmic contacts of a titanium compound, and forming a second electric terminal (57) of the electronic device on the intermediate layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating SiC electronic devices and the SiC electronic devices produced thereby, and in particular to an improved method for forming ohmic contacts on the backside of the electronic devices, which reduces the number of processing steps (flipping) required for the devices. [Background technology]

[0002] As is well known, a wide band gap, particularly a band gap energy value Eg greater than 1.1 eV, and a low on-state resistance (R ON Semiconductor materials with high thermal conductivity, high operating frequencies, and high saturation velocities of charge carriers are ideal for fabricating electronic components such as diodes or transistors, particularly for power applications. A material that possesses these properties and is designed for use in fabricating electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is preferred over silicon in view of the above-mentioned properties.

[0003] Compared to similar devices implemented on silicon substrates, electronic devices implemented on silicon carbide substrates offer numerous advantages, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency. In particular, SiC Schottky diodes have shown higher switching performance, making SiC electronic devices particularly suitable for high-frequency applications. Current applications impose requirements on the electrical characteristics and long-term reliability of the devices.

[0004] Resistance R ONThe value of R depends on several contributions. For example, in a SiC Schottky diode (e.g., 4H-SiC) designed to operate at a voltage of 650 V and provided with a SiC substrate with a thickness equal to several hundred micrometers (e.g., 350 μm), the resistance R ON Approximately 70% of the overall value of R is due to the SiC substrate. As a result, reducing the thickness of the SiC substrate to values approaching one hundred micrometers (e.g., 110 μm) reduces the resistance R ON This allows a significant reduction in the contribution made by the substrate to the overall value of .gtoreq.1.0 (bringing such contribution to a value of about 44%). Therefore, for medium voltage applications (600-1200 V), a polishing process of the wafer on the backside of the SiC substrate is considered appropriate, even if it may not be necessary.

[0005] However, such processing steps pose serious problems in handling and processing of the wafers, for example they may be made too thin and therefore prone to cracking, warping, and generally damaging phenomena.

[0006] FIG. 1 shows a known type of merged PN Schottky (MPS) device 1 in cross section in a Cartesian (three-axis) reference system of the X, Y and Z axes.

[0007] MPS1 includes a substrate 3 of N-type SiC having a thickness of approximately 350 μm and a surface 3 a opposite a surface 3 b and having a first doping concentration; a drift layer 2 (epitaxially grown) of N-type SiC having a thickness in the range of 5-10 μm and extending on the surface 3 a of the substrate 3 and having a second doping concentration lower than the first doping concentration; ohmic contact regions 6 (e.g., nickel silicide) extending on the surface 3 b of the substrate 3; anode metallization 8 extending on the ohmic contact regions 6; multi-junction barrier (JB) elements 9 in the drift layer 2 facing the upper surface 2 a of the drift layer 2 and each including a respective P-type implanted region 9′ and metallic ohmic contact 9″; and, in particular, end termination regions or guard rings 10 (optional), which are P-type implanted regions completely surrounding the implanted region (JB) elements 9.

[0008] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. In particular, a Schottky (semiconductor-metal) junction is formed by portions of the drift layer 2 that are in direct electrical contact with respective portions of the anode metallization 8.

[0009] The region of the MPS device 1 that includes the JB element 9 and the Schottky diode 12 (ie, the region contained within the guard ring 10 ) is the active area 4 of the MPS device 1 .

[0010] 2-5 illustrate, in cross-sectional view, the steps for processing a wafer 20 of semiconductor material to obtain the MPS device 1 of FIG.

[0011] 2, the wafer 20 has a substrate 3 of SiC having a first conductivity type (N). On the front side 3a of the substrate 3, for example, a silicon dioxide film having the first conductivity type (N) and a lower doping concentration than the substrate 3, for example, 1×10 14 ~5×10 16 atoms / cm 3A drift layer 2 of SiC having a doping concentration in the range of 15R to 4H—SiC is formed, for example by epitaxial growth. The drift layer 2 is particularly composed of 4H—SiC, although other polytypes such as 2H, 6H, 3C, and / or 15R may also be used.

[0012] A hard mask 22 is then formed on top of the drift layer 2 by deposition of photoresist, or TEOS, or another material, with a thickness such that it is intended to shield the implantation described below with reference to this same Figure 2. The hard mask 22 thus formed thus extends into the region of the wafer 20 where the active area 14 of the MPS device 1 will be formed in a subsequent step.

[0013] In plan view on the XY plane, hard mask 22 covers the region of upper side 2 a of drift layer 2, which forms Schottky diode 12 and leaves exposed the region of upper side 2 a of drift layer 2 which forms implanted region 9′.

[0014] An implantation step of a doping species (e.g., boron or aluminum) having a second conductivity type (P) is then carried out using the hard mask 22 (the implantation is represented in the figure by arrows 24). During such an implantation step, the guard ring 10, not shown in FIG. 3, is also formed.

[0015] 3, the mask 22 is removed and a thermal annealing step is performed to diffuse and activate the implanted doping species. The thermal annealing is performed, for example, at a temperature higher than 1600° C. (e.g., in the range of 1700-1900° C. and even higher in some cases). After the thermal annealing, the implanted region 9′ has a density of about 1×10 17 〜1×10 20 atoms / cm 3 The doping species has a concentration in the range of .gtoreq. ...1.

[0016] Nickel deposition is carried out exclusively in the implanted regions 9', using in particular a silicon oxide mask (not shown) to cover the surface areas of the wafer 20 other than the implanted regions 9'. Subsequent thermal annealing at high temperature (close to 1000°C for a time period ranging from 1 to 120 minutes) makes it possible to form nickel silicide ohmic contacts 9" by chemical reaction between the deposited nickel and the silicon of the drift layer 2. In fact, the deposited nickel reacts with the surface material of the drift layer 2 to form NiSi (i.e., ohmic contacts), while the nickel in contact with the oxide of the mask does not react. A step of removing the unreacted metal and the mask is then carried out.

[0017] The step of forming the cathode contact is then performed, which includes the ohmic contact 6 and the metallization 16 illustrated in Figure 1. This step requires rotating the wafer 20 so that the back side of the wafer 20 can be processed.

[0018] Forming the cathode contact in this processing step is preferred because the front side of wafer 20 does not have anode metallization and therefore will not experience undesirable interfacial reactions between metal and semiconductor and electrical degradation of Schottky diode 12.

[0019] An interface layer 26 of a metallic material, such as nickel, is deposited on the surface 3b of the substrate 3. The interface layer 26 is deposited, for example, by sputtering, and has a thickness in the range of approximately 10 to 500 nm. A high-temperature thermal anneal (in the range of 900 to 1000°C for a time period in the range of 1 to 120 minutes) then allows the ohmic contact 6 to form, favoring the formation of nickel silicide (NiSi) by chemical reaction between the deposited nickel and the silicon of the substrate 2.

[0020] 5, wafer 20 is then rotated again, and processing of the front side of wafer 20 continues, with lithography and etching steps for depositing and shaping anode metallization 8 (which may require the use of one or more deposition masks and processing steps of wafer 20 at high temperatures, in a manner known per se), thus completing the formation of MPS device 1. Thus, multiple Schottky-type semiconductor-metal junctions are formed between anode metallization 8 and regions of drift layer 2 having the first conductivity type (N). Anode metallization 8 is also formed, which functions as an anode contact terminal. A passivation layer for the anode metallization may also be formed in a known manner (not shown).

[0021] The wafer is then rotated again for backside processing. Further deposition of metal (e.g., Al or Cu, or alloys or compounds such as Ti / NiV / Ag or Ti / NiV / Au) on the ohmic contacts 6 forms the cathode metallization 16.

[0022] Multiple MPS devices 1 can (typically) be formed on the same wafer 20. A final step of wafer singulation is performed to physically separate one MPS device 1 from another.

[0023] 2-5, various processing steps of wafer 20, such as flipping wafer 20 multiple times to process the front and back sides of wafer 20 separately, can damage wafer 20 and / or structures formed on both sides, with the smaller the thickness of wafer 20, the greater the impact.

[0024] In fact, as mentioned above, the resistance R of the MPS device 1 ON If the substrate 3 is made thinner to reduce its contribution to the temperature, handling, lithography, and processing operations at high temperatures may contribute to the occurrence of cracking or warping of the wafer 20.

[0025] The applicant has determined that thinning of the wafer 20 can be achieved by a polishing step performed after the step of Figure 3 and before the step of Figure 4, in which a portion of the substrate 3 at the surface 3b is physically removed to achieve the desired final thickness (e.g., 100-110 μm). This step of thinning the wafer 20 further complicates the subsequent steps of flipping the wafer (after the step of Figure 4 and before the step of Figure 5) and processing the front side of the wafer 20 (step of Figure 5). The wafer 20 will have a total thickness of approximately 110 μm, which would make further processing impossible or require excessive care and attention.

[0026] The above problems have been described with explicit reference to MPS devices for ease of explanation and better understanding, but it should be understood that the thickness of the substrate affects the on-state resistance (R ON It is clear that this can be extended to any SiC-based device where the thickness of the substrate plays a role in determining R. In such devices, reducing the thickness of the substrate ON While this provides an improvement in the field of robotics, the handling and processing problems exemplified above still exist and limit freedom of movement. Summary of the Invention [Problem to be solved by the invention]

[0027] An object of the present invention is to provide a method for manufacturing a SiC electronic device and a SiC electronic device that overcomes the drawbacks of the prior art. [Means for solving the problem]

[0028] According to the present invention, there is provided a method for manufacturing a SiC electronic device, a SiC electronic device, and a system for manufacturing a SiC electronic device, as defined in the claims.

[0029] For a better understanding of the invention, preferred embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a cross-sectional view of an MPS device according to a known embodiment. [Figure 2] 2A-2C are cross-sectional views illustrating certain known steps in manufacturing the device of FIG. 1; [Figure 3] 2A-2C are cross-sectional views illustrating certain known steps in manufacturing the device of FIG. 1; [Figure 4] 2A-2C are cross-sectional views illustrating certain known steps in manufacturing the device of FIG. 1; [Figure 5] 2A-2C are cross-sectional views illustrating certain known steps in manufacturing the device of FIG. 1; [Figure 6] 1 is a cross-sectional view of an MPS device according to one embodiment of the present invention. [Figure 7] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 8] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 9] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 10] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 11] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 12] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. [Figure 13] 7A-7D are cross-sectional views illustrating certain steps in fabricating the device of FIG. 6 according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0031] The present invention will be described with particular reference to a merged PN Schottky (MPS) device, but as will become apparent from the following description, the present invention is generally applicable to any SiC-based electronic device.

[0032] FIG. 6 illustrates a cross-sectional view of a merged PN Schottky (MPS) device 50 in a Cartesian (three-axis) reference system of axes X, Y, and Z according to one aspect of the present invention.

[0033] The MPS device 50 comprises a substrate 53 of N-type SiC having a thickness in the range of 70-180 μm, more particularly in the range of 100-120 μm, for example equal to 110 μm, and having a surface 53 a opposite to a surface 53 b, and having a first doping concentration; a drift layer (epitaxially grown) of N-type SiC having a thickness in the range of 5-10 μm and extending on the surface 53 a of the substrate 53 and having a second doping concentration lower than the first doping concentration; and an ohmic contact region or layer 56 (Ti) extending on the surface 53 b of the substrate 53. x C y , Ti x Si y , and Ti x Si y C z anode metallization 58, for example, of Ti / AlSiCu or Ni / AlSiCu, extending over the upper surface 52a of the drift layer 52; a passivation layer 69 on the anode metallization 58 to protect the anode metallization 58; multiple junction barrier (JB) elements 59 in the drift layer 52 facing the upper surface 52a of the drift layer 52 and each including a respective implanted region 59′ of P-type and an ohmic contact 59″ of metal material; and optional end termination regions or guard rings 60, particularly P-type implanted regions, completely surrounding the junction barrier (JB) elements 59.

[0034] One or more Schottky diodes 62 are formed laterally to the implanted region 59' at the interface between the drift layer 52 and the anode metallization 58. In particular, a Schottky (semiconductor-metal) junction is formed by portions of the drift layer 52 in direct electrical contact with respective portions of the anode metallization 58.

[0035] The region of the MPS device 50 that includes the JB element 59 and the Schottky diode 62 (i.e., the region enclosed within the guard ring 60) is the active area 54 of the MPS device 50.

[0036] According to one aspect of the present invention, as described above, the ohmic contact region 56 is made of titanium silicide (Ti x C y , Ti x Si y , and Ti x Si y C z The titanium-type compound is obtained by depositing titanium on the surface 53b of the substrate 53 and thermally initiating a chemical reaction between the deposited titanium and the material of the substrate 53. The chemical reaction, which is obtained at temperatures in the range of 1400-2600°C, is x C y , Ti x Si y , and Ti x Si y C z -type titanium compound formation, making the ohmic contact region 56 particularly suitable. The steps for forming the ohmic contact region 56 are described below with explicit reference to the steps for fabricating the MPS device 50 (FIGS. 7-13).

[0037] Referring to FIG. 7, a wafer 100 is provided that includes a substrate 53 of SiC (particularly, 4H—SiC, although other polytypes such as, but not exclusively, 2H—SiC, 3C—SiC, and 6H—SiC may also be used).

[0038] The substrate 53 has a first conductivity type (in this example, an N-type dopant) and has a front surface 53a and a rear surface 53b that are opposite to each other along the Z axis. 19 〜1×10 22 atoms / cm 3 The doping concentration is in the range of .mu.m.

[0039] The front side of wafer 100 corresponds to front surface 53a, and the back side of wafer 100 corresponds to back surface 53b. The resistivity of substrate 30 is, for example, in the range of 5 to 40 mΩ·cm.

[0040] On the front surface 53a of the substrate 53, there is a doping concentration lower than the doping concentration of the substrate 53, e.g., 1×10 14 ~5×10 16 atoms / cm 3 A silicon carbide drift layer 52 having a first conductivity type (N) and having a conductivity in the range of 0.1 to 1.0 V is formed, for example by epitaxial growth. Drift layer 52 is composed of SiC, specifically 4H—SiC, although other SiC polytypes such as 2H, 6H, 3C, or 15R could also be used.

[0041] Drift layer 52 has a thickness defined between an upper side 52a and a lower side 52b (lower side 52b is in direct contact with front surface 53a of substrate 53).

[0042] 8, a hard mask 70 is then formed on the top side 52a of the drift layer 52, for example by deposition of photoresist, or TEOS, or another material suitable for that purpose. The hard mask 70 has a thickness in the range of 0.5 to 2 μm, or any thickness that will block the implants described below with reference to the same FIG. 8. The hard mask 70 extends over the areas of the wafer 100 where, in a subsequent step, the active areas 54 of the MPS devices 50 will be formed.

[0043] In plan view in the XY plane, hard mask 70 covers the region of top side 52a of drift layer 52 that will form Schottky cell (diode 62) and leaves exposed the region of top side 52a of drift layer 52 that will form implanted region 59′, as previously described with reference to FIG. 6.

[0044] Then, a step of implanting doping species (e.g., boron or aluminum) having a second conductivity type (P) is carried out using the hard mask 70 (the implantation is indicated by arrows in the figure). During the step of Figure 8, the guard ring 60, if present, is also formed.

[0045] Optionally, the injection step in Figure 8 can be performed with 1 x 10 18 atoms / cm 3 To form implanted region 59' having a doping concentration higher than 1×10, the implant energy is in the range of 30 to 400 keV and the dose is 1×10. 12 〜1×10 15 atoms / cm 2 The method includes implanting one or more doping species having the second conductivity type within the range of .beta.

[0046] 9, mask 70 is removed and a heat treatment (i.e., thermal annealing) step is performed to effect diffusion and activation of the doping species implanted in the step of FIG. 8. The annealing is performed, for example, at a temperature greater than 1600° C. (e.g., in the range of 1700-1900° C., and in some cases even higher). Thus, implanted region 59′ is formed, which has a size of about 1×10 17 〜1×10 20 atoms / cm 3 The doping species has a concentration in the range of .gtoreq. ...1.

[0047] At the same time, a Schottky cell is also formed, with a portion of drift layer 52 extending laterally (along X) toward implant region 59′, or in other words, toward the portion of drift layer 52 that was masked during the implant step of FIG. 8.

[0048] Referring to FIG. 10, an ohmic contact 59″ (in this case, e.g., nickel silicide) is formed to each implanted region 59′, contributing to the formation of a respective JB element 59. The implanted regions 59′ visible in the cross-sectional view are, in a non-limiting example, fully connected to each other (i.e., they form a grid). As a result, the ohmic contacts 59″ are also fully connected to each other and electrically connected to the implanted regions 59′.

[0049] An ohmic contact 59 is also formed on the guard ring 60 (if present) and electrically connected to the ohmic contact 59''.

[0050] Formation of the ohmic contacts 59" involves forming a hard mask of thin oxide (e.g., in the range of 100 to 500 nm), followed by photolithography and chemical etching steps to chemically etch the areas where the ohmic contacts 59" are to be formed, followed by deposition of a metal material (e.g., nickel) and then thermal annealing (e.g., at a temperature in the range of 900 to 1100°C for a time period of 1 to 120 minutes). The metal so deposited reacts with the surface SiC material to form an ohmic compound (e.g., nickel silicide), while the metal in contact with the oxide of the hard mask does not react. A step of removing the unreacted metal and the hard mask is then performed.

[0051] Next, referring to FIG. 11, a step of forming an anode terminal is carried out.

[0052] To that end, an interfacial layer 67 of a metallic material, such as titanium, nickel, or molybdenum, is deposited on the drift layer 52. The interfacial layer 67 is deposited by sputtering and has a thickness in the range of approximately 10 to 500 nm. The interfacial layer 67 contacts the implanted region 59′ via an ohmic contact 59″ and extends in contact with the exposed region of the drift layer 52 (i.e., the Schottky cell). In particular, the interfacial layer 67 contributes to forming a Schottky contact / barrier with the exposed region of the drift layer 52 and a junction barrier (JB) element with the implanted region 59′ via the ohmic contact 59″.

[0053] A further metal layer 68 is then formed on top of and in direct contact with the interface layer 67. The metal layer 68 is made of, for example, aluminum or copper and has a thickness of a few microns, for example in the range 1-10 μm.

[0054] The assembly consisting of the interface layer 67 and the metal layer 68 forms the anode metallization 58 previously described with reference to FIG.

[0055] As shown in FIG. 11, a plurality of Schottky-type semiconductor-metal junctions (Schottky diodes 12) are similarly formed between anode metallization 58 and regions of drift layer 52 having the first conductivity type (N).

[0056] In an alternative embodiment (not shown), interface layer 67 is omitted, so that metal layer 58 extends in direct contact with drift layer 52 .

[0057] Referring to FIG. 12, a passivation layer 69 (e.g., of polyimide) is also formed over the anode metallization 58 and is shaped to open one or more areas for electrical contacts 70 to contact the anode metallization 58.

[0058] 13, a cathode contact terminal is then formed on the backside of the wafer 100, ie, the rear surface 53b of the substrate 53. As shown in FIG.

[0059] Formation of the cathode includes forming a metallization on the rear surface 53b of the substrate 53 and an ohmic contact region or layer between the metallization and the rear surface 53b, the ohmic contact layer providing good electrical contact between the metallization and the substrate 53.

[0060] More specifically, the formation of the ohmic contact comprises depositing, for example by sputtering, an intermediate layer 72 (in particular titanium) on the rear surface 53b of the substrate 53. The intermediate layer 72 has a thickness, for example, in the range of 10 to 200 nm, in particular equal to 100 nm.

[0061] The creation of an ohmic contact requires that the titanium of the intermediate layer 72 react with the carbon and silicon of the substrate 53. The Ti x C y , Ti x Si y , and Ti x Si y C z To generate the thermal conditions in the intermediate layer 72 necessary to generate the compounds, a laser source 80 is used which generates a beam 82 that locally heats the intermediate layer 72 to a temperature in the range of 1400 to 2600°C, for example equal to 2000°C.

[0062] The thickness ( Achieving such a temperature substantially uniformly across the entire surface (Z axis) is x C y , Ti x Si y , and Ti x Si y C zThe formation of a titanium compound of the type Ti is suitable to convert the intermediate layer 72 into the ohmic contact region 56 shown in FIG. x C y , Ti x Si y , and Ti x Si y C z Conversion of the intermediate layer 72 to a Ti-type compound occurs by heating the entire usable surface of the intermediate layer 72. Note that the "usable surface" here refers to the surface portion of the intermediate layer 72 that is desired to act as an ohmic contact (e.g., as defined by design), and may not correspond to the entire surface of the intermediate layer 72 (e.g., portions of the intermediate layer 72 lateral to the active area 54 are not of interest during use of the MPS device 50 because they do not contribute to charge conduction).

[0063] Thus, the intermediate layer 72 becomes the ohmic contact region or layer 56 previously described, i.e., it has ohmic and non-Schottky properties.

[0064] Cathode metallization 57 is then formed on intermediate layer 72 / ohmic contact 56, for example by depositing Ti / NiV / Ag or Ti / NiV / Au by sputtering, thus obtaining MPS device 50 of FIG.

[0065] The laser 80 is, for example, an excimer UV laser. Other types of lasers can also be used, including lasers with wavelengths in the visible light range.

[0066] The configuration and operating parameters of laser 80 optimized to achieve the objectives of the present invention in the case of a titanium intermediate layer 72 (to generate ohmic contacts based on titanium) are as follows: *Wavelengths in the range of 290 to 370 nm, especially 310 nm: * Pulse duration in the range of 100 to 300 ns, especially 160 ns; * Number of pulses in the range of 1 to 10, especially 4; *1 to 4J / cm 2 Within the range of 3J / cm 2 energy density of; * Temperatures in the range of 1400 to 2600 ° C, especially 2000 ° C; As stated above.

[0067] The on-state resistance (R ON ) properties (i.e., R ON 12 and 13, i.e., before forming the ohmic contacts 56. The thinning of the substrate 53 proceeds until it reaches a desired thickness, for example, in the range of 70 to 180 μm.

[0068] It is possible to form multiple MPS devices 50 on the same wafer 100, in which case a final singulation step of the die is performed to physically separate one MPS device 50 from another.

[0069] According to a further embodiment of the present invention, the ohmic contact region 56 is made of a titanium compound (Ti x C y , Ti x Si y , and Ti x Si y C z For example, the ohmic contact region 56 may be formed by depositing (or forming by another technique) an intermediate layer 72 of a metallic material other than titanium on the rear surface 53b of the substrate 53, and then heating such intermediate layer 72 with a laser beam 82 (to a temperature in the range of 1400-2600°C, as previously described) as appropriate to form an ohmic compound or alloy between the material of the intermediate layer 72 and the material of the substrate 53, as previously described.

[0070] For example, when considering a SiC substrate 53, The intermediate layer 72 is made of Mo, and thermal annealing by laser is Mo x C y , Mo x Si y , and Mo x Si y C z Suitable for the generation of The intermediate layer 72 is made of Ta, and the thermal annealing by the laser is Ta x C y , Ta x Si y , and Ta x Si y C z Suitable for the generation of The intermediate layer 72 is made of W, and the thermal annealing by the laser is W x C y , W x Si y Suitable for the generation of The intermediate layer 72 is made of Co, and the thermal annealing by the laser is x Si y Suitable for the generation of The intermediate layer 72 is made of Ni, and the Ni x Si y Suitable for generating

[0071] The advantages of the present invention are apparent from an examination of the properties of the present invention provided by this description.

[0072] In particular, this solution allows for the formation of ohmic contacts on the rear of power devices fabricated on very thin (180 mm or less) wafers of SiC. With this solution, after depositing and defining anode metallization and passivation on the front of the wafer, the substrate is thinned to the desired thickness without the processing limitations of the prior art (which requires thicknesses greater than 180 μm). A Ti layer is then deposited on the rear of the wafer and the formation of the ohmic contact is performed by an annealing laser process, preserving the structures previously created on the front of the wafer. With this solution, the following advantages are obtained: simplification of the process flow (in this solution, wafer thinning is actually performed after completing the front-end processing of the device); Better quality of ohmic contacts (only one processing step following the formation of the ohmic contacts); Reduced risk of wafer cracking (only one rotation and only three processing steps following wafer thinning); No lithographic limitations after the wafer thinning step; Overall R of the device ON a significant reduction in the resistive contribution of the substrate to etc.

[0073] Furthermore, the use of titanium as a starting material for the subsequent formation of titanium-based ohmic contacts has several advantages compared to the use of nickel according to the prior art, such as the continuity and uniformity of the reaction layer, the absence of C agglomerates in the reaction layer, and the mechanical strength of the reaction layer, which are due to the Ti x C y , Ti x Si y , and Ti x Si y C z This is due to the presence of -type compounds.

[0074] Finally, it is clear that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of protection of the present invention as defined in the claims. In particular, as already observed above, the present invention is not limited to forming ohmic contacts on the rear of MPS devices, but extends to the formation of rear ohmic contacts in general vertical conduction electronic devices, such as Schottky diodes, JSB devices, MOSFETs, IGBTs, JFETs, DMOSs, etc.

[0075] Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific embodiments, and it goes without saying that various modifications and alterations can be made without departing from the scope of the present invention defined by the claims.

Claims

1. A method for manufacturing a SiC-based electronic device (50), comprising: (a) preparing a SiC substrate (53) having a front side (53a) and a rear side (53b) opposite to each other along a direction (Z); (b) forming a structural layer (52) of SiC on the front side (53a) of the substrate (53); (c) forming an active region of the electronic device (50) within the structural layer (52) that plays a role in generating and / or conducting electrical current during use of the electronic device (50); (d) forming a first electrical terminal (58) on the structural layer (52); (e) after steps (a) to (d), forming an intermediate layer (72) of a first metal selected from titanium, molybdenum, tantalum, tungsten, cobalt, and nickel on the rear side (53b) of the substrate (53); (f) heating the selective portion of the intermediate layer (72) with a laser beam (82) to cause localized heating of the selective portion at a temperature in the range of 1400 to 2600°C suitable for forming a compound of the first metal in the selective portion; and (g) forming a second electrical terminal (57) of the electronic device (50) on the intermediate layer (72) after step (f); A way of embracing that.

2. The first metal is titanium and the compound of the first metal is Ti ｘ C ｙ , Ti ｘ Si ｙ , or Ti ｘ Si ｙ C ｚ 2. The method of claim 1, comprising:

3. The laser beam (82) is determined according to the following parameters: * Within the range of 290 to 370 nm * Within the range of 100 to 300 ns, * Within the range of 1 to 10 *1 to 4 J / cm ２ Within the range of *Within the range of 1400 to 2600°C 3. The method of claim 2, wherein the signal is generated by:

4. 4. The method of claim 1, wherein the formation of the compound of the first metal occurs throughout the thickness of the intermediate layer (72) along the direction (Z).

5. 5. The method of claim 1, further comprising, before step (e), thinning the substrate (53) at the rear side (53b) until a final thickness of the substrate (53) of 180 μm or less is reached.

6. 6. The method of any one of claims 1 to 5, wherein the substrate is one of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

7. 7. The method of any one of claims 1 to 6, wherein the electronic device (50) is one of a combined PN Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, a DMOS.

8. The electronic device (50) is a combined PN Schottky diode, the structural layer (52) is a drift layer (2) of the Schottky diode having a first conductivity type (N); the active region includes a doped region (59') having a second conductivity type (P) opposite to the first conductivity type (N); the first electrical terminal (58) is an anode metal terminal in electrical contact with the doped region (59') and in direct electrical contact with the drift layer (52) laterally relative to the doped region (59') so as to form a junction-barrier JB diode with the doped region (59') and a Schottky diode with the drift layer (52); The second electrical terminal (57) is a cathode terminal, The junction-barrier JB diode and the Schottky diode define an active area (54) of the electronic device (50). The method of claim 7.

9. 9. The method of claim 8, further comprising the steps of depositing a second metal on the doped region (59') and performing a thermal anneal to enable formation of a silicide of the second metal to form an ohmic contact in the doped region (59').

10. A system for manufacturing a SiC-based electronic device (50), comprising: a first reaction chamber for forming a structural layer (52) of SiC on the front side (53a) of a substrate (53) of SiC; a second reaction chamber for forming in said structural layer (52) an active area having a role in generating and / or conducting electrical current during use of said electronic device (50); a third reaction chamber for forming a first electrical terminal (58) on the structural layer (52) and an intermediate layer (72) of a metal selected from titanium, molybdenum, tantalum, tungsten, and cobalt on the rear side (53b) of the substrate (53); a laser device (80) configured to generate a steerable laser beam (82) toward the selected portion of the intermediate layer (72) to heat the selected portion to generate localized heating to a temperature in the range of 1400 to 2600°C to form a compound of the metal in the selected portion of the intermediate layer (72); A system having:

11. The laser device (80) is configured to have the following parameters: in the range of 290 to 370 nm; in the range of 100 to 300 ns, in the range of 1 to 10, 1 to 4 J / cm ２ Within the range of in the range of 1400 to 2600°C; 11. The system of claim 10, configured to generate the laser beam (82).

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