programmable logic circuit

Abstract

To improve the resource utilization efficiency of a programmable logic circuit when a carry generation signal is a multivariate function.SOLUTION: A programmable logic circuit comprises: a first lookup table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating and outputting a carry propagation signal and a carry generation signal based on a received input signal, and selecting and outputting either the carry propagation signal or the carry generation signal; a first selection circuit for receiving a carry input signal and a carry generation signal, and selecting and outputting either the carry input signal or the carry generation signal based on the carry propagation signal; and a second selection circuit for receiving a first output signal and a second output signal, and selecting and outputting either the first output signal or the second output signal based on a selection output signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This application relates to the field of programmable integrated circuits, and more particularly to programmable logic circuits. [Background technology]

[0002] A programmable logic circuit based on a look-up table (LUT) is the basic logic module of a programmable logic device. It has advantages such as a short development cycle, low cost, low risk, high integration, and high flexibility, and is widely used in fields such as communications, the Internet, automobiles, and aerospace.

[0003] As shown in Figure 1, when an existing programmable logic circuit is used as an adder, the carry input signal of the adder can only be input from port A4. If the carry generation signal of the programmable logic circuit is a function of multiple variables, logic resources other than the programmable logic circuit itself must be consumed, resulting in low resource utilization efficiency. Summary of the Invention

[0004] In view of the above problems, the present application provides a programmable logic circuit for solving the above technical problems.

[0005] The present application provides a programmable logic circuit, a first look-up table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating and outputting a carry propagation signal and a carry generation signal based on the received input signal, and for selecting and outputting the carry propagation signal or the carry generation signal as a second output signal; a first selection circuit that receives a carry in signal and the carry generate signal, and selects and outputs either the carry in signal or the carry generate signal as a carry out signal based on the carry propagate signal; and a second selection circuit for receiving the first output signal and the second output signal, and for selecting and outputting the first output signal or the second output signal as a third output signal based on a selection output signal.

[0006] further, the first lookup table circuit includes a first five-input lookup table and a third selection circuit; a first input terminal to a fourth input terminal of the first five-input lookup table are used to receive first to fourth input signals, respectively; a fifth input terminal of the first five-input lookup table is used to receive a signal output from the third selection circuit; and an output terminal of the first five-input lookup table is used to output the first output signal; The third selection circuit receives a fifth input signal and the carry in signal, and is used to select and output either the fifth input signal or the carry in signal.

[0007] Furthermore, the third selection circuit is further used to receive a cascade input signal, and select one of the cascade input signal, the fifth input signal, and the carry input signal to output to a fifth input end of the first five-input lookup table; The second selection circuit further sets the selected first output signal or the second output signal as a cascade output signal.

[0008] Furthermore, the second lookup table circuit further includes a second five-input lookup table; The first to fourth input terminals of the second five-input lookup table are used to receive the first to fourth input signals, respectively, the fifth input terminal of the second five-input lookup table is used to receive the fifth input signal, the first output terminal of the second five-input lookup table is used to output the carry propagation signal, the second output terminal of the second five-input lookup table is used to output the carry generation signal, and the third output terminal of the second five-input lookup table is used to output the second output signal.

[0009] Furthermore, the second lookup table circuit further includes a fourth selection circuit; The fourth selection circuit receives the fifth input signal and the cascade input signal, and is used to select and output the fifth input signal or the cascade input signal, and the signal output from the fourth selection circuit is used to determine the signal output from the third output terminal of the second five-input lookup table.

[0010] Furthermore, the fourth selection circuit is further used to receive a sixth input signal, select one of the sixth input signal, the fifth input signal, and the cascade input signal, and output it to the fifth input end of the second five-input lookup table.

[0011] Furthermore, the first selection circuit includes a first multiplexer; a first input terminal of the first multiplexer is used to receive the carry generate signal, a second input terminal of the first multiplexer is used to receive the carry in signal, a select terminal of the first multiplexer is used to receive the carry propagate signal, and an output terminal of the first multiplexer is used to select and output the carry generate signal or the carry in signal as a carry out signal based on the carry propagate signal; The second selection circuit includes a second multiplexer, a first input terminal of the second multiplexer is used to receive the first output signal, a second input terminal of the second multiplexer is used to receive the second output signal, a selection terminal of the second multiplexer is used to receive the selection output signal, and an output terminal of the second multiplexer is used to select and output the first output signal or the second output signal as a third output signal based on the selection output signal.

[0012] Furthermore, the third selection circuit includes a third multiplexer; A first input terminal of the third multiplexer is used to receive the fifth input signal, a second input terminal of the third multiplexer is used to receive the carry in signal, a third input terminal of the third multiplexer is used to receive the cascade input signal, and an output terminal of the third multiplexer is used to select one of the fifth input signal, the carry in signal, and the cascade input signal and output it to a fifth input terminal of the first five-input lookup table.

[0013] Furthermore, the fourth selection circuit includes a fourth multiplexer; A first input terminal of the fourth multiplexer is used to receive the fifth input signal, a second input terminal of the fourth multiplexer is used to receive the sixth input signal, a third input terminal of the fourth multiplexer is used to receive the cascade input signal, and an output terminal of the fourth multiplexer is used to select one of the fifth input signal, the sixth input signal, and the cascade input signal and output it to a fifth input terminal of the second five-input lookup table.

[0014] Furthermore, the selection ends of the third multiplexer and the fourth multiplexer are programmed to control signals output from their output ends, and programming methods for the selection ends include at least SRAM programming, Flash programming, fuse programming, and anti-fuse programming.

[0015] In the programmable logic circuit provided by the present application, a second lookup table circuit is provided to output a carry propagation signal and a carry generation signal. When the programmable logic circuit is used as an adder, the carry generation signal is not limited to a single input variable, and addition operations of multi-variable functions can be performed. This improves the degree of freedom in the layout of the programmable logic device and the efficiency of utilization of logic resources in addition operation mode.

[0016] When the programmable logic circuit provided by the present application is used as an adder, the first output signal of the first lookup table circuit is the addition operation result, and the second output signal of the second lookup table circuit is either the addend of the addition operation, and the second selection circuit selects and outputs the first output signal or the second output signal, so that the programmable logic circuit can select and output the addition operation result or the addend of the addition operation.

[0017] In the programmable logic circuit provided by the present application, the first lookup table circuit directly outputs the first output signal, the second lookup table circuit directly outputs the second output signal, and the second selection circuit selects and outputs the first output signal or the second output signal as the third output signal, thereby realizing independent outputs of the first lookup table circuit and the second lookup table circuit, and the programmable logic circuit has a maximum of three outputs. [Brief explanation of the drawings]

[0018] In order to more clearly describe the embodiments of the present application or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments will be briefly described below. Obviously, the accompanying drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these accompanying drawings without any creative work.

[0019] [Figure 1] 1 is a diagram showing the prior art provided by the examples of the present application. [Figure 2] 1 is a block diagram illustrating modules of a programmable logic circuit provided by an embodiment of the present application. [Figure 3] FIG. 2 is a schematic diagram of a first look-up table circuit provided by an embodiment of the present application. [Figure 4] FIG. 2 is another schematic diagram of a first look-up table circuit provided by an embodiment of the present application; [Figure 5] FIG. 2 is a schematic diagram of a second look-up table circuit provided by an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of a first selection circuit provided by an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a second selection circuit provided by an embodiment of the present application. [Figure 8] FIG. 2 is a structural schematic diagram of a first five-input lookup table and a second five-input lookup table provided by an embodiment of the present application; [Figure 9] FIG. 10 is a schematic diagram of a third selection circuit provided by an embodiment of the present application. [Figure 10] FIG. 10 is another schematic diagram of a second selection circuit provided by an embodiment of the present application. [Figure 11] 1 is a schematic diagram of a dual comparator using a programmable logic circuit provided by an embodiment of the present application; [Figure 12] FIG. 10 is another schematic diagram of a second look-up table circuit provided by an embodiment of the present application. [Figure 13] FIG. 10 is yet another schematic diagram of a second look-up table circuit provided by an embodiment of the present application. [Figure 14]FIG. 10 is a schematic diagram of a fourth selection circuit provided by an embodiment of the present application. [Figure 15] 1 is a structural schematic diagram of a programmable logic circuit provided by an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0020] In order to help those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without any creative work are all included in the protection scope of the present application.

[0021] In the examples of the present application, it should be noted that, as used herein, relational terms such as first and second are used to distinguish one entity or operation from another, and do not necessarily require or imply that such an actual relationship or order exists between those entities or operations.

[0022] Furthermore, in the examples of this application, "plurality" means two or more than two, and from this perspective, "plurality" in the examples of this application can also be understood as "at least two." "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and there is no limitation on what is included. For example, when including at least one of A, B, and C, it may include A, B, C, A and B, A and C, B and C, or A, B, and C.

[0023] It should be noted that "connection" in the embodiments of the present application may be understood as an electrical connection, and the connection between two electrical elements may be a direct or indirect connection between the two electrical elements. For example, the connection between A and B may be a direct connection between A and B, or an indirect connection between A and B via one or more other electrical elements.

[0024] A programmable logic circuit based on a look-up table (LUT) is the basic logic module of a programmable logic device. It has advantages such as a short development cycle, low cost, low risk, high integration, and high flexibility, and is widely used in fields such as communications, the Internet, automobiles, and aerospace.

[0025] As shown in Figure 1, this circuit is composed of two four-input lookup tables, multiple multiplexers, and a data selector. It has six inputs (af) and one output (L). This circuit can be used to calculate a five-input function, a limited six-input function, a first-stage arithmetic comparator, or a first-stage adder. When performing an addition operation using this circuit, the carry generation signals of each stage of the adder must all be input from port f. If the carry generation signals are multivariable functions, they cannot be absorbed by the lookup tables, so external logic resources must be used to process the multivariable functions.

[0026] Furthermore, although the lookup table is recursively defined to include one N-input lookup table, two N-1-input lookup tables, and one binary data selector, if the size of the lookup table is simply increased using the technique shown in FIG. 1 to achieve a 6-input lookup table, not only will the inherent efficiency deficiency in addition operations be impossible to overcome, but when used as an arithmetic comparator, it will still only be usable as a comparator, further exacerbating the problem of inefficient resource utilization.

[0027] In view of this, an embodiment of the present application provides a programmable logic circuit, and FIG. 2 is a block diagram showing a module of the programmable logic circuit provided by the embodiment of the present application. As shown in FIG. 2, the programmable logic circuit includes a first lookup table circuit, a second lookup table circuit, a first selection circuit, and a second selection circuit.

[0028] The first lookup table circuit is used to generate and output a first output signal based on the received input signal, and specifically, the value of the first output signal generated by the first lookup table circuit is determined based on the value of the received input signal.

[0029] In some embodiments, FIG. 3 is a schematic diagram of a first lookup table circuit provided by an embodiment of the present application. As shown in FIG. 3, the first lookup table circuit includes: a first five-input lookup table 101 and a third selection circuit; The first to fourth input terminals (A, B, C, D) of the first five-input lookup table 101 are used to receive the first to fourth input signals, respectively, the fifth input terminal E of the first five-input lookup table 101 is used to receive the signal output from the third selection circuit, and the output terminal Y of the first five-input lookup table 101 is used to output the first output signal; The input terminal of the third selection circuit receives the fifth input signal and the carry in signal, and is used to select the fifth input signal or the carry in signal and output it to the fifth input terminal E of the first five-input lookup table 101.

[0030] In the embodiments of the present application, the first lookup table circuit is used to determine the value of a first output signal to be output based on a received input signal. Here, the first lookup table circuit does not use all of the first to fifth input terminals in all applications. For example, when the programmable logic circuit of the embodiments of the present application is used as an adder to add two binary numbers, two input terminals are used to receive the sum and one input terminal is used to receive a carry in signal, and an added sum is output from the output terminal of the first lookup table circuit based on the carry in signal.

[0031] In some embodiments, FIG. 4 is another schematic diagram of the first lookup table circuit provided by the embodiments of the present application. As shown in FIG. 4, the third selection circuit includes a third multiplexer 03, the input terminal of the third multiplexer 03 is used to receive the fifth input signal and the carry in signal, and the output terminal of the third multiplexer 03 is connected to the fifth input terminal E of the first five-input lookup table and is used to select and output the fifth input signal or the carry in signal.

[0032] It should be noted that in the embodiment of the present application, in addition to the third selection circuit being the third multiplexer 03, it is obvious that the third selection circuit may also be designed as other complex circuits having output selection functions, if circuit cost and efficiency are not taken into consideration during the circuit design process.

[0033] The second lookup table circuit is used to generate and output a carry propagation signal and a carry generation signal, respectively, based on the received input signal, and to select and output the carry propagation signal or the carry generation signal as the second output signal; specifically, the value of the carry propagation signal and the value of the carry generation signal are determined based on the value of the input signal received by the second lookup table circuit.

[0034] In some embodiments, FIG. 5 is a schematic diagram of a second lookup table circuit provided by an embodiment of the present application. As shown in FIG. 5, the second lookup table circuit includes a second five-input lookup table 102; The first to fifth input terminals (F, G, H, I, J) of the second five-input lookup table 102 are used to receive the first to fifth input signals, respectively, the first output terminal V of the second five-input lookup table 102 is used to output a carry propagation signal, the second output terminal W of the second five-input lookup table 102 is used to output a carry generation signal, and the third output terminal X of the second five-input lookup table 102 is used to output a second output signal.

[0035] In the embodiment of the present application, the first five-input lookup table 101 and the second five-input lookup table 102 multiplex the first to fifth input signals.

[0036] In an embodiment of the present application, the second lookup table circuit determines the value of a first output signal to be output based on a received input signal, and the second lookup table circuit does not use all of the first to fifth input terminals in all applications. When the programmable logic circuit of an embodiment of the present application is used as an adder to perform two binary additions, the second lookup table circuit uses two input terminals to receive an addition value and one input terminal to receive one input signal in order to select an output signal of the third output terminal of the second lookup table circuit.

[0037] The first selection circuit receives the carry in signal and the carry generate signal, and is used to select and output the carry in signal or the carry generate signal as the carry out signal based on the carry propagate signal.

[0038] In some embodiments, FIG. 6 is a schematic diagram of a first selection circuit provided by an embodiment of the present application. As shown in FIG. 6, the first selection circuit includes a first multiplexer O1, a first input terminal of the first multiplexer O1 is connected to a second output terminal W of the second five-input lookup table 102 and is used to receive a carry generate signal, a second input terminal of the first multiplexer O1 is connected to a third output terminal X of the second five-input lookup table 102 and is used to receive a carry in signal, and a selection terminal of the first multiplexer O1 is connected to a first output terminal V of the second five-input lookup table 102. The first multiplexer 01 is connected to the first multiplexer 01 and is used to receive a carry propagate signal. The output terminal of the first multiplexer 01 is used to select and output the carry generate signal or the carry in signal as the carry out signal based on the carry propagate signal. Specifically, the output terminal of the first multiplexer 01 determines the signal to be output based on the value of the carry propagate signal. For example, if the value of the carry propagate signal is 0, the first multiplexer 01 selects and outputs the carry generate signal as the carry out signal, and if the value of the carry propagate signal is 1, the first multiplexer 01 selects and outputs the carry in signal as the carry out signal.

[0039] The second selection circuit is used to receive the first output signal and the second output signal, and to select and output the first output signal or the second output signal as the third output signal based on the selection output signal.

[0040] In some embodiments, FIG. 7 is a schematic diagram of a second selection circuit provided by an embodiment of the present application. As shown in FIG. 7, the second selection circuit includes a second multiplexer O2; The first input terminal of the second multiplexer 02 is connected to the output terminal Y of the first five-input lookup table 101 and is used to receive the first output signal. The second input terminal of the second multiplexer 02 is connected to the third output terminal X of the second five-input lookup table 102 and is used to receive the second output signal. The selection terminal of the second multiplexer 02 is used to receive the selection output signal. The output terminal of the second multiplexer 02 is used to select and output the first output signal or the second output signal as the third output signal based on the selection output signal. Specifically, the output terminal of the second multiplexer 02 determines the signal to be output based on the value of the selection output signal. For example, if the value of the selection output signal is 0, the second multiplexer 02 selects and outputs the first output signal as the third output signal. If the value of the selection output signal is 1, the second multiplexer 02 selects and outputs the second output signal as the third output signal.

[0041] In the programmable logic circuit provided by the embodiments of the present application, when the programmable logic circuit is used as an adder to perform addition and subtraction operations, the carry generation signal is no longer limited to a single input variable, and addition and subtraction operations of multivariable functions can be performed. This improves the degree of freedom in the layout of the programmable logic device and the utilization efficiency of logic resources in the addition operation mode. In the programmable logic circuit provided by the embodiments of the present application, the first output signal of the first lookup table circuit is the addition operation result, the second output signal of the second lookup table circuit is one of the addends of the addition operation, and the second selection circuit selects either the first output signal or the second output signal. Therefore, the programmable logic circuit can select and output the addition operation result or the sum of the addition operation. Furthermore, in the programmable logic circuit provided in the embodiments of the present application, the first lookup table circuit can directly output the first output signal, the second lookup table circuit can directly output the second output signal, and the second selection circuit can select and output the first output signal or the second output signal as the third output signal, thereby realizing independent outputs of the first lookup table circuit and the second lookup table circuit, and the programmable logic circuit has a maximum of three outputs.

[0042] Hereinafter, an example will be given to explain the application of the programmable logic circuit provided by the embodiment of the present application when it is used as an adder.

[0043] FIG. 8 is a structural schematic diagram of the first five-input lookup table and the second five-input lookup table provided in the embodiment of the present application. As shown in FIG. 8, the first five-input lookup table 101 receives two addends m and n input through the third input terminal C and the fourth input terminal D, and receives a carry-in signal cin through the fifth input terminal E, and performs an addition operation on m and n. The two four-input lookup tables calculate m^n and !(m^n) respectively, and the signal output from the output terminal Y of the first five-input lookup table 101 is the operation result m^n^cin; The second five-input lookup table 102 receives two addends m and n at its third input terminal H and fourth input terminal I, and receives a value 1 at its fifth input terminal J. The two four-input lookup tables respectively calculate a carry propagation signal m^n and a carry generation signal m&&n. The carry generation signal is selected to be output by the first selection circuit only when the carry propagation signal is 0, which indicates that addend m and addend n are equal, and when the carry propagation signal is 0, the carry generation signal is an arbitrary addend. The third output terminal of the second five-input lookup table 102 selects and outputs the carry generation signal based on the received value 1. That is, under the premise that the first lookup table circuit is connected to the second selection circuit, the carry generation signal can be simplified to an arbitrary addend of the addition operation. In the above explanation, "^" indicates XOR, "&&" indicates AND, and "!" indicates NOT.

[0044] Furthermore, depending on the selection output signal of the programmable logic circuit, the third output signal output from the second selection circuit becomes the addition operation result or an arbitrary addend to realize an alternative expression.

[0045] As shown in FIG. 8, the two four-input lookup tables constituting the first five-input lookup table 101 have input terminals labeled a, b, c, and d and an output terminal labeled z, where each symbol is used to easily represent the internal structure of the first five-input lookup table 101 and is used only for describing the embodiments of the present application. Similarly, the two four-input lookup tables constituting the second five-input lookup table 102 have input terminals labeled f, g, h, and i and an output terminal labeled z, where each symbol is used to easily represent the internal structure of the second five-input lookup table 102 and is used only for describing the embodiments of the present application. In some embodiments, FIG. 9 is a schematic diagram of a third selection circuit provided by an embodiment of the present application. As shown in FIG. 9, in the programmable logic circuit provided by the embodiment of the present application, the third multiplexer 03 included in the third selection circuit is further used to receive a cascade input signal and output one of the cascade input signal, the fifth input signal, and the carry input signal to the first lookup table circuit.

[0046] FIG. 10 is another schematic diagram of a second selection circuit provided by an embodiment of the present application. As shown in FIG. 10, in the programmable logic circuit provided by the embodiment of the present application, the second multiplexer 02 included in the second selection circuit is further used to select and output the selected first output signal or the selected second output signal as a cascade output signal.

[0047] The programmable logic circuit provided in the embodiments of the present application further has the dual chain characteristics of a lookup table cascade chain and a carry chain, which allows the programmable logic circuit to function as a dual comparator, thereby improving the efficiency of logic resource utilization of the programmable logic circuit in comparator mode. The dual comparator function of the embodiments of the present application will be described below by way of an example.

[0048] Taking the comparison of X[7:0] > 01000001 and X[7:0] <1000001>0 as an example, the above comparison is realized by providing two cascaded programmable logic circuits. X[7:0] represents the 8-bit binary number of the numerical value X from the upper bit to the lower bit. FIG. 11 is a schematic diagram of a dual comparator by the programmable logic circuit provided by the embodiment of the present application. As shown in FIG. 11, in the first-stage programmable logic circuit, the fourth to first input terminals (I, H, G, F) of the second 5-input lookup table 102 receive the 4-bit binary numbers of X[3:0] respectively. The second 5-input lookup table 102 calculates the truth value of X[3:0] > 0001. The carry generation signal output from the second output terminal W indicates the truth value of X[3:0] > 0001. When the carry generation signal is 1, it indicates that X[3:0] > 0001 is true. When the carry generation signal is 0, it indicates that X[3:0] > 0001 is false. When the carry propagation signal value output from the first output terminal V of the second 5-input lookup table 102 is 0, the first selection circuit selects and outputs the carry generation signal based on the carry propagation signal, functioning as the carry input signal of the second-stage programmable logic circuit. In the first-stage programmable logic circuit, the fourth to first input terminals (D, C, B, A) of the first 5-input lookup table 101 receive the 4-bit binary numbers of X[3:0]. The first 5-input lookup table 101 calculates the truth value of X[3:0] < 0010. When the first output signal value output from the output terminal Y of the first 5-input lookup table 101 is 1, it indicates that X[3:0] < 0010 is true. When the first output signal value is 0, it indicates that X[3:0] < 0010 is false. When the selection output signal value of the second selection circuit is 1, the second selection circuit selects and outputs the first output signal, functioning as the cascaded input signal of the second-stage programmable logic circuit. As shown in FIG. 11, in the second-stage programmable logic circuit, for the second 5-input lookup table 102, the fourth to first input terminals (I, H, G, F) receive four binary numbers of X[7:4]. The second 5-input lookup table 102 calculates the truth value of the carry propagation signal X[7:4]=0100 (indicating equality comparison) and outputs it from the first output port V to the first selection circuit. The second 5-input lookup table 102 calculates the truth value of the carry generation signal X[7:4]>0100 and outputs it from the second output port W to the first selection circuit. The first selection circuit determines whether to output the carry generation signal based on the value of the carry propagation signal or output the carry input signal (X[3:0]>0001) from the first-stage programmable logic circuit. For example, when the carry propagation signal is 0, the carry generation signal is output; when the carry propagation signal is 1, the carry input signal from the first-stage programmable logic circuit is output. Taking the case where the carry propagation signal is 0 and the carry generation signal is 1 as an example, the first selection circuit outputs the carry generation signal, indicating that X[7:0]>01000001 is true. In the second-stage programmable logic circuit, for the first 5-input lookup table 101, the fourth to first input terminals (D, C, B, A) receive four binary numbers of X[7:4]. The fifth input terminal of the first 5-input lookup table 101 receives the cascade input signal (X[3:0]<0010) from the first-stage programmable logic circuit. The first 5-input lookup table 101 calculates the result of the comparator X[7:0]<1000001>0 through the 5-input function (X[7:4]==1000)?(X[3:0]<0010):(X[7:4]<1000). The above formula outputs the truth value of X[3:0]<0010 when X[7:4]==1000 is true, and outputs the truth value of X[7:4]<1000 when X[7:4]==false. The second selection circuit selects and outputs the comparison result as the cascade output signal. When the selection output signal received by the second selection circuit is 1, it indicates that the second selection circuit selects and outputs the output signal of the first 5-input lookup table 101.

[0049] In some embodiments, FIG. 12 is another schematic diagram of the second lookup table circuit provided by the embodiments of the present application, and as shown in FIG. 12 , the second lookup table circuit further includes a fourth selection circuit used to receive a fifth input signal and a cascade input signal, and select and output the fifth input signal or the cascade input signal.

[0050] When the programmable logic circuit provided in the embodiments of the present application is provided with a plurality of the programmable logic circuits and cascaded, the cascade input signal is input by a first lookup table circuit and a second lookup table circuit, and the cascade output signal is output by a second selection circuit, thereby improving the interconnection delay between the programmable logic circuits.

[0051] In some embodiments, FIG. 13 is yet another schematic diagram of a second lookup table circuit provided by an embodiment of the present application. As shown in FIG. 13, the fourth selection circuit is further used to receive a sixth input signal, and select one of the sixth input signal, the fifth input signal, and the cascade input signal to output to the fifth input terminal of the second five-input lookup table 102.

[0052] In some embodiments, FIG. 14 is a schematic diagram of a fourth selection circuit provided by an embodiment of the present application. As shown in FIG. 14, the fourth selection circuit includes a fourth multiplexer 04, a first input terminal of the fourth multiplexer 04 is used to receive a fifth input signal, a second input terminal of the fourth multiplexer 04 is used to receive a sixth input signal, a third input terminal of the fourth multiplexer 04 is used to receive a cascade input signal, and an output terminal of the fourth multiplexer 04 is used to select one of the fifth input signal, the sixth input signal, and the cascade input signal and output it to a fifth input terminal J of the second five-input lookup table 102.

[0053] The programmable logic circuit provided in the embodiments of the present application adds input variables of a first lookup table circuit and a second lookup table circuit, and the programmable logic circuit has a maximum of seven input variables (the input variables include the first to sixth input signals, the carry input signal, and the cascade input signal).

[0054] In some embodiments, the programmable logic circuit provided by the embodiments of the present application has the selection ends of the third multiplexer 03 and the fourth multiplexer 04 programmed to control the signals output from their output ends, and the programming methods of the selection ends include at least SRAM programming, Flash programming, fuse programming, and anti-fuse programming. Specifically, the programming methods of the multiplexer selection ends are conventional methods and will not be repeated in this application.

[0055] FIG. 15 is a structural schematic diagram of a programmable logic circuit provided by an embodiment of the present application. Based on the programmable logic circuit shown in FIG. 15, the function of any one of the programmable logic circuits described above can be realized.

[0056] In addition, in the programmable logic circuit provided by the embodiments of the present application, the first to sixth input signals and the selection output signal may be transferred from an external module / circuit to the programmable logic circuit by providing corresponding circuit ports, and the first output signal, the second output signal, and the third output signal of the programmable logic circuit may be transferred to corresponding circuit ports to interact with an external circuit. Similarly, the carry in signal, the carry out signal, the cascade in signal, and the cascade out signal may also be provided with corresponding ports to realize connections between adjacent programmable logic circuits.

[0057] In the programmable logic circuit provided in the embodiments of the present application, when the programmable logic circuit is used as an adder to perform addition and subtraction operations, the carry generation signal is not limited to a single input variable, and addition and subtraction operations of multivariable functions can be performed. This improves the degree of freedom in the placement of the programmable logic device in addition operation mode and improves the utilization efficiency of logic resources. In the programmable logic circuit provided by the embodiments of the present application, the first output signal of the first lookup table circuit is the addition operation result, and the second output signal of the second lookup table circuit is one of the addends of the addition operation, and the second selection circuit selects and outputs the first output signal or the second output signal, so that the programmable logic circuit can select whether to output the addition operation result or the sum of the addition operation; In the programmable logic circuit provided by the embodiments of the present application, the first lookup table circuit can directly output the first output signal, the second lookup table circuit can directly output the second output signal, the second selection circuit can select and output the first output signal or the second output signal as the third output signal, thereby realizing the independent outputs of the first lookup table circuit and the second lookup table circuit, and the programmable logic circuit can have a maximum of three outputs; Furthermore, the programmable logic circuit provided in the embodiments of the present application further has a dual chain characteristic of a lookup table cascade chain and a carry chain, which allows the programmable logic circuit to function as a dual comparator, thereby improving the efficiency of logic resource utilization of the programmable logic circuit in comparator mode. The dual comparator function of the embodiments of the present application will be described below with an example.

[0058] Furthermore, in the programmable logic circuit provided by the embodiments of the present application, when a plurality of the above-mentioned programmable logic circuits are provided for cascading, the cascade input signal is input by the first lookup table circuit and the second lookup table circuit, and the cascade output signal is output by the second selection circuit, thereby improving the interconnection delay between the programmable logic circuits.

[0059] Furthermore, in the programmable logic circuit provided by the embodiments of the present application, input variables of the first lookup table circuit and the second lookup table circuit are added, so that the programmable logic circuit can have a maximum of seven input variables.

[0060] Although the above description has been provided in further detail in conjunction with specific embodiments, the specific implementation of the present application is not limited to these descriptions. Various simple inferences and substitutions made by those skilled in the art without departing from the concept of the present application shall all fall within the scope of protection of the present application.

Claims

1. A programmable logic circuit that is a basic logic module constituting a programmable logic device, comprising: a first look-up table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating and outputting a carry propagation signal and a carry generation signal based on a received input signal, and for selecting and outputting either the carry propagation signal or the carry generation signal as a second output signal based on the received input signal; a first selection circuit that receives a carry in signal and the carry generate signal, and selects and outputs either the carry in signal or the carry generate signal as a carry out signal based on the carry propagate signal; a second selection circuit that receives the first output signal and the second output signal, and selects and outputs the first output signal or the second output signal as a third output signal based on a selection output signal.

2. the first lookup table circuit includes a first five-input lookup table and a third selection circuit; a first input terminal to a fourth input terminal of the first five-input lookup table are used to receive first to fourth input signals, respectively; a fifth input terminal of the first five-input lookup table is used to receive a signal output from the third selection circuit; and an output terminal of the first five-input lookup table is used to output the first output signal; 2. The programmable logic circuit of claim 1, wherein the third selection circuit receives a fifth input signal and the carry in signal and is used to select and output either the fifth input signal or the carry in signal.

3. the third selection circuit is further used to receive a cascade input signal, and to select one of the cascade input signal, the fifth input signal, and the carry input signal to output to a fifth input end of the first five-input lookup table; 3. The programmable logic circuit of claim 2, wherein the second selection circuit is further used to select either the first output signal or the second output signal as a cascade output signal.

4. the second lookup table circuit includes a second five-input lookup table; 2. The programmable logic circuit of claim 1, wherein first to fourth input terminals of the second five-input lookup table are used to receive first to fourth input signals, respectively, a fifth input terminal of the second five-input lookup table is used to receive a fifth input signal, a first output terminal of the second five-input lookup table is used to output the carry propagation signal, a second output terminal of the second five-input lookup table is used to output the carry generation signal, and a third output terminal of the second five-input lookup table is used to output the second output signal.

5. the second lookup table circuit further includes a fourth selection circuit; 5. The programmable logic circuit of claim 4, wherein the fourth selection circuit receives the fifth input signal and the cascade input signal, and is used to select and output the fifth input signal or the cascade input signal, and the signal output from the fourth selection circuit is used to determine the signal output from the third output terminal of the second five-input lookup table.

6. 6. The programmable logic circuit of claim 5, wherein the fourth selection circuit is further used to receive a sixth input signal and select one of the sixth input signal, the fifth input signal, and the cascade input signal to output to a fifth input terminal of the second five-input lookup table.

7. the first selection circuit includes a first multiplexer; a first input terminal of the first multiplexer is used to receive the carry generate signal, a second input terminal of the first multiplexer is used to receive the carry in signal, a select terminal of the first multiplexer is used to receive the carry propagate signal, and an output terminal of the first multiplexer is used to select and output the carry generate signal or the carry in signal as a carry out signal based on the carry propagate signal; the second selection circuit includes a second multiplexer; 2. The programmable logic circuit of claim 1, wherein a first input terminal of the second multiplexer is used to receive the first output signal, a second input terminal of the second multiplexer is used to receive the second output signal, a select terminal of the second multiplexer is used to receive the select output signal, and an output terminal of the second multiplexer is used to select and output either the first output signal or the second output signal as a third output signal based on the select output signal.

8. the third selection circuit includes a third multiplexer; 4. The programmable logic circuit of claim 3, wherein a first input of the third multiplexer is used to receive the fifth input signal, a second input of the third multiplexer is used to receive the carry in signal, a third input of the third multiplexer is used to receive the cascade in signal, and an output of the third multiplexer is used to select one of the fifth input signal, the carry in signal, and the cascade in signal for output to a fifth input of the first five-input lookup table.

9. the fourth selection circuit includes a fourth multiplexer; 7. The programmable logic circuit of claim 6, wherein a first input of the fourth multiplexer is used to receive the fifth input signal, a second input of the fourth multiplexer is used to receive the sixth input signal, a third input of the fourth multiplexer is used to receive the cascade input signal, and an output of the fourth multiplexer is used to select one of the fifth input signal, the sixth input signal, and the cascade input signal for output to a fifth input of the second five-input lookup table.

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