Backside wafer modification

Abstract

The method can include acquiring characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values ​​for the wafer. The wafer can have a frontside, a backside opposite the frontside, and a set of regions. The set of stress values ​​can include a first stress value corresponding to a first region. In the processed state, one or more frontside processes can be completed on the frontside of the wafer. The method can include determining that the first stress value exceeds a stress threshold and, in response to the determining and based on the characteristic data, creating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating formation of a first trench on the backside in the first region of the wafer based on the compensation map.

Description

[Technical Field]

[0001] The present disclosure relates to wafer manufacturing, and more particularly to backside wafer modification. [Background technology]

[0002] Wafer fabrication can involve performing a series of processing steps on a wafer, e.g., a silicon wafer, to create a set of dies, where each die can include at least one electronic circuit, including operations performed on the front side and operations performed on the back side of the wafer. Summary of the Invention [Means for solving the problem]

[0003] According to an embodiment of the present disclosure, a method can include acquiring characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state. The characteristic data can include a set of stress values for the wafer in the processed state. The wafer can have a frontside, a backside opposite the frontside, and a set of regions. The set of stress values includes a first stress value. The first stress value corresponds to a first region of the set of regions. In the processed state, one or more frontside processes can be completed on the frontside of the wafer. The method can include determining that the first stress value exceeds a stress threshold. The method can include generating a compensation map in response to the determining and based on the characteristic data. The compensation map can identify one or more regions of the set of regions for forming one or more trenches. The method can include initiating forming a first trench on the backside in the first region of the wafer based on the compensation map.

[0004] An embodiment of the present disclosure can be exemplified as a device having a wafer. The wafer can have a frontside and a backside. The frontside can be configured to receive frontside processing features. The frontside processing features can form one or more electronic circuits. The backside can be opposite the frontside. The backside can include a backside surface and a first set of trenches. The first set of trenches can include a first trench and a second trench. The first trench can be substantially parallel to the second trench. The first trench and the second trench can extend substantially perpendicularly from the backside surface toward the frontside.

[0005] An embodiment of the present disclosure can be exemplified as a device having a wafer having a front side and a back side opposite the front side. The front side can include front side processing features. The front side processing features include a first set of deep trenches and a second set of deep trenches. Between the first set of deep trenches and the second set of deep trenches, gap The deep trench may be gap The backside may comprise a backside surface and a first set of trenches. The first set of trenches may comprise a first trench and a second trench. The first trench may be substantially parallel to the second trench. The first trench and the second trench may extend substantially perpendicularly from the backside surface toward the frontside. The first set of trenches may comprise the gap and between the first set of deep trenches and the second set of deep trenches.

[0006] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0007] The drawings included in this application are incorporated in and constitute a part of this specification. They illustrate embodiments of the present disclosure and, together with the detailed description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of certain embodiments and are not intended to limit the disclosure. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 illustrates an example computing environment having a wafer modification system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 illustrates a flow chart diagram of an exemplary method for performing backside wafer modification according to an embodiment of the present disclosure. [Figure 3A] FIG. 3A illustrates a top view representation of a wafer included in a compensation map according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B illustrates a cross-sectional view of the wafer illustrated in FIG. 3A before the wafer is in a processed state, where the wafer has a backside trench according to an embodiment of the present disclosure. [Figure 3C] FIG. 3C illustrates the wafer of FIG. 3B in an as-processed state, according to an embodiment of the present disclosure. [Figure 3D] FIG. 3D illustrates the wafer of FIG. 3B with material introduced into the backside trenches according to an embodiment of the present disclosure. [Figure 3E] FIG. 3E illustrates the wafer of FIG. 3D in an as-processed state, according to an embodiment of the present disclosure. [Figure 3F] FIG. 3F illustrates a cross-sectional view of the wafer illustrated in FIG. 3A in an as-processed state, according to an embodiment of the present disclosure. [Figure 3G] FIG. 3G illustrates the wafer of FIG. 3F with a backside trench according to an embodiment of the present disclosure. [Figure 3H]FIG. 3H illustrates a cross-sectional view of the wafer shown in FIG. 3A before the wafer is in a processed state, where the wafer has material introduced into the backside trenches according to an embodiment of the present disclosure. [Figure 3I] FIG. 3I illustrates the wafer of FIG. 3H in an as-processed state, according to an embodiment of the present disclosure. [Figure 4] FIG. 4 illustrates exemplary major components of a computer system that can be used in accordance with embodiments of the present disclosure.

[0009] While the invention is susceptible to various modifications and alternative forms, specific details thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Aspects of the present disclosure relate to wafer manufacturing, and more particularly to the modification of backside wafers. While the present disclosure is not necessarily limited to such applications, various aspects of the present disclosure may be understood through the description of various examples using this context.

[0011] Wafer fabrication can involve performing a series of processing steps on a wafer, such as a silicon wafer, to create a set of dies, each of which can include at least one electronic circuit. The processing steps can include operations performed on the front side of the wafer and operations performed on the back side. For example, in some embodiments, front side processing steps can include etching and deposition processes to form features, such as circuit layers, conductive traces, and transistors, on the front side of the wafer. In some cases, back side processing steps can include polishing to modify the thickness of the wafer and polishing or application of materials, or a combination thereof, to repair wafer damage caused by such polishing. In some cases, one or more of the front side operations can induce stress within the wafer. Such stress can cause the wafer to curve, such that one or more regions of the wafer deviate from a threshold flatness.

[0012] The wafer curvature can contribute to various problems in subsequent front-side processing operations. For example, front-side processing operations can include deep trench etching (e.g., an etching process to form a front-side trench that extends beyond a buried insulator layer in a silicon-on-insulator process). In some cases, such deep trench etching can induce stresses that cause one or more regions of the wafer to bow. The wafer irregularities caused by the wafer bow can result in undesirable variations in the wafer. For example, in some cases, a straight line pattern to be transferred to the wafer may appear as a curve in the wafer due to the wafer irregularities. In other cases, such non-uniformities can cause some regions of the wafer to lose more material than other regions. Therefore, the wafer bow can result in die defects.

[0013] To address these and other challenges, embodiments of the present disclosure include a wafer modification system. In some embodiments, the wafer modification system can predict whether stresses induced by frontside processing operations may cause wafer bow. In response to a prediction that wafer bow may occur, the wafer modification system can initiate the formation of one or more backside trenches to reduce such predicted bow. In particular, the wafer modification system can create a compensation map based on characterization data for the wafer. The compensation map can identify one or more regions of the wafer where forming a set of backside trenches can compensate for stresses that may contribute to wafer bow. The wafer modification system can initiate the formation of the set of backside trenches based on the compensation map. In some embodiments, the formation of the set of backside trenches can occur before the wafer is processed (e.g., before one or more frontside processes are completed on the front side of the wafer).

[0014] By creating a compensation map, embodiments of the present disclosure can reduce wafer bow in an efficient manner tailored to the characteristics of the particular wafer being processed. For example, embodiments of the present disclosure can initiate backside trench formation in specific instances where wafer bow is predicted to occur and in specific areas of the wafer that can reduce the wafer bow. Additionally, by forming a set of backside trenches before the wafer is in a processed state, embodiments of the present disclosure can proactively address predicted wafer bow. Such a preventative approach can prevent wafer bow during subsequent frontside processing operations performed on the wafer. As a result, embodiments of the present disclosure can reduce die defects.

[0015] In some embodiments, based on the characterization data of the wafer, the wafer modification system can select one or more regions of the wafer for backside trench modification in light of thermal considerations. For example, in some embodiments, such regions can include regions where temperatures, e.g., the operating temperatures of the dies of the wafer, are predicted to exceed a temperature threshold. In some embodiments, such regions can be selected to improve thermal variations on a given die by locally improving heat transfer. In some embodiments, such regions can be selected to increase thermal isolation between portions of a given die, resulting in improved thermal characteristics of sensitive chip areas. Thus, embodiments of the present disclosure can improve the operating performance of one or more dies of the wafer in light of thermal considerations.

[0016] Turning to the figures, Figure 1 illustrates a computing environment 100 comprising one or more of a wafer modification system 110, a wafer processing device 150, a computing device 170, or a network 180, or any combination thereof. In some embodiments, at least one wafer modification system 110, a wafer processing device 150, or a computing device 170, or any combination thereof, can exchange data with at least one other over at least one network 180. One or more of the wafer modification system 110, a wafer processing device 150, a computing device 170, or a network 180, or any combination thereof, can comprise a computer system, such as the computer system 401 described with respect to Figure 4.

[0017] In some embodiments, the wafer modification system 110 can be included in software installed on at least one computer system of the computing device 170 or the wafer processing device 150, or a combination thereof. For example, in some embodiments, the wafer modification system 110 can be provided as a plug-in software component of software installed on the wafer processing device 150. The wafer modification system 110 can include program instructions that are executed by a processor, such as the processor of the wafer processing device 150, to perform one or more of the operations described with respect to Figures 2-3I.

[0018] In some embodiments, wafer modification system 110 may include one or more modules, such as data manager 120, compensation map generator 130, or device manager 140, or a combination thereof. In some embodiments, data manager 120, compensation map generator 130, or device manager 140, or a combination thereof, may be integrated into a single module. In some embodiments, data manager 120 may acquire, interpret, analyze, store, or initiate storage of data, such as wafer characteristic data, or a combination thereof. In some embodiments, compensation map generator 130 may interpret, analyze, or a combination thereof data, such as characteristic data, and generate one or more compensation maps. In some embodiments, wafer modification system 110 may include software for performing structural or thermal analysis, or a combination thereof, of wafer characteristic data. In some embodiments, device manager 140 may send one or more commands to one or more wafer processing devices 150. For example, in some embodiments, device manager 120 can send commands to an etching device to form a set of backside trenches in wafer 160 based on the compensation map. In some embodiments, one or more of data manager 120, compensation map generator 130, or device manager 140, or a combination thereof, can comprise program instructions executed by a processor, such as a processor of wafer processing device 150, to perform one or more of the operations described with respect to Figures 2-3I. For example, in some embodiments, data manager 120 can comprise program instructions to perform operations 210 and 220 of Figure 2. In some embodiments, compensation map generator 130 can comprise program instructions to perform operations 230 and 240 of Figure 2.In some embodiments, device manager 140 may include program instructions for performing operations 250 and 260 of FIG.

[0019] In some embodiments, the one or more wafer processing devices 150 may comprise a set of machines or apparatuses, or a combination thereof, configured to perform processes, such as photolithography, etching, deposition, etc., to form electronic circuits on the wafer 160. In some embodiments, the one or more wafer processing devices 150 may be configured to form backside trenches on the wafer 160, or to introduce one or more materials into the backside trenches of the wafer 160, or a combination thereof, in response to one or more commands issued by the wafer modification system 110. In some embodiments, the wafer modification system 110 may initiate the introduction of such materials to provide the wafer 160 with predetermined structural support, heat transfer properties, or a combination thereof. The wafer 160 may refer to a substrate on which a set of electronic circuits may be formed. The wafer 160 may be composed of a semiconductor material, such as silicon. The wafer 160 may be separated into a set of dies, where each die comprises at least one electronic circuit.

[0020] In some embodiments, one or more computing devices 170 may comprise a computer or a server. For example, in some embodiments, one or more computing devices 170 may comprise a computer of an entity that operates wafer processing device 150, e.g., a fabrication facility. One or more computing devices 170 may be configured to store, process, or both store and process data, e.g., characteristic data, about wafer 160. In some embodiments, one or more computing devices 170 may provide such characteristic data to wafer modification system 110. In some embodiments, network 180 may be a wide area network (WAN), a local area network (LAN), the Internet, or an intranet.

[0021] 2 illustrates a flowchart of an exemplary method 200 for performing backside wafer modification according to an embodiment of the present disclosure. Method 200 can be performed by a wafer modification system, such as wafer modification system 110, described with respect to FIG.

[0022] In operation 210, the wafer modification system may acquire characteristic data about the wafer. In some embodiments, the characteristic data may include information about the wafer to be manufactured. For example, in some embodiments, the characteristic data may include design data about the wafer, such as components (e.g., transistors) to be formed and their locations on the wafer; materials to be included on the wafer and their corresponding properties; features (e.g., front-side trenches) to be formed and their dimensions, locations on the wafer, or quantities, or combinations thereof. In some embodiments, the characteristic data may include characteristics of the wafer in an as-processed state (e.g., stress values or temperature values, or a combination thereof). The as-processed state may refer to the state of the wafer after one or more front-side processes have been completed on the front side of the wafer. For example, in some embodiments, the as-processed state may refer to the state after front-end-of-line processes (e.g., deep-trench etching) or back-end-of-line processes (e.g., metallization layer deposition) have been completed on the wafer. In some embodiments, the processed state can refer to the state after the wafer has been separated into dies. In these embodiments, the characteristic data can include one or more temperature values associated with the die components during operation of the components. For example, in some embodiments, the characteristic data can include predicted operating temperatures of diodes formed on the dies of the wafer.

[0023] In some embodiments, operation 210 may include the wafer modification system obtaining characteristic data from a source, such as a computing device (e.g., computing device 170, FIG. 1) or a wafer processing device (e.g., wafer processing device 150, FIG. 1), or a combination thereof. In some embodiments, operation 210 may include the wafer modification system creating characteristic data. For example, in some embodiments, the wafer modification system may use structural analysis or thermal analysis tools, or a combination thereof, to analyze design data for the wafer. Based on such analysis, the wafer modification system may calculate one or more stress values or temperature values, or a combination thereof, corresponding to the wafer in an as-processed state. Furthermore, based on such analysis, the wafer modification system may determine one or more regions of the wafer that may have such stress values or temperature values, or a combination thereof.

[0024] In operation 220, the wafer modification system may obtain threshold data. In some embodiments, the threshold data may include one or more parameter values that the wafer modification system can use to predict whether wafer bow will occur. For example, in some embodiments, the threshold data may include a stress threshold. In this example, a wafer stress value that exceeds the stress threshold may indicate that wafer bow is likely to occur in response to one or more front-side processing operations. Thus, in this example, the wafer modification system may predict that wafer bow will likely occur in response to determining that the wafer stress value exceeds the stress threshold. In some embodiments, the threshold data may include one or more parameter values that the wafer modification system may use to predict operational characteristics of components formed from the wafer. For example, in some embodiments, the threshold data may include a temperature threshold for the set of transistors formed on a die of the wafer. In this example, operating temperature values for the set of transistors that exceed a temperature threshold may indicate excessive operating temperatures of the die. Thus, in this example, the wafer modification system may predict defective operation of the die in response to determining that an operating temperature value exceeds a temperature threshold.

[0025] In some embodiments, the threshold data can be predetermined by an entity of the wafer modification system, such as a programmer or an operator. In some embodiments, the wafer modification system can obtain the threshold data from a source, such as a web server of a third-party company, that stores data regarding previous structural or thermal analyses of wafers or components of wafers, or combinations thereof.

[0026] In operation 230, the wafer modification system may determine whether the threshold value obtained in operation 220 has been exceeded based on the characteristic data obtained in operation 210. For example, in some embodiments, operation 230 may include the wafer modification system comparing the stress value obtained in operation 210 to the stress threshold value obtained in operation 220 to determine whether the stress value exceeds the stress threshold value. If the wafer modification system determines that the characteristic data exceeds the threshold data, the wafer modification system may proceed to operation 240. Otherwise, if the wafer modification system determines that the characteristic data does not exceed the threshold data, method 200 may end.

[0027] In operation 240, the wafer modification system may create a compensation map. The compensation map may include a set of specifications for forming one or more backside trenches on the wafer. In some embodiments, the set of specifications may include information for one or more backside trenches, such as dimensions, quantity, or formation locations (e.g., areas of the wafer where the backside trenches are to be formed), or a combination thereof. In some embodiments, the compensation map may include a visual representation of the wafer (e.g., a computer model, or a set of images of the wafer, or a combination thereof). In these embodiments, such a visual representation may be displayed on a screen of a computing device or a processing device, or a combination thereof. The visual representation may facilitate a user's ability to view the characteristics of the wafer and interpret the set of specifications for forming one or more backside trenches in the wafer.

[0028] In some embodiments, the wafer modification system can generate a compensation map based, at least in part, on the characteristic data obtained in operation 210. For example, in some embodiments, the characteristic data can include a set of stress values corresponding to a respective set of regions of the wafer in an as-processed state. In this example, the wafer modification system can predict that wafer bow is likely to occur in each region of the set of regions in response to performing operation 230. In response, the wafer modification system can generate, for each region, specifications for forming one or more backside trenches that can reduce stress in the wafer. By reducing such stress, the wafer modification system can reduce the degree of bow in each region. In this example, the wafer modification system can generate specifications by analyzing design data or characteristics, or a combination thereof, of the wafer in an as-processed state using structural analysis tools. Through such analysis, the wafer modification system can determine specifications that can reduce wafer bow.

[0029] In some embodiments, operation 240 may include the wafer modification system considering additional structural or thermal effects, or a combination thereof, resulting from forming backside trenches in the wafer. For example, in some embodiments, the wafer modification system may create a set of specifications for forming one or more backside trenches, in which structural support regions are disposed between the one or more backside trenches and one or more frontside processing features (e.g., frontside trenches) of the wafer. In these embodiments, the wafer modification system may specify dimensions of the structural support regions such that a threshold stiffness or flexibility can be maintained in the wafer. Such threshold stiffness or flexibility may enable the wafer, or dies on the wafer, or a combination thereof, to withstand forces that might otherwise cause physical damage to the wafer, or dies on the wafer, or a combination thereof.

[0030] In some embodiments, operation 240 may include the wafer modification system selecting a material to be introduced into one or more backside trenches. Such introduction of a material may enable the wafer modification system to further adjust the structural or thermal properties, or a combination thereof, of the wafer. In some embodiments, the introduction of a material may also prevent undesired materials from accumulating within the backside trenches. In some embodiments, the wafer modification system may select a material based, at least in part, on one or more stress values or one or more temperature values, or a combination thereof, included in the property data obtained in operation 210. For example, in some embodiments, the wafer modification system may select a material that, when introduced into one or more backside trenches, can reduce the stress value of the wafer while improving the heat transfer characteristics of the wafer, or of a die of the wafer, or a combination thereof. In some embodiments, the wafer modification system may select a material, such as gold, lead, aerogel, or carbon, to modify the stress or stiffness, or a combination thereof, of the wafer. In some embodiments, the wafer modification system can select a material, such as copper or aluminum, to increase thermal conductivity, and the wafer modification system can select an insulating material, such as gas, oil, or aerogel, to decrease thermal conductivity.

[0031] In operation 250, the wafer modification system can initiate the formation of one or more backside trenches based on the compensation map created in operation 240. In some embodiments, operation 250 can include the wafer modification system issuing one or more commands to one or more processing devices (e.g., wafer processing device 150, FIG. 1 ) to form one or more backside trenches. In some embodiments, such commands can include instructions to form one or more backside trenches before the wafer is in a processed state (e.g., before one or more frontside processes are completed on the front side of the wafer). For example, in some embodiments, such commands can include instructions to form a set of backside trenches before a processing device performs a deep trench etch on the front side of the wafer. In this way, the wafer modification system can proactively compensate for frontside process-induced stresses that are predicted to cause wafer bow. In some embodiments, such commands can include instructions to a processing device to form a set of backside trenches after the wafer is in a processed state. In these embodiments, the wafer modification system can form a set of backside trenches to alter the expected operating temperature of components formed from the wafer or to reduce stresses that may arise after frontside processing (e.g., stresses due to thermal expansion or die packaging, or a combination thereof).

[0032] In operation 260, the wafer modification system may begin introducing a material into one or more of the backside trenches formed in operation 250. Such introduction of a material may be based on the compensation map created in operation 240. In some embodiments, operation 260 may include the wafer modification system issuing one or more commands to one or more processing devices (e.g., wafer processing device 150, FIG. 1 ) to insert a material into the one or more backside trenches. In some embodiments, the one or more processing devices may introduce the material into the one or more backside trenches through a deposition process. In some embodiments, such commands may include instructions to insert the material before the wafer is in a processed state. In this manner, the wafer modification system may proactively compensate for stress or temperature gradients, or a combination thereof, induced by frontside processing. In some embodiments, such commands may include instructions to insert the material after the wafer is in a processed state. In these embodiments, the wafer modification system can adjust the set of backside trenches to change the expected operating temperature of components formed from the wafer, or to reduce stresses that may develop after frontside processing, or a combination thereof.

[0033] 3A-3I illustrate a wafer according to an embodiment of the present disclosure. The figures are not drawn to scale, and features included in these figures are shown enlarged for clarity. Moreover, the number of features / regions, the shapes of the features / regions, the locations of the features / regions, and the relationships between the features / regions (e.g., relative positions, relative sizes, etc.) are shown for illustrative purposes and are not to be construed as limiting.

[0034] 3A illustrates a top-view representation 300 of a wafer 302 included in a compensation map according to an embodiment of the present disclosure. The wafer 302 has a frontside 305 opposite a backside (not shown). The representation 300 shows regions 320 and 325 of the wafer 302 where the wafer modification system can initiate backside trench formation to compensate for stress induced by frontside processing operations on the wafer 302. The representation 300 also illustrates regions 310, 315, 330, and 335 of the wafer 302 where the wafer modification system can initiate backside trench formation to alter the thermal characteristics (e.g., operating temperature) of the die of the wafer 302.

[0035] FIG. 3B illustrates a cross-sectional view of the wafer 302 illustrated in FIG. 3A before the wafer 302 is in a processed state (e.g., before one or more frontside processes are completed on the frontside 340 of the wafer 302). A set of backside trenches 350 is formed on the backside 345 of the wafer 302 and within region 320 according to an embodiment of the present disclosure. The set of backside trenches 350 includes multiple trenches that are substantially parallel to one another. Spaces 352 horizontally separate each of the multiple trenches from another trench. In some embodiments, such spaces 352 have substantially equal widths. Additionally, the set of backside trenches 350 extends substantially vertically from the backside surface 312 of the backside 345 toward the frontside 340 of the wafer 302.

[0036] FIG. 3C illustrates the wafer 302 of FIG. 3B in an as-processed state, according to an embodiment of the present disclosure. In FIG. 3C, front-side processing features 355 including multiple sets of deep trenches 360 are formed on the frontside 340 of the wafer 302. In some embodiments, the frontside processing features 355 can include functions such as conductive traces, metallization layers, and transistors. The frontside processing features 355 including multiple sets of deep trenches 360 can form one or more electronic circuits on the frontside 340 of the wafer 302. FIG. 3C illustrates the frontside processing features 355 including multiple sets of deep trenches 360 formed after the set of backside trenches 350 has been formed. The wafer 302 additionally includes a structural support region 365 disposed between the multiple sets of deep trenches 360 and the set of backside trenches 350. More specifically, structural support regions 365 are disposed below the sets of deep trenches 360 and above both the backside surface 312 and the set of backside trenches 350. The trenches do not extend into the structural support regions 365. The wafer 302 also has a plurality of trenches 360 between the sets of deep trenches 360. gap 362. Deep trench is gap 362. FIG. gap 362. In some embodiments, such a configuration can reduce the predicted bow of the wafer 302.

[0037] 3D illustrates the wafer 302 of FIG. 3B having a material 390 introduced into the set of backside trenches 350 according to an embodiment of the present disclosure. In some embodiments, the material 390 can substantially fill the set of backside trenches 350 (e.g., the material 390 can fill at least about 90 percent of the volume of each of the backside trenches). In some embodiments, the material 390 can include gold, lead, aerogel, or carbon.

[0038] 3E illustrates the wafer 302 of FIG. 3D in an as-processed state, according to an embodiment of the present disclosure. FIG. 3E illustrates a front-side processing feature 355 comprising multiple sets of deep trenches 360 formed after material 390 has been introduced into the set of back-side trenches 350.

[0039] 3F illustrates a cross-sectional view of the wafer 302 illustrated in FIG. 3A in an as-processed state, according to an embodiment of the present disclosure. Accordingly, frontside processing features 375 (e.g., conductive traces, metallization layers, transistors, etc.) are formed on the frontside 340 of the wafer 302. The frontside processing features 375 may form one or more electronic circuits on the frontside 340 of the wafer 302. Regions 310 and 315 represent regions where the wafer modification system may begin forming backside trenches on the backside 345 of the wafer, according to an embodiment of the present disclosure.

[0040] FIG. 3G illustrates the wafer 302 of FIG. 3F having multiple sets of backside trenches 380 according to an embodiment of the present disclosure. The multiple sets of backside trenches 380 are formed in the backside 345 of the wafer 302 in regions 310 and 315. FIG. 3G shows the multiple sets of backside trenches 380 formed after frontside processing features 375 are formed in the frontside 340 of the wafer 302. The multiple sets of backside trenches 380 include multiple trenches that are substantially parallel to one another. Spaces 377 horizontally separate each of the multiple trenches from another trench. In some embodiments, such spaces 377 have substantially equal widths. Additionally, the multiple sets of backside trenches 380 extend substantially vertically from the backside surface 312 of the backside 345 toward the frontside 340 of the wafer 302. Wafer 302 additionally includes structural support regions 385 disposed between frontside processing features 375 and the plurality of sets of backside trenches 380. More specifically, structural support regions 385 are disposed below frontside processing features 375 and above both backside surface 312 and the plurality of sets of backside trenches 380.

[0041] 3H illustrates a cross-sectional view of the wafer 302 illustrated in FIG. 3A before the wafer 302 is in a processed state. Sets of backside trenches 380 are formed in the backside 345 of the wafer 302 and within regions 310 and 315. A material 395 is introduced into the sets of backside trenches 380 according to embodiments of the present disclosure. In some embodiments, the material 395 can substantially fill the sets of backside trenches 380 (e.g., the material 395 can fill at least about 90 percent of the volume of each of the backside trenches). In some embodiments, the material 395 can include copper, aluminum, gas, oil, or aerogel.

[0042] 3I illustrates the wafer of FIG. 3H in an as-processed state, according to an embodiment of the present disclosure. FIG. 3I illustrates the frontside processing features 375 formed after material 395 has been introduced into the sets of backside trenches 380. The wafer 302 additionally includes structural support regions 385 disposed between the frontside processing features 375 and the sets of backside trenches 380.

[0043] 4 illustrates representative major components of an exemplary computer system 401 that can be used in accordance with embodiments of the present disclosure. The specific components illustrated are presented for illustrative purposes only and are not necessarily all that may be present. Computer system 401 can include a processor 410, memory 420, an input / output interface (also referred to herein as I / O (Input / Output) or I / O interface) 430, and a main bus 440. Main bus 440 can provide a communication path for other components of computer system 401. In some embodiments, main bus 440 can connect to other components, such as a specialized digital signal processor (not shown).

[0044] The processor 410 of the computer system 401 may comprise one or more CPUs 412. The processor 410 may additionally comprise one or more memory buffers or caches (not shown) that provide temporary storage of instructions and data for the CPU 412. The CPU 412 may execute instructions on input provided from the cache or from the memory 420 and output results to the cache or memory 420. The CPU 412 may comprise one or more circuits configured to execute one or more methods consistent with embodiments of the present disclosure. In some embodiments, the computer system 401 may include multiple processors 410, as is typical of relatively large systems. However, in other embodiments, the computer system 401 may be a single processor with a single CPU 412.

[0045] The memory 420 of the computer system 401 may comprise a memory controller 422 and one or more memory modules (not shown) for temporarily or permanently storing data. In some embodiments, the memory 420 may comprise a random-access semiconductor memory, storage device, or storage medium (either volatile or non-volatile) for storing data and programs. The memory controller 422 may communicate with the processor 410 and may facilitate the storage and retrieval of information in the memory module. The memory controller 422 may communicate with the I / O interface 430 and may facilitate the storage and retrieval of input or output in the memory module. In some embodiments, the memory module may be a dual in-line memory module.

[0046] I / O interface 430 may include an I / O bus 450, a terminal interface 452, a storage interface 454, an I / O device interface 456, and a network interface 458. I / O interface 430 may connect main bus 440 to I / O bus 450. I / O interface 430 may direct instructions and data from processor 410 and memory 420 to various interfaces of I / O bus 450. I / O interface 430 may also direct instructions and data from various interfaces of I / O bus 450 to processor 410 and memory 420. The various interfaces may include terminal interface 452, storage interface 454, I / O device interface 456, and network interface 458. In some embodiments, the various interfaces may include a subset of the interfaces described above (e.g., an embedded computer system in an industrial application may not include terminal interface 452 and storage interface 454).

[0047] The logical modules throughout computer system 401 (including, but not limited to, memory 420, processor 410, and I / O interface 430) can communicate faults and changes to one or more components to a hypervisor or operating system (not shown). The hypervisor or operating system can allocate the various resources available in computer system 401 and track the location of data within memory 420 and the locations of processes assigned to the various CPUs 412. In embodiments that combine or rearrange elements, aspects of the capabilities of the logical modules can be combined or redistributed. These variations will be apparent to those skilled in the art.

[0048] As described in more detail herein, it is contemplated that some or all of the operations of some of the method embodiments described herein may be performed in an alternate order, or may not be performed at all. Moreover, multiple operations may occur simultaneously or as part of a larger process.

[0049] The present invention may be a system, method, or computer program product, or combination thereof, at any level of technical detail where integration is possible. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0050] The computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punch card or a ridge structure in a groove in which instructions are recorded, or any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0051] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing device / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may be comprised of copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing device / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions to the respective computing device / processing device for storage in a computer-readable storage medium.

[0052] The computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, such as object-oriented programming languages, e.g., Smalltalk, C++, etc., or conventional procedural programming languages (e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any kind of network, such as a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., over the Internet using an Internet Service Provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the invention.

[0053] Aspects of the present invention are described herein with reference to flowchart illustrations or block diagrams, or combinations thereof, of methods, apparatus (systems), and computer program products or computer programs according to embodiments of the invention. It will be understood that each block of the flowchart illustrations or block diagrams, or combinations thereof, and combinations of blocks in the flowchart illustrations or block diagrams, or combinations thereof, can be implemented by computer-readable program instructions.

[0054] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing apparatus to create a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart diagrams or block diagrams, or any combination thereof. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or any combination thereof, to function in a particular manner, and the computer-readable storage medium having instructions stored therein comprises an article of manufacture containing instructions that implement one or more specified functional / act aspects of the flowchart diagrams or block diagrams, or any combination thereof.

[0055] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable data processing apparatus, or other device, implement the functions / acts identified in one or more blocks of the flowchart diagrams or block diagrams, or a combination thereof, to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process.

[0056] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products or computer programs according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be accomplished as a single step performed simultaneously, substantially simultaneously, partially, or fully in a time-overlapping manner, depending on the functionality involved, or the blocks may be performed in the reverse order. It should be noted that each block of the block diagrams or flowchart diagrams or combinations thereof, and combinations of multiple blocks in the block diagrams or flowchart diagrams or combinations thereof, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations, or may execute a combination of special-purpose hardware and computer instructions.

[0057] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A computer-implemented method comprising: acquiring characteristic data for a wafer, the characteristic data corresponding to the wafer in a processed state and including a set of stress values for the wafer in the processed state, the wafer having a front side and a back side opposite the front side and comprising a set of regions, each of the set of stress values corresponding to a respective one of the set of regions, the processed state being a state of the wafer after one or more front side processes have been completed on the front side of the wafer, the one or more front side processes being front end of line processes or back end of line processes; determining a stress value from the set of stress values that exceeds a stress threshold, wherein the wafer stress value that exceeds the stress threshold is associated with wafer bow in response to the one or more front side processing operations, and wherein said determining can predict that the wafer bow will occur; In response to the determining and based on the characterization data, identifying regions in the set of regions corresponding to stress values exceeding the stress threshold to create a compensation map for forming one or more trenches; and initiating forming a first trench on the backside in the identified region of the wafer based on the compensation map, wherein forming the first trench on the backside occurs before the one or more frontside processes. The method for controlling a wafer processing apparatus that performs the above-mentioned steps by a computer.

2. Selecting a first material based on the set of stress values; and beginning to introduce the first material into the first trench; The computer-implemented method of claim 1 , further comprising:

3. 3. The computer-implemented method of claim 2, wherein the first material is selected from the group consisting of gold, lead, and carbon.

4. the characteristic data further includes a set of temperature values of the wafer in the processed state; each of the set of temperature values corresponds to a respective one of the set of regions, and includes a temperature value (hereinafter referred to as a second temperature value) corresponding to a second region of the set of regions; The method comprises: determining that the second temperature value exceeds a temperature threshold; and initiating forming a second trench at the backside in the second region of the wafer based on the compensation map and in response to determining that the second temperature value exceeds the temperature threshold. The computer-implemented method of claim 1 , further comprising:

5. 5. The computer-implemented method of claim 4, further comprising forming the second trench before the wafer is in the processed state.

6. Selecting a second material based on the set of temperature values; and beginning to introduce the second material into the second trench; The computer-implemented method of claim 4 further comprising:

7. 7. The computer-implemented method of claim 6, wherein the second material is selected from the group consisting of copper, aluminum, and oil, or is in the form of an aerogel.

8. A computer-implemented method as described in claim 1, further comprising performing one or more front side processes on the wafer after forming the first trench.

9. The computer-implemented method of claim 1, wherein the set of stress values indicates wafer warpage.

10. the one or more front side processes include forming a deep trench on the front side of the wafer; and The method comprises: forming the first trench such that a structural support region is disposed between the deep trench and the first trench; The computer-implemented method of claim 1 , further comprising:

11. A device, the device comprising: a wafer having a front side and a back side, wherein one or more electronic circuits are formed on the front side and the back side is opposite the front side; the front side comprises a first set of deep trenches and a second set of deep trenches; a gap disposed between the first set of deep trenches and the second set of deep trenches; the backside comprises a backside surface and a set of trenches (hereinafter referred to as a first set of trenches); the first set of trenches comprises a first trench and a second trench; the first trench is substantially parallel to the second trench; and the first trench and the second trench extend substantially vertically from the backside surface toward the frontside; the first set of trenches being disposed below the gap and between the first set of deep trenches and the second set of deep trenches; The device.

12. 12. The device of claim 11, wherein the first trench and the second trench comprise a material that substantially fills the first trench and the second trench, wherein the material is selected from the group consisting of gold, lead, and carbon, or is in the form of an aerogel.

13. the backside further comprising a second set of trenches different from the first set of trenches, the second set of trenches comprising a third trench and a fourth trench; the third trench is substantially parallel to the fourth trench; wherein the third trench and the fourth trench extend substantially vertically from the backside surface toward the frontside; the third trench and the fourth trench include a material that substantially fills the third trench and the fourth trench; and Neither the material filled in the first trench nor the material filled in the second trench includes the material. The device of claim 11.

14. 14. The device of claim 13, wherein the material is selected from the group consisting of copper and aluminum.

15. a structural support region disposed beneath the first set of deep trenches and the second set of deep trenches; the structural support region is disposed above the backside surface; and none of the first set of deep trenches, the second set of deep trenches, and the first set of trenches extend into the structural support region; The device of claim 11.

16. The first set of trenches further comprising a fifth trench; the fifth trench is substantially parallel to the second trench; the fifth trench extends substantially vertically from the backside surface toward the frontside; a first space having a first width horizontally separating the first trench from the second trench; a second space having a second width horizontally separating the second trench from the fifth trench; and the first width and the second width are substantially equal; The device of claim 11.

17. A device as described in claim 11, wherein the first set of trenches are formed in locations where warping of the wafer is predicted to occur due to the formation of the one or more electronic circuits.

18. The predicted location is: acquiring characteristic data for a wafer, the characteristic data corresponding to the wafer in a processed state and including a set of stress values for the wafer in the processed state, each stress value in the set corresponding to a respective one of a set of regions of the wafer, the processed state being a state of the wafer after one or more front-side processes have been completed on the front-side of the wafer, the front-side processes being front-end of line processes or back-end of line processes; determining that a stress value in the set of stress values exceeds a stress threshold, wherein a wafer stress value that exceeds the stress threshold indicates that wafer bow in response to the one or more front side processing operations is likely to occur, and wherein said determining can predict that wafer bow is likely to occur; and identifying, in response to said determining and based on said characteristic data, a region from said set of regions corresponding to a stress value that exceeds said stress threshold.

18. The device of claim 17, wherein the region is identified by:

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