Silicon substrate processing method and liquid ejection head manufacturing method

Abstract

To improve the uniformity of the depths of holes by reducing the influence of a loading effect when a process for providing the holes arrayed on a silicon substrate is carried out.SOLUTION: A processing method for arranging a plurality of opening patterns 101 on a silicon substrate (wafer 100) comprises: a step of forming, regarding at least one opening pattern 101, on the surface of the silicon substrate, a mask pattern 104 configured so as to arrange a plurality of split opening patterns 103 in a region contoured by the opening pattern 101; and an etching step of processing the silicon substrate 100 by means of reactive ion etching via the mask pattern 104. During the etching step or after the end of the etching step, a separation wall 105 for separating the split opening patterns 103 from each other is removed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for processing a silicon substrate by dry etching, and a method for manufacturing a liquid ejection head using this processing method. [Background technology]

[0002] The process of forming holes through silicon substrates or of a similar depth is widely used in the manufacture of MEMS (Micro Electro Mechanical Systems) and liquid ejection heads. To form such holes, dry etching techniques using fluorine radicals, such as the Bosch process, are used, which enable high-speed processing perpendicular to the substrate surface. However, dry etching using fluorine radicals can cause a phenomenon known as the loading effect, in which the etching rate increases at the outer periphery of the substrate, even when the plasma density is uniform. Summary of the Invention [Problem to be solved by the invention]

[0003] When a silicon substrate is processed by dry etching to open an array of holes, the depth of each hole formed is not uniform across the surface of the silicon substrate due to the loading effect, which prevents the formation of holes with uniform shape and depth.

[0004] An object of the present invention is to provide a method for processing a silicon substrate that can reduce the influence of the loading effect and improve the in-plane uniformity of hole depth, and a method for manufacturing a liquid ejection head using that processing method. [Means for solving the problem]

[0005] A method for processing a silicon substrate of the present invention is a processing method for arranging a plurality of opening patterns on a silicon substrate, the method comprising: a step of forming a mask pattern on a surface of the silicon substrate, the mask pattern being configured so that, for at least one opening pattern, a plurality of divided opening patterns are arranged within an area defined by the opening pattern; and an etching step of processing the silicon substrate by reactive ion etching via the mask pattern; the opening areas of the divided opening patterns arranged within the contour regions of the opening patterns are set for each opening pattern in the mask pattern so that at least a part of the change in etching rate due to a loading effect according to the position of the opening pattern within the surface of the silicon substrate is offset by the change in etching rate due to a microloading effect according to the opening areas of the divided opening patterns; The separation walls separating the divided opening patterns from each other are removed during or after the etching step. [Effects of the Invention]

[0006] According to the present invention, when processing a silicon substrate, the influence of the loading effect is reduced and the in-plane uniformity of the depth of holes is improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating the difference in etching characteristics between ions and radicals. [Figure 2] FIG. 10 is a plan view showing an example of an arrangement of opening patterns on a wafer. [Figure 3] FIG. 1 is a plan view illustrating the basic concept of the present invention. [Figure 4] 10 is a graph showing the distribution of etching rates due to a loading effect. [Figure 5] 1A to 1C are cross-sectional views illustrating steps of a processing method according to an embodiment of the present invention. [Figure 6] 10 is a graph illustrating the microloading effect. [Figure 7] FIG. 10 is a cross-sectional view showing the disappearance of the separation wall. [Figure 8] FIG. 10 is a plan view illustrating removal of the separation wall. [Figure 9] FIG. 10 is a plan view showing the relationship between the distribution of etching rates and opening patterns. [Figure 10] FIG. 10 is a plan view showing an example of the arrangement of divided aperture patterns. [Figure 11]10 is a graph showing the relationship between opening width and etching rate. [Figure 12] 3A to 3C are cross-sectional views illustrating the manufacturing process of the liquid ejection head in Example 1. [Figure 13] 10A to 10C are diagrams illustrating a manufacturing process of a liquid ejection head according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings. First, prior to describing the embodiments of the present invention, dry etching of a silicon substrate by the Bosch process and the loading effect will be described.

[0009] Dry etching using the Bosch process is a type of reactive ion etching (RIE) that is suitably used as a processing method for quickly forming nearly perpendicular holes in silicon substrates. Dry etching using the Bosch process is a technique consisting of a cycle in which the following three steps (a) to (c) are continuously repeated in order: (a) Etching of silicon by fluorine radicals, (b) forming a fluorocarbon-based passivation layer on the silicon surface; and (c) Removal of the passivation layer at the bottom of the hole by ions.

[0010] A vertical etching profile can be achieved by protecting the sidewalls of the hole formed in step (a) with the passivation layer formed in step (b). Typically, C4F8 is used as the process gas in step (b), and SF6 is used in steps (a) and (c).

[0011] In general, in dry etching, charged ions and electrically neutral radicals contribute to the etching. However, in high-speed etching of silicon using fluorine-based gases such as SF6, the reaction proceeds spontaneously with radicals alone, even without ion bombardment. In this system, the etching rate of silicon can be considered to be determined by the behavior of radicals. Therefore, the mechanism of the loading effect will be explained based on the characteristics of the reactions of ions and radicals. Figure 1 shows the difference in etching characteristics between ions and radicals when etching a silicon substrate 11 through the opening 13, with a mask 12 formed as a mask pattern on the surface of the substrate 11. In the figure, radicals are indicated by "R" and positive ions are indicated by "+".

[0012] Ions are accelerated by the bias voltage and become directional, so the number of ions that reach the opening 13 is simply proportional to the area of the opening. For example, most of the ions that contribute to etching of the substrate 11 under a certain mask pattern are those that exist in the region extending from the opening 13 in the mask 12 in a direction perpendicular to the substrate surface, as shown in Figure 1(a). Since the number of ions that enter the opening 13 can be considered to be proportional to the plasma density, if we assume that etching is mainly ion-based, ideally the etching depth will be uniform if the plasma density is made uniform.

[0013] Since uncharged radicals have no directionality, not only the region extending vertically from the opening 13 but also the radicals present around the opening 13 contribute to etching. In this case, if the opening 13 is isolated, the radicals around the opening 13 are consumed only on the surface of the substrate 11 exposed at the opening 13, as shown in FIG. 1(b). In contrast, if two or more openings 13 are close to each other in the mask pattern, the openings 13 compete for radicals, as shown in FIG. 1(c). In other words, even if the plasma density during etching is the same and the opening shapes in the mask pattern are the same, the etching rate will change significantly if the density of surrounding openings is different.

[0014] As an example, consider dry etching a silicon substrate wafer 100 so that opening patterns 101 are regularly arranged. The opening patterns 101 are openings or holes formed in the wafer 100 by etching using a mask pattern having openings. FIG. 1(d) is a plan view of the wafer 100 at this stage, and FIG. 1(e) is a cross-sectional view of the wafer 100 after etching, taken along the line EE in FIG. 1(d). The hatched area in FIG. 1(d) indicates the area on the surface of the wafer 100 where a mask 12 is formed. In the example shown in FIG. 1(d), a plurality of opening patterns 101, each having a rectangular planar shape, are arranged in an array on the substantially circular wafer 100. The planar shape of the opening pattern refers to the shape of the opening pattern formed as holes in the wafer 100 on the surface of the wafer 100.

[0015] When dry etching the wafer 100 shown in Figure 1(d) using the Bosch process, fluorine radicals present in the outer peripheral region of the wafer 100 also contribute to the etching rate at the wafer's periphery. This is the same as a situation where the opening density in the mask pattern is reduced. This is the mechanism behind the increased etching rate at the wafer's periphery due to the loading effect. This phenomenon becomes more pronounced when the opening area of the wafer 100 is large. For example, the effect is insignificant when the opening ratio is 5% or less, but becomes a major problem when the opening ratio exceeds 10%. The opening ratio is the ratio of the area of the openings in the opening pattern to the total area of the wafer 100 surface. If the etching rate is not uniform across the substrate surface, it becomes difficult to create holes with uniform depth when the same opening pattern is repeated. In the example shown in Figures 1(d) and 1(e), the same opening pattern 101 is being formed on the wafer 100. However, the depth of the holes formed by the opening pattern 101 is shallower in the center of the wafer 100 and deeper at the periphery.

[0016] To reduce the impact of this loading effect, etching equipment can be designed to reduce plasma density at the periphery of the substrate or wafer being etched. For example, the plasma generation area within the equipment can be minimized to allow radicals to diffuse toward the periphery. Alternatively, an aperture or other device can be placed between the plasma generation area and the object being etched to reduce the effective diameter of the plasma. While these countermeasures result in a uniform radical etching rate, the ion density distribution decreases toward the periphery of the substrate or wafer. As a result, the ions follow a trajectory that diffuses from high concentration to low concentration. In other words, when ions are used to remove the passivation layer at the bottom of the hole in step (c) above, the ions enter the substrate at an angle that spreads toward the outside of the substrate. This repetition results in the hole being formed at an angle rather than vertically.

[0017] There are also methods for improving the etching rate distribution by changing the process conditions. For example, when using SF6 as the process gas, one method is to increase the flow rate of the process gas while simultaneously lowering the pressure. Lowering the process gas pressure reduces the radical density, suppressing the generation of excess radicals, while increasing the process gas flow rate increases the exhaust rate and reduces the partial pressure of reaction products. This makes it less likely that the radical density distribution will affect the etching rate distribution, resulting in improved etching rate uniformity. However, this method also reduces the radical density, which reduces the overall etching rate and significantly reduces productivity.

[0018] Therefore, in a silicon substrate processing method according to the present invention, the uniformity of the etching depth in the in-plane direction of the substrate to be processed is improved by modifying the mask pattern used for dry etching without making any special modifications to the etching apparatus itself. The processing method according to the present invention is described in detail below. Hereinafter, openings are formed in a silicon substrate by reactive ion etching, such as the Bosch process, which uses fluorine-based gas. Therefore, when simply referring to "etching," we refer to reactive ion etching, such as the Bosch process, which uses fluorine-based gas. Figure 2 is a diagram illustrating the processing method of the present invention, showing a plan view of a substantially circular wafer 100, which is a silicon substrate, in which multiple rectangular opening patterns 101 are arranged in an array on the wafer 100. In the rectangular planar shape of the opening pattern 101, the length of the short side is A and the length of the long side is B. In the example shown in Figure 2, after the opening patterns 101 are formed, chips 102 are cut out from the wafer 100 so that each chip 102 includes one opening pattern 101. The area of each chip 102 on the wafer 100 is also shown. The lines that define the boundaries between the chips 102 are also the cutting lines used when cutting the chips 102 out of the wafer 100 .

[0019] When holes are formed as opening patterns in a silicon substrate wafer by etching based on a mask pattern, the depth of the holes, i.e., the etching depth d, can be expressed for each opening pattern by equation (1). Since the etching depth d is proportional to the etching rate, the right-hand side of equation (1) can also be said to represent the etching rate. d=f(S,R,P) (1)

[0020] Here, S is the opening area in the mask pattern, R is the local opening ratio at the position of interest on the wafer, and P is a variable dependent on the plasma. Here, the variables R and P vary depending on the in-plane position on the wafer. Equation (1) indicates that the etching depth d is a function of the opening area S, the local opening ratio R, and the plasma-dependent variable P, but the contribution of each variable to the variation in etching depth d is considered to be nearly independent. Therefore, equation (1) can be approximated as equation (2), where D is the reference etching depth. d=f s (Science fiction r (R)·f p (P)·D (2)

[0021] The opening area S is the area of the openings actually formed in the mask pattern, and in the example shown in FIG. 2, it is the area of the opening pattern 101 itself, i.e., A × B. The local opening ratio R is a parameter used to indicate that the area density of radicals incident on the openings of the mask decreases as the opening density increases, and is a parameter used to indicate the difference between region C and region D shown by the dashed dotted line in FIG. 2. In other words, the local opening ratio R is the opening ratio in the region surrounding the position of the opening pattern of interest, and varies depending on the in-plane position on the wafer 100. When calculating the local opening ratio R, the extent to which the periphery of the opening pattern of interest is included varies depending on the etching conditions, etc., but the local opening ratio G is calculated based on the opening area within a region of, for example, 5 mm square to 20 mm square. In the example shown in FIG. 2, the opening ratio in region C is approximately half the opening ratio in region D. Therefore, f r (R) is a term that represents the contribution of the loading effect.

[0022] f p (P) is a term that represents the etching condition dependency (i.e., plasma dependency), and is determined by the aforementioned pressure, the flow rate of SF6, which is the process gas, and the density of the plasma. The parameter P also changes depending on the in-plane position of the wafer 100. p(P) is also a function of the plasma conditions in the 4 mm square to 20 mm square area around the aperture pattern of interest.

[0023] f s (S) is a function of the opening area S of the opening pattern and represents the contribution of a phenomenon called the microloading effect. This phenomenon occurs because the smaller the opening area S, the lower the etching rate. As the opening area becomes smaller, the ion and radical components that contribute to etching have difficulty penetrating deep into the wafer through the opening. The influence of the microloading effect on etching depth is generally said to depend on the logarithm of the opening area S, and is expressed by equation (3). f s (S)=A×log 10 S+B (3) Here, A and B are constants.

[0024] Among the dry etching methods for silicon substrates, silicon insulating film etching and sputter etching, in which etching by ion components is dominant, s (S) and f r The fluctuation of (R) is small, especially f r In dry etching where radical etching is dominant, such as reactive ion etching using fluorine-based gas, the term (R) need not be taken into consideration. s (S) and f r The fluctuation of (R) becomes very large. r To change the value of (R), for example, a method of placing a dummy pattern on the outer periphery, i.e., the peripheral part of the wafer can be used. By placing a dummy pattern, the influence of the loading effect can be reduced, but there are problems such as the difficulty of placing the dummy pattern in terms of layout, the limitation of the number of chips that can be obtained from the wafer, and the reduction of the mechanical strength of the wafer. In addition, reducing the plasma generation area or the effective diameter can also reduce the f p However, there are problems as mentioned above, and in order to offset the influence of the loading effect,p It is not realistic to control the depth of the opening pattern by changing (P).

[0025] Therefore, in the present invention, f sThe microloading effect (S) is utilized to control the depth and reduce the impact of the loading effect. For example, as shown in FIG. 2, a wafer 100 is ultimately desired, with multiple chips 102 each having an opening pattern 101. When cutting the individual chips 102 from the wafer 100 after processing, the multiple chips 102 are preferably arranged in an array, as shown in the figure. When the wafer 100 shown in FIG. 2 is directly processed by reactive ion etching using a fluorine-based gas, the opening pattern 101 on the periphery of the wafer 100 becomes deeper than the opening pattern 101 in the center. In the present invention, as shown in FIG. 3, a mask pattern 104 is formed on the surface of the wafer 100 so that multiple divided opening patterns 103 smaller than the opening pattern 101 are arranged in an array within the contour region of the opening pattern 101. The opening area of the divided opening pattern 103 is made smaller in positions on the surface of the wafer 100 where the etching rate is higher due to the loading effect, and the number of divided opening patterns 103 arranged within the opening pattern 101 is changed accordingly. That is, at least a portion of the change in etching rate due to the loading effect according to the position of opening pattern 101 within the surface of wafer 100 is offset by the change in etching rate due to the microloading effect according to the opening area of divided opening pattern 103. In the example shown in Fig. 3, opening pattern 101 is not divided into multiple divided opening patterns 103 at the center of wafer 100, and opening pattern 101 at the outermost periphery is divided into 12 divided opening patterns 103 arranged in a 3 x 4 matrix. Between the center and outermost periphery of wafer 100, opening pattern 101 closer to the center is divided into three divided opening patterns 103 arranged in a 1 x 3 matrix, and opening pattern 101 closer to the outermost periphery is divided into six divided opening patterns 103 arranged in a 3 x 2 matrix. The number of divided opening patterns 103 into which opening pattern 101 is divided is determined depending on the etching conditions, and the number of divisions shown here is merely an example. It should be noted that, as will be described later, separation walls 105 exist between adjacent divided aperture patterns 103 within the contour region of aperture pattern 101, but these separation walls 105 are eventually removed.

[0026] Figure 4 shows an example of the in-plane distribution of etching rate when etching a silicon substrate using the Bosch process. Here, the shape of the opening pattern is the same and the influence of the microloading effect can be ignored, and the change in etching rate due to the loading effect, i.e., the contribution of the term fr(R), is shown. Since the hole depth is proportional to the etching rate, Figure 4 can also be said to show the situation in which the opening pattern, i.e., the hole depth, changes. The etching rate and in-plane position in the figure are both normalized to 1 at the wafer edge. In this example, for an opening pattern with an opening rate of 30%, the in-plane uniformity was 17.6%. The in-plane uniformity is In-plane uniformity = (maximum etching rate - minimum etching rate) / (maximum etching rate + minimum etching rate) x 100 (%) is defined as follows. FIG. 4 shows the distribution of the etching rate as a one-dimensional distribution along the radial direction of wafer 100. If considered in two dimensions, i.e., the entire surface of wafer 100, the distribution becomes concentric. Therefore, as shown in FIG. 3, the closer opening pattern 101 is to the outer periphery of wafer 100, the smaller the opening area of each divided opening pattern 103 provided within the region outlined by opening pattern 101. Assume that a first opening pattern 101 and a second opening pattern 101 that is closer to the outer periphery of wafer 100 than first opening pattern 101 are arranged on wafer 100. In this case, it is sufficient that the opening area of each divided opening pattern 103 arranged within the region outlined by second opening pattern 101 is smaller than the opening area of each divided opening pattern 103 arranged within the region outlined by first opening pattern 101.

[0027] By forming the opening pattern 101 as a collection of divided opening patterns 103 with small opening areas, the etching rate of the opening pattern 101 is reduced due to the microloading effect. As a result, the etching depth can be made shallower than when etching is performed without dividing the opening pattern 101 into a plurality of divided opening patterns 103. That is, f sThe decrease in etching rate due to the microloading effect represented by (S) causes f r This offsets the increase in etching rate due to the loading effect represented by (R). It is possible to form an opening pattern 101 with excellent depth uniformity over the entire surface of the wafer 100. The processing method according to the present invention thus includes a step of forming a mask pattern 104 on the surface of a silicon substrate such as the wafer 100, and an etching step of processing the silicon substrate by reactive ion etching through the mask pattern 104. The mask pattern 104 used here is configured such that, for at least one opening pattern 100, multiple divided opening patterns 103 are arranged within an area defined by that opening pattern 100. Separation walls 105 are formed between the divided opening patterns 103, but the separation walls 105 are removed after the etching step. Alternatively, the etching conditions in the etching step may be selected so that the separation walls 105 are removed during the etching step. Furthermore, in the processing method according to the present invention, the shapes and dimensions of the multiple divided opening patterns 103 arranged within an area defined by the opening pattern 100 in at least one opening pattern 100 may be the same. It should be noted that even if there are slight differences due to manufacturing errors, the shape and dimensions are considered to be the same. Furthermore, in at least one aperture pattern 100, the aperture areas of the multiple divided aperture patterns 103 arranged within the region defined by that aperture pattern 100 may vary, i.e., may be different from each other.

[0028] FIG. 5 is a cross-sectional view illustrating a processing method according to one embodiment of the present invention. FIG. 5(a) shows a cross-section of a wafer 100 after processing when the opening pattern 101 is not divided by divided opening patterns 103. The opening patterns 101 closer to the periphery of the wafer 100 are formed deeper than the opening patterns 101 in the center. In contrast, FIG. 5(b) shows a cross-section of a wafer 100 after processing when the opening patterns 101 closer to the periphery are divided by divided opening patterns 103 with smaller individual opening areas. The depth of the opening patterns 101 or divided opening patterns 103 is uniform. Separation walls 105 remain between adjacent divided opening patterns 103. Because the width of the separation walls 105 can be made to be at most several μm, the separation walls 105 can be easily removed by isotropic etching or the like, leaving only the outline of the pattern 101 remaining on the wafer 100, as shown in FIG. 5(c). This means that multiple opening patterns 101 are formed at the same depth within the plane of the wafer 100.

[0029] By adjusting the etching rate using the microloading effect, it is possible to offset depth nonuniformity due to the loading effect as well as depth nonuniformity due to plasma dependency. For example, increasing the pressure during etching improves the overall etching rate but reduces uniformity. Applying etching rate adjustment using the microloading effect to such high-pressure etching conditions can improve within-wafer uniformity and is expected to improve productivity.

[0030] When the opening area of the divided opening pattern 103 is reduced toward the outer periphery of the wafer 100, precise calculation of the opening area of each divided opening pattern 103 according to the position of the opening pattern 101 improves the uniformity of the etching depth. With such precise calculation, the opening area of the divided opening pattern 103 changes continuously along the radial direction of the wafer 100. However, divided opening patterns 103 having the same opening area can also be applied to several opening patterns 101 that are adjacent in the radial direction of the wafer 100. That is, if an opening pattern 101 is formed for each chip 102 as shown in FIG. 2, the divided opening patterns 103 provided within the opening pattern 101 may be arranged in the same manner for several chips 102. In this case, as shown in FIG. 5(d), differences in depth occur between adjacent opening patterns 101, but the uniformity of the depth distribution is still significantly improved compared to when the divided opening pattern 103 is not used.

[0031] When a plurality of divided aperture patterns 102 are arranged within the contour of aperture pattern 101, adjacent divided aperture patterns 102 are separated by separation walls 105. If the area of separation walls 105 on the surface of wafer 100 is sufficiently small compared to the area of aperture pattern 101, a loading effect is not observed. r The value of (R) can be considered to be the same whether or not the separation wall 105 is present. Because the separation wall 105 will eventually be removed, it is preferable that the separation wall 105 be as narrow as possible. However, even if the area of the separation wall 105 is not negligible compared to the area of the opening pattern 101 on the surface of the wafer 100, it is possible to perform correction using the microloading effect, taking into account the contribution of the area of the separation wall 105.

[0032] Below, we will show a specific example of how the microloading effect can be actively used to improve the uniformity of depth. Figure 6 is a graph showing the relationship between the opening area and the etching rate when etching a silicon substrate under certain etching conditions, and shows the change in etching rate due to the microloading effect. When the results shown in Figure 6 were fitted using equation (3), the values A = 1.424 and B = 0.007443 were obtained. That is, f s (S)·D=1.424×log 10 S+0.007443 (4) The constants A and B here include the influence of the reference etching depth D.

[0033] Assume that the opening pattern 101 is a rectangular opening measuring 200 μm wide and 20,000 μm long, and that multiple opening patterns 101 are arranged and formed on the wafer 100 by etching. The width of the separation wall 105 is, for example, approximately 2 μm. Based on this assumption, we investigated the arrangement and shape of divided opening patterns 103 that would result in a uniform depth of the opening pattern 101 across the wafer 100 when the in-plane uniformity of the etching rate due to the loading effect is 10%, 17.6%, 30%, and 50%. The in-plane uniformity of the etching rate is calculated in the same manner as described using FIG. 4. The results are shown in Table 1. Table 1 shows how the opening pattern 101 is divided into divided opening patterns 103 according to its position across the wafer 100, based on the dimensions of the divided opening patterns 103 and the number of divided opening patterns 103 arranged in the vertical and horizontal directions. The divided opening patterns 103 are rectangular, and all of them have the same shape and are evenly arranged within the same opening pattern 101. Furthermore, the "area ratio of separation walls" in Table 1 indicates the value obtained by dividing the area of separation walls 105 that are produced when opening pattern 101 is divided by divided opening patterns 103 by the opening area of opening pattern 101. The dimensions and number of divided opening patterns 103 shown here are just an example, and there are other division forms when dividing opening pattern 101 into a plurality of divided opening patterns 103 according to the in-plane position on wafer 100 besides those shown here.

[0034] [Table 1]

[0035] In Table 1, the "Rate Value Positioning" indicates the etching rate taking into account the loading effect, divided into three levels: "Minimum," "Average," and "Maximum." Because the etching rate taking into account the loading effect varies depending on the in-plane position on the wafer 100, the "Rate Value Positioning" ultimately indicates the in-plane position on the wafer 100. "Minimum" corresponds to the position at the center of the wafer 100 where the etching rate is minimum. At this position, as shown in Table 1, the opening pattern 101 is configured as a single divided opening pattern 103, i.e., the opening pattern 101 is not divided into multiple divided opening patterns 103. On the other hand, "Maximum" in the "Rate Value Positioning" corresponds to the position at the outer periphery of the wafer 100 where the etching rate is maximum due to the loading effect. "Average" corresponds to the position where the average etching rate is obtained in the distribution of etching rates along the radial direction of the wafer 100.

[0036] Consider suppressing depth variations in opening pattern 101 when the in-plane etching rate uniformity is 10% due to the loading effect. In this case, Table 1 shows that, at the "average" position, opening pattern 101 should have one vertical row and four horizontal rows of divided opening patterns 103 each measuring 20,000 μm in length and 47 μm in width. Similarly, at the "maximum" position, opening pattern 101 should have two vertical rows and seven horizontal rows of divided opening patterns 103 each measuring 9,997 μm in length and 26 μm in width. If the in-plane etching rate uniformity is 50%, for example, at the "average" position, 198 vertical rows and nine horizontal rows of divided opening patterns 103 measuring 99 μm in length and 20 μm in width should be arranged. At the "maximum" position, 1,000 vertical rows and 18 horizontal rows of divided opening patterns 103 measuring 18 μm in length and 9 μm in width should be arranged.

[0037] In this embodiment, it is assumed that the etching depth of the wafer 100, i.e., the silicon substrate, is approximately 500 μm. Although reactive ion etching using a fluorine-based gas allows vertical etching, when a 500 μm hole is formed in a silicon substrate, etching may proceed laterally by approximately 1 μm. The value of approximately 2 μm for the width of the separation wall 105 is a value assuming that the separation wall 105 will not disappear during etching when a hole approximately 500 μm deep is formed by etching. Since the separation wall 105 is ultimately removed, it does not matter if some or all of the separation wall 105 disappears during etching. However, if the divided opening patterns 103 communicate with each other, the ions and radicals incident thereon will no longer be restricted by the separation wall 105, resulting in a correspondingly higher etching rate. Taking into account the increase in etching rate due to the disappearance of the separation wall 105, the shape and arrangement of the divided opening patterns 103 provided in each opening pattern 101 may be determined so that the depths of the opening patterns 101 are ultimately uniform. 7 is a cross-sectional view illustrating the disappearance of separation wall 105 during the etching process. Fig. 7 shows that separation wall 105 separating divided opening pattern 103 has disappeared on the bottom side of opening pattern 101. It also shows that the holes in opening pattern 101 have widened toward the bottom side as etching progresses in the lateral direction.

[0038] After etching to form the opening pattern 101, the separation wall 105 is removed. The separation wall 105 can be removed by, for example, isotropic dry etching using SF or anisotropic wet etching using tetramethylammonium hydroxide (TMAH). Figure 8 is a plan view illustrating the removal of the separation wall 105, showing a portion corresponding to one chip 102 on the wafer 100 shown in Figure 2. Figure 8(a) shows the state before etching to remove the separation wall 105, and Figure 8(b) shows the state after the separation wall 105 has been removed. Removing the separation wall 105 means that the opening formed by the opening pattern 101 expands to a size approximately equal to that of the separation wall 105, i.e., by an area 106 in the figure, as shown by the change from Figure 8(a) to Figure 8(b). It is desirable to minimize the expansion of the opening size resulting from the removal of the separation wall 105. However, the value of approximately 2 μm described here is 1% of the 200 μm short side (horizontal) dimension of the opening pattern 101, which is within an acceptable range.

[0039] In the above description, one opening pattern 101 is divided into a plurality of divided opening patterns 103 of the same shape and size. However, depending on the distribution of the etching rate within the surface of the wafer 100 and the arrangement of the opening patterns 101, significant differences in etching rate may occur even within the region of one opening pattern 101. How to deal with such a case will now be described. The above-mentioned FIG. 4 is a graph showing the distribution of the etching rate when the in-plane uniformity of the etching rate distribution is 17.6%. In this graph, the etching rate rises sharply at the outer periphery of the wafer 100. The etching rate reaches its average value (normalized to approximately 0.85) at a position approximately 80% of the radius from the center of the wafer 100. For a wafer 100 with a diameter of 200 mm (an 8-inch wafer), this position is 80 mm from the center, and the etching rate rises sharply from this position toward the periphery of the wafer 100. 9 is a plan view showing the distribution shown in FIG. 4 as the distribution of etching rates within the surface of wafer 101 using shading, and indicates that the etching rate is lower near the center of wafer 101 and higher near the periphery, as indicated by the arrows in the figure. When the etching rate is distributed in this manner and changes sharply, opening pattern 101 may be set across the region where the etching rate changes sharply. In the example shown in FIG. 9, opening pattern 101, which is a rectangle measuring 200 μm wide and 20,000 μm long, is set across the position where the etching rate is "lowest" and "highest," as represented by the "rate value positioning" described in relation to Table 1.

[0040] When the etching rate due to the loading effect varies significantly within a single opening pattern 101, multiple divided opening patterns 103 with different shapes and dimensions can be used in combination within the opening pattern 101. For example, in the example of opening pattern 101 shown in FIG. 9, the upper end of the illustration represents the position where the etching rate is "highest," and the lower end of the illustration represents the position where the etching rate is "lowest." Therefore, at the upper end, nine divided opening patterns 103 each measuring 1998 μm in length and 20 μm in width are arranged horizontally, and at the lower end, seven divided opening patterns each measuring 9997 μm in length and 26 μm in width are arranged horizontally. In the region between the upper and lower end positions, divided opening patterns 103 are arranged so that the vertical length and the horizontal number of divided opening patterns change continuously. FIG. 10 shows the arrangement of such divided opening patterns 103 within the region of opening pattern 101 shown in FIG. 9.

[0041] Next, we will explain the change in the loading effect due to the presence of separation walls 105, which change the local aperture ratio R. Here, we calculated the average etching rate within the surface of wafer 100, a silicon substrate, when etching was performed on the surface of wafer 100, with multiple aperture patterns 101 of the same shape and size. Each aperture pattern 101 had a fixed vertical length of 20,000 μm, and its horizontal length, i.e., aperture width, was varied between 160 μm and 225 μm. Since the number of aperture patterns 101 arranged on wafer 100 was the same, varying the aperture width of each aperture pattern 101 meant varying the aperture ratio across the entire wafer 100. The aperture patterns 101 were not divided by divided aperture patterns 103. The results are shown in Figure 11 and Table 2. In Table 2, the "fitted value" is the fitted value obtained by linearly fitting the measured average etching rate for each aperture width.

[0042] [Table 2]

[0043] From Figure 11 and Table 2, it can be seen that the etching rate increases as the opening width becomes smaller. Therefore, the percentage of variation in the average etching rate at each opening width was calculated using an opening width of 225 μm as the base. The results are shown in Table 2 as the rate of variation Δ of etching rate variation. Furthermore, by substituting the opening area, which is the product of the opening width and the vertical length, into equation (4), it is possible to calculate the variation in etching rate due to the microloading effect, using an opening width of 225 μm as the base. In Table 2, the calculated value of the variation in etching rate due to the microloading effect is shown as "f s (S) Calculated values due to the microloading effect. For example, if the opening width is reduced from 225 μm to 160 μm, it can be expected that the etching rate will decrease by 2.22% due to the microloading effect. However, in reality, the etching rate increases by 7.22%. This is thought to be because the local opening ratio R decreases when the opening width is reduced while keeping the number of opening patterns 101 the same, and as a result, the influence of the loading effect appears. As shown in equation (2), f s The contribution of the microloading effect represented by (S) and f r Since the contribution of the loading effect represented by (R) can be treated as independent, f r (R) can be calculated from equation (5). f r (R)=Δ / f s (S) (5)

[0044] For example, when the opening width is reduced from 225 μm to 160 μm, the fluctuation rate Δ of the measured etching rate is +7.22%, which is the contribution of the microloading effect (f s (S)) is -2.22%. Substituting this into equation (5), we get f r (R) = (100 + 7.22) / (100 - 2.22) =1.0966 In other words, we can conclude that the loading effect caused an increase in the etching rate of 9.66%. The contribution of the loading effect calculated in this way is shown as "fr (R) Calculated value” column.

[0045] The reduction rate of the opening area of opening pattern 101 due to changing the opening width from 225 μm to 160 μm is 28.9%. If we consider that this reduction in area is replaced by a reduction in the opening due to the provision of separation wall 105, the impact on the loading effect is the same. In other words, if the area ratio of separation wall 105 in opening pattern 101 is 28.9%, the etching rate in this opening pattern 101 will increase by 9.66% due to the loading effect.

[0046] Table 1 shows the dimensions and arrangement of the divided opening pattern 103 when the opening pattern 101 is divided by the divided opening pattern 103, but does not take into account the contribution of the loading effect due to the reduction in the opening ratio caused by the provision of the separation wall 105. Table 1 shows that when the loading effect due to the provision of the separation wall 105 is not contributed, the non-uniformity of the etching rate can be corrected even if the in-plane uniformity of the etching rate is 50%. However, if the impact of the area of the separation wall 105 on the loading effect is too large, further correction using the microloading effect must be considered, and the calculation of the dimensions and arrangement of the divided opening pattern 103 becomes very complicated. Therefore, it is preferable that the increase in the etching rate due to the loading effect caused by the provision of the separation wall 105 be approximately 5% or less. Table 3, based on the results shown in Table 2, calculates the contribution of the loading effect (f r (R)). From Table 3, f r (R) increases by 5%, i.e., f r It can be seen that (R)=1.05 means that the area ratio of the separation walls 105 to the openings of the opening pattern 101 is about 15%. In other words, in the present invention, it can be seen that it is preferable that the ratio of the area of the separation walls 105 to the area of the outline region of the opening pattern 101 is 15% or less.

[0047] [Table 3]

[0048] Table 1 also shows the area ratio of the separation wall 105 in the opening of the opening pattern 101. Only at the "maximum" position when the in-plane etching rate uniformity is 50% does the area ratio of the separation wall 105 exceed 15%. In other examples in Table 1, the area ratio of the separation wall 105 is within 15%. That is, in many cases of etching a silicon substrate wafer 100, the area ratio of the separation wall 105 in the opening of the opening pattern 101 can be considered to be within 15%. Furthermore, the area ratio of the separation wall 105 at the "maximum" position when the in-plane uniformity is 50% is 26.9%, but this is calculated assuming the separation wall 105 has a width of 2 μm. Reducing the width of the separation wall 105 from 2 μm to 1 μm reduces the area ratio to 14.7%. That is, if processes such as resist mask patterning can be performed, a narrower width of the separation wall 105 is preferable. In practice, a realistic value is selected as the width of the separation wall 105, taking into consideration the resolution of the resist and the amount of etching in the lateral direction during etching.

[0049] The silicon substrate processing method according to the present invention is preferably used for manufacturing a liquid ejection head used in a liquid ejection device that ejects a liquid such as ink onto a recording medium such as paper for recording. The manufacturing of the liquid ejection head will be described below.

[0050] A liquid ejection head uses a chip cut from a silicon substrate as an element substrate. In a liquid ejection head, an ejection port forming member is disposed on one surface of the substrate. The ejection port forming member has ejection ports for ejecting droplets formed therein, and pressure chambers communicating with the ejection ports are formed as spaces between the ejection port forming member and the substrate. In general, in a liquid ejection head, multiple pressure chambers are arranged in a row. Multiple energy generating elements are disposed on one surface of the substrate so as to face the pressure chambers. Energy generated by the energy generating elements causes the liquid in the pressure chambers to be ejected as droplets from the ejection ports. The substrate is formed with multiple supply channels communicating with the multiple pressure chambers, respectively, and a common liquid chamber communicating with these supply channels as holes. The common liquid chamber is formed as an opening pattern at a predetermined depth from the other surface of the substrate, and the supply channels are formed as holes that penetrate the substrate for each pressure chamber, communicating between the bottom of the common liquid chamber and the pressure chamber. In such a liquid ejection head, droplets can be ejected from the ejection orifices by heating and foaming the liquid using thermal energy from an energy generating element such as a heater. At this time, liquid is supplied from the supply channel to the pressure chamber, and liquid is supplied to the supply channel from the common liquid chamber.

[0051] Such a liquid ejection head is manufactured by forming pressure chambers and supply channels corresponding to multiple liquid ejection heads in a silicon substrate, bonding ejection port-forming members corresponding to the multiple liquid ejection heads, and then dividing the substrate into individual liquid ejection heads. The common liquid chamber is formed as the aforementioned opening pattern in the silicon substrate. Furthermore, the substrates constituting the individual liquid ejection heads are cut out as the aforementioned chips from the silicon substrate. Therefore, when applying the processing method of the present invention to the manufacture of liquid ejection heads, a silicon substrate large enough to accommodate an array of multiple liquid ejection heads is first prepared. Then, in a first step, the processing method based on the present invention is applied to the silicon substrate to simultaneously form the common liquid chambers in the substrates of the multiple liquid ejection heads as opening patterns. A separation step is then performed to cut out the substrates of the individual liquid ejection heads from the silicon substrate. When manufacturing a liquid ejection head, after the first step and before the separation step, it is preferable to perform a step of forming a supply channel connecting the other surface of the substrate with the common liquid chamber. Furthermore, by changing the opening area in the divided opening pattern, the depth of the common liquid chamber in the area near the position where the common liquid chamber connects to the supply channel may be made greater than the depth in other areas of the common liquid chamber. [Example]

[0052] [Example 1] An example in which the processing method of the present invention is applied to the manufacture of a liquid ejection head will be described. A liquid ejection head was manufactured using the mask pattern 104 described in the embodiment above. FIG. 12 is a cross-sectional view showing the manufacturing method in sequence. A silicon substrate 201 having a diameter of 200 mm and a surface with a plane index of (100) was prepared, and multiple liquid ejection heads were to be manufactured simultaneously from it. As shown in FIG. 12(a), a mask pattern 104 was formed on one surface (the upper surface in the figure) of the silicon substrate 201, and energy generating elements 202 were previously formed on the other surface (the lower surface in the figure) via an insulating film 208. The silicon substrate 201 had a thickness of 625 μm. The mask pattern 104 was formed by coating one surface of the silicon substrate 201 with a 17 μm-thick photosensitive positive resist and exposing the coated positive resist using a g-line 1:1 exposure device.

[0053] The opening pattern 101 for forming the common liquid chamber was designed as a rectangular opening with a width of 200 μm and a length of 20,000 μm. However, taking into account the expansion that occurs when the separation wall is removed (e.g., 2 μm in the example shown in FIG. 8), the opening formed in the mask pattern 104 was designed to be 198 μm in width and 19,998 μm in length. This type of opening pattern 101 was arranged in an array on the surface of the silicon substrate 201 to form the final shape. The aperture ratio was 36%, which significantly increases the loading effect. The in-plane uniformity of the etching rate in the high-speed silicon etching process described below was calculated to be 17.6% using the method described with reference to FIG. 4. In FIG. 12, the right edge of the illustration is the center of the silicon substrate 201, and the left edge is the peripheral edge, i.e., the outer periphery, of the silicon substrate 201.

[0054] The depth of the common liquid chamber formed in the silicon substrate 201 needs to be uniform in the in-plane direction of the silicon substrate 201. Of the positions where the opening patterns 101 are formed, position 203 is the "maximum" position on the periphery of the silicon substrate 201 and is described using Table 1, position 204 is the "average" position, and position 205 is the "minimum" position near the center of the silicon substrate 201. Position 204, which is the "average" position, is located 20 mm from the periphery of the silicon substrate 201. In order to correct the etching rate using the divided opening patterns 103, each opening pattern 101 was divided by the divided opening patterns 103 as follows. That is, at position 203, which is the "maximum" position, 10 rows and 9 rows of divided opening patterns 103, each with openings measuring 1998 μm in length and 20 μm in width, were arranged within the area outlined by the opening pattern 101. Similarly, at position 204, which is the "average" position, divided aperture patterns 103 with apertures of 9997 μm in length and 26 μm in width were arranged in two vertical rows and seven horizontal rows. At position 205, which is the "minimum" position, the aperture was made up of aperture pattern 101 itself. In other words, aperture pattern 101 was not divided by divided aperture patterns 103. At positions between these three positions 203, 204, and 205, the opening area of divided aperture pattern 103 was set to the intermediate value of the values at those positions. The width of separation wall 105 was set to 2 μm. This width of separation wall 105 is close to the resolution limit of the exposure equipment and resist used.

[0055] After forming the mask pattern 104 as described above, high-speed silicon etching was performed to form a common liquid chamber 206, with a target depth of 475 μm, as shown in FIG. 12(b). The etching conditions were such that the opening pattern 101 was not divided by the divided opening patterns 103, and the etching rate was 11.5 μm / min at the periphery of the silicon substrate 201 and 8.1 μm / min at the center of the silicon substrate 201. Under these etching conditions, the in-plane uniformity of the etching rate was 17.6%. In this example, dividing the opening pattern 101 into divided opening patterns as described above resulted in an almost uniform etching depth for all opening patterns 101. Next, the resist forming the mask pattern 104 was removed by ashing, and then the separation walls 105 were removed by isotropic etching using SF6, as shown in FIG. 12(c).

[0056] Next, a supply channel 207 was formed on the other surface of the silicon substrate 201. First, the insulating film 208 formed on the other surface of the silicon substrate 201 when the energy generating element 202 was fabricated was removed in the shape of the supply channel 207. Then, as shown in FIG. 12(d), high-speed etching of the silicon was performed to connect the supply channel 207 to the common liquid chamber 206.

[0057] Finally, a film of photosensitive epoxy resin was laminated onto the other surface of the silicon substrate 201 to form a discharge port forming member 209. Then, by repeating exposure and development twice on the discharge port forming member 209, discharge ports 210 and pressure chambers 211 extending from the supply channels 207 to the discharge ports 210 were formed, and a liquid discharge head was fabricated as shown in FIG. 12(e).

[0058] In a liquid ejection head, the depth of the common liquid chamber 206 affects flow resistance, so a deeper chamber is desirable. On the other hand, if the chamber is made too deep, the remaining portion 212 (see FIG. 12(e)) of the silicon substrate 201 becomes thinner. The remaining portion 212 maintains the rigidity of the liquid ejection head and also functions as a heat storage layer, so if this portion is reduced too much, it may affect the performance of the liquid ejection head. When manufacturing a large number of liquid ejection heads from the silicon substrate 201, the occurrence of a depth distribution of the common liquid chamber 206 within the surface of the silicon substrate 201 is undesirable, as it limits the design margin for achieving good performance as a liquid ejection head. Therefore, it is extremely effective to be able to form the common liquid chamber 206 with a uniform depth, as shown in this embodiment.

[0059] [Example 2] As described above, in order to maintain the rigidity of the liquid ejection head and to function as a heat storage layer, it is necessary to leave a portion of the silicon substrate 201 with a certain thickness as the remaining portion 212. On the other hand, from the viewpoint of reducing flow resistance and refilling the pressure chambers 211 with liquid, it is preferable to have a short supply path 207. Since the sum of the length of the supply path 207 and the depth of the common liquid chamber 206 is the thickness of the silicon substrate 201, the length of the supply path 207 is automatically determined by the depth of the common liquid chamber 206. In Example 2, we investigated shortening only the length of the supply path 207 while maintaining the thickness of the remaining portion 212. Figure 13 explains the manufacture of a liquid ejection head in Example 2, where Figure 13(a) is a plan view and Figure 13(b) is a cross-sectional view.

[0060] In Example 2, as shown in FIG. 13(a), the mask pattern 104 was designed so that the opening area of the divided opening pattern 103 was larger only in the portion corresponding to the supply channel 207 than in the surrounding area. The method for manufacturing the liquid ejection head conformed to Example 1. As a result, as shown in FIG. 13(b), a pinpointed portion 301 where the common liquid chamber 206 is slightly deeper could be formed only in the portion of the common liquid chamber 206 corresponding to the supply channel 207. In the example shown in FIG. 13, the depth of the common liquid chamber 206 in the region near the position where it connects to the supply channel 207 is greater than the depth in other regions of the common liquid chamber 206. This made it possible to substantially shorten the supply channel 207 while maintaining the rigidity and heat storage function of the liquid ejection head. [Explanation of symbols]

[0061] 100 wafers 101 Opening Pattern 102 chips 103 Split Opening Pattern 104 Mask Pattern

Claims

1. A processing method for arranging a plurality of opening patterns on a silicon substrate, comprising: forming a mask pattern on the surface of the silicon substrate, the mask pattern being configured such that a plurality of divided opening patterns are arranged within an area defined by at least one of the opening patterns; an etching step of processing the silicon substrate by reactive ion etching through the mask pattern; and an opening area of the divided opening pattern arranged within a region of a contour of the opening pattern is set for each opening pattern in the mask pattern so that at least a part of a change in etching rate due to a loading effect depending on a position of the opening pattern in a plane of the silicon substrate is offset by a change in etching rate due to a microloading effect depending on the opening area of the divided opening pattern; a separation wall separating the divided opening patterns from each other is removed during the etching step or after the etching step is completed.

2. 2. The processing method according to claim 1, wherein when a first opening pattern and a second opening pattern that is closer to an outer periphery of the silicon substrate than the first opening pattern are arranged on the silicon substrate, the mask pattern is formed such that an opening area of each of the divided opening patterns arranged within an area outlined by the second opening pattern is smaller than an opening area of each of the divided opening patterns arranged within an area outlined by the first opening pattern.

3. 3. The processing method according to claim 1, wherein in at least one of the aperture patterns, the divided aperture patterns arranged within the region defined by the aperture pattern have the same shape and size.

4. The processing method according to claim 1 , wherein in at least one of the opening patterns, the opening areas of the plurality of divided opening patterns arranged within an area defined by the opening pattern are different from each other.

5. A processing method for arranging a plurality of opening patterns on a silicon substrate, comprising: forming a mask pattern on the surface of the silicon substrate, the mask pattern being configured such that a plurality of divided opening patterns are arranged within an area defined by at least one of the opening patterns; an etching step of processing the silicon substrate by reactive ion etching through the mask pattern; and when arranging a first opening pattern and a second opening pattern that is closer to the outer periphery of the silicon substrate than the first opening pattern on the silicon substrate, the mask pattern is formed such that an opening area of each of the divided opening patterns that is arranged in a region defined by the second opening pattern is smaller than an opening area of each of the divided opening patterns that is arranged in a region defined by the first opening pattern, a separation wall separating the divided opening patterns from each other is removed during the etching step or after the etching step is completed.

6. The processing method according to claim 1 , wherein a ratio of an area of the separation wall to an area of a contour region of the opening pattern is 15% or less.

7. 7. The processing method according to claim 1, wherein the separation wall is removed by isotropic dry etching or anisotropic wet etching after the etching step.

8. The processing method according to claim 1 , wherein the plurality of opening patterns are arranged in an array on the silicon substrate.

9. 9. The processing method according to claim 8, further comprising the step of cutting out a chip including the opening pattern from the silicon substrate after the etching step.

10. A method for manufacturing a liquid ejection head in which a plurality of energy generating elements are arranged on one surface of a substrate and a common liquid chamber is formed as an opening on the other surface of the substrate, a first step of performing the processing method according to any one of claims 1 to 7 on a silicon substrate having the plurality of energy generating elements formed on one surface thereof, and collectively forming the plurality of common liquid chambers arranged in an array as the opening pattern on the other surface of the silicon substrate; a separation step of cutting out the substrates of the liquid ejection heads individually from the silicon substrate after the first step; A method for manufacturing a liquid ejection head, comprising:

11. 11. The method for manufacturing a liquid ejection head according to claim 10, further comprising the step of forming a supply path that connects the one surface of the silicon substrate with the common liquid chamber after the first step and before the separation step.

12. A method for manufacturing a liquid ejection head in which a plurality of energy generating elements are arranged on one surface of a substrate and a common liquid chamber is formed as an opening on the other surface of the substrate, a first step of carrying out the processing method according to claim 4 on a silicon substrate having the plurality of energy generating elements formed on one surface thereof, and collectively forming the plurality of common liquid chambers arranged in an array as the opening pattern on the other surface of the silicon substrate; a step of forming a supply path that communicates the one surface of the silicon substrate with the common liquid chamber after the first step; a separation step of cutting out the substrates of the liquid ejection heads individually from the silicon substrate after forming the supply paths; and A method for manufacturing a liquid ejection head, characterized in that by making the opening areas of the divided opening patterns different from each other, the depth of the common liquid chamber in an area near the position where the common liquid chamber connects to the supply path is made greater than the depth in other areas of the common liquid chamber.

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