Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving reliability of a trench gate structure.SOLUTION: A semiconductor device includes a semiconductor part, first to third electrodes, a control electrode, and first to third insulating films. The first electrode is disposed on a back side surface of the semiconductor part and the second electrode is disposed on a front side surface thereof. The semiconductor part has a trench which has an opening in the surface, and the third electrode is provided in an inside of the trench. In the inside of the trench, the control electrode is disposed at the opening side and has first and second control parts which are arranged in a direction parallel to the back surface. The first insulating film is disposed between the semiconductor part and the third electrode, and the second insulating film is disposed between the semiconductor part and the control electrode. The third electrode has an edge portion extending between the first and second control parts, and the first insulating film has an extending portion extending between the edge portion of the third electrode and the control electrode. The third insulating film extends between the extending portion and the edge portion of the third electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices are required to have improved reliability. For example, some trench-gate MOSFETs have a structure in which a field plate is placed inside the gate trench. In such semiconductor devices, it is desirable to increase the dielectric strength of the insulating film that electrically insulates the gate electrode from the field plate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-150185 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device with improved reliability of a trench gate structure. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, first to third electrodes, a control electrode, and first to third insulating films. The first electrode is provided on a back surface of the semiconductor portion, and the second electrode is provided on a front surface of the semiconductor portion opposite the back surface. The third electrode is provided between the first electrode and the second electrode. The semiconductor portion has a trench with an opening in the front surface, and the third electrode extends within the trench in a first direction from the first electrode to the second electrode. The control electrode is provided within the trench on the opening side of the trench and has first and second control portions aligned in a second direction parallel to the back surface of the semiconductor portion. The third electrode has an end portion extending between the first and second control portions of the control electrode. The first insulating film is provided between the semiconductor portion and the third electrode and electrically insulates the third electrode from the semiconductor portion. The second insulating film is provided between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion. The third insulating film covers the end of the third electrode and electrically insulates the third electrode from the control electrode. The control electrode is located between the first insulating film and the second electrode, and the first insulating film has an extension that extends between the end of the third electrode and the control electrode. The third insulating film extends between the extension of the first insulating film and the end of the third electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3] 3A to 3C are schematic cross-sectional views showing the manufacturing process following FIG. 2. [Figure 4] 4A to 4C are schematic cross-sectional views showing the manufacturing process following FIG. 3. [Figure 5] 5A to 5C are schematic cross-sectional views showing the manufacturing process following FIG. 4. [Figure 6] FIG. 2 is another schematic cross-sectional view showing the semiconductor device according to the embodiment. [Figure 7]FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a power MOSFET. The semiconductor device 1 includes, for example, a semiconductor portion 10, a drain electrode 20, a source electrode 30, a field plate electrode (hereinafter, referred to as an FP electrode 40), and a gate electrode 50.

[0010] The semiconductor portion 10 is made of, for example, silicon. The semiconductor portion 10 has a back surface 10B and a front surface 10F opposite to the back surface 10B. A drain electrode 20 (first electrode) is provided on the back surface 10B of the semiconductor portion 10. A source electrode 30 (second electrode) is provided on the front surface 10F of the semiconductor portion 10. The FP electrode 40 is provided inside the semiconductor portion 10 between the drain electrode 20 and the source electrode 30.

[0011] The semiconductor portion 10 includes, for example, an n-type drift layer 11, a p-type base layer 13, an n-type source layer 15, a p-type contact layer 17, and an n-type buffer layer 19. In the following description, the first conductivity type is referred to as n-type and the second conductivity type is referred to as p-type.

[0012] The n-type drift layer 11 (first layer) extends between the drain electrode 20 and the source electrode 30. The p-type base layer 13 (second layer) is provided between the n-type drift layer 11 and the source electrode 30. The p-type source layer 15 (third layer) is provided between the p-type base layer 13 and the source electrode 30.

[0013] The semiconductor portion 10 has a gate trench GT. The gate trench GT has an opening in a surface 10F of the semiconductor portion 10 (see FIG. 2(a)). The gate trench GT has a depth extending from the surface 10F of the semiconductor portion 10 into the n-type drift layer 11. The FP electrode 40 and the gate electrode 50 are provided inside the gate trench GT.

[0014] The FP electrode 40 (third electrode) extends in a first direction, for example, the Z direction, from the drain electrode 20 toward the source electrode 30 inside the gate trench GT. The FP electrode 40 is electrically insulated from the semiconductor portion 10 by a field plate insulating film 43 (first insulating film). The field plate insulating film 43 (hereinafter, FP insulating film 43) is provided between the semiconductor portion 10 and the FP electrode 40. The FP electrode 40 is provided to face the n-type drift layer 11 with the FP insulating film 43 interposed therebetween.

[0015] The gate electrode 50 (control electrode) is provided on the opening side of the gate trench GT. The gate electrode 50 is electrically insulated from the semiconductor portion 10 by a gate insulating film 53 (second insulating film). The gate insulating film 53 is provided between the semiconductor portion 10 and the gate electrode 50. The gate electrode 50 faces the p-type base layer 13 via the gate insulating film 53. In addition, the n-type source layer 15 is provided between the p-type base layer 13 and the source electrode 30 so as to be in contact with the gate insulating film 53.

[0016] Furthermore, the gate electrode 50 includes a first control unit 50a and a second control unit 50b. The first control unit 50a and the second control unit 50b are aligned in a second direction, for example, the X direction, parallel to the back surface 10B of the semiconductor unit 10. The first control unit 50a and the second control unit 50b are connected, for example, at a portion not shown, and biased to have the same potential.

[0017] 1, the FP electrode 40 has an end 40e that extends between the first control unit 50a and the second control unit 50b of the gate electrode 50. The end 40e of the FP electrode 40 is electrically insulated from the gate electrode 50 by an inter-electrode insulating film 45 (third insulating film). The inter-electrode insulating film 45 covers the end 40e of the FP electrode 40.

[0018] The gate electrode 50 is located between the FP insulating film 43 and the source electrode 30. The FP insulating film 43 includes an extension 43e that extends between the end 40e of the FP electrode 40 and the gate electrode 50. The inter-electrode insulating film 45 is provided to extend between the end 40e of the FP electrode 40 and the extension 43e of the FP insulating film 43.

[0019] That is, the extension 43e of the FP insulating film 43 and the inter-electrode insulating film 45 are interposed between the end 40e of the FP electrode 40 and the first control unit 50a and second control unit 50b of the gate electrode 50, respectively. The FP electrode 40 is electrically insulated from the gate electrode 50 by two insulating films aligned in the direction from the end 40e toward the gate electrode 50. This makes it possible to increase the dielectric strength voltage between the FP electrode 40 and the gate electrode 50.

[0020] An interlayer insulating film 55 (fourth insulating film) is provided above the FP electrode 50 and the gate electrode 50. The interlayer insulating film 55 is provided between the semiconductor portion 10 and the source electrode 30, between the FP electrode 40 and the source electrode 30, and between the gate electrode 50 and the source electrode 30. The interlayer insulating film 55 electrically insulates the gate electrode 50 from the source electrode 30.

[0021] The source electrode 30 has a contact portion 30c that penetrates the interlayer insulating film 55 and is connected to the semiconductor portion 10. The contact portion 30c extends into a contact hole provided in the interlayer insulating film 55.

[0022] The contact portion 30c of the source electrode 30 is in contact with and electrically connected to the n-type source layer 15 and the p-type contact layer 17. The p-type contact layer 17 is provided between the p-type base layer 13 and the contact portion 30c. The p-type contact layer 17 contains a p-type impurity at a concentration higher than the concentration of the p-type impurity in the p-type base layer 13. The p-type base layer 13 is electrically connected to the source electrode 30 via the p-type contact layer 17.

[0023] The n-type buffer layer 19 is provided between the n-type drift layer 11 and the drain electrode 20. The n-type buffer layer 19 contains an n-type impurity at a concentration higher than the concentration of the n-type impurity in the n-type drift layer 11. The drain electrode 20 is electrically connected to the n-type drift layer via the n-type buffer layer 19.

[0024] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 2(a) to 5(c). Figures 2(a) to 5(c) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0025] The semiconductor device 1 uses, for example, a silicon wafer 100. The silicon wafer 100 includes an n-type silicon substrate 101 and an n-type silicon layer 103. The n-type silicon layer 103 is, for example, epitaxially grown on the n-type silicon substrate 101. The n-type silicon layer 103 contains an n-type impurity at a concentration lower than the concentration of the n-type impurity in the n-type silicon substrate 101.

[0026] 2(a), a gate trench GT is formed in the n-type silicon layer 103. The gate trench GT has an opening in a surface 103F of the n-type silicon layer 103. The gate trench GT is formed by using, for example, anisotropic RIE (Reactive Ion Etching).

[0027] 2(b), an FP insulating film 43 is formed on the n-type silicon layer 103. The FP insulating film 43 is formed so as to cover the inner surface of the gate trench GT. The FP insulating film 43 is formed so as to leave a space SP1 inside the gate trench GT.

[0028] The FP insulating film 43 is formed, for example, by thermally oxidizing the n-type silicon layer 103 and then using CVD (Chemical Vapor Deposition). The FP insulating film 43 is, for example, a silicon oxide film. The FP insulating film 43 includes, for example, a thermally oxidized silicon film and a film deposited by CVD.

[0029] As shown in FIG. 2(c), a conductive film 105 is formed on the FP insulating film 43. The conductive film 105 is formed so as to fill the space SP1 in the gate trench GT. The conductive film 105 is, for example, a conductive polysilicon film. The conductive film 105 is formed using, for example, CVD.

[0030] 3A, the FP electrode 40 is formed in the gate trench GT by partially removing the conductive film 105. The conductive film 105 is removed by, for example, isotropic dry etching, leaving behind the portion embedded in the gate trench GT.

[0031] 3(b), the FP insulating film 43 is partially removed to flatten the surface 103F side of the n-type silicon layer 103. The FP insulating film 43 is removed by, for example, isotropic dry etching.

[0032] As shown in FIG. 3(c), the FP insulating film 43 is partially removed to form a gate space GS. The FP insulating film 43 is removed by, for example, dry etching using an etching mask (not shown). The gate space GS is formed so that the upper part of the inner wall of the gate trench GT is exposed. The gate space GS is formed on both sides of the end 40e of the FP electrode 40. An extension 43e of the FP insulating film 43 is left between the gate space GS and the end 40e of the FP electrode 40.

[0033] As shown in FIG. 4A, an inter-electrode insulating film 45 and a gate insulating film 53 are formed. The inter-electrode insulating film 45 and the gate insulating film 53 are formed by, for example, thermal oxidation. The gate insulating film 53 is formed by oxidizing the exposed surface of the n-type silicon layer 103. The inter-electrode insulating film 45 is formed by thermally oxidizing the end 40e of the FP electrode 40. During this process, not only the exposed top end of the FP electrode 40 but also the side surface of the end 40e is oxidized. The end 40e of the FP electrode 40 is oxidized by oxygen that has passed through the extension 43e of the FP insulating film 43. In other words, the extension 43e of the FP insulating film 43 is formed to a thickness that allows the end 40e of the FP electrode 40 to be oxidized. As a result, the inter-electrode insulating film 45 is formed to cover the end 40e of the FP electrode 40 and extend between the end 40e and the extension 43e of the FP insulating film 43.

[0034] The interelectrode insulating film 45 and the gate insulating film 53 are, for example, silicon oxide films. The interelectrode insulating film 45 has a film density different from that of the extension 43e of the FP insulating film 43. In other words, the number of dangling bonds of silicon atoms that are not bonded to oxygen in the interelectrode insulating film 45 is smaller than that of the dangling bonds of silicon atoms in the FP insulating film 43. Therefore, in a cross-sectional TEM image or SEM image, the brightness of the interelectrode insulating film 45 is different from that of the extension 43e of the FP insulating film 43.

[0035] As shown in FIG. 4(b), a conductive film 107 is formed on the surface 103F side of the n-type silicon layer 103. The conductive film 107 is provided so as to fill the gate space GS. The conductive film 107 is, for example, polysilicon having conductivity. The conductive film 107 is formed using, for example, CVD.

[0036] 4(c), the conductive film 107 is removed, leaving the portion filling the gate space GS. This forms the first control portion 50a and the second control portion 50b of the gate electrode 50. The end portion 40e of the FP electrode 40 is located between the first control portion 50a and the second control portion 50b.

[0037] As shown in FIG. 5( a), a p-type base layer 13 and an n-type source layer 15 are formed on an n-type silicon layer 103. The n-type source layer 15 is formed on the p-type base layer 13. The p-type base layer 13 is formed by ion-implanting p-type impurities, such as boron (B), into the n-type silicon layer 103 and performing heat treatment. The ion-implanted p-type impurities are activated by the heat treatment and diffuse into the n-type silicon layer 103. The n-type source layer 15 is formed by ion-implanting n-type impurities, such as arsenic (As), into the p-type base layer 13 and performing heat treatment to activate them. The heat treatment is performed so that the n-type impurities do not diffuse into the p-type base layer 13.

[0038] 5(b), an interlayer insulating film 55 is formed on the surface 103F side of the n-type silicon layer 103. The interlayer insulating film 55 is formed so as to cover the FP electrode 40 and the gate electrode 50. The interlayer insulating film 55 is, for example, a silicon oxide film. The interlayer insulating film 55 is formed using, for example, CVD.

[0039] Subsequently, a contact trench CT is formed above the n-type source layer 15. The contact trench CT has a depth that reaches from the surface of the interlayer insulating film 55 to the semiconductor portion 10. The contact trench CT is formed to a depth that penetrates the n-type source layer 15 and reaches the p-type base layer 13, for example.

[0040] 5(c), after the p-type contact layer 17 is formed on the p-type base layer 13, the source electrode 30 is formed on the interlayer insulating film 55. The p-type contact layer 17 is formed by implanting p-type impurities, for example, boron (B), into the semiconductor portion 10 through the contact trench CT and activating the impurities by heat treatment. The source electrode 30 extends into the contact trench CT and has a contact portion 30c in contact with the n-type source layer 15 and the p-type contact layer 17.

[0041] The source electrode 30 includes, for example, tungsten (W), aluminum (Al), titanium (Ti), or the like. The source electrode 30 includes, for example, a tungsten film formed to fill the contact trench CT, and an aluminum film formed on the tungsten film. The tungsten film is formed, for example, by CVD. The aluminum film is formed, for example, by sputtering.

[0042] Next, the back surface side of the n-type silicon substrate 101 is thinned by grinding or etching. As a result, an n-type buffer layer 19 is formed by thinning the n-type silicon substrate 101. The n-type silicon layer 103 becomes the n-type drift layer 11. Furthermore, a drain electrode 20 is formed on the back surface side of the n-type buffer layer 19, thereby completing the semiconductor device 1. The drain electrode 20 is formed, for example, by sputtering, and contains titanium (Ti), nickel (Ni), or the like.

[0043] The above manufacturing method is merely an example, and the embodiment is not limited thereto. For example, the FP insulating film 43 and the inter-electrode insulating film 45 may be insulating films other than silicon oxide films. Furthermore, the FP insulating film 43 may be an insulating film having a different composition from the inter-electrode insulating film 45.

[0044] FIG. 6 is another schematic cross-sectional view showing the semiconductor device 1 according to the embodiment. 6, the source electrode 30 further includes, for example, a contact portion 30d. The contact portion 30d is formed in, for example, a contact hole provided in the interelectrode insulating film 45 and the interlayer insulating film 55, and is connected to the source electrode 30. The FP electrode 40 is electrically connected to the source electrode 30 via the contact portion 30d. As a result, the FP electrode 40 and the source electrode 30 have the same potential.

[0045] 7 is a schematic cross-sectional view showing a semiconductor device 2 according to a modified example of the embodiment. In this example, the FP electrode 40 also has an end portion 40e extending between the first control portion 50a and the second control portion 50b of the gate electrode 50. The FP electrode 40 is also electrically connected to the source electrode 30 at a portion not shown.

[0046] The FP insulating film 43 includes an extension 43e extending between an end 40e of the FP electrode 40 and the gate electrode 50. The extension 43e has, for example, a first film thickness in the X direction at the tip in the Z direction and a second film thickness in the X direction between the FP electrode 40 and the lower end of the gate electrode 50 that contacts the FP insulating film 43, and is provided so that the first film thickness is thinner than the second film thickness.

[0047] Furthermore, the upper end of the gate electrode 50 facing the interlayer insulating film 55 is in contact with the interelectrode insulating film 45. The film thickness (third film thickness) in the X direction of the portion of the interelectrode insulating film 45 that is in contact with the gate electrode 50 is greater than the film thickness (fourth film thickness) in the X direction of the portion that faces the lower end of the gate electrode 50 via the extension portion 43e of the FP insulating film 43.

[0048] In this example as well, by providing a two-layer insulating film including the extension 43e of the FP insulating film 43 and the inter-electrode insulating film 45 between the end 40e of the FP electrode 40 and the gate electrode 50, it is possible to increase the dielectric strength voltage between the FP electrode 40 and the gate electrode 50. This improves the reliability of the trench gate electrode.

[0049] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0050] 1, 2...semiconductor device, 10...semiconductor portion, 10B...back surface, 10F, 103F...surface, 11...n-type drift layer, 13...p-type base layer, 15...n-type source layer, 17...p-type contact layer, 19...n-type buffer layer, 20...drain electrode, 30...source electrode, 30c, 30d...contact portion, 40...field plate (FP) electrode, 40e...edge, 43...field plate (FP) insulating film, 43e...extension portion, 45...inter-electrode insulating film, 50...gate electrode, 50a...first control portion, 50b...second control portion, 53...gate insulating film, 55...interlayer insulating film, 100...silicon wafer, 101...n-type silicon substrate, 103...n-type silicon layer, 105, 107...conductive film, CT...contact trench, GS...gate space, GT: Gate trench, SP1: Space

Claims

1. A semiconductor part; a first electrode on a back surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode, wherein the semiconductor portion has a trench having an opening in the surface, and the third electrode extends in the trench in a first direction from the first electrode toward the second electrode; a control electrode provided inside the trench on the opening side, the control electrode having a first control portion and a second control portion aligned in a second direction parallel to the back surface of the semiconductor portion, wherein an end of the third electrode extends between the first control portion and the second control portion; a first insulating film provided between the semiconductor portion and the third electrode, electrically insulating the third electrode from the semiconductor portion; a second insulating film provided between the semiconductor portion and the control electrode, electrically insulating the control electrode from the semiconductor portion; a third insulating film covering the end of the third electrode and electrically insulating the third electrode from the control electrode; Equipped with the control electrode is located between the first insulating film and the second electrode, the first insulating film has an extension extending between an end of the third electrode and the control electrode, the third insulating film extends between the extending portion of the first insulating film and the end portion of the third electrode, a first end of the control electrode on the second electrode side contacts the third insulating film; a second end of the control electrode on the first insulating film side contacts the first insulating film.

2. 2. The semiconductor device according to claim 1, wherein the extension of the first insulating film has a first film thickness in the second direction at the tip in the first direction, and a second film thickness in the second direction between the second end of the control electrode and the third electrode, and the first film thickness is thinner than the second film thickness.

3. the third insulating film has a third film thickness at a portion contacting the first end of the control electrode and a fourth film thickness at a portion facing the second end of the control electrode via the extension portion of the first insulating film, The semiconductor device according to claim 1 , wherein the third film thickness is greater than the fourth film thickness.

4. 4. The semiconductor device according to claim 1, further comprising a fourth insulating film provided between the second electrode and the control electrode and between the second electrode and the third electrode, electrically insulating the control electrode from the second electrode.

5. the semiconductor portion includes: a first layer of a first conductivity type extending between the first electrode and the second electrode; a second layer of a second conductivity type provided between the first layer and the second electrode; and a third layer of the first conductivity type provided between the second layer and the second electrode and in contact with the second insulating film; 5. The semiconductor device according to claim 1, wherein the second layer faces the control electrode via the second insulating film.

6. the semiconductor portion further includes a fourth layer of the second conductivity type provided between the second layer and the second electrode and containing a second conductivity type impurity at a concentration higher than that of the second conductivity type impurity of the second layer; 6. The semiconductor device according to claim 5, wherein the second electrode has a first contact portion that is in contact with and electrically connected to the third layer and the fourth layer.

7. 7. The semiconductor device according to claim 1, wherein the second electrode has a second contact portion extending into the third insulating film and connected to the third electrode, and is electrically connected to the third electrode via the second contact portion.

Images