Transistor Cell

Abstract

To provide a GaN field effect transistor including a plurality of transistor cells.SOLUTION: A gate metal layer 150 of a transistor cell includes a gate-drain overhang (width 0.2 μm to 2.5 μm) and a gate-source overhang (width 0.3 μm to 1 μm), and a widening at each narrow edge of the transistor cell, wherein the width of the widening of gate metal layer is of 2 to 5 μm. A metal 1 layer of the transistor cell extends beyond metal 0 layer. A last metal layer includes a drain plate and a source plate, each having a trapezoid form. More than two vias are located in a widening for connecting the gate metal layer to the gate bus. More than six vias distributed along a longitudinal dimension of the transistor cell connect metal 1 layer to metal 0 layer. A plurality of type 2 vias connect the metal 1 layer to the last metal layer.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] Various products and systems, such as televisions, electric vehicles, radar systems, electric motor controls, and / or uninterruptible power supply systems, may require a supply of relatively large amounts of power that can be delivered from a high voltage power supply. Various types of semiconductor field effect transistors (FETs) can be used as power switches to perform the switching functions that may be required by the products and / or systems. Summary of the Invention [Means for solving the problem]

[0002] According to an embodiment of the present invention, there is provided a GaN field effect transistor (FET) including a plurality of transistor cells having a longitudinal dimension, wherein each transistor cell includes a silicon substrate, a III-V nitride semiconductor layer, an ohmic metal layer including an ohmic metal source terminal and an ohmic metal drain terminal, a gate metal layer including a gate-drain overhang, a gate-source overhang, and a widening at a narrow end of each of the transistor cells, wherein the gate-drain overhang has a width between 0.2 μm and 2.5 μm, the gate-source overhang has a width between 0.3 μm and 1 μm, and the widening of the gate metal layer has a width between 2 and 5 μm, a metal 0 layer, and a gate bus, and a metal 1 layer extending beyond the metal 0 layer along the longitudinal dimension of the transistor cell toward a center of the transistor cell and defining a second field plate, the second field plate including a metal 0 layer and a gate bus. a metal 1 layer having a field plate width of 3 to 6 μm and an overlap between the metal 1 layer and the metal 0 layer of −1 μm to 7 μm; a final metal layer including drain and source plates each having a trapezoidal shape; two first via 1 arrays disposed at the widening of the gate metal layer, each for electrically connecting the gate metal layer to a gate bus, each first via 1 array including more than two vias; more than six type 1 vias distributed along the longitudinal dimension of the transistor cell for electrically connecting the metal 1 layer to the metal 0 layer; and a plurality of type 2 vias electrically connecting the drain region from the metal 1 layer to the drain plate in the final metal layer and the source region from the metal 1 layer to the source plate in the final metal layer, wherein the gate metal layer, the metal 0 layer, and the metal 1 layer are insulated by a dielectric material.

[0003] According to an embodiment of the present invention, the GaN FET is a D-mode or E-mode GaN FET.

[0004] According to an embodiment of the present invention, the metal 1 layer includes an opening that extends along the longitudinal dimension of each transistor cell.

[0005] According to an embodiment of the present invention, the number of type 2 vias electrically connecting the drain regions from the metal 1 layer to the drain plate in the final metal layer is adapted to the width of the drain plate, and the number of type 2 vias electrically connecting the source regions from the metal 1 layer to the source plate in the final metal layer is adapted to the width of the source plate.

[0006] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. For simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity of presentation. Furthermore, reference numerals may be repeated among the figures to indicate corresponding or similar elements. However, the specification, both as to organization and method of operation, together with their objects, features, and advantages, will best be understood by reference to the following detailed description read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 3A-3C are schematic top views of the metal 1 and final metal layers of multiple adjacent transistor cells according to some embodiments of the present invention. [Figure 2] 2A-2C are schematic partial top views of the gate metal layer, metal 0 layer, and metal 1 layer of a transistor cell according to some embodiments of the present invention. [Figure 3] 1 is a schematic partial cross-sectional view of an exemplary transistor cell according to some embodiments of the present invention. [Figure 4] 2A-2C are schematic partial top view diagrams of gate metal layers of transistor cells according to some embodiments of the present invention. [Figure 5] FIG. 2 is a schematic partial top view of the gate metal layer, metal 0 and metal 1 layers, and several other layers of a transistor cell. [Figure 6] 2A-2C are schematic partial top views of the gate metal layer, metal 0 layer, and metal 1 layer of a transistor cell according to some embodiments of the present invention. [Figure 7] FIG. 2 is a schematic partial top view of the metal 1 layer (the top of the cell, including part of the gate bus), according to some embodiments of the present invention. [Figure 8] 3A-3C are schematic partial top view illustrations of a final metal layer according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of some embodiments. However, one skilled in the art will understand that some embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, units and / or circuits have not been described in detail so as not to obscure the discussion.

[0009] The terms "plurality" and "a plurality," as used herein, include, for example, "multiple" or "two or more." For example, "a plurality of items" includes two or more items.

[0010] References to "one embodiment," "one embodiment," "exemplary embodiment," "exemplary embodiment," "various embodiments," etc., mean that the embodiment(s) so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase "in one embodiment" does not necessarily refer to the same embodiment, although it may.

[0011] As used herein, unless specifically stated otherwise, the use of ordinal adjectives such as "first," "second," "third," etc. to describe general objects merely indicates that different instances of a similar object are being referred to, and is not intended to imply that the objects so described must be in a given order, temporally, spatially, sequentially, or in any other way.

[0012] According to some demonstrative embodiments, a semiconductor field effect transistor (FET) may be based on silicon (Si) material and / or other materials. For example, a FET may include a source terminal and a drain terminal, which may be used to connect a power source to a load. An additional terminal in the FET may be disposed between the source and drain terminals, which may be referred to as a gate terminal. The gate terminal may control the resistance of a current-carrying channel.

[0013] In operation, a voltage, which may be relative to a common ground, may be applied to the gate terminal. For example, this voltage may create an electric field within the FET, which may act, for example, to control the resistance of the FET and turn the transistor on and / or off. For example, when the FET is turned on, the voltage applied to the gate terminal may reduce the resistance in the current-carrying channel, for example, to allow a relatively large current to flow between the source and drain terminals. When the FET is turned on, the total resistance between the source and drain terminals may be referred to as the on-resistance, Rdson, of the transistor.

[0014] According to some illustrative embodiments, nitride-based semiconductors, such as gallium nitride (GaN) and aluminum nitride (AlN), can be characterized as having a relatively large bandgap. For example, the bandgap can be approximately 3.4 eV for GaN and / or approximately 6.2 eV for AlN. For example, a FET that can include a nitride semiconductor layer structure can further include a small bandgap layer adjacent to a large bandgap layer. These FETs can have a relatively high concentration of high-mobility electrons, which can be characterized as having a high saturated drift velocity. The high-mobility electrons can accumulate in narrow triangular potential wells at the interfaces between layers, forming a relatively thin sheet of electron concentration, which can be referred to as a two-dimensional electron gas (2DEG). For example, due to the geometry and / or location of the 2DEG, electrons within the 2DEG can generally exhibit very low donor-impurity scattering and, as a result, can have a lattice constant of, for example, 1800 cm , respectively. 2 / V*s and a relatively high electron mobility and / or velocity on the order of 1.5×10 cm / s. The concentration of electrons in the 2DEG is 1×10 cm / s. 2 As a result of the above, for example, FET transistors can have very low specific Rds(on).

[0015] According to some exemplary embodiments, a FET transistor that operates by generating and / or controlling high-mobility electrons in a 2DEG can be referred to as a high electron mobility transistor (HEMT). A semiconductor layer structure that can include multiple layers of different compositions can be referred to as having a heterostructure, and the interface between two adjacent layers of different compositions can be referred to as a heterojunction. In some embodiments, the present technology relates to a circuit that includes multiple parallel connections of transistor cells.

[0016] According to some embodiments, the term "cell" or "transistor cell" can be used to describe a basic device unit that can switch between a current flow mode and a voltage blocking mode according to embodiments of the present invention. A GaN switch power transistor, or GaN FET, can use one, two, or more cells connected in parallel by metal interconnects to provide a given performance of the GaN transistor, for example, to enable a higher current and lower Rdson of the GaN FET.

[0017] As known in the art, GaN FET transistors are typically designed and fabricated using known, well-established foundry-specific design rules that are usually supplied as a process design kit (PDK). While the basic operation and layer structure and functionality of the transistor cells disclosed herein are similar to GaN FET transistors, embodiments of the present invention, as detailed herein, deviate significantly from known reference cells, resulting in superior performance in terms of Miller ratio, Cgs to Cgd ratio, switching time, switching energy, etc.

[0018] Reference is now made to Figure 1, which is a schematic top view of the metal 1 layer 170 and final metal layer 180 of multiple adjacent FET cells, also referred to herein as transistor cells 100, in accordance with some embodiments of the present invention. The transistor cells 100 may be D-mode or E-mode GaN FETs. Region B in Figure 1 generally defines a single transistor cell 100. As can be seen, the transistor cell 100 has a general longitudinal shape with two narrow ends 113 and including a source plate 111 and a drain plate 112.

[0019] Reference is now made to Figure 2, which is a schematic partial top view of gate metal layer 150, metal 0 layer 160, and metal 1 layer 170 of transistor cell 100, in accordance with some embodiments of the present invention. Figure 2 is an expanded view of marked area A of Figure 1, with the layers defined above. Axis BB defines the center of transistor cell 100 along its longitudinal dimension.

[0020] Reference is now made to FIG. 3 , which is a schematic partial cross-sectional view of an exemplary transistor cell 100 along section line AA depicted in FIG. 2 , in accordance with an embodiment of the present invention. According to an embodiment of the present invention, the transistor cell 100 may be a layered structure including, listed from bottom to top, the following layers: a silicon substrate 110, a III-V nitride semiconductor layer 120, an ohmic metal source terminal 130, an ohmic metal drain terminal 140, and multiple conductive metal interconnect layers insulated by dielectric material 122. The metal layers may include (also listed from bottom to top) an ohmic metal layer 135, a gate metal layer 150, a metal 0 layer 160, a metal 1 layer 170, and a final metal layer 180. The metal layers may be electrically interconnected, as needed, by interconnect vias, e.g., via 1 190 and via 2 195. The ohmic metal layer 135 may include an ohmic drain 140 and an ohmic source 130.

[0021] The gate metal layer 150 may include a gate metal 152, which may be a protrusion, extending from the gate metal layer 150 to the semiconductor layer 120 between the ohmic drain 140 and the ohmic source 130. According to some embodiments, the length of the gate metal 152, marked Lr on FIG. 3, may be in the range of 1 to 2.5 micrometers (μm), excluding 2 μm. This range is different from the reference length of the gate.

[0022] The gate metal layer 150 may include a gate-drain overhang 154, which is an extension of the gate metal layer 150 toward the ohmic drain 140, and a gate-source overhang 156, which is an extension of the gate metal layer 150 toward the ohmic source 130. The width of the gate-drain overhang 154, marked as Lfpgd in FIG. 3 , and the width of the gate-source overhang 156, marked as Lfpgs in FIG. 3 , may affect the gate-drain capacitance Cgd and the gate-source capacitance Cgs, respectively, of the transistor cell 100. The width Lfpgd of the gate-drain overhang 154 may be in the range of 0.2 μm to 2.5 μm. The width Lfpgs of the gate-source overhang 156 may be in the range of 0.3 μm to 1 μm. Varying the widths of the gate-drain overhang 154 and the gate-source overhang 156 can change Cgd and Cgs, respectively, and can decrease the Cgd to Cgs ratio, which is equal to the Miller ratio. As is known, decreasing the Miller ratio can improve the performance of the transistor cell 100.

[0023] As known to those skilled in the art, widening the gate-drain overhang 154 (increasing Lfpgd) has the positive effect of reducing the electric field and the negative effect of increasing the Miller effect. Reducing the width of the gate-drain overhang 154 to the ranges specified herein improves the performance of the transistor cell 100, but at the same time risks increasing the electric field to a level that reduces reliability. However, the transistor cell 100 disclosed herein provides desirable reliability despite reducing the width of the gate field plate 154, while also providing the benefits of a reduced Miller effect.

[0024] Reference is now made to FIG. 4, which is a schematic, partial top view of the gate metal layer 150 of a transistor cell 100, according to some embodiments of the present invention. The gate metal layer 150 may include widenings 115 at the narrow ends of the transistor cell 100 on both sides of the transistor cell 100. The width of the widenings 115 of the gate metal layer 150 may be in the range of 2 to 5 μm. Such a configuration may improve the RC time constant of the gate or gate network and may provide an expanded area for placing a via 1 array 192 (e.g., an array including multiple type 1 vias) for electrically connecting the gate metal layer 150 to a gate bus 172 that is part of the metal 1 layer 170 (shown in FIGS. 6 and 7). The via 1 array 192 of the transistor cell 100 can be seen in FIGS. 2 and 6. Prior art designs typically include two vias for connecting the gate metal layer to the gate bus. The charging and discharging current of the gate capacitance typically flows through the via 1 array 192. Having a small number of vias in Via 1 Array 192 can result in overheating of Via 1 Array 192, thus limiting or reducing charge and discharge currents and reducing transistor reliability. Furthermore, limiting charge and discharge currents can result in degradation of switching times and reduce overall system efficiency. Typical designs include only two vias because known gate metal layers are not wide enough to accommodate more than two vias, and widening the gate metal layer can undesirably increase parasitic capacitance between the source and gate of the cell transistor. The rounded shape and size of widening 115 disclosed herein can provide a good tradeoff between charge and discharge current values and excess parasitic capacitance, eliminating sharp edges that can cause premature transistor failure.

[0025] Reference is now made to FIG. 5, which is a schematic, partial top view of gate metal layer 550, metal 0 layer 560, and metal 1 layer 570 of reference transistor cell 500, and FIG. 6, which is a schematic, partial top view of metal 0 layer 160 and metal 1 layer 170 of transistor cell 100. Metal 1 layer 170 includes gate bus 172, and metal 1 layer 570 includes gate bus 572. FIG. 5 illustrates the prior art connection of metal 1 layer 570 to metal 0 layer 560, while FIG. 6 illustrates the connection of metal 1 layer 170 to metal 0 layer 160 in accordance with some embodiments of the present invention. Via 194 electrically connecting metal 0 layer 160 and metal 1 layer 170 is a Type 1 via. In the prior art design depicted in FIG. 5 , typically two type 1 vias 590 are placed in each rounded end of the transistor cell 500, therefore, a total of four type 1 vias 590 connect the metal 1 layer 570 to the metal 0 layer 560. According to an embodiment of the present invention, as shown in FIG. 2 , type 1 vias 194 are placed along the longitudinal dimension of the transistor cell 100. As can be seen from FIG. 2 , the type 1 vias 194 can be distributed along the longitudinal dimension of the transistor cell 100. Therefore, the total number of type 1 vias 194 electrically connecting the metal 0 layer 160 and the metal 1 layer 170 can be greater than six. The advantage of using more vias is that a large number of vias can result in quick voltage distribution across the metal 0 layer 160, thereby improving the switching speed of the transistor cell 100.

[0026] 6 further illustrates the relative positions of the metal 1 layer 170 and the metal 0 layer 160 according to some embodiments. As can be seen, the metal 1 layer 170 can extend beyond the metal 0 layer 160 towards the center of the transistor cell 100 to create or define a second field plate 176. The width of the field plate 176, which can be in the range of 3-6 μm according to embodiments of the present invention, is marked Lfpm1 on FIG. 3. This second field plate 176 can improve the electric field distribution within the gate-drain region of the transistor cell 100. The overlap Lfpm1 between the metal 1 layer 170 and the metal 0 layer 160 can be from -1 μm to 7 μm (i.e., from a separation of 1 μm to 1 μm), as desired. 7 The thickness can vary (up to 1 μm overlap).

[0027] Reference is now made to Figure 7, which is a schematic, partial top view of metal 1 layer 170, according to some embodiments of the present invention. According to some embodiments, metal 1 layer 170 may include an opening 174 that may extend along the longitudinal dimension of transistor cell 100. According to some embodiments, opening 174 may be located above a gate-drain region. The size, shape, and placement of opening 174 within transistor cell 100 may affect the value of Cgd. Specifically, opening 174 may desirably reduce Cgd.

[0028] Reference is now made to FIG. 8 , which is a schematic, partial top view of final metal layer 180, according to some embodiments of the present invention. According to some embodiments, final metal layer 180 may include drain plates 112 and source plates 111, each having a trapezoidal shape (e.g., the trapezoidal shape shown in FIG. 8 ) and may extend under two columns of transistor cells 100. For example, source plate 111 may be back-to-back with drain plate 112, such that when the wider base of the trapezoid of drain plate 112 is on one side, the wider base of the trapezoid of source plate 111 is on the opposite side. Source plate 111 and drain plate 112 may provide good electrical connection to metal 1 layer 170 through type 2 vias 195 in source plate 111 and drain plate 112. Having trapezoidal drain and source plates 112, 111 on final metal layer 180 can help keep the current density in transistor cell 100 substantially constant along drain and source plates 112, 111 due to bond pad locations at the widest ends of the source and drain on the final metal layer electrodes. Final metal layer 180 is further described in commonly assigned U.S. Pat. No. 9,064,864, which is incorporated herein by reference in its entirety.

[0029] 1 , an arrangement of type 2 vias 195 that electrically connect the metal 1 layer 170 to the final metal layer 180 is shown, according to some demonstrative embodiments. For example, the type 2 vias 195 may connect drain regions from the metal 1 layer 170 to drain plates 112 in the final metal layer 180 that collect drain currents from various transistor cells 100, according to some demonstrative embodiments. Similarly, the type 2 vias 195 may connect source regions from the metal 1 layer 170 to source regions 111 in the final metal layer 180 that collect source currents from various transistor cells 100. As can be seen from FIG. 1 , the number or quantity of type 2 vias 195 is adapted to the local size or width of the corresponding drain plates 112 or source plates 111 in the final metal layer 180. For example, the drain plates 112 in the right-most cell of FIG. 1 are larger or wider than the other cells, and the number of type 2 vias 195 connecting the metal 1 layer 170 to the drain plates 112 in the final metal layer 180 is greater, respectively. However, because the source plate 111 of that cell is relatively small or narrow, a relatively small number of type 2 vias 195 connect the metal 1 layer 170 to the source plate 111 in the last metal layer 180 in that cell. The situation is reversed for the leftmost cell. The size or width of the drain plate 112 and source plate 111 are designed for the current density in those plates, so, for example, if the current density is expected to be high, the area of the drain plate 112 will be larger or wider, and vice versa, and the number of type 2 vias 195 will increase in areas of high current density.

[0030] While certain features of the present invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. A GaN field effect transistor (FET) comprising a plurality of transistor cells (100) having a longitudinal dimension and a narrow dimension defined by two narrow ends (113), each of the transistor cells comprising: A silicon substrate; a III-V nitride semiconductor layer; an ohmic metal layer (135) with an ohmic metal source terminal (130) and an ohmic metal drain terminal (140); a gate metal layer (150) having a stadium shape in plan view with elongated ends along the long dimension of the transistor cell and rounded ends along the narrow dimension of the cell, the gate metal (152) including gate-drain overhangs (154, Lfpgd), gate-source overhangs (156, Lfpgs) thereon, and wide regions (115) at each narrow end, wherein the widths of the gate-drain overhangs are between 0.2 μm and 2.5 μm, the widths of the gate-source overhangs are between 0.3 μm and 1 μm, and the widths of the wide regions of the gate metal layer are between 2 and 5 μm; a metal 0 layer (160) that acts as a first field plate; A Metal 1 layer (170), a first region electrically connected to the ohmic metal source terminal (130), extending to the center (BB) of the transistor cell and having an overlap (LOLM0M1) with the metal 0 layer of between 0 μm and 1 μm or a gap of between 0 μm and 1 μm; a second region (176) that defines a second field plate extending beyond the metal 0 layer along the longitudinal dimension of the transistor cell toward a center of the transistor cell and having a width (Lfpm1) of between 3 and 6 μm; a metal 1 layer (170) comprising a gate bus (172); a final metal layer (180) comprising a drain plate (112) and a source plate (111) each having a trapezoidal shape; two first via 1 arrays (192), each array comprising three or more type 1 vias (194), electrically connecting the wide regions (115) of the gate metal layer (150) to the gate bus (172) at different ends of the gate metal layer; more than six type 1 vias (194) distributed along the longitudinal dimension of the transistor cell and electrically connecting the metal 1 layer (170) to the metal 0 layer (160); a plurality of type 1 vias (190) electrically connecting an ohmic metal drain terminal (140) to a drain region of the metal 1 layer electrically connected to a drain plate (112) of the final metal layer (180) by a plurality of type 2 vias (195), and electrically connecting an ohmic metal source terminal (130) to a drain region of the metal 1 layer electrically connected to a source plate (111) of the final metal layer (180) by a plurality of type 2 vias (195); Equipped with The gate metal layer (150), the metal 0 layer (160), and the metal 1 layer (170) are insulated by a dielectric material (122). GaN FETs.

2. The GaN FET of claim 1 , wherein the GaN FET is a D-mode or E-mode GaN FET.

3. The GaN FET of claim 1 , wherein the metal 1 layer includes an opening (174) that extends along the longitudinal dimension of each of the transistor cells.

4. 2. The GaN FET of claim 1, wherein the number of type 2 vias electrically connecting drain regions from the metal 1 layer to the drain plate (112) in the final metal layer (180) is matched to the width of the drain plate, and the number of type 2 vias electrically connecting source regions from the metal 1 layer to the source plate (111) in the final metal layer (180) is matched to the width of the source plate.

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