Solid-state device having multiple thermopower states - Patent Application 20070122967

Abstract

An aspect of a storage device is provided that applies advanced thermal throttling in response to temperature changes based on multiple thermal power states for different types of cells, such as SLC and MLC. First, a controller determines that a temperature of the memory meets a thermal throttling threshold of multiple thermal throttling thresholds. The controller then transitions to one thermal power state of multiple thermal power states when the temperature meets the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state. The controller then determines that the temperature of the memory has reached thermal equilibrium in the thermal power state based on the thermal mitigation configuration. Thus, the performance of the storage device is improved by advanced thermal throttling without compromising data integrity.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application incorporates by reference herein the entire contents of U.S. Non-Provisional Application No. 17 / 741,242, entitled "SOLID-STATE DEVICE WITH MULTIPLE THERMAL POWER STATES," filed May 10, 2022, for all purposes.

[0002] FIELD OF THE INVENTION FIELD OF THE DISCLOSURE The present disclosure relates generally to electronic devices, and more particularly to storage devices. [Background technology]

[0003] introduction Storage devices allow users to store and retrieve data. Examples of storage devices include non-volatile memory devices. Non-volatile memory generally retains data after a power cycle. One example of non-volatile memory is flash memory, which may include an array(s) of NAND cells on one or more dies. Flash memory may be found in solid-state drives (SSDs), secure digital (SD) cards, etc.

[0004] Flash storage devices can store data in NAND cells of flash memory. NAND cells can include single-level cell (SLC) or multi-level cell (MLC). Examples of MLC include triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC). Generally, flash storage devices can write data directly to pages of SLC blocks. However, data can only be erased within blocks of flash memory. Therefore, when an SLC block becomes full, the flash storage device can relocate the data to an empty block through a garbage collection process to free up space in the flash memory. For example, data may be relocated to an MLC block.

[0005] As data is stored and accessed, the temperature of NAND cells may rise above their reliable operating temperature. For example, if the temperature of the MLC exceeds a certain thermal throttling threshold (e.g., 86°C) due to data relocation from the SLC, the integrity or reliability of the MLC data may be affected. Therefore, to maintain system data integrity, thermal throttling may be applied to keep the flash storage device below the thermal throttling threshold. For example, when the cell temperature exceeds 86°C, the flash storage device may disable parallel access to one or more dies or otherwise reduce the rate at which data is written to the NAND cells to reduce power consumption and then return the temperature below the threshold. However, this reduction in NAND operation may significantly reduce the performance of the flash storage device (e.g., by at least 50%), resulting in a degraded user experience and preventing the system from meeting performance benchmarks. Summary of the Invention

[0006]

[0009] An aspect of a storage device is disclosed herein. The storage device includes a memory and a controller. The controller is configured to determine a temperature of the memory satisfies a thermal throttle threshold among a plurality of thermal throttle thresholds, transition to a thermal power state among a plurality of thermal power states when the temperature satisfies the thermal throttle threshold, apply a thermal mitigation configuration associated with the thermal power state, and determine, based on the thermal mitigation configuration, that the temperature of the memory has reached thermal equilibrium with the thermal power state.

[0007] Another aspect of a storage device is disclosed herein. The storage device includes a memory and a controller. The controller is configured to adjust one or more thermal relaxation parameters associated with a thermal power state among a plurality of thermal power states based on a transition to the thermal power state when a temperature of the memory satisfies a thermal throttle threshold, and to determine that the temperature of the memory has reached thermal equilibrium with the thermal power state based on the adjusted one or more thermal relaxation parameters.

[0008]

[0010] Further aspects of a storage device are disclosed herein. The storage device includes a memory and a controller. The memory has a block of cells. The controller is configured to apply a thermal mitigation configuration associated with one of a plurality of thermal power states based on a transition to a thermal power state when a temperature of the block of cells meets a thermal throttling threshold, and to determine that the temperature of the block of cells has reached thermal equilibrium in the thermal power state based on the thermal mitigation configuration.

[0009] It is understood that other aspects of the storage device will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of the device and method are shown and described by way of example. As will be understood, these aspects may be implemented in other and different forms, and their several details are capable of modification in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature, and not as restrictive. [Brief explanation of the drawings]

[0010] Various aspects of the present invention will now be presented in the detailed description, by way of example and not limitation, with reference to the accompanying drawings, in which: [Figure 1] 1 is a block diagram illustrating an exemplary embodiment of a storage device in communication with a host device. [Figure 2] 2 is a conceptual diagram showing an example of a logical-to-physical mapping table in a nonvolatile memory of the storage device of FIG. 1. FIG. [Figure 3] 2 is a conceptual diagram showing an example of an arrangement of memory cells in the memory device of FIG. 1. FIG. [Figure 4] 2 is a conceptual diagram showing an example of an arrangement of blocks in the storage device of FIG. 1. FIG. [Figure 5] 2 is a graph showing an example of a voltage distribution diagram of a triple-level cell in the storage device of FIG. 1. FIG. [Figure 6] FIG. 2 is a conceptual diagram illustrating an example of a garbage collection (GC) process that may be implemented in the storage device of FIG. 1. [Figure 7] 1 shows an exemplary diagram of thermal throttling in a storage device. [Figure 8] 2 is a conceptual diagram illustrating a controller using advanced thermal throttling in the storage device of FIG. 1 to write data to a block at different data rates corresponding to different temperatures of the block. [Figure 9] 2 is a flowchart illustrating an example process for advanced thermal throttling in the storage device of FIG. 1. [Figure 10] FIG. 2 is a conceptual diagram illustrating a controller for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. [Figure 11] 2 is a flowchart illustrating an example process for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. [Figure 12] 2A-2C are conceptual diagrams illustrating various examples of advanced thermal throttling in the storage device of FIG. 1. [Figure 13] FIG. 2 is a conceptual diagram illustrating a state machine for multiple thermal power states for advanced thermal throttling in the storage device of FIG. 1. [Figure 14] 2 is a flowchart illustrating an exemplary process for an advanced thermal throttling first thermal power state in the storage device of FIG. 1. [Figure 15] 2 is a flowchart illustrating an exemplary process for an advanced thermal throttling second thermal power state in the storage device of FIG. 1. [Figure 16] 2 is a flowchart illustrating an exemplary process for a third thermal power state of advanced thermal throttling in the storage device of FIG. 1. [Figure 17] 10 is a flowchart illustrating an exemplary process for a fourth thermal power state of advanced thermal throttling in the storage device of FIG. [Figure 18A] FIG. 2 is a graph illustrating performance benchmarking using legacy thermal throttling in the storage device of FIG. 1. [Figure 18B] FIG. 2 is a graph illustrating performance benchmarking with advanced thermal throttling in the storage device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0011] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the present invention.

[0012] The words "exemplary" and "example" are used herein to mean "serving as an example, instance, or illustration." Any exemplary embodiment described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other exemplary embodiments. Similarly, the term "exemplary embodiment" of a device, method, or article of manufacture does not require that all exemplary embodiments of the invention include the described component, structure, feature, function, process, advantage, benefit, or mode of operation.

[0013] As used herein, the term "coupled" is used to indicate either a direct connection between two components, or, where appropriate, an indirect connection to one another through intervening or intermediate components. In contrast, when a component is referred to as being "directly coupled" to another component, there are no intervening components present.

[0014] In the following detailed description, various aspects of a storage device in communication with a host device are presented. These aspects are well suited to flash storage devices such as SSDs and SD cards. However, those skilled in the art will understand that these aspects may be extended to all types of storage devices capable of storing data. Accordingly, any reference to a specific device or method is intended solely to illustrate various aspects of the invention, with the understanding that such aspects may have a wide range of applications without departing from the spirit and scope of the present disclosure.

[0015] When a storage device performs thermal throttling, the storage device typically reduces the rate at which data is written to NAND cells as soon as the temperature of the die containing the NAND cells exceeds a threshold. However, when performing thermal throttling, the thermal throttling causes a hard transition at the thermal throttling threshold. For example, a storage device typically performs thermal throttling with a relatively large variation in data rate between transitions. For example, the storage device may reduce the write data rate using a first set of parameters when the die exceeds a first thermal throttling threshold at 80°C, and further reduce the write data rate using a second set of parameters that vary significantly from the first set of fixed parameters when the die exceeds a second thermal throttling threshold at 86°C. As a result of these large variations between transitions, device performance and power consumption may vary significantly between transitions over time, and user experience may be affected.

[0016] Therefore, to improve storage device performance and enhance user experience, the present disclosure enables a storage device to reach optimized and deterministic performance within a thermal envelope targeting reduced latency and minimal quality-of-service disruptions by selectively selecting a specific thermal configuration and dynamically adjusting internal mitigation parameters over time (or preemptively) to gradually align the storage device with host-specified thermal framework parameters. Typically, a storage device's controller routes data to memory in response to write commands from a host by storing the data directly in SLC blocks at a first data rate (e.g., full clock rate). As the number of free SLC blocks decreases, the controller reallocates data in the SLC blocks to MLC blocks. This reallocation may increase the temperature of the MLC blocks. When the temperature of the MLC blocks rises above a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller changes how data is routed to memory by disabling data reallocation from SLC blocks to MLC blocks and by restricting host data writes to SLC blocks. However, the controller now performs thermal throttling by applying a selected thermal mitigation configuration associated with a thermal power state by scaling the power budget based on a temperature gradient to maintain maximum possible performance while maintaining thermal balance within the thermal power state. This contrasts with large performance switches between thermal power state transitions when the storage device exceeds a corresponding thermal throttling threshold, thus allowing data to be written at thermally throttled data rates that translate to desired performance benchmarks for various workloads within the adjusted power budget.

[0017] The controller may initially begin writing host data to the block of cells at a first data rate (e.g., at the full clock rate) in response to a write command. The controller may then continue writing host data to the block of cells in response to the write command, which may cause the temperature of the block of cells to increase. If the temperature of the block of cells increases above a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller may transition to a first thermal power state and enable thermal throttling. For example, the controller may reduce the rate of data written to the SLC and MLC blocks to a smaller second data rate (e.g., at 60% of the full clock rate), e.g., by applying a thermal mitigation configuration associated with the first thermal power state. The controller may reduce a power budget parameter (which reduces the amount of power consumption allocated to the storage device) based on the applied thermal mitigation configuration until thermal equilibrium is reached (e.g., a temperature gradient based on the measured temperature indicates neither a positive nor a negative rate of change in temperature).

[0018] As a result, rather than employing thermal throttling that results in hard power state transitions (resulting in reduced performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling with multiple thermal power states that gradually reduce power based on a temperature gradient along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables performance benchmarks to be met, and maintains data reliability through efficient NAND block usage.

[0019] FIG. 1 illustrates an exemplary block diagram 100 of a storage device 102 in communication with a host device 104 (also referred to as a “host”), according to an exemplary embodiment. The host 104 and the storage device 102 may form a system, such as a computer system (e.g., a server, a desktop, a mobile / laptop, a tablet, a smartphone, etc.). The components of FIG. 1 may or may not be physically collocated. In this regard, the host 104 may be located remotely from the storage device 102. While FIG. 1 illustrates the host 104 as being separate from the storage device 102, the host 104 in other embodiments may be integrated, in whole or in part, into the storage device 102. Alternatively, the host 104 may be distributed across multiple remote entities, either in its entirety or, alternatively, with some functionality within the storage device 102.

[0020] Those skilled in the art will appreciate that other exemplary embodiments may include more or fewer elements than those shown in Figure 1, and that the disclosed processes may be implemented in other environments. For example, other exemplary embodiments may include a different number of hosts in communication with storage device 102, or multiple storage devices 102 in communication with a host(s).

[0021] The host device 104 can store data in and / or retrieve data from the storage device 102. The host device 104 can include any computing device, including, for example, a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (e.g., laptop) computer, a tablet computer, a mobile computing device such as a smartphone, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, etc. The host device 104 can include at least one processor 101 and host memory 103. The at least one processor 101 can include any form of hardware capable of processing data, and can include a general-purpose processing unit (such as a central processing unit (CPU)), dedicated hardware (such as an application-specific integrated circuit (ASIC)), a digital signal processor (DSP), configurable hardware (such as a field-programmable gate array (FPGA)), or any other form of processing unit configured by software instructions, firmware, etc. The host memory 103 may be used by the host device 104 to store data or instructions to be processed by the host or data received from the storage device 102. In some examples, the host memory 103 may include non-volatile memory such as magnetic memory devices, optical memory devices, holographic memory devices, flash memory devices (e.g., NAND or NOR), phase change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM), and any other type of non-volatile memory device. In other examples, the host memory 103 may include volatile memory such as random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, etc.)).Host memory 103 may also include both non-volatile and volatile memory, whether integrated together or as separate units.

[0022] The host interface 106 is configured to interface the storage device 102 with the host 104 via a bus / network 108, and may interface using, for example, bus standards such as Ethernet or WiFi, or Serial Advanced Technology Attachment (SATA), PCI Express (PCIe), Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS), among other possible candidates. Alternatively, the host interface 106 may be wireless, and may interface the storage device 102 with the host 104 using, for example, cellular communications (e.g., 5G NR, 4G LTE, 3G, 2G, GSM / UMTS, CDMA One / CDMA2000, etc.), wireless distribution methods via access points (e.g., IEEE 802.11, WiFi, HiperLAN, etc.), infrared (IR), Bluetooth, Zigbee, or other wireless wide area network (WWAN), wireless local area network (WLAN), wireless personal area network (WPAN) technologies, or equivalent wide area, local area, and personal area technologies.

[0023] The storage device 102 includes memory. For example, in the exemplary embodiment of FIG. 1, the storage device 102 may include a non-volatile memory (NVM) 110 for persistently storing data received from the host 104. The NVM 110 may include, for example, a flash integrated circuit, a NAND memory (e.g., SLC memory, MLC memory, TLC memory, QLC memory, PLC memory, or any combination thereof), or a NOR memory. The NVM 110 may include a plurality of memory locations 112 that may store system data for operating the storage device 102 or user data received from the host for storage in the storage device 102. For example, the NVM may have a cross-point architecture that includes a 2-D NAND array of memory locations 112 having n rows and m columns, where m and n are predefined according to the size of the NVM. In the exemplary embodiment of FIG. 1, each memory location 112 may be a die 114 that includes a plurality of planes, each including a plurality of blocks of a plurality of cells 116. Alternatively, each memory location 112 may be a plane including a plurality of blocks of cells 116. The cells 116 may be, for example, single-level cells, multi-level cells, triple-level cells, quad-level cells, and / or penta-level cells. Other examples of the memory locations 112 are possible. For example, each memory location may be a block or a group of blocks. Each memory location may include one or more blocks in a 3D NAND array. Each memory location 112 may include one or more logical blocks that map to one or more physical blocks. Alternatively, the memory and each memory location may be implemented in other ways known to those skilled in the art.

[0024] Storage device 102 also includes volatile memory 118, which may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Data stored in volatile memory 118 may include data read from or written to NVM 110. In this regard, volatile memory 118 may include a write buffer or a read buffer for temporarily storing data. Although FIG. 1 depicts volatile memory 118 as separate from controller 123 of storage device 102, volatile memory 118 may also be integrated into controller 123.

[0025] The memory (e.g., NVM 110) is configured to store data 119 received from the host device 104. The data 119 may be stored in cells 116 of any of the memory locations 112. As an example, although FIG. 1 shows the data 119 stored in different memory locations 112, the data may be stored in the same memory location. In another example, the memory locations 112 may be different dies, and the data may be stored in one or more of the different dies.

[0026] Each of the data 119 may be associated with a logical address. For example, the NVM 110 may store a logical-to-physical (L2P) mapping table 120 for the storage device 102 that associates each data 119 with a logical address. The L2P mapping table 120 stores a mapping between logical addresses specified for data written from the host 104 and physical addresses within the NVM 110 that indicate the location(s) where each data is stored. This mapping may be performed by the storage device's controller 123. The L2P mapping table may be a table or other data structure that includes identifiers, such as logical block addresses (LBAs), associated with each memory location 112 in the NVM where data is stored. While FIG. 1 shows a single L2P mapping table 120 stored in one of the memory locations 112 of the NVM to avoid overly obscuring the concepts of FIG. 1, the L2P mapping table 120 may actually include multiple tables stored in one or more memory locations of the NVM.

[0027] FIG. 2 is a conceptual diagram 200 of an example L2P mapping table 205 illustrating the mapping of data 202 received from a host device to logical and physical addresses within NVM 110 of FIG. 1. Data 202 may correspond to data 119 of FIG. 1, and L2P mapping table 205 may correspond to L2P mapping table 120 of FIG. 1. In an exemplary embodiment, data 202 may be stored in one or more pages 204, e.g., pages 1 through x, where x is the total number of pages of data to be written to NVM 110. Each page 204 may be associated with one or more entries 206 in L2P mapping table 205 that identify a logical block address (LBA) 208, a physical address 210 associated with the data written to NVM, and a length 212 of the data. LBA 208 may be a logical address specified in a write command for data received from a host device. Physical address 210 may indicate the block and offset to which the data associated with LBA 208 is physically written. Length 212 may indicate the size of the data written (eg, 4 KB or some other size).

[0028] Referring again to FIG. 1 , the volatile memory 118 also stores a cache 122 for the storage device 102. The cache 122 contains entries that indicate a mapping of logical addresses specified for data requested by the host 104 to physical addresses in NVM 110 that indicate the location(s) where the data is stored. This mapping may be performed by the controller 123. When the controller 123 receives a read or write command for data 119, it checks the cache 122 for a logical-to-physical mapping for each piece of data. If a mapping does not exist (e.g., if this is the first request for the data), the controller accesses the L2P mapping table 120 and stores the mapping in the cache 122. When the controller 123 executes a read or write command, it accesses the mapping from the cache and reads or writes the data from or to NVM 110 at the specified physical address. The cache may be stored in the form of a table or other data structure that includes a logical address associated with each memory location 112 in NVM from which data is being read.

[0029] The NVM 110 includes a sense amplifier 124 and a data latch 126 connected to each memory location 112. For example, the memory location 112 may be a block including cells 116 on multiple bit lines, and the NVM 110 may include a sense amplifier 124 on each bit line. Additionally, one or more data latches 126 may be connected to the bit lines and / or the sense amplifiers. The data latches may be, for example, shift registers. When data is read from a cell 116 of a memory location 112, the sense amplifier 124 senses the data by amplifying the voltage on the bit line to a logic level (e.g., readable as a "0" or a "1"), and the sensed data is stored in the data latch 126. The data is then transferred from the data latch 126 to the controller 123, after which the data is stored in the volatile memory 118 until it is transferred to the host device 104. When data is written to a cell 116 of a memory location 112 , the controller 123 stores the programmed data in a data latch 126 , and the data is then transferred from the data latch 126 to the cell 116 .

[0030] The memory device 102 includes a controller 123 that includes circuitry such as one or more processors for executing instructions and may include a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), hardwired logic, analog circuitry, and / or combinations thereof.

[0031] The controller 123 is configured to receive data transferred from one or more of the cells 116 of the various memory locations 112 in response to a read command. For example, the controller 123 may read the data 119 by activating the sense amplifiers 124 to sense the data from the cells 116 to the data latches 126, and the controller 123 may receive the data from the data latches 126. The controller 123 is also configured to program data into one or more of the cells 116 in response to a write command. For example, the controller 123 may write the data 119 by sending the data to be programmed into the cells 116 to the data latches 126. The controller 123 is further configured to access the L2P mapping table 120 in the NVM 110 when reading and writing data to the cells 116. For example, in response to a read or write command from the host device 104, the controller 123 can receive a logical-to-physical address mapping from the NVM 110, identify the physical address mapped to the logical address identified in the command (e.g., translate the logical address to a physical address), and access or store data in the cell 116 located at the mapped physical address.

[0032] Controller 123 and its components may be implemented using embedded software that performs the various functions of the controller described throughout this disclosure. Alternatively, software for implementing each of the foregoing functions and components may be stored in NVM 110 or in memory external to storage device 102 or host device 104 and accessed by controller 123 for execution by one or more processors of controller 123. Alternatively, the functions and components of the controller may be implemented in hardware within controller 123 or using a combination of the foregoing hardware and software.

[0033] During operation, host device 104 stores data in storage device 102 by sending a write command to storage device 102 that specifies one or more logical addresses (e.g., LBAs) and the length of the data to be written. Interface element 106 receives the write command, and the controller allocates memory locations 112 in NVM 110 of storage device 102 to store the data. Controller 123 stores an L2P mapping in NVM (and cache 122) to map the logical address associated with the data to the physical address of the memory locations 112 allocated for the data. The controller also stores the length of the L2P-mapped data. Controller 123 then stores the data in memory locations 112 by sending the data to one or more data latches 126 connected to the allocated memory locations, from which the data is programmed into cells 116.

[0034] Host 104 may retrieve data from storage device 102 by sending a read command that specifies one or more logical addresses associated with the data to be retrieved from storage device 102, as well as the length of the data to be read. Interface 106 receives the read command, and controller 123 accesses cache 122 or an L2P mapping in NVM to translate the logical address specified in the read command into a physical address indicating the location of the data. Controller 123 then reads the requested data from memory location 112 specified by the physical address by sensing the data using sense amplifiers 124 and storing them in data latches 126 until the read data is returned to host 104 via host interface 106.

[0035] 3 illustrates an example of a NAND memory array 300 of cells 302. The cells 302 may correspond to the cells 116 in the NVM 110 of FIG. 1. The cells 302 are coupled to word lines 304 and bit lines 306. For example, the memory array 300 may include n word lines and m bit lines within a block of the die 114 of the NVM 110, where n and m are predetermined according to the size of the block. Each word line and bit line may be associated with a row address and a column address, respectively, and the controller 123 may use the row address and the column address to select a particular word line and bit line (e.g., using a row decoder and a column decoder). For example, word lines 0-n may each be associated with their own row address (e.g., word line 0 may correspond to word line address 0, word line 1 may correspond to word line address 1, etc.), and bit lines 0-m may each be associated with their own column address (e.g., bit line 0 may correspond to bit line address 0, bit line 1 may correspond to bit line address 1, etc.). Select gate source (SGS) cells 308 and select gate drain (SGD) cells 310 are coupled to the memory cells 302 on each bit line 306. The SGS cells 308 and SGD cells 310 connect the memory cells 302 to source lines 312 (e.g., ground) and bit lines 306, respectively. A string 314 may include a group of cells 302 (including the SGS cells 308 and SGD cells 310) coupled to one bit line within a block, and a page 316 may include a group of cells 302 coupled to one word line within a block.

[0036] 4 shows an example of a NAND memory array 400 of a block 402 including multiple strings 404. The block 402 may correspond to a block of the die 114 in the NVM 110 of FIG. 1, and the strings 404 may each correspond to the strings 314 of FIG. 3. As in the memory array 300 of FIG. 3, each string 404 may include a group of memory cells, each coupled to a bit line 406 and individually coupled to a respective word line 408. Similarly, each string may include SGS cells 410 and SGD cells 412 that connect the memory cells in each string 404 to source lines 414 and bit lines 406, respectively.

[0037] When the controller 123 reads data from or writes data to a page 316 of cells 302 (i.e., on word lines 304, 408), the controller can send commands to apply a read voltage or a program voltage to selected word lines and a pass-through voltage to other word lines. The read or programmed state of a cell (e.g., a logic "0" or a logic "1" for an SLC) may be determined based on the threshold voltage of the cell 302. For example, during an SLC read operation, if the threshold voltage of the cell 302 is less than the read voltage (i.e., if a current flows through the cell in response to the read voltage), the controller 123 may determine that the cell is storing a logic "1," and if the threshold voltage of the cell 302 is greater than the read voltage (i.e., if a current does not flow through the cell in response to the read voltage), the controller 123 may determine that the cell is storing a logic "0." Similarly, during an SLC program operation, the controller may store a logic "0" by sending a command to apply a program voltage to the cell 302 on the word line 304, 408 until the cell reaches the threshold voltage, and during an erase operation, the controller may send a command to apply an erase voltage to the block 402 containing the cell 302 (e.g., to the cell's substrate, such as a p-well) until the cell returns below the threshold voltage (returns to a logic "1").

[0038] For cells that store multiple bits (e.g., MLC, TLC, etc.), each word line 304, 408 may include multiple pages 316 of cells 302, and the controller may similarly send commands to apply read or program voltages to the word lines and determine the read or program state of the cells based on the cell's threshold voltage. For example, for TLC, each word line 304, 408 may include three pages 316, including a lower page (LP), a middle page (MP), and an upper page (UP), each corresponding to a different bit stored in the TLC. When programming a TLC, the LP may be programmed first, followed by the MP, and then the UP. For example, a program voltage may be applied to the cell on the word line 304, 408 until the cell reaches a first intermediate threshold voltage corresponding to the cell's least significant bit (LSB). Next, LP may be read to determine a first intermediate threshold voltage, and then a program voltage may be applied to the cell on the word line until the cell reaches a second intermediate threshold voltage corresponding to the cell's next bit (between the LSB and the most significant bit (MSB)). Finally, MP may be read to determine a second intermediate threshold voltage, and then a program voltage may be applied to the cell on the word line until the cell reaches a final threshold voltage corresponding to the cell's MSB. Similarly, when reading a TLC, controller 123 may read LP to determine whether the LSB stores a logic 0 or a logic 1 depending on the cell's threshold voltage, read MP to determine whether the next bit stores a logic 0 or a logic 1 depending on the cell's threshold voltage, and read UP to determine whether the last bit stores a logic 0 or a logic 1 depending on the cell's threshold voltage.

[0039] FIG. 5 shows an example voltage distribution diagram 500 illustrating different NAND states of a TLC (e.g., cell 116, 302) storing three bits of data (e.g., logic 000, 001, etc., up to logic 111). The TLC may include an erased state 502 corresponding to logic “111” and multiple programmed states 504 (e.g., A-G) corresponding to other logic values “000-110.” The programmed states 504 may be separated by different threshold voltages 506. Initially, cell 116, 302 may be in the erased state 502, for example, after controller 123 erases block 402 containing the cell. When controller 123 programs LP, MP, and UP as described above, the voltage of cell 116, 302 may be increased until the threshold voltage 506 corresponding to the logic value to be stored is met, at which point the cell transitions to its respective programmed state 504. 5 shows eight NAND states for TLC, the number of states may vary depending on the amount of data stored in each cell 116, 302. For example, SLC may have two states (e.g., logic 0 and logic 1), MLC may have four states (e.g., logic 00, 01, 10, 11), and QLC may have 16 states (e.g., erased and A through N).

[0040] FIG. 6 is a conceptual diagram 600 of an example garbage collection process in which data stored in a page 604 of a block 602 of SLC cells is relocated to a page 608 of a block 606 of MLC cells. The data may correspond to data 119 of FIG. 1, blocks 602, 606 may correspond to block 402 of FIG. 4, and the SLC / MLC cells may correspond to cells 116, 302 of FIGS. 1 and 3. Each page 604, 608 contains data stored in multiple cells along the same row or word line (e.g., word line 304, 408) of the NVM. Thus, each page 604 may contain data stored in a row of cells 116 of one block, and each page 608 may contain data stored in a row of cells 116 of another block. For simplicity of explanation, the example of FIG. 6 shows blocks 602, 606 each containing only four pages 604, 608. However, it should be appreciated that each block may contain any number of pages.

[0041] 6, data represented by identifiers A, B, and C are stored in different pages 604 of block 602. Originally, data A, B, and C would be stored in three pages of block 602 in response to a write command from a host device, leaving one of the pages free in this example. When the storage device receives new or updated data, this data is stored in free page 610. For example, updated data A′ may be received from the host device and written to free page 610. Because flash memory does not allow data to be overwritten, invalid data A remains stored in block 602. As a result of the new and invalid data, block 602 may quickly become full.

[0042] To free up space in the SLC block, the original data and updated data in block 602 can be transferred to block 606. The invalid data remains in the old block. For example, in the example of Figure 6, original data B and C and updated data A' are read from page 604 of block 602 and written to one or more pages 608 of block 606. Invalid data A remains in block 602. When block 602 is subsequently erased, the invalid data is discarded and block 602 can be reused to store new data.

[0043] 1, if there are no empty cells available in an SLC block (e.g., block 602) for storing data, controller 123 performs garbage collection (e.g., as described above with respect to FIG. 6) by transferring data from cells 116 in the SLC block to available cells in an MLC block (e.g., block 606). Controller 123 can then erase the SLC block containing cells 116. Once cells 116 are free, the controller can continue to write data to the empty cells.

[0044] When cells 116 in an MLC block (e.g., block 606) are read or written, or when the ambient temperature of the memory device 102 increases, the cells may exceed their reliable operating temperature, compromising data integrity. For example, as the temperature of the cells increases, the cell's threshold voltage 506, which separates different program states 504, may change. At a certain temperature, the threshold voltage can no longer sufficiently separate different program states, thus causing potential read errors and affecting data reliability.

[0045] When a storage device performs thermal throttling, the controller 123 generally reduces the rate at which data is written to NAND cells (e.g., 606) as soon as the temperature of the die containing the NAND cells exceeds a thermal threshold. However, when performing thermal throttling, the thermal throttling causes a hard transition at the thermal throttling threshold. For example, the controller 123 typically performs thermal throttling with a relatively large variation in data rate between transitions. For example, the controller 123 may reduce the write data rate using a first set of parameters when the MLC block (e.g., 606) exceeds a first thermal throttling threshold at 80° C., and may further reduce the write data rate using a second set of parameters that vary significantly from the first set of fixed parameters when the MLC block exceeds a second thermal throttling threshold at 86° C. As a result of these large variations between transitions, device performance and power consumption may vary significantly between transitions over time, and user experience may be affected.

[0046] Therefore, to improve storage device performance and enhance user experience, the present disclosure enables the controller 123 to selectively choose a specific thermal configuration and dynamically adjust internal mitigation parameters to gradually adjust the internal mitigation parameters over time (or preemptively) to align the storage device with host-specified thermal framework parameters, thereby reaching optimized and deterministic performance within a thermal envelope targeted at reducing latency and minimizing quality of service disruptions. Typically, in response to write commands from the host device 104, the controller 123 routes data to memory by storing the data directly in SLC blocks at a first data rate (e.g., full clock rate). As the number of free SLC blocks decreases, the controller 123 reallocates data in the SLC blocks to MLC blocks. This reallocation may increase the temperature of the MLC blocks. When the temperature of the MLC block rises above a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller changes how data is routed to the memory by disabling data relocation from SLC blocks to MLC blocks and by restricting host data writes to the SLC blocks. However, the controller 123 now performs thermal throttling by applying a selected thermal mitigation configuration associated with the thermal power state by scaling the power budget based on a temperature gradient to maintain maximum possible performance while maintaining thermal balance within the thermal power state. This contrasts with causing a large performance switch between thermal power state transitions when a block of cells (e.g., 602, 606) exceeds the corresponding thermal throttling threshold, thus allowing data to be written at thermally throttled data rates that translate to desired performance benchmarks for various workloads within the adjusted power budget.

[0047] The controller 123 may initially begin writing host data to the block of cells (e.g., 606) at a first data rate (e.g., at the full clock rate) in response to a write command. The controller 123 then continues writing host data in response to the write command to the block of cells, which may cause the temperature of the block of cells to increase. If the temperature of the block of cells increases above a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller 123 may transition to a first thermal power state and enable thermal throttling. For example, the controller 123 may reduce the rate of data written to the SLC blocks and MLC blocks to a smaller second data rate (e.g., 60% of the full clock rate), for example, by applying a thermal mitigation configuration associated with the first thermal power state. Based on the applied thermal mitigation configuration, the controller 123 may reduce a power budget parameter (which reduces the power consumption allocated to the storage device) until thermal equilibrium is reached (e.g., a temperature gradient based on the measured temperature indicates neither a positive nor a negative rate of change in temperature). The controller 123 can further reduce power consumption through additional thermal power states, which in turn reduces temperature.

[0048] As a result, rather than employing thermal throttling that results in hard power state transitions (and therefore reduced performance) when the temperature of a block of cells exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling having multiple thermal power states that gradually reduce power based on a temperature gradient, along with adjustments to other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables performance benchmarks to be met, and maintains data reliability through efficient NAND block usage.

[0049] FIG. 7 illustrates an example diagram 700 of thermal throttling in a storage device. In thermal throttling, a controller increasingly restricts access to cells as temperature increases in order to cool the storage device. For example, cells may be included in one or more dies, and the controller may disable parallel access to an increasing number of dies as temperature exceeds various thermal thresholds. In the example diagram 700, several thermal thresholds are configured for different levels of throttling, including a low (LO) thermal threshold 702, a medium (MED) thermal threshold 704, a high (HI) thermal threshold 706, and a thermal shutdown (TSD) thermal threshold 708. For example, for QLC temperatures, the LO thermal threshold 702 may be 80° or another degree, the MED thermal threshold 704 may be 86° or another degree, the HI thermal threshold 706 may be 94° or another degree, and the TSD thermal threshold 708 may be the maximum write temperature, e.g., 95°. These thermal thresholds are merely examples. Any number of temperature thermal thresholds of various degrees may be used. Furthermore, the thermal thresholds may vary depending on the cell type. For example, for TLC temperatures, the thermal thresholds may all be higher, and for PLC temperatures, the thermal thresholds may all be lower.

[0050] The controller can implement different levels of throttling when the temperature of a cell exceeds various thermal thresholds to reduce the temperature more quickly. For example, when reducing die parallelism, the controller can apply light throttling 712 (e.g., throttling one die) when the temperature exceeds a LO thermal threshold 702, heavy throttling 714 (e.g., throttling two die) when the temperature exceeds a MED thermal threshold 704, extreme throttling 716 (e.g., throttling three die) when the temperature exceeds a HI thermal threshold 706, and thermal shutdown 718 (e.g., shutting down access to a die) when the temperature exceeds a TSD thermal threshold 708. Other examples of throttling may also be used. For example, instead of disabling parallel access to one, two, or three dies, respectively, the memory device may disable parallel access to different numbers of dies, prevent reads or writes to different numbers of dies, limit or restrict access to different numbers or types of memory locations on the same die, or implement other temperature reduction schemes.

[0051] 7 thus illustrates various examples 722, 724, 726, 728 of different throttle level operation when cell temperatures 730, 732, 734, 736 increase due to, for example, read or write operations or an increase in ambient temperature. Referring to the first example 722, the storage device initially operates in the full power region 710, e.g., without throttling. When the temperature 730 exceeds the LO thermal threshold 702, the controller implements light throttling 712. In this example, the light throttling 712 is sufficient to gradually reduce the temperature, and throttling continues until the temperature falls below the LO thermal threshold 702. The storage device then disables throttling and resumes full power operation.

[0052] Referring to a second example 724, the storage device initially operates in the full power region 710 without throttling. However, unlike the first example, when the temperature 732 exceeds the LO thermal threshold 702, the light throttling 712 is insufficient to reduce the temperature, and therefore, the temperature 732 continues to rise. When the temperature exceeds the MED thermal threshold 704, the controller implements heavy throttling 714. In this example, the heavy throttling 714 is sufficient to gradually reduce the temperature, and throttling continues until the temperature drops below the MED thermal threshold 704. At that point, the controller switches to light throttling 712, which continues to run until the temperature drops below the LO thermal threshold 702. The storage device then disables throttling and resumes full power operation.

[0053] Referring to a third example 726, the storage device initially operates in the full power region 710 without throttling. However, unlike the first and second examples, when the temperature 734 exceeds the LO thermal threshold 702 and the MED thermal threshold 704, the light throttling 712 and heavy throttling 714 are insufficient to reduce the temperature, and therefore, the temperature 734 continues to rise. When the temperature exceeds the HI thermal threshold 706, the controller implements extreme throttling 716. In this example, extreme throttling 716 is sufficient to gradually reduce the temperature, and throttling continues until the temperature drops below the HI thermal threshold 706. At that point, the controller switches to heavy throttling 714, which continues to run until the temperature drops below the MED thermal threshold 704. At that point, the controller switches to light throttling 712, which continues to run until the temperature drops below the LO thermal threshold 702. The storage device then disables throttling and resumes full power operation.

[0054] Referring to a fourth example 728, the storage device initially operates in the full power region 710 without throttling. However, unlike the first and second examples, when the temperature 736 exceeds the LO thermal threshold 702 and the MED thermal threshold 704, the light throttling 712 and the heavy throttling 714 are insufficient to reduce the temperature, and thus the temperature 736 continues to rise. Once the temperature exceeds the HI thermal threshold 706, the controller implements extreme throttling 716. In this example, the extreme throttling 716 is insufficient to gradually reduce the temperature, and thus the temperature continues to rise until it reaches the TSD thermal threshold 708. At this point, the controller implements a thermal shutdown 718, for example, shutting down access to the cells and / or storage device until the temperature drops to a normal level.

[0055] When a storage device performs thermal throttling, the storage device generally reduces the rate at which data is written to NAND cells as soon as the temperature of the die containing the NAND cells exceeds a thermal threshold. Thermal throttling, as described with respect to FIG. 7, can reduce the temperature of the storage device, but it can also reduce system performance. However, when performing thermal throttling, the thermal throttling causes hard transitions at the thermal throttling thresholds. For example, a storage device typically performs thermal throttling with relatively large variations in data rate between transitions. For example, the storage device may reduce the write data rate using a first set of parameters when the die exceeds a first thermal throttling threshold at 80° C., and further reduce the write data rate using a second set of parameters that vary significantly from the first set of fixed parameters when the die exceeds a second thermal throttling threshold at 86° C. As a result of these large variations between transitions, device performance and power consumption may vary significantly between transitions over time, and user experience may be affected. Therefore, device performance and user satisfaction may be reduced.

[0056] To improve device performance, controller 123 can selectively select a particular thermal configuration and dynamically adjust internal mitigation parameters to reach optimized, deterministic performance within a thermal envelope targeting reduced latency and minimal quality-of-service disruption by gradually adjusting the internal mitigation parameters over time (or preemptively) to align the storage device with host-specified thermal framework parameters, as described below with respect to Figures 8-17. For example, controller 123 can perform thermal throttling by applying a selected thermal mitigation configuration associated with a thermal power state by scaling a power budget based on a thermal gradient to maintain maximum possible performance while maintaining thermal balance within the thermal power state. This contrasts with large performance switches between thermal power state transitions when the storage device exceeds a corresponding thermal throttling threshold, thereby allowing data to be written at thermally throttled data rates that translate to desired performance benchmarks for various workloads within the adjusted power budget.

[0057] The controller 123 may initially begin writing host data in response to a write command to the block of cells at a first data rate (e.g., at the full clock rate). The controller 123 then continues writing host data in response to the write command to the block of cells, which may cause the temperature of the block of cells to increase. If the temperature of the block of cells increases above a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller 123 may transition to a first thermal power state and enable thermal throttling. For example, the controller 123 may reduce the rate of data written to the SLC blocks and MLC blocks to a smaller second data rate (e.g., to 60% of the full clock rate), e.g., by applying a thermal mitigation configuration associated with the first thermal power state. Based on the applied thermal mitigation configuration, the controller 123 may reduce a power budget parameter (which reduces the power consumption allocated to the storage device) until thermal equilibrium is reached (e.g., a temperature gradient based on the measured temperature indicates neither a positive nor a negative rate of change in temperature).

[0058] As a result, rather than employing thermal throttling that results in hard power state transitions (resulting in reduced performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling with multiple thermal power states that gradually reduce power based on a temperature gradient along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables performance benchmarks to be met, and maintains data reliability through efficient NAND block usage.

[0059] FIG. 8 shows an example diagram 800 of a controller 802 of a storage device using advanced thermal throttling with multiple thermal power states in the storage device of FIG. 1 to write data received from a host device 804 to one or more blocks 806, 808, 810 at different data rates corresponding to different temperatures of the blocks. Block 808 may include cells that store more bits than the cells of block 806. For example, block 806 may include SLC pages, and block 808 may include MLC pages (e.g., 2-bit cells, TLC, QLC, PLC, etc.). With reference to FIG. 1, controller 802 may correspond to controller 123, SLC block 806 may correspond to block 602 including cell 116, and MLC block 808 may correspond to block 606 including cell 116. Block 806 and blocks 808, 810 may be stored in separate partitions of die 812 (e.g., die 114 of FIG. 1). For example, block 806 may be stored in an SLC partition of die 812, and blocks 808 and 810 may be stored in an MLC partition of die 812.

[0060] The controller 802 can communicate with a temperature sensor 814 coupled to the die 812. The controller 802 can determine a temperature 816 of the cells in the blocks 806, 808, 810 based on periodically monitored readings from the temperature sensor 814. Upon determining the temperature, the controller 802 can apply advanced thermal throttling to the die 812 based on the different thermal power states of the blocks 806 and 808. For example, the controller 802 can initially write first data 840 (e.g., data in response to a write command) to the blocks 806, 808 at a first data rate 842 when the temperature 816 is below a first thermal threshold (TMT1 822). Thereafter, the controller 802 may write second data 844 (e.g., data in response to another write command) to the blocks 806, 808 at a second data rate 846 (a throttle rate less than the first data rate 842) when the temperature 816 meets a first thermal threshold (TMT1 822). The controller 802 may write third data 848 (e.g., data in response to another write command) to the blocks 806, 808 at a third data rate 850 (a throttle rate less than the second data rate 846) when the temperature 816 meets a second thermal threshold (TMT2 824). The controller 802 may write fourth data 852 (e.g., data in response to another write command) to the blocks 806, 808 at a third data rate 854 (a throttle rate less than the third data rate 850) when the temperature 816 meets a third thermal threshold (TMT3 826). The controller 802 may write fifth data 856 (e.g., data in response to another write command) to the blocks 806, 808 at a fifth data rate 858 (a throttle rate less than the fourth data rate 854) when the temperature 816 meets a fourth thermal threshold (TMT4 828). Additionally, the controller may also perform a thermal shutdown or disable all data writes when the temperature 816 meets a thermal shutdown temperature (TMTSD 830) higher than TMT4.For example, in one example, TMT1 may be 80° C., TMT2 may be 86° C., TMT3 may be 92° C., TMT4 may be 94° C., and TMTSD may be 95° C. Alternatively, in other examples, TMT1, TMT2, TMT3, TMT4, and TMTSD may be different. Before a thermal throttling (e.g., in TMT1) or thermal shutdown (e.g., in TMTSD) occurs, the controller may send a message 831 notifying the host device 804 of such an event.

[0061] To release block 806 before temperature 816 reaches TMT1 822, controller 802 can transfer data from block 806 to block 808 without thermal throttling in response to temperature 816. For example, the controller can perform data relocation at a first data rate 842 when the temperature is below TMT1 822 (e.g., below 80°C). If controller 802 determines that temperature 816 later meets TMT1 822 (e.g., 80°C), the controller can perform thermal throttling by applying a thermal mitigation configuration for the first thermal power state, such that subsequent data (e.g., second data 844) can be written to block 808 at a second data rate 846. For example, the controller can decrease power consumption in the first thermal power state by reducing a power budget parameter value until a temperature gradient indicates that temperature 816 reaches thermal equilibrium. In another example, the controller may reduce power consumption by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, reducing the number of bus interconnect lanes to block 808, and / or reducing the host interface queue depth. If the temperature 816 later drops below TMT1 822 in response to the throttled rate, the controller can re-enable data relocation from block 806 to block 808, and the controller can again write data to blocks 806, 808 at the first data rate 842 without thermal throttling. If the temperature 816 instead rises to TMT2 824 despite the throttled rate, the controller can perform thermal throttling by applying a thermal mitigation configuration for the second thermal power state, thereby writing subsequent data (e.g., third data 848) to block 808 at a third data rate 850. For example, the controller can decrease power consumption in the second thermal power state by reducing the power budget parameter value until the temperature gradient indicates that the temperature 816 has reached thermal equilibrium.In another example, the controller may reduce power consumption by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, reducing the number of bus interconnect lanes to block 808, and / or reducing the host interface queue depth.

[0062] If the temperature 816 then drops below TMT2 822 in response to the throttled rate, the controller applies the thermal mitigation configuration for the first thermal power state, resulting in subsequent data being written to block 808 at a second data rate 846. If the temperature 816 instead rises to TMT3 826 despite the throttled rate, the controller may perform thermal throttling by applying the thermal mitigation configuration for the third thermal power state, resulting in subsequent data (e.g., fourth data 852) being written to block 808 at a fourth data rate 854. For example, the controller may reduce power consumption in the third thermal power state by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, and / or reducing the host interface queue depth.

[0063] If the temperature 816 then drops below TMT3 824 in response to the throttled rate, the controller applies the thermal mitigation configuration for the second thermal power state, resulting in subsequent data being written to block 808 at a third data rate 850. If the temperature 816 instead rises to TMT4 828 despite the throttled rate, the controller may perform thermal throttling by applying the thermal mitigation configuration for the fourth thermal power state, resulting in subsequent data (e.g., fifth data 856) being written to block 808 at a fourth data rate 858. For example, the controller may reduce power consumption in the fourth thermal power state by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, and / or reducing the operating duty cycle.

[0064] If the temperature 816 then drops below TMT4 828 in response to the throttled rate, the controller applies the thermal mitigation configuration for the third thermal power state, resulting in subsequent data being written to block 808 at a fourth data rate 854. If the temperature 816 instead rises to TMTSD 830 despite the throttled rate, the controller may initiate a thermal shutdown and disable further data writes to block 808 until the temperature drops below TMT4.

[0065] 9 is a flowchart 900 illustrating an exemplary embodiment of a method for advanced thermal throttling with multiple thermal power states. For example, the method may be performed in storage device 102 as shown in FIG. 1. Each step in the flowchart may be controlled using a controller (e.g., controller 123, 802) as described below, or by any other suitable means.

[0066] The controller may periodically monitor the NAND temperature, as represented by block 902. For example, with reference to Figures 1 and 8, the controller 123, 802 may obtain the temperature 816 of the blocks 402, 806, 808 of the die 114, 812 of the NVM 110 from the temperature sensor 814 at regular intervals, such as every minute or other amount of time.

[0067] As represented by block 904, the controller may determine whether the obtained temperature is greater than a first thermal threshold. For example, with reference to Figures 1 and 8, the controller 123, 802 may determine whether the temperature 816 is greater than TMT1 822.

[0068] If the temperature 816 is greater than TMT1 822, the controller may reduce power consumption based on the temperature gradient, as represented by block 906. For example, with reference to Figures 1 and 8, the controller 123, 802 may enable thermal throttling 906 in a first thermal power state (e.g., TPS1). If the temperature 816 is not greater than TMT1, the controller may return to block 902 and continue to periodically monitor the NAND temperature.

[0069] Further, as represented by block 908, the controller may apply a thermal mitigation configuration for a first thermal power state (e.g., TPS1). For example, with reference to FIGS. 1 and 8, the controller 123, 802 may reduce power consumption using the thermal mitigation configuration in the first thermal power state by reducing the power budget parameter value until the temperature gradient indicates that the temperature 816 has reached thermal equilibrium. In another example, the controller may further reduce power consumption with the thermal mitigation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), reducing the voltage of the corresponding voltage domain, and / or reducing the number of bus interconnect lanes to block 808.

[0070] As represented by block 910, the controller may determine whether the obtained temperature is greater than a second thermal threshold. For example, with reference to Figures 1 and 8, the controller 123, 802 may determine whether the temperature 816 is greater than TMT2 824.

[0071] If the temperature 816 rises to TMT2 824 despite the throttled rate, the controller may perform thermal throttling by applying a thermal mitigation configuration for a second thermal power state (e.g., TPS2), as represented by block 912. For example, with reference to FIGS. 1 and 8, the controller 123, 802 may reduce power consumption using the thermal mitigation configuration in the second thermal power state by reducing the power budget parameter values until the temperature gradient indicates that the temperature 816 reaches thermal equilibrium. In another example, the controller may further reduce power consumption with the thermal mitigation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), by reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), and / or by reducing the number of bus interconnect lanes to block 808.

[0072] If the temperature 816 does not rise to TMT2 822 in response to the throttled rate, the controller may return to block 904 and check whether the temperature meets the first thermal threshold TMT1. In some aspects, the controller may also continue to monitor the NAND temperature as described above in block 902. If so, the controller may apply a thermal mitigation configuration to the first thermal power state to further gradually reduce the temperature while maintaining the performance benchmark.

[0073] As represented by block 914, the controller may determine whether the obtained temperature is greater than a third thermal threshold. For example, with reference to Figures 1 and 8, the controller 123, 802 may determine whether the temperature 816 is greater than TMT3 826.

[0074] If the temperature 816 rises to TMT3 826 despite the throttled rate, the controller may perform thermal throttling by applying a thermal mitigation configuration for a third thermal power state (e.g., TPS3), as represented by block 916. For example, with reference to FIGS. 1 and 8, the controller 123, 802 may reduce power consumption using the thermal mitigation configuration in the third thermal power state by reducing the power budget parameter value to the minimum allowed power consumption. In another example, the controller may further reduce power consumption with the thermal mitigation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), by reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), by reducing the number of bus interconnect lanes to block 808, and / or by reducing the host interface queue depth.

[0075] If the temperature 816 does not rise to TMT3 826 in response to the throttled rate, the controller may return to block 910 and check whether the temperature meets the second thermal threshold TMT2. In some aspects, the controller may also continue to monitor the NAND temperature as described above in block 902. If so, the controller may apply a thermal mitigation configuration to a second thermal power state to further gradually reduce the temperature while maintaining the performance benchmark.

[0076] As represented by block 918, the controller may determine whether the obtained temperature is greater than a fourth thermal threshold. For example, with reference to Figures 1 and 8, the controller 123, 802 may determine whether the temperature 816 is greater than TMT4 828.

[0077] If the temperature 816 rises to TMT4 828 despite the throttled rate, the controller may perform thermal throttling by applying a thermal mitigation configuration for a fourth thermal power state (e.g., TPS4), as represented by block 920. For example, with reference to FIGS. 1 and 8, the controller 123, 802 may reduce power consumption using the thermal mitigation configuration in the fourth thermal power state by reducing the power budget parameter value to the minimum allowed power consumption. In another example, the controller may further reduce power consumption with the thermal mitigation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), by reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), by reducing the number of bus interconnect lanes to block 808, and / or by reducing the operating duty cycle.

[0078] If the temperature 816 does not rise to TMT4 828 in response to the throttled rate, the controller may return to block 914 and check whether the temperature meets the third thermal threshold TMT3. In some aspects, the controller may also continue to monitor the NAND temperature as described above in block 902. If so, the controller may apply a thermal mitigation configuration to a third thermal power state to further gradually reduce the temperature while maintaining the performance benchmark.

[0079] As represented by block 918, the controller may determine whether the obtained temperature is greater than a fourth thermal threshold. For example, with reference to Figures 1 and 8, the controller 123, 802 may determine whether the temperature 816 is greater than TMT4 828.

[0080] If the temperature 816 rises to TMTSD 830 despite the throttled rate, the controller may initiate a thermal shutdown and disable further data writes to the NAND memory until the temperature drops below TMT4, as represented by block 920. If the temperature 816 does not rise to TMTSD 830 in response to the throttled rate, the controller may return to block 918 and check whether the temperature meets the third thermal threshold TMT4. In some aspects, the controller may also continue to monitor the NAND temperature as described above in block 902. If so, the controller may apply a thermal mitigation configuration to a fourth thermal power state to further gradually reduce the temperature while maintaining the performance benchmark.

[0081] 10 is a conceptual diagram illustrating a controller 1010 for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. The controller 1010 is communicatively coupled to a temperature sensor 1002 via a maximum value filter module 1004 and to sensors 1006 and 1008. The controller 1010 is also communicatively coupled to a host-controlled thermal management (HCTM) module 1050 and a non-volatile memory host controller module 1060. The controller 1010 includes temperature comparators 1011-1015 and a thermal power state driver 1020. The controller 1010 is also communicatively coupled to a history database 1030 and a predictive model 1040. In some aspects, the history database 1030 may store historical information regarding temperature measurements of the storage device, including performance benchmarks correlating with any historical adjustments of temperature and / or power. In some embodiments, the predictive model 1040 may be a neural network trained to infer the temperature of a storage device based on real-time information from the storage device and / or historical information stored in the historical database 1030.

[0082] The thermal power state driver 1020 includes a temperature gradient module 1022, a power budget scaling module 1024, a dynamic voltage frequency scaling module 1026, and a host interface management (HIM) queue depth (QD) control module 1028. The HCTM module 1050 may be communicatively coupled to the temperature comparators 1013 and 1014. The temperature sensor 1006 may be communicatively coupled to the temperature comparator 1015 and the temperature comparator 1064. The sensor 1008 may be communicatively coupled to the thermal power state driver 1020. The maximum value filter module 1004 may be communicatively coupled to the temperature comparators 1011-1014, the thermal power state driver 1020, and the temperature comparator 1062. The temperature comparators 1062 and 1064 may be communicatively coupled to a thermal shutdown (TSD) driver 1068. The history database 1030 and the prediction module 1040 may be communicatively coupled to the thermal power state driver 1020 .

[0083] Figure 11 is a flowchart illustrating an exemplary process for advanced thermal throttling using multiple thermal power states in the storage device of Figure 1. For example, the method may be performed in storage device 102 as shown in Figure 1. Each step in the flowchart may be controlled using a controller (e.g., controller 123, 802, 1010) as described below, or by any other suitable means.

[0084] As represented by block 1102, the controller 1010 can periodically monitor the NAND temperature. For example, referring to FIGS. 1 and 10, the controller 123, 1010 may obtain the temperature of the block 402 in the die 114, 812 in the NVM 110 from the temperature sensor 1002 and / or the sensors 1006, 1008 at regular intervals, such as periodically every minute or other amount of time. In some aspects, the controller 1010 may obtain the NAND temperature of the NVM 110 at a first sampling rate based on the NAND temperature of the NVM 110 not exceeding a first thermal threshold (e.g., TMT1 set to 80° C.). In other aspects, the controller 1010 may obtain the NAND temperature of the NVM 110 at a second sampling rate greater than the first sampling rate based on the NAND temperature of the NVM 110 exceeding the first thermal threshold (e.g., TMT1). For example, the temperature sampling rate may be increased by a factor of four after the temperature exceeds TMT1.

[0085] In some aspects, the maximum value filter module 1004 may receive an array of temperature measurements from the temperature sensors 1002. In one or more implementations, the maximum value filter module 1004 may filter the temperature measurements such that the sample with the highest measured temperature may be filtered out and provided to the controller 1010 for processing by the temperature comparators 1011-1014. In one or more other implementations, the maximum value filter module 1004 may filter out the highest measured temperature sample for each of the temperature sensors 1002 to be processed by the temperature comparators 1011-1014.

[0086] As represented by block 1104, the controller may determine that the temperature of the memory meets one thermal threshold of multiple thermal thresholds. For example, referring to FIGS. 1 and 10, the controller 1010 may compare the NAND temperature of NVM 110 with temperature comparator 1014 to determine whether the temperature meets or exceeds TMT1. In another example, referring to FIGS. 1 and 10, the controller 1010 may compare the NAND temperature of NVM 110 with temperature comparator 1013 to determine whether the temperature meets or exceeds TMT2. In yet another example, referring to FIGS. 1 and 10, the controller 1010 may compare the NAND temperature of NVM 110 with temperature comparator 1012 to determine whether the temperature meets or exceeds TMT3. In yet another example, referring to FIGS. 1 and 10, the controller 1010 may compare the NAND temperature of NVM 110 with temperature comparator 1011 to determine whether the temperature meets or exceeds TMT4. In some aspects, the controller 1010 may compare the temperature obtained by the temperature sensor 1006 with a temperature comparator 1015 to determine whether the temperature meets or exceeds a thermal threshold specific to an application specific integrated circuit (ASIC) in the storage device of FIG. 1. In yet another example, referring to FIGS. 1 and 10, the controller 1010 may compare the NAND temperature of the NVM 110 with a temperature comparator 1062 to determine whether the temperature meets or exceeds a TMTSD. In other aspects, the controller 1010 may compare the temperature obtained by the temperature sensor 1006 with a temperature comparator 1064 to determine whether the temperature meets or exceeds a thermal shutdown threshold specific to an ASIC in the storage device of FIG. 1. Based on the comparison results of the temperature comparators 1062 and / or 1064, the TSD driver 1068 may be triggered to issue a thermal shutdown of the NVM 110.

[0087] As represented by block 1106, the controller may transition to one of a plurality of thermal power states when the temperature meets a thermal threshold. For example, referring to FIG. 10 , the controller 1010 may follow a state machine algorithm that controls the transition between thermal power states. Results from one or more of the temperature comparators 1011-1014 may be provided as inputs to the state machine. For example, referring to FIG. 10 , the controller 1010 may transition to a first thermal power state based on the temperature comparator 1014 indicating that the NAND temperature meets or exceeds TMT1. In another example, referring to FIG. 10 , the controller 1010 may transition to a second thermal power state based on the temperature comparator 1013 indicating that the NAND temperature meets or exceeds TMT2. In yet another example, referring to FIG. 10 , the controller 1010 may transition to a third thermal power state based on the temperature comparator 1012 indicating that the NAND temperature meets or exceeds TMT3. In yet another example, referring to FIG. 10, the controller 1010 may transition to a fourth thermal power state based on the temperature comparator 1011 indicating that the NAND temperature meets or exceeds TMT4.

[0088] As represented by block 1108, the controller may apply a thermal mitigation configuration associated with the thermal power state. In applying the thermal mitigation configuration, the controller may adjust one or more thermal mitigation parameters associated with the thermal power state. For example, with reference to Figures 1 and 10, the controller 1010 may apply a selective thermal mitigation configuration that gradually reduces power consumption to proportionally reduce the temperature within NVM 110 while maintaining a performance benchmark for the storage device.

[0089] In some aspects of adjusting one or more thermal mitigation parameters, the controller may adjust a power budget parameter based on a temperature gradient associated with the temperature. In some aspects, the power budget parameter indicates a power consumption allocation corresponding to a maximum performance achievable by one or more storage operations of a storage device operating in a thermal power state. For example, with reference to FIG. 10 , the controller 1010 may adjust the power budget parameter using a power budget scaling module 1024 based on a temperature gradient value provided by a temperature gradient module 1022. In some aspects, the temperature gradient module 1022 may obtain temperature measurements from the temperature sensor 1002 and determine a rate of change of the temperature along with a direction of the change (e.g., positive to indicate a rate increase, negative to indicate a rate decrease, or neutral to indicate no change).

[0090] In some aspects of adjusting a power budget parameter, the controller may reduce the value of the power budget parameter based on the temperature gradient indicating a positive rate of change of temperature. In some aspects, the value of the power budget parameter is reduced until the temperature gradient indicates thermal equilibrium (e.g., a neutral value indicating no change in temperature). In other aspects of adjusting a power budget parameter, the controller may increase the value of the power budget parameter based on the temperature gradient indicating a negative rate of change of temperature. In some aspects, the value of the power budget parameter is increased until the temperature gradient indicates thermal equilibrium. In this regard, if the temperature gradient does not indicate a rate of change in either direction, the power budget parameter is not adjusted.

[0091] In another aspect of adjusting one or more thermal mitigation parameters, the controller may adjust clock frequency parameters associated with one or more clock domains of the storage device using values corresponding to predetermined clock frequencies associated with thermal power states. For example, referring to FIG. 10 , the controller 1010 may adjust the clock frequency parameters using the dynamic voltage frequency scaling module 1026. For example, for TPS1, the clock frequency parameters are adjusted from the full clock rate to 60% of the full clock rate. In another example, for TPS2, the clock frequency parameters are adjusted from the full clock rate to 40% of the full clock rate. In yet another example, for TPS3 and / or TPS4, the clock frequency parameters are adjusted from the full clock rate to 10% of the full clock rate.

[0092] In yet another aspect of adjusting one or more thermal mitigation parameters, the controller can adjust voltage parameters associated with one or more voltage ranges of the storage device using values corresponding to predetermined voltages associated with thermal power states. For example, with reference to FIG. 10, the controller 1010 can adjust the voltage parameters using the dynamic voltage frequency scaling module 1026. For example, for any of the thermal power states (e.g., TPS1-TPS4), the voltage parameters are adjusted from full voltage to 75% of full voltage for a particular voltage range (e.g., core voltage).

[0093] In yet another aspect of adjusting one or more thermal mitigation parameters, the controller may adjust a bus interface parameter associated with the interconnect between the memory and the controller using a first value corresponding to a predetermined number of interconnect lanes associated with a thermal power state. For example, with reference to FIG. 10, the controller 1010 may adjust the bus interface parameter using the non-volatile memory host controller module 1060. For example, for some of the later thermal power states (e.g., TPS2-TPS4), the bus interface parameter is adjusted proportionally downward from the total number of lanes available for bandwidth.

[0094] In yet another aspect of adjusting one or more thermal mitigation parameters, the controller may adjust a queue depth parameter associated with the host interface of the storage device by a value corresponding to a predetermined queue depth associated with the thermal power state. For example, with reference to Figure 10, the controller 1010 may adjust the queue depth parameter using the HIM QD control module 1028. For example, for some of the thermal power states (e.g., TPS3-TPS4), the queue depth parameter is adjusted from a full queue depth of 256 to a reduced queue depth of 8.

[0095] As represented by block 1110, the controller may determine that the temperature of the memory has reached thermal equilibrium in the thermal power state based on the thermal mitigation configuration. For example, with reference to Figures 1 and 10, the controller 1010 may determine that the rate of change of the NAND temperature of NVM 110 has slowed to a point where the rate of change indicated by the temperature gradient is near zero (or neutral). In this regard, the controller 1010 may refrain from enabling any thermal throttling via the thermal power state driver 1020 and resume any storage device operations using NVM 110 until the temperature gradient indicates a rate of change of temperature.

[0096] FIG. 12 shows an example diagram 1200 of advanced thermal throttling in a storage device. In thermal throttling, a controller increasingly restricts access to cells as temperature increases in order to cool the storage device. For example, cells may be included on one or more dies, and the controller may disable parallel access to an increasing number of dies as the temperature exceeds various thermal thresholds. In the example diagram 1200, several thermal thresholds are configured for different levels of throttling, including a low (LO) thermal threshold 1202, a medium (MED) thermal threshold 1204, a high (HI) thermal threshold 1206, an extra-high (XTRA HI) thermal threshold 1208, and a thermal shutdown (TSD) thermal threshold 1210. For example, for QLC temperatures, the LO thermal threshold 1202 may be 80° or another temperature, the MED thermal threshold 1204 may be 86° or another temperature, the HI thermal threshold 1206 may be 92° or another temperature, the XTRA HI thermal threshold 1208 may be 94° or another temperature, and the TSD thermal threshold 1208 may be the maximum write temperature, e.g., 95° or another temperature. These thermal thresholds are merely examples. Any number of temperature thermal thresholds of varying magnitudes may be used. Furthermore, the thermal thresholds may vary depending on the cell type. For example, for TLC temperatures, the thermal thresholds may all be higher, and for PLC temperatures, the thermal thresholds may all be lower.

[0097] The controller can implement different levels of throttling when the temperature of a cell exceeds various thermal thresholds to reduce the temperature more quickly. For example, when reducing die parallelism, the controller may apply a light throttle 1214 (e.g., throttling one die) when the temperature exceeds a low thermal threshold 1202, a heavy throttle 1216 (e.g., throttling two die) when the temperature exceeds a medium thermal threshold 1204, a first tier extreme throttle 1218 (e.g., throttling three die) when the temperature exceeds a high thermal threshold 1206, a second tier extreme throttle 1220 when the temperature exceeds an extra high thermal threshold 1208, and a thermal shutdown 1222 (e.g., shutting down access to the die) when the temperature exceeds a high thermal threshold 1210. Other examples of throttling may also be used. For example, instead of disabling parallel access to one, two, or three dies, respectively, a storage device may disable parallel access to a different number of dies, prevent reading from or writing to a different number of dies, limit or restrict access to different numbers or types of memory locations on the same die, or implement other temperature reduction schemes.

[0098] 12 thus illustrates various examples 1224, 1226, 1228, 1230, 1232 of different throttle level operation when cell temperatures 1234, 1236, 1238, 1240, 1242 increase due to, for example, read or write operations or an increase in ambient temperature. Referring to the first example 1224, the storage device initially operates in the full power region 1212, e.g., without throttling. When the temperature 1234 exceeds the LO thermal threshold 1202, the controller implements light throttling 1214. In this example, the light throttling 1214 is sufficient to gradually reduce the temperature, and throttling continues until the temperature falls below the LO thermal threshold 1202. The storage device then disables throttling and resumes full power operation.

[0099] Referring to a second example 1226, the storage device initially operates in the full power region 1212 without throttling. However, unlike the first example, when the temperature 1236 exceeds the LO thermal threshold 1202, the light throttling 1214 is insufficient to reduce the temperature, and therefore, the temperature 1236 continues to rise. Once the temperature exceeds the MED thermal threshold 1204, the controller implements heavy throttling 1216. In this example, the heavy throttling 1216 is sufficient to gradually reduce the temperature, and throttling continues until the temperature drops below the MED thermal threshold 1204. At that point, the controller switches to light throttling 1214, which continues until the temperature drops below the LO thermal threshold 1202. The storage device then disables throttling and resumes full power operation.

[0100] Referring to a third example 1228, the storage device initially operates in the full power region 1212 without throttling. However, unlike the first and second examples, when the temperature 1238 exceeds the LO thermal threshold 1202 and the MED thermal threshold 1204, the light throttle 1214 and heavy throttle 1216 are insufficient to reduce the temperature, and therefore the temperature 1238 continues to rise. When the temperature 1238 exceeds the HI thermal threshold 1206, the controller implements extreme throttle 1216. In this example, the first tier extreme throttle 1218 is sufficient to gradually reduce the temperature, and throttling continues until the temperature falls below the HI thermal threshold 1206. At that point, the controller switches to heavy throttle 1216, which continues to run until the temperature drops below the MED thermal threshold 1204. At that point, the controller switches to light throttle 1214, which continues to run until the temperature falls below the LO thermal threshold 1202. The storage device then disables the throttle and resumes full power operation.

[0101] Referring to a fourth example 1230, the storage device initially operates in the full power range 1212 without throttling. However, unlike the first through third examples, when the temperature 1240 exceeds the LO thermal threshold 1202, the MED thermal threshold 1204, and the HI threshold 1206, the light throttle 1214, the heavy throttle 1216, and the first tier extreme throttle 1218 are insufficient to reduce the temperature, and therefore, the temperature 1240 continues to rise. When the temperature exceeds the XTRA HI thermal threshold 1208, the controller implements the second tier extreme throttle 1220. In this example, the second tier extreme throttle 1220 is sufficient to gradually reduce the temperature, and throttling continues until the temperature falls below the XTRA HI thermal threshold 1208. At that point, the controller switches to the first tier extreme throttle 1218, which continues to execute until the temperature falls below the HI thermal threshold 1206. At that point, the controller switches to heavy throttling 1216, which continues to run until the temperature drops below the MED thermal threshold 1204. At that point, the controller switches to light throttling 1214, which continues to run until the temperature drops below the LO thermal threshold 1202. The storage device then disables throttling and resumes full power operation.

[0102] Referring to the fifth example 1232, the storage device initially operates in the full power range 1212 without throttling. However, unlike the first through fourth examples, when the temperature 1242 exceeds the LO thermal threshold 1202, the MED thermal threshold 1204, the HI thermal threshold 1206, the light throttling 1214, the heavy throttling 1216, and the first tier extreme throttling 1218 are insufficient to reduce the temperature, and thus the temperature 1242 continues to rise. Once the temperature exceeds the XTRA HI thermal threshold 1208, the controller implements the second tier extreme throttling 1220. In this example, the second tier extreme throttling 1220 is insufficient to gradually reduce the temperature, and thus the temperature continues to rise until it reaches the TSD thermal threshold 1210. At this point, the controller implements a thermal shutdown 1222, for example, shutting down access to the cells and / or storage device until the temperature drops to a normal level.

[0103]

[0013] Figure 13 is a conceptual diagram illustrating a state machine 1300 of multiple thermal power states for advanced thermal throttling in the storage device of Figure 1. The state machine 1300 may include a finite number of thermal power states. For example, the state machine 1300 includes a first thermal power state 1302 (TPS0) representing a state of the storage device without thermal throttling, a second thermal power state 1304 (TPS1) associated with a first thermal threshold (TMT1), a third thermal power state 1306 (TPS2) associated with a second thermal threshold (TMT2), a fourth thermal power state 1308 (TPS3) associated with a third thermal threshold (TMT3), and a fifth thermal power state 1310 (TPS4) associated with a fourth thermal threshold (TMT4).

[0104] 1 and 10 , when the temperature of the NVM 110 is determined to meet (or exceed) TMT1, the state machine 1300 indicates a transition from TPS0 1302 to TPS1 1304. Similarly, when the temperature of the NVM 110 is determined to meet (or exceed) TMT2, the state machine 1300 indicates a transition from TPS1 1304 to TPS2 1306. Conversely, when the temperature of the NVM 110 is determined to meet (or not exceed) TMT1b, the state machine 1300 indicates a transition from TPS1 1304 back to TPS0 1302. In some aspects, TMT1b is less than TMT1. For example, TMT1 may be set to 80° C. and TMT1b may be set to 77° C.

[0105] If the temperature of NVM 110 is determined to meet (or exceed) TMT3, then state machine 1300 indicates a transition from TPS2 1306 to TPS3 1308. Conversely, if the temperature of NVM 110 is determined to meet (or not exceed) TMT2b, then state machine 1300 indicates a transition from TPS2 1306 back to TPS1 1304. In some embodiments, TMT2b is less than TMT2. For example, TMT2 can be set to 86°C and TMT2b can be set to 83°C.

[0106] If the temperature of the NVM 110 is determined to meet (or exceed) TMT4, the state machine 1300 indicates a transition from TPS3 1308 to TPS4 1310. Conversely, if the temperature of the NVM 110 is determined to meet (or not exceed) TMT3b, the state machine 1300 indicates a transition from TPS3 1308 back to TPS2 1306. In some embodiments, TMT3b is less than TMT3. For example, TMT3 can be set to 92°C, and TMT3b can be set to 89°C. Similarly, if the temperature of the NVM 110 is determined to meet (or not exceed) TMT4b, the state machine 1300 indicates a transition from TPS4 1310 back to TPS3 1308. In some embodiments, TMT4b is less than TMT4. For example, TMT4 can be set to 94°C, and TMT4b can be set to 92°C.

[0107] Figure 14 is a flowchart illustrating an exemplary process for an advanced thermal throttling first thermal power state in the storage device of Figure 1. For example, the method may be performed in storage device 102 as shown in Figure 1. Each step in the flowchart may be controlled using a controller (e.g., controller 123, 802, 1010) as described below, or by any other suitable means.

[0108] 10 and 13, the controller 1010 can transition to a first thermal power state (e.g., TPS1 1304) of a plurality of thermal power states (e.g., TPS1-TPS4). In some aspects, the controller 1010 can apply the thermal mitigation configuration by applying one or more thermal mitigation parameters of a first thermal mitigation configuration associated with the first thermal power state.

[0109] The controller obtains the temperature, as represented by block 1402. For example, with reference to Figures 1 and 10, the controller 1010 may measure a first temperature of the NVM 110 in a first thermal power state based on the applied one or more thermal mitigation parameters of the first thermal mitigation configuration.

[0110] As represented by block 1404, the controller 1010 may apply a power budget adjustment (e.g., PB = PB(n)a) and apply a clock frequency scaling adjustment to a first predetermined percentage (e.g., x = 60% of the full clock rate).

[0111] As represented by block 1406, the controller 1010 can determine a temperature gradient from the measured first temperature. For example, the controller 1010 can determine whether the rate of change of the measured temperature is positive (increasing), negative (decreasing), or neutral (no change).

[0112] As represented by block 1408, the controller 1010 may determine that the measured first temperature is greater than an exit thermal threshold associated with the first thermal power state and less than an entrance thermal threshold associated with a second thermal power state of the plurality of thermal power states (e.g., TMT2>Temp>TMT1b). If not, the process exits the thermal power state.

[0113] As represented by block 1410, the controller 1010 may determine whether the temperature gradient indicates that the measured first temperature is in thermal equilibrium. In other words, the controller 1010 may determine whether the temperature gradient is equal to a zero value. For example, as represented by block 1410, the controller 1010 may determine that the temperature gradient is positive (or greater than zero) and proceed to block 1412. Alternatively, for example, as represented by block 1410, the controller 1010 may determine that the temperature gradient is not positive (or less than or equal to zero) and proceed to block 1416.

[0114] As represented by block 1416, the controller 1010 determines that the temperature gradient is negative (or less than 0) and proceeds to block 1418. Otherwise, the controller 1010 determines that the temperature gradient is not negative and proceeds to block 1422.

[0115] As represented by blocks 1412 and 1418, the controller 1010 can adjust a first power budget parameter of the first thermal relaxation configuration when the temperature gradient indicates that the measured first temperature is not in thermal equilibrium. As represented by block 1414, the controller 1010 can adjust the power consumption by reducing the power budget value in proportion to the degree of change of the temperature gradient when the temperature gradient indicates a positive rate of change of temperature. As represented by block 1420, the controller 1010 can adjust the power consumption by increasing the power budget value in proportion to the degree of change of the temperature gradient when the temperature gradient indicates a negative rate of change of temperature.

[0116] As represented by block 1422, the controller 1010 may refrain from adjusting the first power budget parameter when the temperature gradient indicates that the measured first temperature is in thermal equilibrium. In this regard, the controller 1010 determines that there is no rate of change of temperature (and thus is in temperature equilibrium). Thus, the power budget parameter remains unchanged.

[0117] Figure 15 is a flowchart illustrating an exemplary process for an advanced thermal throttling second thermal power state in the storage device of Figure 1. For example, the method may be performed in storage device 102 as shown in Figure 1. Each step in the flowchart may be controlled using a controller (e.g., controller 123, 802, 1010) as described below, or by any other suitable means.

[0118] 10 and 13, the controller 1010 may transition to a second thermal power state (e.g., TPS2 1306) of the plurality of thermal power states (e.g., TPS1-TPS4). In some aspects, the controller 1010 may apply the thermal mitigation configuration by applying one or more thermal mitigation parameters of a second thermal mitigation configuration associated with the second thermal power state.

[0119] The controller obtains the temperature, as represented by block 1502. For example, with reference to Figures 1 and 10, the controller 1010 may measure a second temperature of the NVM 110 in the second thermal power state based on the applied one or more thermal mitigation parameters of the second thermal mitigation configuration.

[0120] As represented by block 1504, the controller 1010 may apply a power budget adjustment (e.g., PB = PB(n)a) and apply a clock frequency scaling adjustment to a second predetermined percentage (e.g., x = 40% of the full clock rate).

[0121] As represented by block 1506, the controller 1010 can determine a temperature gradient from the measured second temperature. For example, the controller 1010 can determine whether the rate of change of the measured temperature is positive (increasing), negative (decreasing), or neutral (no change).

[0122] As represented by block 1508, the controller 1010 may determine that the measured second temperature is greater than the exit thermal threshold associated with the second thermal power state and less than the entrance thermal threshold associated with a third thermal power state of the plurality of thermal power states (e.g., TMT3>Temp>TMT2b). If not, the process exits the thermal power state.

[0123] As represented by block 1510, the controller 1010 may determine whether the temperature gradient indicates that the measured second temperature is in thermal equilibrium. In other words, the controller 1010 may determine whether the temperature gradient is equal to a zero value. For example, as represented by block 1510, the controller 1010 may determine that the temperature gradient is positive (or greater than zero) and proceed to block 1512. Alternatively, for example, as represented by block 1510, the controller 1010 may determine that the temperature gradient is not positive (or less than or equal to zero) and proceed to block 1516.

[0124] As represented by block 1516, the controller 1010 determines that the temperature gradient is negative (or less than 0) and proceeds to block 1518. Otherwise, the controller 1010 determines that the temperature gradient is not negative and proceeds to block 1522.

[0125] As represented by blocks 1512 and 1518, the controller 1010 can adjust a second power budget parameter of the second thermal relaxation configuration when the temperature gradient indicates that the measured second temperature is not in thermal equilibrium. As represented by block 1514, the controller 1010 can adjust the power consumption by reducing the power budget value in proportion to the degree of change of the temperature gradient when the temperature gradient indicates a positive rate of change of temperature. As represented by block 1520, the controller 1010 can adjust the power consumption by increasing the power budget value in proportion to the degree of change of the temperature gradient when the temperature gradient indicates a negative rate of change of temperature.

[0126] As represented by block 1522, the controller 1010 may refrain from adjusting the second power budget parameter when the temperature gradient indicates that the measured second temperature is in thermal equilibrium. In this regard, the controller 1010 determines that there is no rate of change of temperature (and thus is in temperature equilibrium). Thus, the power budget parameter remains unchanged.

[0127] 16 is a flowchart illustrating an exemplary process for a third thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in storage device 102 as shown in FIG. 1. The steps in the flowchart may be controlled using a controller (e.g., controller 123, 802, 1010) as described below or by some other suitable means. In one or more implementations, controller 1010 may transition to a third thermal power state (e.g., TPS3 1308) of a plurality of thermal power states (e.g., TPS1-TPS4).

[0128] As represented by block 1602, the controller 1010 may apply a third thermal mitigation configuration associated with the third thermal power state. In some aspects, the third thermal mitigation configuration sets a power budget for the third thermal power state that may correspond to an allowed minimum power consumption allocation. In some aspects, the third thermal mitigation configuration reduces the host interface queue depth size from a full queue depth (e.g., 256) to a reduced queue depth (e.g., 8). In other aspects, the third thermal mitigation configuration reduces the clock frequency of the storage device by a predetermined percentage. For example, the third thermal mitigation configuration may scale the clock frequency from a full clock rate (or a previous clock rate) to 10% of the full clock rate.

[0129] The controller obtains the temperature, as represented by block 1604. For example, with reference to Figures 1 and 10, the controller 1010 may measure a third temperature of the memory in a third thermal power state based on the applied one or more thermal mitigation parameters of the third thermal mitigation configuration.

[0130] As represented by block 1606, the controller may determine whether the measured third temperature is greater than an exit thermal threshold associated with the third thermal power state and less than an entrance thermal threshold associated with a fourth thermal power state of the plurality of thermal power states (e.g., TMT4>Temperature>TMT3b). If the measured third temperature satisfies the condition, the process returns to block 1604. If not, the process exits the thermal power state.

[0131] 17 is a flowchart illustrating an exemplary process for a fourth thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in storage device 102 as shown in FIG. 1. Each step in the flowchart may be controlled using a controller (e.g., controller 123, 802, 1010) as described below or by some other suitable means. In one or more implementations, the controller may transition to a fourth thermal power state (e.g., TPS4 1310) of a plurality of thermal power states (e.g., TPS1-TPS4).

[0132] As represented by block 1702, the controller 1010 may apply a fourth thermal mitigation configuration associated with the fourth thermal power state. In some aspects, the fourth thermal mitigation configuration sets a power budget for the fourth thermal power state that may correspond to the minimum allowed power consumption allocation. In some aspects, the fourth thermal mitigation configuration reduces the host interface queue depth size from the full queue depth (e.g., 256) to a reduced queue depth (e.g., 8). In other aspects, the fourth thermal mitigation configuration reduces the clock frequency of the storage device by a predetermined percentage. For example, the fourth thermal mitigation configuration may scale the clock frequency from the full clock rate (or a previous clock rate) to 10% of the full clock rate. Additionally, the fourth thermal mitigation configuration may reduce the operational clock duty cycle (e.g., to 10% of the full clock duty cycle).

[0133] The controller obtains the temperature, as represented by block 1704. For example, with reference to Figures 1 and 10, the controller 1010 may measure a fourth temperature of the memory in a fourth thermal power state based on the applied one or more thermal mitigation parameters of the fourth thermal mitigation configuration.

[0134] As represented by block 1706, the controller may determine whether the measured fourth temperature is greater than the exit thermal threshold associated with the fourth thermal power state and less than the entrance thermal threshold associated with the thermal shutdown state (e.g., TMTSD>Temp>TMT4b). If the measured fourth temperature satisfies the condition, the process returns to block 1704. If not, the process exits the thermal power state.

[0135] Figure 18A is a graph illustrating performance benchmarking using legacy thermal throttling in the storage device of Figure 1. Figure 18A shows a graph 1810 illustrating changes in memory temperature over time, a graph 1812 illustrating memory performance over time based on changes in memory temperature, and a graph 1814 illustrating memory power consumption due to memory performance based on changes in memory temperature. Graphs 1812 and 1814 respectively illustrate the large fluctuations in performance and power consumption due to hard power state transitions under legacy thermal throttling techniques.

[0136] Figure 18B is a graph illustrating performance benchmarks using advanced thermal throttling for the storage device of Figure 1. Figure 18B shows a graph 1820 illustrating changes in memory temperature over time, a graph 1822 illustrating memory performance over time based on changes in memory temperature, and a graph 1824 illustrating memory power consumption due to memory performance based on changes in memory temperature. In contrast to Figure 18A, graphs 1822 and 1824 show smaller (and more gradual) fluctuations in performance and power consumption, respectively, due to more gradual power state transitions under advanced thermal throttling techniques with multiple thermal power states.

[0137] Thus, the storage device of the present disclosure improves performance and user experience without compromising data integrity based on multiple thermal power states. Rather than employing thermal throttling that results in hard power state transitions (and therefore reduced performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling with multiple thermal power states that gradually reduce power based on a temperature gradient along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables performance benchmarks to be met, and maintains data reliability through efficient NAND block usage.

[0138] Various aspects of this disclosure are provided to enable those skilled in the art to practice the present invention. Various modifications to the exemplary embodiments presented throughout this disclosure will be readily apparent to those skilled in the art, and the concepts disclosed herein may be extended to other magnetic storage devices. Accordingly, the claims are not limited to various aspects of this disclosure, but are to be accorded the full scope consistent with the language of the claims. All structural and functional equivalents to the various components of the exemplary embodiments described throughout this disclosure that are known or later become known to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is expressly recited in the claims. Claim elements are not to be construed under 35 U.S.C. §112(f) in the United States or any similar statute or rule of law in another jurisdiction unless the element is expressly recited using the phrase "means for," or, in the case of a method claim, unless the element is recited using the phrase "step for."

Claims

1. 1. A storage device comprising: Memory and a controller coupled to the memory, the controller comprising: determining whether a temperature of the memory satisfies one thermal throttling threshold of a plurality of thermal throttling thresholds; transitioning to one of a plurality of thermal power states in response to the temperature satisfying the thermal throttling threshold; applying a thermal mitigation configuration associated with the thermal power state; determining whether the temperature of the memory has reached thermal equilibrium in the thermal power state in response to the thermal relaxation configuration; refraining from further application of the thermal mitigation configuration in response to the temperature of the memory reaching the thermal equilibrium; obtaining the temperature of the memory at a first sampling rate before the temperature of the memory meets the thermal throttling threshold; responsive to the temperature of the memory satisfying the thermal throttling threshold, acquiring the temperature of the memory at a second sampling rate greater than the first sampling rate.

2. The storage device of claim 1 , wherein the controller configured to apply the thermal mitigation configuration is further configured to adjust one or more thermal mitigation parameters associated with the thermal power state.

3. 3. The storage device of claim 2, wherein the controller configured to adjust the one or more thermal relaxation parameters is further configured to adjust a power budget parameter based on a thermal gradient associated with the temperature, the power budget parameter indicating a power consumption allocated to the storage device in the thermal power state.

4. 4. The storage device of claim 3, wherein the controller configured to adjust the power budget parameter is further configured to reduce a value of the power budget parameter in response to the temperature gradient indicating a positive rate of change of the temperature, the value of the power budget parameter being reduced until the temperature gradient indicates the thermal equilibrium.

5. 4. The storage device of claim 3, wherein the controller configured to adjust the power budget parameter is further configured to increase a value of the power budget parameter in response to the temperature gradient indicating a negative rate of change of the temperature, the value of the power budget parameter being increased until the temperature gradient indicates the thermal equilibrium.

6. 3. The storage device of claim 2, wherein the controller configured to adjust the one or more thermal mitigation parameters is further configured to adjust clock frequency parameters associated with one or more clock domains of the storage device using values corresponding to predetermined clock frequencies associated with the thermal power states.

7. 3. The storage device of claim 2, wherein the controller configured to adjust the one or more thermal relaxation parameters is further configured to adjust voltage parameters associated with one or more voltage domains of the storage device using values corresponding to predetermined voltages associated with the thermal power states.

8. 3. The storage device of claim 2, wherein the controller configured to adjust the one or more thermal mitigation parameters is further configured to adjust a bus interface parameter associated with an interconnect between the memory and the controller by a value corresponding to a predetermined number of interconnect lanes associated with the thermal power state.

9. The controller configured to transition to the thermal power state is further configured to transition to a first thermal power state of the plurality of thermal power states, and the controller configured to apply the thermal mitigation configuration is further configured to apply one or more first thermal mitigation parameters of a first thermal mitigation configuration associated with the first thermal power state, and the controller: measuring a first temperature of the memory in the first thermal power state based on the one or more first thermal relaxation parameters of the first thermal relaxation configuration; determining a first temperature gradient from the measured first temperature; determining whether the measured first temperature is greater than a first outlet thermal throttling threshold associated with the first thermal power state and less than a first inlet thermal throttling threshold associated with a second thermal power state of the plurality of thermal power states; determining whether the first temperature gradient indicates that the measured first temperature is in thermal equilibrium in response to the measured first temperature being greater than the first outlet thermal throttling threshold and less than the first inlet thermal throttling threshold; adjusting a first power budget parameter of the first thermal relaxation configuration in response to the first temperature gradient indicating that the measured first temperature is not in thermal equilibrium; 2. The storage device of claim 1, further configured to refrain from adjusting the first power budget parameter in response to the first temperature gradient indicating that the measured first temperature is in thermal equilibrium.

10. the controller configured to transition to the thermal power state is further configured to transition to the second thermal power state, and the controller configured to apply the thermal mitigation configuration is further configured to apply one or more second thermal mitigation parameters of a second thermal mitigation configuration associated with the second thermal power state, and the controller: measuring a second temperature of the memory in the second thermal power state based on the one or more second thermal relaxation parameters of the second thermal relaxation configuration; determining a second temperature gradient from the measured second temperature; determining whether the measured second temperature is greater than a second exit thermal throttling threshold associated with the second thermal power state and less than a second entrance thermal throttling threshold associated with a third thermal power state of the plurality of thermal power states; determining whether the second temperature gradient indicates that the measured second temperature is at the thermal equilibrium in response to the measured second temperature being greater than the second outlet thermal throttling threshold and less than the second inlet thermal throttling threshold; adjusting a second power budget parameter of the second thermal relaxation configuration in response to the second temperature gradient indicating that the measured second temperature is not at thermal equilibrium; 10. The storage device of claim 9, further configured to refrain from adjusting the second power budget parameter in response to the second temperature gradient indicating that the measured second temperature is in thermal equilibrium.

11. The controller configured to transition to the thermal power state is further configured to transition to the third thermal power state, and the controller configured to apply the thermal mitigation configuration is further configured to apply one or more third thermal mitigation parameters of a third thermal mitigation configuration associated with the third thermal power state, and the controller is configured to reduce a queue depth size and reduce a clock frequency by a predetermined percentage in the third thermal mitigation configuration, and the controller: measuring a third temperature of the memory in the third thermal power state based on the one or more third thermal relaxation parameters of the third thermal relaxation configuration; 11. The storage device of claim 10, further configured to: maintain the third thermal power state in response to the measured third temperature being greater than a third exit thermal throttling threshold associated with the third thermal power state and less than a third entrance thermal throttling threshold associated with a fourth thermal power state of the plurality of thermal power states.

12. the controller configured to transition to the thermal power state is further configured to transition to the fourth thermal power state, the controller configured to apply the thermal relaxation configuration is further configured to apply one or more fourth thermal relaxation parameters of a fourth thermal relaxation configuration associated with the fourth thermal power state, the controller is configured to reduce a clock duty cycle in the fourth thermal relaxation configuration, and the controller: measuring a fourth temperature of the memory in the fourth thermal power state based on the one or more fourth thermal relaxation parameters of the fourth thermal relaxation configuration; 12. The storage device of claim 11, further configured to: maintain the fourth thermal power state in response to the measured fourth temperature being greater than a fourth exit thermal throttling threshold associated with the fourth thermal power state and less than a fourth entrance thermal throttling threshold associated with a thermal shutdown state of the plurality of thermal power states.

13. 1. A storage device comprising: Memory and a controller coupled to the memory, the controller comprising: adjusting one or more thermal mitigation parameters, including a bus interface parameter, associated with an interconnect between the memory and the controller, the bus interface parameter being adjusted by a value corresponding to a predetermined number of interconnect lanes associated with the thermal power state following a transition to one of a plurality of thermal power states in response to the temperature of the memory satisfying a thermal throttle threshold; The storage device is configured to refrain from further adjusting the one or more thermal relaxation parameters in response to determining that the temperature of the memory has reached thermal equilibrium in the thermal power state in response to the adjusted one or more thermal relaxation parameters.

14. 14. The storage device of claim 13, wherein the controller configured to adjust the one or more thermal relaxation parameters is further configured to adjust a power budget parameter based on a thermal gradient associated with the temperature, the power budget parameter indicating a power consumption allocated to the storage device in the thermal power state to maintain one or more storage operations of the storage device.

15. 14. The storage device of claim 13, wherein the controller configured to adjust the one or more thermal mitigation parameters is further configured to adjust clock frequency parameters associated with one or more clock domains of the storage device to correspond to predetermined clock frequencies associated with the thermal power states.

16. 14. The storage device of claim 13, wherein the controller configured to adjust the one or more thermal mitigation parameters is further configured to adjust voltage parameters associated with one or more voltage domains of the storage device to correspond to predetermined voltages associated with the thermal power states.

17. The controller obtaining the temperature of the memory at a first sampling rate before the temperature of the memory meets the thermal throttling threshold; 14. The storage device of claim 13, further configured to: in response to the temperature of the memory satisfying the thermal throttling threshold, obtain the temperature of the memory at a second sampling rate greater than the first sampling rate.

18. 1. A storage device comprising: a memory having blocks of cells; a controller coupled to the memory, the controller comprising: responsive to the temperature of the block of cells satisfying a thermal throttling threshold, applying a thermal mitigation configuration associated with the one thermal power state of a plurality of thermal power states following a transition to the one thermal power state of the plurality of thermal power states, the thermal mitigation configuration configuring a reduction in a size of a queue depth; determining whether the temperature of the block of cells has reached thermal equilibrium in the thermopower state in response to the thermal relaxation configuration; responsive to the temperature reaching the thermal equilibrium, refrain from further application of the thermal relaxation arrangement.

19. The controller configured to apply the thermal mitigation arrangement further comprises: adjusting a power budget parameter based on a thermal gradient associated with the temperature, the power budget parameter indicating a power consumption allocated to the storage device in the thermal power state; adjusting clock frequency parameters associated with one or more clock domains of the storage device to correspond to predetermined clock frequencies associated with the thermal power state; adjusting voltage parameters associated with one or more voltage domains of the storage device to correspond to predetermined voltages associated with the thermal power states; 20. The storage device of claim 18, further configured to adjust bus interface parameters associated with an interconnect between the memory and the controller to correspond to a predetermined number of interconnect lanes associated with the thermal power condition.

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