nitride semiconductor devices

Abstract

To provide a method for manufacturing a nitride semiconductor device capable of forming a highly concentrated P-type region, and a nitride semiconductor device.SOLUTION: A method for manufacturing a nitride semiconductor device includes: a step of forming N-type regions in a nitride semiconductor layer; a step of implanting ions of an acceptor element into a region sandwiched by the N-type regions on both sides in the nitride semiconductor layer; and a step of forming a P-type region sandwiched by the N-type regions on both sides by subjecting the nitride semiconductor layer in which the N-type regions are formed and into which ions of the acceptor element are implanted to heat treatment and activating the acceptor element. In the step of forming the N-type regions, ions of a donor element are implanted to the nitride semiconductor layer at a high concentration in such a way that concentration of the donor element in the N-type regions has a value equal to or greater than concentration of the acceptor element in the P-type region. In the step of implanting ions of the acceptor element, ions of the acceptor element are implanted in such a way that concentration of the acceptor element in the P-type region is 1×1019 cm-3 or more and 1×1021 cm-3 or less.SELECTED DRAWING: Figure 3B

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] Nitride semiconductor devices having a vertical MOS (Metal Oxide Semiconductor) structure are known (see, for example, Patent Document 1). In addition, in nitride semiconductor devices, it is possible to control the P-type conductivity by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

[0003] To achieve good ohmic contact in nitride semiconductor devices, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. Ion implantation is a desirable method for selectively forming a P-type region from the viewpoints of cost, productivity, and reliability. However, when high-concentration Mg ions are implanted into a nitride semiconductor and heat treatment is performed at a high temperature exceeding 1300°C to activate the Mg, the Mg segregates into rod-like structures at high density. When Mg segregates into rod-like structures at high density, the Mg concentration decreases in regions other than the segregated regions (see, for example, Non-Patent Document 1). Furthermore, when heat treatment is performed at a high temperature exceeding 1400°C under an ultra-high pressure atmosphere, the Mg diffuses deeply, resulting in a decrease in concentration (see, for example, Non-Patent Document 2). For this reason, it has been difficult to form a high-concentration P-type region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-096744 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-086698 [Non-patent literature]

[0005] [Non-Patent Document 1] Kumar et.al.,J.Appl.Phys.126(2019)235704. [Non-patent document 2] H.Sakurai et.al.,Appl.Phys.Lett. 115,142104(2019). [Non-patent document 3] G. Miceli, A. Pasquarello PRB (2016). Summary of the Invention [Problem to be solved by the invention]

[0006] When Mg is activated by heat treatment to form a P-type region, the Fermi level of the P-type region approaches the valence band. When the Fermi level approaches the valence band, the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) increases, making the activation of Mg unstable (see, for example, Non-Patent Document 3). The high-density segregation of Mg described above is thought to occur when the activation of Mg becomes unstable, making it easier for Mg to segregate through defects.

[0007] The present invention was made through extensive research by the inventors based on this idea, and aims to provide a method for manufacturing a nitride semiconductor device that is capable of forming a highly-doped P-type region, and a nitride semiconductor device. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, a nitride semiconductor device manufacturing method according to one aspect of the present invention includes the steps of: forming an N-type region in a nitride semiconductor layer; ion-implanting an acceptor element into regions of the nitride semiconductor layer sandwiched between the N-type regions; and forming P-type regions sandwiched between the N-type regions by activating the acceptor element by performing a heat treatment on the nitride semiconductor layer in which the N-type region is formed and in which the acceptor element has been ion-implanted. In the step of forming the N-type region, the donor element is ion-implanted into the nitride semiconductor layer at a high concentration so that the concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in the P-type region. In the step of ion-implanting the acceptor element, the concentration of the acceptor element in the P-type region is 1×10 19 cm -3 More than 1×10 21 cm -3 The acceptor element is ion-implanted so as to satisfy the following conditions.

[0009] A nitride semiconductor device according to one aspect of the present invention includes a nitride semiconductor layer, an N-type region provided on one surface of the nitride semiconductor layer, and a P-type region provided on the one surface of the nitride semiconductor layer and sandwiched between the N-type regions. The concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in the P-type region. The concentration of the acceptor element in at least a portion of the P-type region is 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a nitride semiconductor device manufacturing method capable of forming a highly doped P-type region, and a nitride semiconductor device. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a GaN semiconductor device 100 according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a plan view showing a configuration example of a vertical MOSFET according to the first embodiment of the present invention. [Figure 2B] FIG. 2B is a plan view showing an area enclosed by a dashed line in the plan view of FIG. 2 in a further enlarged manner. [Figure 3A] FIG. 3A is a cross-sectional view showing an example of the configuration of a vertical MOSFET according to the first embodiment of the present invention. [Figure 3B] FIG. 3B is an enlarged cross-sectional view of the P+ region and its surrounding area in the cross-sectional view of FIG. 3A. [Figure 4A] FIG. 4A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4B] FIG. 4B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4C] 4A to 4C are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4D] 4A to 4D are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4E] FIG. 4E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4F] 4F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 5] FIG. 5 is a band diagram of the contact portion between N-type GaN and P-type GaN and its vicinity, showing the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after heat treatment for activating the acceptor element (e.g., Mg) ion-implanted into the P-type GaN. [Figure 6] FIG. 6 is a band diagram of P-type GaN in the absence of N-type GaN, showing the valence band Ev, conduction band Ec, and Fermi level Ef before and after heat treatment for activating the acceptor element. [Figure 7]FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. [Figure 8] FIG. 8 is a graph showing the relationship between the acceptor concentration of P-type GaN and the width of the depletion layer formed in P-type GaN due to contact with N-type GaN. [Figure 9] FIG. 9 is a graph showing an example of the Mg and Si profiles in GaN. [Figure 10] FIG. 10 is a plan view showing a configuration example of a GaN semiconductor device according to the second embodiment of the present invention. [Figure 11A] FIG. 11A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a second embodiment of the present invention. [Figure 11B] FIG. 11B is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the second embodiment of the present invention. [Figure 12] FIG. 12 is a plan view showing a configuration example of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 13A] FIG. 13A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 3 of the present invention. [Figure 13B] FIG. 13A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 3 of the present invention. [Figure 14] FIG. 14 is a plan view showing a configuration example of a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a fourth embodiment of the present invention. [Figure 16] FIG. 16 is a plan view showing a configuration example of a GaN semiconductor device according to a fifth embodiment of the present invention. [Figure 17A] FIG. 17A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 5 of the present invention. [Figure 17B] FIG. 17B is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 5 of the present invention. [Figure 18] FIG. 18 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a sixth embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the seventh embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an eighth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10 (i.e., the thickness direction of the GaN substrate 10). The X-axis, Y-axis, and Z-axis directions are orthogonal to one another.

[0014] In the following description, the term "planar view" means, for example, a view from a direction (for example, the Z-axis direction) perpendicular to a surface 10a of a GaN substrate 10 described below.

[0015] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship between regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0016] In the following description, + or - attached to P or N indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same P and P (or N and N) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0017] <Embodiment 1> (Configuration example) FIG. 1 is a plan view showing an example configuration of a gallium nitride semiconductor device 100 according to a first embodiment of the present invention (an example of the "nitride semiconductor device" of the present invention; hereinafter, referred to as a GaN semiconductor device). FIG. 1 is an XY plan view. As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 23 and a source electrode 25, respectively, which will be described later.

[0018] In a plan view from the Z-axis direction, edge termination region 130 surrounds the periphery of active region 110. Edge termination region 130 may have one or more of a guard ring structure and a JTE (Junction Termination Extension) structure. Edge termination region 130 may have the function of preventing electric field concentration in active region 110 by extending a depletion layer generated in active region 110 to edge termination region 130.

[0019] Fig. 2A is a plan view showing an example of the configuration of the vertical MOSFET 1 according to the first embodiment of the present invention. Fig. 2A shows an enlarged view of a part of the active region 110 shown in Fig. 1, and omits the gate pad 112, the source pad 114, the gate electrode 23, and the source electrode 25 in order to show the shape of the source region 18 and the like in a plan view from the Z-axis direction. Fig. 2B is a plan view showing a further enlarged view of the region surrounded by the dashed line in the plan view of Fig. 2A.

[0020] 3A is a cross-sectional view showing a configuration example of the vertical MOSFET 1 according to the first embodiment of the present invention. FIG. 3A shows a cross section taken along line X1-X'1 in the plan view of FIG. 2A. FIG. 3B is a cross-sectional view showing an enlarged view of the P+ type region 20 and its surrounding region in the cross-sectional view of FIG. 3A. FIG. 3B shows a cross section taken along line X2-X'2 in the plan view of FIG. 2B.

[0021] 2A and 3A includes a gallium nitride substrate 10 (an example of a "nitride semiconductor layer" according to the present invention; hereinafter, referred to as a GaN substrate) and a plurality of vertical MOSFETs 1 (an example of a "field-effect transistor" according to the present invention) provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (for example, the X-axis direction).

[0022] As shown in FIGS. 2A and 3A , the vertical MOSFET 1 includes an N− type drift region 12, a P type well region 14, an N+ type source region 18 (an example of an “N-type region” according to the present invention), and a P+ type region 20 (an example of a “P-type region” according to the present invention) provided in a GaN substrate 10, a gate insulating film 21 provided on a front surface 10 a (an example of a “one surface” according to the present invention) of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, a source electrode 25 (an example of an “electrode” according to the present invention) provided on the front surface 10 a side of the GaN substrate 10 and electrically connected to the N+ type source region 18 and the P+ type region 20, and a drain electrode 27 provided on the back surface 10 b side of the GaN substrate 10 and electrically connected to the drift region 12.

[0023] The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a front surface 10a and a back surface 10b located opposite the front surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1×10 7 cm -2 It is a free-standing GaN substrate with low dislocation density.

[0024] The donor element (N-type impurity) contained in the GaN substrate 10 may be one or more of Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0025] Because the GaN substrate 10 is a freestanding GaN substrate with low dislocations, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. Furthermore, during the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations.

[0026] The GaN substrate 10 may be N-type instead of N-type. The GaN substrate 10 may also include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N-type, and the GaN layer may be N type or N-type. The GaN single crystal substrate may also be a low-dislocation freestanding GaN substrate.

[0027] In the vertical MOSFET 1, the GaN substrate 10 may contain one or more elements of aluminum (Al) and indium (In). The GaN substrate 10 may be an alloy semiconductor containing trace amounts of Al and In in GaN, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0028] A drift region 12, a P-type well region 14, an N+ type source region 18, and a P+ type region 20 are provided on a GaN substrate 10. The well region 14, the N+ type source region 18, and the P+ type region 20 are each formed by ion-implanting impurities to a predetermined depth from the surface 10a of the GaN substrate 10 and activating the impurities by heat treatment.

[0029] For example, a P+ type region 20 is provided on the surface side of a P type well region 14. The P+ type region 20 is in contact with the well region 14. The P+ type region 20 has a higher P type impurity concentration than the well region 14. The well region 14 and the P+ type region 20 contain at least one of Mg and Be as an acceptor element.

[0030] For example, the well region 14 and the P+ type region 20 contain Mg as an acceptor element. The Mg concentration in the well region 14 is 1×10 16 cm -3 3x10 or more 18 cm -3 The Mg concentration in at least a portion of the P+ type region 20 (for example, the second region 202 described below) is 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0031] The drift region 12 is an N-type region. The N+ type source region 18 has a higher N-type impurity concentration than the N- type drift region 12. The drift region 12 and the N+ type source region 18 contain, for example, Si as an N-type impurity. For example, the N-type impurity concentration of the drift region 12 is the same as the N-type impurity concentration of the GaN substrate 10. In this case, the drift region 12 does not need to be ion-implanted with N-type impurities. The Si concentration in the drift region 12 is 1×10 15 cm -3 More than 1×10 17 cm -3 The following is the result.

[0032] The N+ type source region 18 is provided on the surface side of the well region 14. The N+ type source region 18 is formed by ion-implanting Si into the surface side of the well region 14 and activating the Si by heat treatment. The Si concentration in the N+ type source region 18 is 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0033] An upper portion of the N+ type source region 18 is exposed on the surface 10a of the GaN substrate 10. The N+ type source region 18 has one side in the X-axis direction and another side located opposite the one in the X-axis direction. One side and a bottom of the N+ type source region 18 contact the well region 14, and the other side of the N+ type source region 18 contacts the P+ type region 20. One side of the N+ type source region 18 is located on the side of a region where a channel of the vertical MOSFET 1 is formed (hereinafter referred to as a channel region). The channel of the vertical MOSFET 1 is formed in the well region 14.

[0034] The P+ type region 20 is exposed on the surface 10a of the GaN substrate 10. Both sides of the P+ type region 20 in the X-axis direction are in contact with the N+ type source region 18, and the bottom is in contact with the well region 14. The well region 14, the P+ type region 20, and the N+ type source region 18 have, for example, a stripe shape extending in the Y-axis direction.

[0035] An upper portion (hereinafter referred to as the upper region) 121 of the drift region 12 is exposed on the surface 10a of the GaN substrate 10. The upper region 121 is in contact with the gate insulating film 21 on the surface 10a. The upper region 121 is located between a pair of well regions 14 facing each other in the Y-axis direction. The upper region 121 may also be called a JFET region. The upper region 121 may be N-type instead of N-type. This allows the on-resistance of the vertical MOSFET 1 to be reduced.

[0036] A lower portion (hereinafter referred to as the lower portion) 122 of the drift region 12 contacts the bottom of the well region 14. The lower portion 122 is located between the upper portion 121 and the drain electrode 27, and between the well region 14 and the drain electrode 27. The lower portion 122 is provided continuously in the X-axis direction between a plurality of vertical MOSFETs 1 (i.e., a plurality of unit structures) repeated in the X-axis direction.

[0037] The drift region 12 functions as a current path between the drain electrode 27 and the channel region. The P+ type region 20 is a region for making contact between the well region 14 and an electrode (e.g., the source electrode 25). The P+ type region 20 also functions as a hole extraction path when the gate is off.

[0038] The gate insulating film 21 is, for example, a silicon oxide film (SiO2 film). The gate insulating film 21 is provided on, for example, the flat surface 10a.

[0039] The gate electrode 23 is provided above the channel region via the gate insulating film 21. For example, the gate electrode 23 is a planar type provided on the flat gate insulating film 21. The gate electrode 23 is formed of a material different from that of the gate pad 112. The gate electrode 23 is formed of polysilicon doped with impurities, and the gate pad 112 is formed of Al or an Al-Si alloy.

[0040] The source electrode 25 is provided on the surface 10a of the GaN substrate 10. The source electrode 25 is in contact with a part of the N+ type source region 18 and the P+ type region 20. The source electrode 25 may also be provided on the gate electrode 23 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 23 so that the gate electrode 23 and the source electrode 25 are not electrically connected.

[0041] The source electrode 25 is made of the same material as the source pad 114. For example, the source electrode 25 made of Al or an Al-Si alloy also serves as the source pad 114. The source electrode 25 may have a barrier metal layer between the front surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer. The drain electrode 27 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the back surface 10b. The drain electrode 27 is also made of the same material as the source electrode 25.

[0042] In FIG. 3A , the gate terminal, the source terminal, and the drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or greater than the threshold voltage is applied to the gate electrode 23 via the gate terminal G, an inversion layer is formed in the channel region. With the inversion layer formed in the channel region, when a predetermined high potential is applied to the drain electrode 27 and a low potential (e.g., ground potential) is applied to the source electrode 25, a current flows from the drain terminal D to the source terminal S. On the other hand, when a potential lower than the threshold voltage is applied to the gate electrode 23, no inversion layer is formed in the channel region and the current is blocked. This allows the vertical MOSFET 1 to switch the current between the source terminal S and the drain terminal D.

[0043] As shown in FIGS. 2B and 3B, the P+ type region 20 has a first region 201 and a second region 202 located on both sides of the first region 201 in the X-axis direction. The second region 202 is located between the first region 201 and the N+ type source region 18 and contacts both the first region 201 and the N+ type source region 18. Of the P+ type region 20, the second region 202 contacts the N+ type source region 18. If the length (i.e., width) of the P+ type region 20 in the X-axis direction is W, the width of the first region 201 is W1, and the width of the second region 202 is W2, then the relationship W=W1+W2×2 holds. W is, for example, 50 nm or more and 500 nm or less. W1 is, for example, 0 nm or more and 498 nm or less. W2 is, for example, 1 nm or more and 25 nm or less.

[0044] Since the P+ type region 20 is sandwiched between the N+ type source regions 18 on both sides, the width W of the P+ type region 20 can also be rephrased as the spacing between the N+ type source regions 18. In other words, the width W can also be rephrased as the spacing between the portions of the N+ type source region 18 that sandwich the P+ type region 20 on both sides.

[0045] In the P+ type region 20, the density of Mg segregation in the second region 202 is lower than the density of Mg segregation in the first region 201. For example, Mg segregation is classified into rod-shaped Mg segregation and non-rod-shaped Mg segregation. Rod-shaped Mg segregation has a length of 30 nm or more in one direction and a Mg concentration of 5×10 20 cm -3 The non-rod-shaped Mg segregation is a type of segregation with a length of less than 30 nm in one direction and a Mg concentration of 5×10 20 cm -3 The density of the rod-shaped acceptor segregation in the second region 202 is 1×10 14 cm -3 and the density of non-rod-shaped acceptor segregation is 1×10 15 cm -3 The density of the rod-shaped acceptor segregation and the density of the non-rod-shaped acceptor segregation in the first region 201 are higher than the respective densities in the second region 202.

[0046] As will be described later, this is achieved by forming the N+ type source region 18 adjacent to the P+ type formation region 20′ beforehand when activating the Mg ions implanted into the P+ type formation region 20′ (see FIG. 4D ). By contacting the N+ type source region 18 with the P+ type formation region 20′, a depletion layer is generated on the side of the P+ type formation region 20′ (the region corresponding to the second region 202), preventing the Fermi level in the depletion layer from approaching the valence band (more preferably, the conduction band). This prevents Mg segregation in the second region 202.

[0047] By suppressing the segregation of Mg, a P+ type with high concentration and small concentration variation is realized. In the P+ type region 20, the depletion layer extends from the N+ type source region 18, so that the segregation of Mg is suppressed in the second region 202 compared to the first region 201, and the Mg concentration is higher. For example, the Mg concentration in the second region 202 is 1×10 19 cm -3 More than 1×10 21 cm -3 The Mg concentration in the first region 201 is lower than the Mg concentration in the second region 202, and is 3×10 18 cm -3 It has dropped to nearby levels.

[0048] Furthermore, the concentration of the donor element (for example, Si) in the N+ type source region 18 is equal to or greater than the Mg concentration in the second region 202. This makes it easier for the depletion layer to spread widely from the N+ type source region 18 toward the second region 202, and makes it easier for the second region 202 with a high Mg concentration to be formed widely.

[0049] The second region 202 has a high Mg concentration and small variations in the Mg concentration, so that good ohmic contact can be achieved between the P+ type region 20 and the source electrode 25.

[0050] 3B, the depth d18 of the N+ type source region 18 from the surface 10a and the depth d20 of the P+ type region 20 from the surface 10a are preferably the same. For example, the depth d18 of the N+ type source region 18 and the depth d20 of the P+ type region 20 are each 1 nm or more and 500 nm or less, e.g., in the range of several nm to several tens of nm. The difference between the depth d18 of the N+ type source region 18 and the depth d20 of the P+ type region 20 is preferably 50 nm or less (|d18-d20|≦50 nm). This is because if the P+ type region 20 is shallower than the N+ type source region 18, the lower part of the P+ type region 20 will be depleted, increasing the connection resistance between the P+ type region 20 and the P-type well region 14. Furthermore, if the P+ type region 20 is deeper than the N+ type source region 18, this deeper portion is separated from the N+ type source region 18, making it difficult for the depletion layer to expand and for Mg in the deeper portion to be activated.

[0051] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 100 according to embodiment 1 of the present invention will be described. Figures 4A to 4F are cross-sectional views showing the manufacturing method for GaN semiconductor device 100 according to embodiment 1 of the present invention in the order of steps. GaN semiconductor device 100 is manufactured using various types of equipment, such as a film formation apparatus, an exposure apparatus, an etching apparatus, an ion implantation apparatus, and a heat treatment apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing equipment.

[0052] First, the manufacturing equipment performs ion implantation to form well region 14 (see FIG. 3A). For example, as shown in FIG. 4A, the manufacturing equipment forms a mask (not shown) on GaN substrate 10, which opens an area above region 14' where well region 14 will be formed (hereinafter referred to as well formation region) and covers the area above the other areas, and then ions of Mg as an acceptor element are implanted into GaN substrate 10 on which this mask has been formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from GaN substrate 10.

[0053] In the ion implantation step for forming the well region 14, the Mg implantation energy (acceleration voltage) is set so that the well region 14 is formed deeper from the surface 10a of the GaN substrate 10 than the N+ type source region 18 and the P+ type region 20 (see FIG. 3A). This ion implantation step may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. In addition, in this ion implantation step, the Mg concentration in the well region 14 is set to 1×10 16 cm -3 3x10 or more 18 cm -3 The dose of Mg is set as follows:

[0054] Next, the manufacturing equipment performs ion implantation to form N+ type source region 18 (see FIG. 3A). For example, the manufacturing equipment forms a mask (not shown) on GaN substrate 10 that opens above a region where N+ type source region 18 is to be formed (hereinafter referred to as source formation region 18') and covers above other regions, and then ions of Si as a donor element are implanted into GaN substrate 10 with this mask formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from GaN substrate 10.

[0055] In the ion implantation step for forming the N+ type source region 18, the implantation energy (acceleration voltage) of Si is set so that the depth d18 (see FIG. 3B) of the N+ type source region 18 is 1 nm or more and 500 nm or less. In this ion implantation step, it is preferable to set the implantation energy (acceleration voltage) of Si so that the depth d18 of the N+ type source region 18 (see FIG. 3B) is the same as the depth d20 of the P+ type region 20.

[0056] In the ion implantation process for forming the N+ type source region 18, the dose of Si is set so that the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the P+ type region 20. For example, when the Si concentration in the N+ type source region 18 is 1×10 19 cm -3 More than 1×10 22 cm-3 The dose of Si is set as follows:

[0057] Next, the manufacturing equipment subjects the GaN substrate 10 to a heat treatment at a maximum temperature of 1200°C or less. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg and Si ions implanted into the GaN substrate 10, and as shown in FIG. 4B, a P-type well region 14 and an N+-type source region 18 are formed in the GaN substrate 10, and the drift region 12 is defined. This heat treatment also allows defects caused by the Mg and Si ion implantation in the GaN substrate 10 to be repaired to some extent. Note that this heat treatment may be performed with a protective film formed on the GaN substrate 10. For example, aluminum nitride (AlN) or silicon nitride (SiN) may be used as the protective film. This protective film is removed after the heat treatment.

[0058] Next, as shown in FIG. 4C, the manufacturing equipment forms a mask 51 on the GaN substrate 10, which opens an area above a region (hereinafter, P+ type formation region) 20′ where the P+ type region 20 (see FIG. 3A) will be formed and covers the other areas. The mask 51 is, for example, a resist pattern. As shown in FIG. 4C, the P+ type formation region 20′ may be set so as to partially overlap the N+ type source region 18. Next, the manufacturing equipment ions implants Mg as an acceptor element into the GaN substrate 10 on which the mask 51 has been formed. After the ion implantation, the manufacturing equipment removes the mask 51 from the GaN substrate 10.

[0059] In the ion implantation step for forming the P+ type region 20, the implantation energy (acceleration voltage) of Mg is set so that the depth d20 (see FIG. 3B) of the P+ type region 20 is 1 nm or more and 500 nm or less. In this ion implantation step, it is preferable to set the implantation energy (acceleration voltage) of Mg so that the depth d20 of the P+ type region 20 is the same as the depth d18 of the N+ type source region 18 (see FIG. 3B).

[0060] In the ion implantation step for forming the P+ type region 20, the dose of Mg is set so that the Mg concentration in the P+ type region 20 is equal to or lower than the Si concentration in the N+ type source region 18. For example, when the Mg concentration in the P+ type region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 The dose of Mg is set as follows:

[0061] 4D, the manufacturing equipment then forms a protective film 53 on the GaN substrate 10. The protective film 53 is, for example, AlN or SiN.

[0062] Next, the manufacturing equipment subjects GaN substrate 10 covered with protective film 53 to a heat treatment at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg ions implanted into GaN substrate 10, and as shown in FIG. 4E, P+ type regions 20 are formed in GaN substrate 10. This heat treatment also allows defects in GaN substrate 10 caused by the Mg ion implantation to be repaired to some extent. After the heat treatment, the manufacturing equipment removes protective film 53 from surface 10a of GaN substrate 10.

[0063] Next, as shown in FIG. 4F, the manufacturing equipment forms a gate insulating film 21 on the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 23 and a source electrode 25. Next, the manufacturing equipment forms an interlayer insulating film (not shown) on the front surface 10a of the GaN substrate 10 so as to cover the gate electrode 23 and the source electrode 25. Next, the manufacturing equipment forms a gate pad 112 (see FIG. 1) electrically connected to the gate electrode 23 and a source pad 114 (see FIG. 1) electrically connected to the source electrode 25. Thereafter, the manufacturing equipment forms a drain electrode 27 on the back surface 10b of the GaN substrate 10. Through these steps, a GaN semiconductor device 100 (see FIG. 3A) including a vertical MOSFET 1 is completed.

[0064] (Fermi level of the depletion layer in GaN) 5 is a band diagram of the contact portion between the N-type GaN and the P-type GaN and its vicinity, showing the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after heat treatment for activating the acceptor element (e.g., Mg) ion-implanted into the P-type GaN. The N-type GaN before and after heat treatment in FIG. 5 corresponds to the N+ type source region 18 of this embodiment. The P-type GaN before heat treatment in FIG. 5 corresponds to the P+ type formation region 20' of this embodiment, and the P-type GaN after heat treatment corresponds to the P+ type region 20 of this embodiment.

[0065] As shown in Figure 5, a depletion layer occurs at the contact point between n-type GaN and p-type GaN. The depletion layer bends the band structure, and the Fermi level Ef of n-type GaN coincides with the Fermi level Ef of p-type GaN. When heat treatment is performed in this state, Mg is activated in p-type GaN, and the Fermi level approaches the valence band, but the band structure is bent in the depletion layer. Therefore, in the region where the depletion layer occurs in p-type GaN, the approach of the Fermi level Ef to the valence band is suppressed compared to regions where the depletion layer does not occur.

[0066] Figure 6 is a band diagram of p-type GaN in the absence of n-type GaN, showing the valence band Ev, conduction band Ec, and Fermi level Ef before and after heat treatment to activate the acceptor element. When there is no n-type GaN in the vicinity, no depletion layer is formed in the p-type GaN, as shown in Figure 6, and no bending of the band structure occurs in the depletion layer. When p-type GaN covered with an insulating film is subjected to heat treatment, the acceptor element (e.g., Mg) ion-implanted into the p-type GaN is activated, and the Fermi level of the p-type GaN approaches the valence band.

[0067] (Suppression of Mg segregation by controlling the Fermi level) FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. This graph shows data calculated using first-principles calculations. The horizontal axis of FIG. 7 represents the Fermi level Ef (eV), and the vertical axis of FIG. 7 represents energy (eV). The solid line (a) in FIG. 7 shows the relationship between the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) and the Fermi level Ef of GaN. The dashed line (b) in FIG. 7 shows the relationship between the energy required to insert Ga into the GaN interstitial space and the Fermi level Ef of GaN.

[0068] In Figure 7, the closer the Fermi level Ef is to 0 (eV) (i.e., the closer the Fermi level Ef is to the valence band and the closer the conductivity type of GaN is to P-type), the higher the formation energy of Mg acceptors. Also, the closer the Fermi level is to 0 (eV), the lower the energy required for Ga to enter the GaN interstitial space.

[0069] 7, it can be seen that the closer the Fermi level of GaN is to the valence band and the closer the conductivity type of GaN is to P-type, the more difficult it is for Mg to be activated and the less likely it is to function as an acceptor. In other words, the closer the Fermi level of GaN is to the conduction band and the closer the conductivity type of GaN is to N-type, the more easily Mg is activated and the more easily it can function as an acceptor.

[0070] In the embodiment of the present invention, a depletion layer is formed on both sides of the P+ type formation region 20' due to contact with the N+ type source region 18, and the Fermi level Ef of the depletion layer is prevented from approaching the valence band Ev. The Fermi level Ef on both sides of the P+ type formation region 20' is controlled so as not to approach the valence band. As a result, Mg is easily activated on both sides of the P+ type formation region 20', making it easier for it to function as an acceptor.

[0071] (depletion layer width) Figure 8 is a graph showing the relationship between the acceptor concentration of p-type GaN and the width of the depletion layer formed in p-type GaN due to contact with n-type GaN. The horizontal axis of Figure 8 is the acceptor concentration (cm-3 ) and the vertical axis of FIG. 8 represents the width (nm) of the depletion layer formed in the P-type GaN.

[0072] As shown in Figure 8, when the acceptor concentration in p-type GaN is 1×10 18 cm -3 More than 1×10 21 cm -3 Below, the donor concentration in N-type GaN is 1×10 19 cm -3 More than 1×10 22 cm -3 In the following cases, the width (depth) of the depletion layer formed in P-type GaN due to contact with N-type GaN is approximately several nm to 60 nm. The higher the donor concentration in N-type GaN, the wider the depletion layer formed in P-type GaN tends to be. Also, the higher the acceptor concentration in P-type GaN, the narrower the depletion layer formed in P-type GaN tends to be.

[0073] For example, the acceptor concentration in p-type GaN is 1×10 19 cm -3 More than 1×10 21 cm -3 Below, the donor concentration in N-type GaN is 1×10 19 cm -3 More than 1×10 22 cm -3 In the following cases, the width (depth) of the depletion layer formed in the P-type GaN due to contact with the N-type GaN is 1 nm or more and 25 nm or less. 19 cm -3 When the donor concentration is 1×10 19 cm -3 More than 1×10 22 cm -3 The width of the depletion layer formed in the P-type GaN due to contact with the N-type GaN below is substantially about 25 nm.

[0074] As shown in FIG. 4D, the P+ type formation region 20′ is sandwiched between the N+ type source regions 18. Therefore, when the acceptor concentration (for example, Mg concentration) of the P+ type formation region 20′ is 1×10 19cm -3 When the substrate is in the pedestal state, a depletion layer of about 25 nm is formed on both sides of the P+ type formation region 20'.

[0075] (Mg, Si profile) 9 is a graph showing an example of Mg and Si profiles in the X-axis direction of GaN, where the horizontal axis represents the X-axis direction and the vertical axis represents the Mg or Si concentration.

[0076] 9, for example, the N+ implanted region corresponds to the source formation region 18' (see FIG. 4A), and the P+ implanted region corresponds to the P+ type formation region 20' (see FIG. 4C). The N+, P+ overlapping region corresponds to the overlapping region between the source formation region 18' and the P+ type formation region 20'. Since the Si implanted into the N+ implanted region has a higher concentration than the Mg implanted into the P+ implanted region, the conductivity type of the overlapping region between the source formation region 18' and the P+ type formation region 20' becomes N type. Also, in FIG. 9, for example, the Mg concentration reduced region corresponds to the first region 201 (see FIG. 3B), and the Mg concentration maintained region corresponds to the second region 202 (see FIG. 3B). The Mg concentration maintained regions are located on both sides of the Mg concentration reduced region.

[0077] The Mg concentration maintaining region is depleted by contact with an activated N+ implantation region (e.g., N+ type source region 18), and the Fermi level Ef is controlled so as not to approach the valence band. As a result, Mg activation is stabilized in the Mg concentration maintaining region, and Mg segregation is suppressed, so that a high Mg concentration is maintained.

[0078] As described above, the width of the Mg concentration maintaining region is 1 nm or more and 25 nm or less, for example, 25 nm. The width of the spacing between the N+ implanted regions (i.e., the P+ regions) is, for example, 50 nm or more and 500 nm or less, preferably 100 nm or less. Narrowing the spacing between the N+ implanted regions increases the area ratio of the Mg concentration maintaining region to the P+ region.

[0079] The Mg concentration reduced region is not depleted because it is far from the N+ implanted region, and the Fermi level Ef approaches the valence band. In the Mg concentration reduced region, Mg activation is less stable than in the Mg concentration maintained region, and Mg segregation is more likely, resulting in a decrease in Mg concentration. For example, in the Mg concentration reduced region, even if Mg ions are implanted at the same concentration as in the Mg concentration maintained region, the Mg concentration after activation will be 3×10 due to Mg precipitation. 18 cm -3 It drops to near

[0080] (Effects of the First Embodiment) As described above, the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of forming the N+ type source region 18 in the GaN substrate 10, ion-implanting an acceptor element (e.g., Mg) into regions of the GaN substrate 10 sandwiched between the N+ type source regions 18, and activating the Mg by heat-treating the GaN substrate 10 in which the N+ type source region 18 has been formed and into which the Mg has been ion-implanted, thereby forming the P+ type region 20 sandwiched between the N+ type source region 18. In the step of forming the N+ type source region 18, Si is ion-implanted into the GaN substrate 10 at a high concentration so that the concentration of the donor element (e.g., Si) in the N+ type source region 18 is equal to or greater than the Mg concentration in the P+ type region 20. In the step of ion-implanting Mg, the Mg concentration in the P+ type region 20 is increased to 1×10 19 cm -3 More than 1×10 21 cm -3 Mg ions are implanted as follows:

[0081] According to this, contact between the N+ type source region 18 and the P+ type formation region 20′ causes depletion layers to form on both sides of the P+ type formation region 20′, and the Fermi levels of these sides coincide with the Fermi level of the N+ type source region 18. Because the N+ type source region 18 is N+ type, the Fermi levels of the depletion layers formed on both sides of the P+ type formation region 20′ can be prevented from approaching the valence band. As a result, the formation energy of Mg acceptors can be maintained low on both sides of the P+ type formation region 20′, making it easier to activate Mg. This prevents Mg segregation due to heat treatment and a decrease in the Mg concentration due to Mg segregation.

[0082] Furthermore, the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the P+ type formation region 20'. As a result, a wide depletion layer is formed on both sides of the P+ type formation region 20', and a wide second region 202 is formed in which a decrease in the Mg concentration due to Mg segregation is suppressed. This allows a high-concentration P+ type region 20 to be realized.

[0083] Furthermore, by joining the source electrode 25 to such a P+ type region 20, a source contact with excellent ohmic properties can be realized.

[0084] A GaN semiconductor device 100 according to a first embodiment of the present invention includes a GaN substrate 10, an N+ type source region 18 provided on the surface 10a side of the GaN substrate 10, and a P+ type region 20 provided on the surface 10a side of the GaN substrate 10 and sandwiched between the N+ type source region 18. The Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the P+ type region 20. The Mg concentration in at least a portion of the P+ type region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 For example, the Mg concentration in the second region 202 of the P+ type region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3The GaN semiconductor device 100 having such a configuration can be manufactured by the manufacturing method described above.

[0085] <Embodiment 2> In the above tenth embodiment, the P+ type region 20 has been described as having a stripe shape extending in the Y-axis direction in plan view. However, in the present invention, the shape of the P+ type region 20 in plan view is not limited to this. The P+ type region 20 may have a portion extending in the X-axis direction.

[0086] Fig. 10 is a plan view showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. Figs. 11A and 11B are cross-sectional views showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. Fig. 11A shows a cross section of the plan view of Fig. 10 taken along line X3-X'3. Fig. 11B shows a cross section of the plan view of Fig. 10 taken along line X4-X'4.

[0087] 10 to 11B, in GaN semiconductor device 100A according to embodiment 2, P+ type region 20 has, in plan view, first portion 20Y extending in the Y-axis direction and second portion 20X extending in the X-axis direction, with first portion 20Y and second portion 20X connected to each other to form a comb-like shape. In plan view, first portion 20Y and second portion 20X are each sandwiched between N+ type source regions 18, and each have first region 201 and second regions 202 located on both sides of first region 201.

[0088] Like the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100A according to the second embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type source region 18. Furthermore, in the GaN semiconductor device 100A, the second region 202 in which Mg segregation is suppressed and a decrease in the Mg concentration is suppressed is formed not only in the first portion 20Y but also in the second portion 20X. This allows the highly concentrated P+ type region 20 to be formed over a wider area.

[0089] <Embodiment 3> In an embodiment of the present invention, P+ type regions 20 may be arranged in a dotted pattern in a plan view. FIG. 12 is a plan view showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. FIGS. 13A and 13B are cross-sectional views showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. FIG. 13A shows a cross section of the plan view of FIG. 12 taken along line X5-X'5. FIG. 13B shows a cross section of the plan view of FIG. 12 taken along line X6-X'6.

[0090] 12 to 13B, in the GaN semiconductor device 100B according to the third embodiment, the P+ type regions 20 are arranged in a dotted pattern in a plan view. The P+ type regions 20 arranged in a dotted pattern are surrounded by the N+ type source regions 18 in all directions in a plan view, and therefore the proportion of the activation range in one P+ type region 20 (i.e., the proportion of the area of the second region 202) can be increased.

[0091] Like the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100B according to the third embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type source region 18. Furthermore, in the GaN semiconductor device 100B, the proportion of the activated range in the P+ type region 20 (i.e., the proportion of the area of the second region 202) can be increased, thereby enabling the P+ type region 20 to be further highly concentrated.

[0092] The dot-shaped P+ type regions 20 may be arranged arbitrarily as long as they are surrounded by the N+ type source regions 18 in a plan view. While Fig. 12 shows the dot-shaped P+ type regions 20 as being square in a plan view, this is merely an example. The dot-shaped P+ type regions 20 may be rectangular or circular in a plan view.

[0093] <Embodiment 4> Fig. 14 is a plan view showing a configuration example of a GaN semiconductor device 100C according to embodiment 4 of the present invention. Fig. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100C according to embodiment 4 of the present invention. Fig. 15 shows a cross section taken along line X7-X'7 in the plan view of Fig. 14.

[0094] As shown in FIGS. 14 and 15 , in a GaN semiconductor device 100C according to the fourth embodiment, two P+ type regions 20 extending in the Y-axis direction are disposed below one source electrode 25. An N+ type region 28 is disposed between the two P+ type regions 20. In the X-axis direction, the N+ type source region 18, the first P+ type region 20, the N+ type region 28, the second P+ type region 20, and the N+ type source region 18 are disposed side by side in this order. Each of the two P+ type regions 20 is sandwiched between the N+ type source region 18 and the N+ type region 28 on both sides. In the fourth embodiment, the N+ type source region 18 and the N+ type region 28 are examples of the “N-type region” of the present invention.

[0095] The concentration of the dopant element (e.g., Si concentration) in the N+ type region 28 may be the same as or different from the concentration of the dopant element (e.g., Si concentration) in the N+ type source region 18, but is equal to or greater than the concentration of the acceptor element (e.g., Mg concentration) in the P+ type region 20. In addition, as shown in Fig. 15, the depth of the N+ type region 28 from the surface 10a is the same as the depth of the P+ type region 20 from the surface 10a.

[0096] Like the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100C according to the fourth embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type source region 18. Furthermore, in the GaN semiconductor device 100C, Mg segregation is suppressed and a decrease in the Mg concentration is suppressed not only in the N+ type source region 18 but also in the second region 202 adjacent to the N+ type region 28. As a result, even when multiple P+ type regions 20 are disposed below the source electrode 25, the second region 202 can be formed on both sides of each of the multiple P+ type regions 20, making it possible to increase the concentration of each of the multiple P+ type regions 20.

[0097] 14 shows an example in which the N+ type source region 18 and the N+ type region 28 are not connected in a planar view, but this is merely an example. In the fourth embodiment of the present invention, the N+ type source region 18 and the N+ type region 28 may be connected in a planar view.

[0098] Furthermore, in the fourth embodiment, an example has been given in which two P+ type regions 20 extending in the Y-axis direction are arranged under one source electrode 25, but this is merely one example. In the fourth embodiment, three or more P+ type regions 20 extending in the Y-axis direction may be arranged under one source electrode 25. In such a case, too, by arranging an N+ type region 28 between one P+ type region 20 and the other P+ type region 20 adjacent to each other in the X-axis direction, it is possible to increase the concentration of each of the three or more P+ type regions 20.

[0099] <Embodiment 5> Fig. 16 is a plan view showing a configuration example of a GaN semiconductor device 100D according to embodiment 5 of the present invention. Figs. 17A and 17B are cross-sectional views showing a configuration example of a GaN semiconductor device 100D according to embodiment 5 of the present invention. Fig. 17A shows a cross section of the plan view of Fig. 16 taken along line X8-X'8. Fig. 17B shows a cross section of the plan view of Fig. 16 taken along line X9-X'9.

[0100] 16, in the GaN semiconductor device 100D according to the fifth embodiment, N+ type regions 28 are scattered throughout the P+ type region 20 in a plan view. As shown in FIGS. 16 to 17B, the P+ type region 20 is sandwiched between N+ type source regions 18 on both sides in the X-axis direction. A portion of the P+ type region 20 is in contact with the N+ type regions 28 scattered throughout the P+ type region 20, and is sandwiched between the N+ type regions 28 (or the N+ type regions 28 and the N+ type source regions 18) on both sides. The distance between the N+ type source regions 18 and the N+ type regions 28 in the X-axis direction is the same as the distance W shown in FIG. 2B, and is, for example, 50 nm or more and 500 nm or less.

[0101] In the fifth embodiment, as in the fourth embodiment, the concentration of the dopant element (e.g., Si concentration) in the N+ type region 28 may be the same as or different from the concentration of the dopant element (e.g., Si concentration) in the N+ type source region 18, but is equal to or greater than the concentration of the acceptor element (e.g., Mg concentration) in the P+ type region 20. Also, as shown in Fig. 16, the depth of the N+ type region 28 from the surface 10a is the same as the depth of the P+ type region 20 from the surface 10a.

[0102] A depletion layer extends from the N+ type region 28 to the P+ type region 20. As a result, in the P+ type region 20, a second region 202 having a higher acceptor concentration (for example, Mg concentration) than the first region 201 is formed not only in a region adjacent to the N+ type source region 18 but also in a region adjacent to the N+ type region 28.

[0103] Like the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100D according to the fifth embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type source region 18. Furthermore, in the GaN semiconductor device 100D, Mg segregation is suppressed and a decrease in the Mg concentration is suppressed not only in the N+ type source region 18 but also in the second region 202 adjacent to the N+ type region 28. As a result, in the GaN semiconductor device 100D, the proportion of the activated area in the P+ type region 20 (i.e., the proportion of the area of the second region 202) can be increased, thereby enabling the P+ type region 20 to be further highly concentrated.

[0104] 16 shows an example in which the N+ type source region 18 and the N+ type region 28 are not connected in plan view, but this is merely an example. In the fifth embodiment of the present invention, the N+ type source region 18 and the N+ type region 28 may also be connected in plan view.

[0105] Furthermore, the dot-shaped N+ type regions 28 may be arranged arbitrarily as long as they are surrounded by the P+ type regions 20 in a plan view. Also, while Figure 12 shows a case where the dot-shaped N+ type regions 28 are square in a plan view, this is merely an example. The dot-shaped N+ type regions 28 may be rectangular or circular in a plan view.

[0106] <Embodiment 6> In the above-described first to fifth embodiments, the vertical MOSFET included in the GaN semiconductor device is a planar type. However, in the embodiments of the present invention, the vertical MOSFET included in the GaN semiconductor device is not limited to a planar type, and may be a trench gate type.

[0107] 18 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100E according to embodiment 6 of the present invention. As shown in Fig. 18, the GaN semiconductor device 100E according to embodiment 6 has a trench H provided in a GaN substrate 10. The trench H opens to the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the P-type well region 14, and the bottom of the trench H reaches the N-type drift region 12.

[0108] A gate insulating film 21 and a gate electrode 23 are disposed inside the trench H. The inner side and bottom surfaces of the trench H are covered with the gate insulating film 21. The gate electrode 23 is buried in the trench H via the gate insulating film 21. In the trench gate structure, the well region 14, which faces the gate electrode 23 via the gate insulating film 21 provided on the side surface of the trench H, becomes the channel region of the vertical MOSFET.

[0109] The GaN semiconductor device 100E according to the sixth embodiment can realize a highly concentrated P+ type region 20, similar to the GaN semiconductor device 100 according to the first embodiment. Furthermore, the vertical MOSFET employs a trench gate structure, which allows the channel regions to be arranged more densely, facilitating miniaturization of the device.

[0110] <Embodiment 7> The present invention may be applied to a diode.

[0111] 19 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200 according to embodiment 7 of the present invention. As shown in FIG. 19, the GaN semiconductor device 200 according to embodiment 7 includes a GaN substrate 10 and one or more PN diodes 2 provided on the GaN substrate 10.

[0112] PN diode 2 includes N-type region 13 provided in GaN substrate 10, P-type region 15 provided in GaN substrate 10 and in contact with N-type region 13, P+-type region 20 provided in GaN substrate 10 and in contact with P-type region 15, N+-type region 28 (an example of an "N-type region" in the present invention) provided in GaN substrate 10 and in contact with P-type region 15 and P+-type region 20, anode electrode 35 (an example of an "electrode" in the present invention) provided on the front surface 10a of GaN substrate 10 and in contact with P+-type region 20 and N+-type region 28, and cathode electrode 37 provided on the back surface 10b of GaN substrate 10 and in contact with N-type region 13. P-type region 15 and P+-type region 20 form the anode region of PN diode 2. N-type region 13 forms the cathode region of PN diode 2.

[0113] The P-type region 15 is formed by ion-implanting an acceptor element into the N-type GaN substrate 10 and then heat-treating the substrate 10. The acceptor element is, for example, Mg.

[0114] The anode electrode 35 and the cathode electrode 37 are made of, for example, Al or an Al-Si alloy. The anode electrode 35 and the cathode electrode 37 may have a barrier metal layer between them and the GaN substrate 10. Ti may be used as the material for the barrier metal layer.

[0115] 19, the P+ type regions 20 and the N+ type regions 28 are arranged alternately in the X-axis direction. As a result, in the P+ type region 20, a depletion layer extends from the N+ type region 28, and a second region 202 having a higher concentration of the acceptor element (for example, Mg concentration) than the first region 201 is formed.

[0116] The GaN semiconductor device 200 according to the seventh embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type region 28. Furthermore, by joining the anode electrode 35 to the highly concentrated P+ type region 20, an anode contact with excellent ohmic properties can be realized between the P+ type region 20 and the anode electrode 35.

[0117] <Embodiment 8> Fig. 20 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200A according to embodiment 8 of the present invention. As shown in Fig. 20, the GaN semiconductor device 200A according to embodiment 7 includes a GaN substrate 10 and an MPS (Merged PiN Schottky) diode 2A provided on the GaN substrate 10. The MPS diode 2A is an element that combines a PN diode and a Schottky diode.

[0118] The MPS diode 2A has an N-type region 13 provided on the GaN substrate 10, a plurality of P-type regions 15 provided on the GaN substrate 10 and in contact with the N-type region 13, a P+ type region 20 provided on the GaN substrate 10 and in contact with the P-type region 15, an N+ type region 28 provided on the GaN substrate 10 and in contact with the P-type region 15 and the P+ type region 20, an anode electrode 35 provided on the front surface 10a side of the GaN substrate 10 and in contact with the N-type region 13, the P-type region 15, the P+ type region 20 and the N+ type region 28, and a cathode electrode 37 provided on the back surface 10b side of the GaN substrate 10 and in contact with the N-type region 13.

[0119] As shown in FIG. 20 , multiple P-type regions 15 are arranged spaced apart from one another. An N-type region 13 is arranged between adjacent P-type regions 15. The connection between the anode electrode 35 and the P+ type region 20, and the connection between the N- type region 13 and the cathode electrode 37 are ohmic connections. The anode electrode 35, the P+ type region 20, the P-type region 15, the N- type region 13, and the cathode electrode 37 form a PN diode. The P-type region 15 and the P+ type region 20 are the anode region of the PN diode. The N- type region 13 is the cathode region of the PN diode.

[0120] The anode electrode 35 and the N-type region 13 are connected by a Schottky junction. The anode electrode 35, the N-type region 13, and the cathode electrode 37 form a Schottky diode.

[0121] The anode electrode 35 and the cathode electrode 37 may be made of the same material or different materials. For example, the anode electrode 35 is made of one of nickel (Ni), platinum (Pt), and palladium (Pd). The cathode electrode 37 is made of Al, an Al-Si alloy, or titanium (Ti).

[0122] 20, in the MPS diode 2A, the P+ type regions 20 and the N+ type regions 28 are also arranged alternately in the X-axis direction. As a result, in the P+ type region 20, a depletion layer extends from the N+ type region 28, and a second region 202 having a higher concentration of the acceptor element (for example, Mg concentration) than the first region 201 is formed.

[0123] Like the GaN semiconductor device 200 according to the seventh embodiment, the GaN semiconductor device 200A according to the eighth embodiment can realize a highly concentrated P+ type region 20 in which Mg segregation is suppressed in the second region 202 adjacent to the N+ type region 28. Furthermore, by joining the anode electrode 35 to the highly concentrated P+ type region 20, an anode contact with excellent ohmic properties can be realized between the P+ type region 20 and the anode electrode 35.

[0124] <Other embodiments> As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0125] For example, in the present invention, the vertical MOSFETs of the GaN semiconductor devices 100A to 100D shown in the second to fifth embodiments may have a trench gate structure as shown in the sixth embodiment, instead of a planar structure.

[0126] Furthermore, the P+ type region 20 may be included in a lateral MOSFET in which a current flows in the horizontal direction of the GaN substrate 10, rather than in a vertical MOSFET in which a current flows in the vertical direction of the GaN substrate 10.

[0127] Furthermore, the gate insulating film 21 is not limited to an SiO2 film, and may be another insulating film. A silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, or an aluminum oxide (Al2O3) film may also be used as the gate insulating film 21. A composite film formed by stacking several single-layer insulating films may also be used as the gate insulating film 21. A vertical MOSFET using an insulating film other than an SiO2 film as the gate insulating film 21 may be called a vertical MISFET. MISFET refers to an insulated gate transistor, which is a more comprehensive term that includes MOSFETs.

[0128] In the above-described first to sixth embodiments, the electrode in contact with the P+ type region 20 is the source electrode 25. In the above-described seventh and eighth embodiments, the electrode in contact with the P+ type region 20 is the anode electrode 35. However, the embodiments of the present invention are not limited to this. The P+ type region 20 may be in contact with an electrode other than a source electrode or an anode electrode. Furthermore, the P-type region exemplified as the P+ type region 20 may be included in an element other than a MISFET or a PN diode, and may be included in, for example, a bipolar transistor, a capacitance element, a resistance element, or the like.

[0129] As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present. [Explanation of symbols]

[0130] 1 Vertical MOSFET 2 PN diodes 2A MPS diode 10 GaN substrate 10a surface 10b back side 12 Drift Region 13 N-type region 14 well area 14´ Well formation area 15 P-type region 18 N+ type source region 18´ Source formation region 20 P+ type region 20´ P+ type formation area 20X 2nd part 20Y 1st part 21 Gate insulating film 23 Gate electrode 25 Source electrode 27 Drain electrode 28 N+ type region 35 Anode electrode 37 Cathode electrode 51 Mask 53 Protective film 100, 100A, 100B, 100C, 100D, 100E, 200, 200A GaN semiconductor devices 110 Active area 112 Gate Pad 114 Saucepad 121 Upper area 122 Lower area 130 Edge Termination Area 201 1st area 202 Second area D Drain terminal Gate terminal S Source terminal

Claims

1. a nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the P-type region; The concentration of the acceptor element in at least a portion of the P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ is as follows: The P-type region is A first region; a second region located between the first region and the N-type region and in contact with the first region and the N-type region, the second region has a higher concentration of the acceptor element than the first region; The concentration of the acceptor element in the second region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The nitride semiconductor device is as follows:

2. 2. The nitride semiconductor device according to claim 1, wherein the distance between the portions of said N-type region that sandwich said P-type region on both sides is not less than 50 nm and not more than 500 nm.

3. 3. The nitride semiconductor device according to claim 1, wherein the depth of said N-type region from said one surface and the depth of said P-type region from said one surface are the same.

4. The nitride semiconductor device according to claim 1 , wherein said nitride semiconductor layer is made of gallium nitride.

5. 5. The nitride semiconductor device according to claim 1, wherein said acceptor element includes at least one of magnesium and beryllium.

6. The nitride semiconductor device according to claim 1 , wherein a density of the acceptor segregation in said second region is lower than a density of the acceptor segregation in said first region.

7. The acceptor segregation is The length in one direction is 30 nm or more, and the concentration of the acceptor element is 5×10 ２０ cm －３ Rod-like acceptor segregation, The length in one direction is less than 30 nm, and the concentration of the acceptor element is 5×10 ２０ cm －３ and non-rod-shaped acceptor segregation, In the second region, the density of the rod-shaped acceptor segregation is 1×10 １４ cm －３ and the density of the non-rod-shaped acceptor segregation is 1×10 １５ cm －３ The nitride semiconductor device according to claim 6 , wherein the n-type impurity concentration is less than 1000 ppm.

8. 8. The nitride semiconductor device according to claim 1, wherein a length of said second region in a direction in which said N-type region sandwiches said P-type region from both sides is not less than 1 nm and not more than 25 nm.

9. The nitride semiconductor device according to claim 1 , further comprising an electrode provided on the P-type region.

10. a P-type well region provided in the nitride semiconductor layer; a field effect transistor provided in the nitride semiconductor layer, the field effect transistor having a channel formed in the well region; The nitride semiconductor device according to claim 1 , wherein said P-type region has a higher concentration of said acceptor element than said well region and is in contact with said well region.

11. a diode provided in the nitride semiconductor layer, The nitride semiconductor device according to claim 1 , wherein said P-type region is included in an anode region of said diode.

12. a nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the P-type region; The concentration of the acceptor element in at least a portion of the P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ is as follows: The P-type region is A first region; a second region located between the first region and the N-type region and in contact with the first region and the N-type region, the second region has a higher concentration of the acceptor element than the first region; a density of the acceptor segregation in the second region being lower than a density of the acceptor segregation in the first region.

13. a nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the P-type region; The P-type region is A first region; a second region located between the first region and the N-type region and in contact with the first region and the N-type region, the second region has a higher concentration of the acceptor element than the first region; a density of the acceptor segregation in the second region being lower than a density of the acceptor segregation in the first region.

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