Semiconductor device manufacturing method

Abstract

To make uniform the thickness of a semiconductor substrate in manufacture of a semiconductor device.SOLUTION: A manufacturing method of a semiconductor device including a semiconductor substrate includes a grinding step of grinding a first surface of the semiconductor substrate to form a peripheral surplus region on the periphery of the semiconductor substrate, and a spin etching step of etching the first surface of the semiconductor substrate with a chemical solution, and in the region of the semiconductor substrate inside the peripheral surplus region, the thickness of the semiconductor substrate at the ends of the region is greater than the thickness of the semiconductor substrate at the central portion of the region.SELECTED DRAWING: Figure 7a

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, in the processing method of semiconductor substrates, a technique has been known in which "only the back surface corresponding to the device region of the wafer is ground and a ring-shaped reinforcing portion is formed on the outer periphery of the back surface corresponding to the peripheral excess region surrounding the device region" (see, for example, Patent Document 1 and Patent Document 2). Patent Document 1: Japanese Patent Application Laid-Open No. 2007-19461 Patent Document 2: Japanese Patent Application Laid-Open No. 2008-60470 Summary of the Invention [Problem to be solved by the invention]

[0003] In the manufacture of semiconductor devices, it is preferable to make the thickness of the semiconductor substrate uniform. [Means for solving the problem]

[0004] In order to solve the above problem, one aspect of the present invention provides a method for manufacturing a semiconductor device including a semiconductor substrate. The method for manufacturing a semiconductor device may include a grinding step. In the grinding step, a first surface of the semiconductor substrate may be ground to form a peripheral excess region on the periphery of the semiconductor substrate. The method for manufacturing a semiconductor device may include a spin etching step. In the spin etching step, the first surface of the semiconductor substrate may be etched with a chemical solution. In a region of the semiconductor substrate inside the peripheral excess region, the thickness of the semiconductor substrate at the edge of the region may be greater than the thickness of the semiconductor substrate at the center of the region.

[0005] After the grinding step, the semiconductor substrate may have a sloped portion in contact with the peripheral excess region, and the sloped portion may have an inclination angle of 1 degree or less.

[0006] The height of the sloped portion may be 20 μm or less The height of the sloped portion may be equal to or less than the thickness of the semiconductor substrate.

[0007] The width of the sloped portion may be 15 mm or more. The width of the sloped portion may be 10% or more of the radius of the semiconductor substrate. The semiconductor substrate may have a diameter of 300 mm or more.

[0008] In the grinding step, the semiconductor substrate may be ground by tilting the rotation axis of the grindstone relative to the radial direction of the semiconductor substrate.

[0009] In the grinding step, the semiconductor substrate may be ground by moving a grindstone from an end of the region to a center of the region. The diameter of the grindstone may be larger than the radius of the region. In the grinding step, the semiconductor substrate may be ground by tilting the grindstone with respect to the circumferential direction of the semiconductor substrate. The diameter of the grindstone may be 110% or more and 130% or less of the radius of the region.

[0010] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0011] [Figure 1] 2A to 2C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100. [Figure 2] 1 is a diagram illustrating an example of a semiconductor device 100. FIG. [Figure 3a] 10A and 10B are diagrams illustrating the semiconductor device 100 during grinding in the grinding step S101. [Figure 3b] 10A and 10B are diagrams illustrating the semiconductor device 100 after grinding in the grinding step S101. [Figure 4a] 10A and 10B are diagrams illustrating the semiconductor device 100 during processing in the spin etching stage S102. [Figure 4b] 10A and 10B are diagrams illustrating the semiconductor device 100 after processing in the spin etching step S102. [Figure 5]FIG. 10 is a diagram showing the amount of etching within the surface of the semiconductor substrate 10 when the semiconductor substrate 10 is rotated at a low speed. [Figure 6] 10 is a diagram showing the thickness of the semiconductor substrate 10 after the grinding step S101 and the spin etching step S102. FIG. [Figure 7a] 10A and 10B are diagrams illustrating the semiconductor device 100 during the grinding step S101 in the embodiment. [Figure 7b] 10A and 10B are diagrams illustrating the semiconductor device 100 after the grinding step S101 in the embodiment. [Figure 8a] 10A and 10B are diagrams illustrating the semiconductor device 100 during processing in the spin etching stage S102. [Figure 8b] 10A and 10B are diagrams illustrating the semiconductor device 100 after processing in the spin etching step S102. [Figure 9a] 10A and 10B are diagrams illustrating a semiconductor device 100 during the grinding step S101 in another example. [Figure 9b] 10A and 10B are diagrams illustrating a semiconductor device 100 during the grinding step S101 in another example. [Figure 9c] 10A and 10B are diagrams illustrating the semiconductor device 100 after the grinding step S101 in another example. [Figure 10] FIG. 9B is a diagram illustrating in detail an area A in FIG. 9C. [Figure 11a] 10A and 10B are diagrams illustrating a semiconductor device 100 during the grinding step S101 in another example. [Figure 11b] 10A and 10B are diagrams illustrating the semiconductor device 100 after the grinding step S101 in another example. [Figure 12] FIG. 10 is a diagram illustrating a forward tilt angle θ5. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0013] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0014] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0015] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0016] 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device 100. The method for manufacturing a semiconductor device 100 includes a grinding step S101 and a spin etching step S102.

[0017] 2 is a diagram illustrating an example of a semiconductor device 100. The semiconductor device 100 functions as a power conversion device such as an inverter, for example. The semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), a combination of these, such as an RC (Reverse Conducting)-IGBT, and a MOS transistor, but is not limited to these examples.

[0018] The semiconductor device 100 includes a semiconductor substrate 10. In this example, the semiconductor substrate 10 is a wafer having a substantially circular shape in a top view. In this specification, processes other than the process of grinding the semiconductor substrate 10 are omitted. The manufacturing method of the semiconductor device 100 may include the processes of implanting impurities into predetermined regions of the semiconductor substrate 10, annealing the semiconductor substrate 10, and forming insulating films, electrodes, wiring, etc. on the surface of the semiconductor substrate 10. These processes form semiconductor elements such as transistors in the semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. The diameter D1 of the semiconductor substrate 10 is often 200±5 mm or 300±5 mm, for example. However, it is not limited to these values. In this example, the diameter D1 of the semiconductor substrate 10 is 300 mm or more. A wafer having a diameter D1 of the semiconductor substrate 10 of 300 mm or more is considered a large-diameter wafer. However, the diameter D1 of the semiconductor substrate 10 may be 200 mm±5 mm.

[0019] The second surface 12 of the semiconductor substrate 10 may be a surface on which a gate structure such as an IGBT or a MOS transistor is formed. The gate structure includes at least one of a gate electrode, a gate insulating film, a source region, an emitter region, and a channel region. In the grinding step S101, the second surface 12 may or may not have a gate structure formed thereon. The second surface 12 of the semiconductor substrate 10 may be a so-called device surface.

[0020] The first surface 11 of the semiconductor substrate 10 may be the surface opposite to the second surface 12 of the semiconductor substrate 10. In this example, the first surface 11 of the semiconductor substrate 10 is the processed surface in the grinding step S101 and the spin etching step S102. For the sake of explanation, a comparative example of the grinding step S101 and a comparative example of the spin etching step S102 will be described first.

[0021] 3a and 3b are diagrams illustrating a comparative example of grinding step S101. Fig. 3a is a diagram illustrating the semiconductor device 100 during grinding in grinding step S101. Fig. 3b is a diagram illustrating the semiconductor device 100 after grinding in grinding step S101.

[0022] In the grinding step S101, the first surface 11 of the semiconductor substrate 10 is ground. In the grinding step S101, the semiconductor substrate 10 is supported on a table 112. In FIG. 3A, the second surface 12 of the semiconductor substrate 10 is supported on the table 112. The table 112 may be a chuck table. A protective tape may be provided between the second surface 12 of the semiconductor substrate 10 and the table 112. By providing the protective tape between the second surface 12 of the semiconductor substrate 10 and the table 112, the second surface 12 of the semiconductor substrate 10 can be protected. The protective tape is often an adhesive tape such as a pressure-sensitive tape or a UV tape. However, other types of protective tape, such as an organic coating film such as a resist, an electrostatically adsorbed sheet, or a support disk coated with an adhesive, can also be used. When a protective tape is provided between the second surface 12 of the semiconductor substrate 10 and the table 112, a protective tape peeling step may be performed after the grinding step S101 or the spin etching step S102.

[0023] In the grinding step S101, the first surface 11 of the semiconductor substrate 10 is ground by a grinding wheel 110. The grinding step S101 is performed using a grinding device such as a back grinder (BG). In addition, in the grinding step S101, the grinding wheel 110 is rotated. The number of rotations per minute of the grinding wheel 110 is, for example, 2000 to 4000 rpm. The grinding wheel 110 may be moved parallel to the Z axis while rotating to perform grinding. The grinding wheel 110 may also move in the radial direction during grinding. In the grinding step S101, the semiconductor substrate 10 may be ground while being rotated.

[0024] 3b, after the grinding step S101 according to the comparative example, the semiconductor substrate 10 is processed to a constant thickness T1. The thickness T1 may be constant even if there is an error of 10% or more. In this specification, the thickness refers to the difference in height between the top surface and the bottom surface in the Z-axis direction. Figure 3b In FIG. 3B, the thickness T1 of the semiconductor substrate 10 is the difference between the height of the first surface 11 and the height of the second surface 12. In this specification, the height refers to the height from a certain reference point. In each figure, the reference point may be the lowest part of each component of the semiconductor device 100 in the Z-axis direction. In FIG. 3B, the reference point is, for example, the second surface 12 of the semiconductor substrate 10.

[0025] In this example, in the grinding step S101, a peripheral surplus region 52 is formed on the outer periphery of the semiconductor substrate 10. That is, in the grinding step S101, the inside of the peripheral surplus region 52 is ground so that the peripheral surplus region 52 remains on the outer periphery of the semiconductor substrate 10. By leaving the peripheral surplus region 52 on the periphery, a ring-shaped reinforcing structure can be left on the semiconductor substrate 10. Therefore, warping of the semiconductor substrate 10 can be suppressed after the grinding step S101. Furthermore, handling of the semiconductor substrate 10 becomes easier in processes after the grinding step S101. The region of the semiconductor substrate 10 inside the peripheral surplus region 52 is referred to as region 54. The shape of the peripheral surplus region 52 will be described in detail with reference to FIG. 10.

[0026] In this example, the thickness of the semiconductor substrate 10 excluding the peripheral surplus region 52 is defined as T1. T1 may be the thickness of the semiconductor substrate 10 in the region 54. Also, in this example, the thickness of the semiconductor substrate 10 in the peripheral surplus region 52 is defined as T2. T2 may be the maximum thickness of the semiconductor substrate 10 in the peripheral surplus region 52. The grinding depth in the grinding step S101 may be the difference between T2 and T1. The grinding depth in the grinding step S101 may be 400 μm or more. Since the strength of the semiconductor substrate 10 increases as T2 increases, it is preferable that T2 be as thick as possible. T1 must be set to a thickness required depending on the withstand voltage of the semiconductor device. Therefore, T1 is, for example, 50 to 300 μm. Also, T2 may be around 700 μm. Therefore, the grinding depth in the grinding step S101 is 400 μm or more.

[0027] 4a and 4b are diagrams illustrating a comparative example of the spin etching step S102. Fig. 4a is a diagram illustrating the semiconductor device 100 during processing in the spin etching step S102. Fig. 4b is a diagram illustrating the semiconductor device 100 after processing in the spin etching step S102.

[0028] In the spin etching step S102, the first surface 11 of the semiconductor substrate 10 is etched with a chemical solution. The chemical solution used in the spin etching step S102 is referred to as chemical solution A. Chemical solution A may be a chemical solution that etches the semiconductor substrate 10. In this example, chemical solution A is a silicon etching solution. The silicon etching solution is, for example, a fluoronitric acid solution or a mixed solution containing fluoronitric acid. The silicon etching solution may be a commercially available chemical solution. In FIG. 4a, an apparatus 120 may dispense chemical solution A onto the first surface 11 of the semiconductor substrate 10. The apparatus 120 may have a nozzle that dispenses chemical solution A.

[0029] It is known that after the grinding step S101, a processing strain layer having a thickness of several micrometers to several tens of micrometers remains on the first surface 11 of the semiconductor substrate 10. The thickness of the processing strain layer depends on the abrasive grain size of the grindstone used in the grinding step S101. Using a rough grindstone with a larger abrasive grain size improves the throughput of the grinding step S101, but the thickness of the processing strain layer increases. This processing strain layer can cause wafer cracking. By performing the spin etching step S102, the processing strain layer can be removed. Therefore, wafer cracking can be suppressed. As shown in FIG. 4b, after the spin etching step S102, the semiconductor substrate 10 is processed to a thickness T3.

[0030] In the spin etching step S102, the semiconductor substrate 10 may be etched with the chemical solution A while being rotated. The number of rotations per minute of the semiconductor substrate 10 is, for example, in the range of 500 rpm or more and 1500 rpm or less. The higher the rotation speed of the semiconductor substrate 10, the better the etching uniformity, but if the rotation speed exceeds 1500 rpm, the wafer is likely to be damaged. The spin etching step S102 may be performed by a single-wafer spin etching method.

[0031] Before the damaged layer is removed, wafer cracking is likely to occur. Therefore, if the semiconductor substrate 10 is rotated at a high speed in the spin etching step S102, wafer cracking is likely to occur. This problem is particularly noticeable in large-diameter wafers having a diameter D1 of 300 mm or more. Therefore, in the case of large-diameter wafers, it is preferable to reduce the rotation speed of the semiconductor substrate 10 in the spin etching step S102.

[0032] FIG. 5 is a diagram showing the etching amount within the surface of the semiconductor substrate 10 when the semiconductor substrate 10 is rotated at a low speed. In FIG. 5, the solid line indicates the results when the semiconductor substrate 10 is rotated at a low speed. The horizontal axis indicates the relative position from the center of the semiconductor substrate 10, and the vertical axis indicates the etching amount at that relative position. In this example, the diameter D1 of the semiconductor substrate 10 is approximately 300 mm. Therefore, the locations at relative positions of 144 mm and -144 mm from the center of the semiconductor substrate 10 are near the outer periphery of the semiconductor substrate 10. The number of rotations per minute of the semiconductor substrate 10 in FIG. 5 is, for example, 500 rpm. As shown in FIG. 5, there is a tendency for the etching amount to be higher on the outer periphery of the semiconductor substrate 10 compared to the center of the semiconductor substrate 10.

[0033] FIG. 6 is a diagram showing the thickness of the semiconductor substrate 10 after the grinding step S101 and the spin etching step S102. The horizontal axis indicates the relative position from the center of the semiconductor substrate 10, and the vertical axis indicates the thickness of the semiconductor substrate 10 at that relative position. In FIG. 6, the number of rotations per minute of the semiconductor substrate 10 is also 500 rpm. The thickness of the semiconductor substrate 10 after the grinding step S101 may be the thickness T1 in FIG. 3b. The thickness of the semiconductor substrate 10 after the spin etching step S102 may be the thickness T3 in FIG. 4b.

[0034] The thickness of the semiconductor substrate 10 becomes thinner on the outer periphery of the semiconductor substrate 10 after the spin etching step S102 compared to after the grinding step S101. This is because, as explained in FIG. 5, when the semiconductor substrate 10 is rotated at a low speed, the amount of etching increases on the outer periphery of the semiconductor substrate 10 compared to the center of the semiconductor substrate 10. This is thought to be because the centrifugal force acting on the chemical solution is weak when rotating at a low speed, and the chemical solution does not pass through the outer periphery excess region 52 and instead remains on the outer periphery of the semiconductor substrate 10. This therefore deteriorates the uniformity within the surface of the semiconductor substrate 10.

[0035] 7a and 7b are diagrams illustrating an example of grinding step S101. Fig. 7a is a diagram illustrating the semiconductor device 100 during grinding step S101 in the example. Fig. 7b is a diagram illustrating the semiconductor device 100 after grinding step S101 in the example.

[0036] In FIG. 7B, the portion of the region 54 including the center in the XY plane is designated as the central portion 14. The ends of the region 54 in the X and Y axes are designated as the end portions 16. In FIG. 7B, in the region 54 of the semiconductor substrate that is located inside the peripheral excess region 52, the thickness of the semiconductor substrate 10 at the end portion 16 of the region 54 is greater than the thickness of the semiconductor substrate 10 at the central portion 14 of the region 54. In this example, the thickness of the semiconductor substrate 10 monotonically decreases from the end portion 16 to the central portion 14 in the region 54. That is, after the grinding step S101, the thickness of the semiconductor substrate 10 on the peripheral side is made thicker than the thickness of the semiconductor substrate 10 on the central side. By processing the semiconductor substrate 10 in this manner in the grinding step S101, the thickness of the semiconductor substrate 10 can be made uniform in the spin etching step S102. Furthermore, the semiconductor substrate 10 can be processed at a low rotation speed in the spin etching step S102, preventing damage to the wafer.

[0037] 7b, the semiconductor substrate 10 may have a sloped portion 56 in the region 54. The sloped portion 56 may be a portion whose height changes in the radial direction of the semiconductor substrate 10. The height of the sloped portion 56 may be determined based on the portion where the first surface 11 of the semiconductor substrate 10 has the smallest thickness. In other words, the height of the sloped portion 56 may be determined based on the height of the first surface 11 of the semiconductor substrate 10 at the center. In this example, the radial direction of the semiconductor substrate 10 is the X-axis direction. The radial direction of the semiconductor substrate 10 may be perpendicular to the circumferential direction of the semiconductor substrate 10. In this example, the height of the sloped portion 56 decreases toward the center of the semiconductor substrate 10. The sloped portion 56 may be in contact with the peripheral excess region 52. By forming the sloped portion 56, the thickness of the semiconductor substrate 10 at the end 16 of the region 54 can be made thicker than the thickness of the semiconductor substrate 10 at the central portion 14 of the region 54. In this example, the region 54 has only the sloped portion 56. In other words, the entire region 54 may be the slope portion 56 .

[0038] To form the sloped portion 56, in FIG. 7A, the semiconductor substrate 10 is ground by tilting the rotation axis of the grindstone 110 with respect to the radial direction of the semiconductor substrate 10. In the example of FIG. 7A, the lower surface of the grindstone 110 is disposed so as to be tilted in the X-axis direction. That is, the rotation axis of the grindstone 110 is tilted with respect to a direction (X-axis direction) perpendicular to the direction (Y-axis direction) in which the rotation axis of the grindstone 110 is tilted forward. The direction (Y-axis direction) in which the rotation axis of the grindstone 110 is tilted forward will be described later with reference to FIG. 12. In FIG. 7A, the rotation axis of the grindstone 110 is tilted at an angle θ1 with respect to the Z-axis direction. By grinding the semiconductor substrate 10 with the rotation axis of the grindstone 110 tilted with respect to the radial direction of the semiconductor substrate 10, the sloped portion 56 can be formed.

[0039] The diameter D3 of the grindstone 110 may be larger than the radius of the region 54 (half the diameter D4 of the region 54). However, if the diameter D3 is too large compared to the radius of the region 54, a concentric depression will be formed around the center of the region 54. By setting the diameter D3 to approximately 110% or less of the radius of the region 54, the amount of depression can be kept to approximately 1 / 10 of the height H5, so that no problems arise with the device characteristics, etc. Therefore, it is preferable that the diameter D3 be greater than the radius of the region 54 and less than approximately 110% of the radius.

[0040] In FIG. 7B, the inclination angle of the slope portion 56 is θ2. The inclination angle θ2 of the slope portion 56 is the inclination angle with respect to the radial direction of the semiconductor substrate 10. To determine the inclination angle θ2, for example, the distribution of the etching amount in the diameter direction, as shown in FIG. 5, may be used as a reference. According to FIG. 5, the etching amount tends to increase in the region from the outer periphery of the semiconductor substrate 10 to approximately 30 mm, and the increase in the etching amount is particularly large in the region from the outer periphery of the semiconductor substrate 10 to approximately 15 mm. Although specific numerical values are not shown in FIG. 5, the difference between the maximum and minimum etching amounts is 50 μm or less. Therefore, the inclination angle θ2 of the slope portion 56 may be 1 degree or less. The inclination angle θ2 of the slope portion 56 may be 0.1 degrees or less. By setting the inclination angle θ2 of the slope portion 56 to 1 degree or less, the slope portion 56 can be formed over a wide range of the region 54.

[0041] The height of the slope portion 56 is defined as H5. The height H5 of the slope portion 56 may be the maximum height of the slope portion 56. The height H5 of the slope portion 56 may be the height of the portion of the slope portion 56 that contacts the peripheral excess region 52. The height H5 of the slope portion 56 may be determined from the difference between the maximum and minimum etching amounts in FIG. 5. Although the difference between the maximum and minimum etching amounts is described as being 50 μm or less, the inventors of the present application have found that it can be adjusted to 20 μm or less by adjusting the etching apparatus. Therefore, the height H5 of the slope portion 56 may be 50 μm or less. The height H5 of the slope portion 56 may be 20 μm or less. The height H5 of the slope portion 56 may be equal to or less than the thickness of the semiconductor substrate 10. For example, the height H5 of the slope portion 56 is equal to or less than the thickness T2 of the semiconductor substrate 10 in the peripheral excess region 52.

[0042] The width of the slope portion 56 is defined as D5. In FIG. 7b, the width D5 of the slope portion 56 is the radial width of the slope portion 56 in the circumferential direction of the semiconductor substrate 10. The width D5 of the slope portion 56 may be 15 mm or more. The width D5 of the slope portion 56 may be 20 mm or more. The width D5 of the slope portion 56 may be 30 mm or more. The width D5 of the slope portion 56 may be 100 mm or more. The width D5 of the slope portion 56 may be 10% or more of the radius of the semiconductor substrate 10 (half the diameter D1 of the semiconductor substrate 10). By setting the height H5 and the width D5 of the slope portion 56 to these values, the inclination angle of the slope portion 56 can be 1 degree or less.

[0043] 8a and 8b are diagrams illustrating an example of spin etching step S102. FIG. 8a is a diagram illustrating semiconductor device 100 during processing in spin etching step S102. FIG. 8b is a diagram illustrating semiconductor device 100 after processing in spin etching step S102. Note that the spin etching process in FIG. 8a may be the same as the spin etching process in FIG. 4a.

[0044] 8b, since the thickness of the semiconductor substrate 10 on the outer periphery side is made thicker than the thickness of the semiconductor substrate 10 on the center side in the grinding step S101, the thickness T3 of the semiconductor substrate 10 can be made uniform in the spin etching step S102. Furthermore, the semiconductor substrate 10 can be processed at a low rotation speed in the spin etching step S102, which prevents damage to the wafer.

[0045] 9a, 9b, and 9c are diagrams illustrating another example of grinding step S101. Fig. 9a shows the state when grinding of the semiconductor substrate 10 starts. Fig. 9b shows the state when grinding of the semiconductor substrate 10 is completed. Fig. 9c is a diagram illustrating the semiconductor device 100 after grinding step S101.

[0046] 9a and 9b, in the grinding step S101, the semiconductor substrate 10 is ground while the grindstone 110 is moved from the end 16 of the region 54 toward the central portion 14 of the region 54. In this example, the grindstone 110 is moved toward the center of the semiconductor substrate 10 in the circumferential direction of the semiconductor substrate 10. By moving the grindstone 110 to grind the semiconductor substrate 10, a slope portion 56 can be formed in the semiconductor substrate 10.

[0047] In this example, the position of the grinding wheel 110 is lowered as it moves toward the center. The height H2 of the grinding wheel 110 from the table 112 in Fig. 9b is lower than the height H1 of the grinding wheel 110 from the table 112 in Fig. 9a. By moving the grinding wheel 110 in this manner, the slope portion 56 can be easily formed.

[0048] Furthermore, the diameter D3 of the grinding wheel 110 needs to be equal to or greater than the radius of the region 54 (half the diameter D4 of the region 54), but if it is too large, the formation of grinding marks becomes a problem, so it is preferable to make it less than about 110% of the radius of the region 54. As an example, the diameter D3 of the grinding wheel 110 may be equal to or greater than 100% and less than 110% of the radius of the region 54.

[0049] 9c, the region 54 may have a flat portion 58 in addition to the slope portion 56. The flat portion 58 may be a region where the thickness T4 of the semiconductor substrate 10 is constant. The flat portion 58 may be surrounded by the slope portion 56. The thickness T4 of the semiconductor substrate 10 in the flat portion 58 may be the thickness of the semiconductor substrate 10 in the central portion 14.

[0050] 7b, the inclination angle θ2 of the slope portion 56 may be 1 degree or less. Similarly to FIG. 7b, the height H5 of the slope portion 56 may be 20 μm or less. Similarly to FIG. 7b, the width D5 of the slope portion 56 may be 15 mm or more.

[0051] FIG. 10 is a diagram illustrating region A in FIG. 9c in detail. In FIG. 9c, region A is the region surrounded by a dashed line. In FIG. 10, the semiconductor substrate 10 has a peripheral surplus region 52, a sloped portion 56, and a flat portion 58. FIG. 10 illustrates the peripheral surplus region 52, which was omitted in FIG. 9c, in detail. The peripheral surplus region 52 in FIG. 7b and FIG. 11b, which will be described later, may have the same structure as that in FIG. 10. Note that FIG. 10 illustrates an example in which grinding step S101 is performed using a two-axis grinding machine. If grinding step S101 is performed using a different type of grinding machine, the resulting shape will not be the same. A two-axis grinding machine may be a machine equipped with two rotation axes for grinding wheels 110. In grinding step S101, grinding may be performed first using a rotation axis equipped with a coarse grinding wheel 110 having a large abrasive grain size, followed by grinding using a rotation axis equipped with a grinding wheel 110 having a small abrasive grain size. Using a grinding wheel with a large abrasive grain size improves the throughput of the grinding step S101, but increases the thickness of the processing strain layer. Using a grinding wheel 110 with a small abrasive grain size reduces the throughput of the grinding step S101, but reduces the thickness of the processing strain layer. In this example, the shape of the outer circumferential surplus region 52 will be described in detail. The outer circumferential surplus region 52 in FIG. 7b may have a similar shape. Note that the shape and dimensions of the semiconductor substrate 10 in FIG. 10 do not necessarily match the shape and dimensions of the semiconductor substrate 10 in FIG. 9c.

[0052] The outer circumferential surplus region 52 may have a sloped portion 64. In this example, the outer circumferential surplus region 52 may have a first portion 62, a sloped portion 64, and a second portion 66. The first portion 62 and the second portion 66 may be portions with a constant thickness in the radial direction of the semiconductor substrate 10. The sloped portion 64 may be a portion with a varying thickness in the radial direction of the semiconductor substrate 10. In this example, the radial direction is the X-axis direction.

[0053] The width of the first portion 62 is defined as D6. In FIG. 10, the width D6 of the first portion 62 is the radial width of the first portion 62 in the circumferential direction of the semiconductor substrate 10. The width D6 of the first portion 62 may be 1 mm or more and 5 mm or less. The thickness of the semiconductor substrate 10 in the first portion 62 may be defined as the thickness T2 of the semiconductor substrate 10 in the outer circumferential excess region 52. The thickness T2 may be, for example, 700 μm or more and 800 μm or less.

[0054] In FIG. 10 , the inclination angle of the slope portion 64 is θ3. The inclination angle θ3 of the slope portion 64 may be 30 degrees or greater. The inclination angle θ3 of the slope portion 64 may be 45 degrees or less. In other words, the inclination angle θ3 of the slope portion 64 of the outer circumferential surplus region 52 may be greater than the inclination angle θ2 of the slope portion 56 of the region 54. The inclination angle θ3 of the slope portion 64 of the outer circumferential surplus region 52 may be 30 times or greater than the inclination angle θ2 of the slope portion 56 of the region 54. Therefore, the slope portion 64 of the outer circumferential surplus region 52 and the slope portion 56 of the region 54 can be distinguished. Note that the inclination angle θ3 of the slope portion 64 of the outer circumferential surplus region 52 is not limited to an example of 30 degrees or greater and 45 degrees or less. The inclination angle θ3 of the slope portion 64 of the outer circumferential surplus region 52 may be 80 degrees or greater. In other words, the slope portion 64 of the outer peripheral excess region 52 may be approximately perpendicular to the second portion 66.

[0055] The width of the second portion 66 is defined as D7. In Fig. 10, the width D7 of the second portion 66 is the radial width of the second portion 66 in the circumferential direction of the semiconductor substrate 10. The width D7 of the second portion 66 may be 0.1 mm or more and 1.0 mm or less.

[0056] The thickness of the semiconductor substrate 10 in the second portion 66 is defined as T6. The difference between the thickness T6 of the semiconductor substrate 10 in the second portion 66 and the thickness T4 of the semiconductor substrate 10 in the flat portion 58 is defined as thickness T7. Thickness T7 may be 30 μm or more. Thickness T7 may be 80 μm or less. Note that the thickness T4 of the semiconductor substrate 10 in the flat portion 58 may be 60 μm or more. The thickness T4 of the semiconductor substrate 10 in the flat portion 58 may be 350 μm or less.

[0057] 11a and 11b are diagrams illustrating another example of the grinding step S101. Fig. 11a shows a state when grinding of the semiconductor substrate 10 starts. Fig. 11b is a diagram illustrating the semiconductor device 100 after the grinding step S101.

[0058] In this example, the rotation axis of the grindstone 110 is tilted forward in the state shown in FIG. 11a, and the first surface 11 is ground. Tilting the rotation axis of the grindstone 110 forward means tilting the lower surface of the grindstone 110 with respect to the circumferential direction of the semiconductor substrate 10. In this example, the circumferential direction of the semiconductor substrate 10 is the Y-axis direction. The lower surface of the grindstone 110 in this example is tilted in the YZ plane. In this example, the lower surface of the grindstone 110 is disposed so as to have an inclination (forward inclination angle) with respect to the Y-axis direction. The forward inclination angle will be described later with reference to FIG. 12. By grinding the first surface 11 with the rotation axis of the grindstone 110 tilted forward, a sloped portion that contacts the outer circumferential excess region 52 can be formed in the semiconductor substrate 10.

[0059] In FIG. 11b, a portion of the region 54 including the center in the XY plane is defined as a central portion 14. The end portions of the region 54 in the X-axis and Y-axis are defined as end portions 16. In this example, in the XZ plane of the region 54 passing through the central portion 14, the first surface 11 may have a downwardly convex parabolic shape between the central portion 14 and the end portion 16. In this example, the thickness of the semiconductor substrate 10 at the central portion 14 is defined as T10. The thickness of the semiconductor substrate 10 at the end portion 16 is defined as T11. The thinnest portion of the semiconductor substrate 10 between the central portion 14 and the end portion 16 is defined as a thin portion 15, and the thickness of the semiconductor substrate 10 at the thin portion 15 is defined as T12. The portion of the first surface 11 between the end portion 16 and the thin portion 15 is defined as a slope portion 68, and the height of the slope portion 68 is defined as H11. The thickness of the semiconductor substrate 10 monotonically decreases from the end portion 16 to the thin portion 15. That is, the height H11 of the slope portion 68 may be the height at the end portion 16. The height H11 may be the difference between the thickness T11 and the thickness T12. Furthermore, the first surface 11 between the central portion 14 and the thin portion 15 is defined as a slope portion 69, and the height of the slope portion 69 is defined as H10. The thickness of the semiconductor substrate 10 decreases monotonically from the central portion 14 to the thin portion 15. In other words, the height H10 of the slope portion 69 may be the height at the central portion 14. The height H10 of the slope portion 69 may be the difference between the thickness T10 and the thickness T12. The slope portions 68 and 69 may be portions whose height changes in the radial direction of the semiconductor substrate 10.

[0060] In FIG. 11b, the inclination angle of the slope portion 68 is θ4. The inclination angle θ4 of the slope portion 68 may be the angle with respect to a reference plane when a straight line connects the thin portion 15 and the end portion 16. The reference plane is, for example, a plane parallel to the second surface 12 of the semiconductor substrate 10. Furthermore, the width of the slope portion 68 is D8. The width D8 of the slope portion 68 may be the width between the end portion 16 and the thin portion 15.

[0061] In this example, as shown in FIG. 11b, the central portion 14 becomes convex. However, through the inventor's experiments, it was found that by making the diameter D3 of the grinding stone 110 larger than the radius of the region 54 (half of the diameter D4 of the region 54), it is possible to make the height H10 smaller than the height H11. As an example, by making the diameter D3 of the grinding stone 110 110% or more of the radius of the region 54, H10 could be made about 20% or less of H11. That is, by making the diameter D3 of the grinding stone 110 110% or more of the radius of the region 54, T10 and T11 are larger than T12, and T10 is smaller than T11, such that T12 < It was found that T10 < T11 can be achieved.

[0062] Also, it was found that if the diameter D3 is made too large compared to the radius of the region 54, deep grinding marks on the grinding surface will increase. As an example, in this example, by making the diameter D3 of the grinding stone 110 130% or less of the radius of the region 54, it was possible to suppress an increase in deep grinding marks on the grinding surface in the grinding stage S101. That is, by making the diameter D3 of the grinding stone 110 between 110% and 130% of the radius of the region 54 (half of the diameter D4 of the region 54), while suppressing an increase in deep grinding marks on the grinding surface, a slope portion 68 with a desired height can be formed, and the height of the slope portion 69 can be made smaller than the height of the slope portion 68. Then, by processing the semiconductor substrate 10 in this way in the grinding stage S101, the thickness of the semiconductor substrate 10 can be made uniform in the spin etching stage S102. Also, in the spin etching stage S102, the semiconductor substrate 10 can be processed at a low rotation speed, preventing breakage of the wafer.

[0063] Also, similar to FIG. 7b, the inclination angle θ4 of the slope portion 68 may be 1 degree or less. Similar to FIG. 7b, the height H11 of the slope portion 68 may be 20 μm or less. Similar to FIG. 7b, the width D8 of the slope portion 68 may be 15 mm or more.

[0064] Fig. 12 is a diagram illustrating the forward tilt angle θ5. Fig. 12 shows the grinding stage S101 in the YZ plane. The lower surface of the grindstone 110 is disposed so as to have a forward tilt angle θ5 with respect to the Y-axis direction.

[0065] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0066] 10 semiconductor substrate, 11 first surface, 12 second surface, 14 central portion, 15 thin portion, 16 edge portion, 52 peripheral excess region, 54 region, 56 slope portion, 58 flat portion, 62 first portion, 64 slope portion, 66 second portion, 68 slope portion, 69 slope portion, 100 semiconductor device, 110 grinding wheel, 112 table, 120 apparatus

Claims

1. A method for manufacturing a semiconductor device including a semiconductor substrate, a grinding step of grinding a first surface of the semiconductor substrate to form a peripheral excess region on an outer periphery of the semiconductor substrate; a spin etching step of etching the first surface of the semiconductor substrate with a chemical solution; Equipped with After the grinding step, in a region of the semiconductor substrate that is more inward than the outer peripheral excess region, a thickness of the semiconductor substrate at an end of the region is greater than a thickness of the semiconductor substrate at a center of the region; After the grinding step, the semiconductor substrate has a slope portion in the region that contacts the outer peripheral excess region, the height of the sloped portion is maximum at a position where the sloped portion contacts the peripheral surplus region, and decreases from the position where the sloped portion contacts the peripheral surplus region toward the center of the semiconductor substrate; The peripheral excess region is provided so as to protrude higher than the maximum height of the slope portion from a position where it contacts the slope portion to the peripheral edge of the semiconductor substrate. A method for manufacturing a semiconductor device.

2. A method for manufacturing a semiconductor device including a semiconductor substrate, a grinding step of grinding a first surface of the semiconductor substrate to form an outer periphery excess region on an outer periphery of the semiconductor substrate; a spin etching step of etching the first surface of the semiconductor substrate with a chemical solution; Equipped with After the grinding step, in a region of the semiconductor substrate that is more inward than the outer peripheral excess region, a thickness of the semiconductor substrate at an end of the region is greater than a thickness of the semiconductor substrate at a center of the region; After the grinding step, the semiconductor substrate has a slope portion in the region that is provided from a position in contact with the peripheral excess region to the center of the region, The height of the sloped portion is maximum at a position where the sloped portion contacts the peripheral surplus region, and decreases from the position where the sloped portion contacts the peripheral surplus region toward the center of the semiconductor substrate. A method for manufacturing a semiconductor device.

3. The slope angle is 1 degree or less.

3. The method for manufacturing a semiconductor device according to claim 1.

4. The height of the slope portion is 20 μm or less. The method for manufacturing a semiconductor device according to claim 1 .

5. The height of the sloped portion is equal to or less than the thickness of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1 .

6. The width of the slope portion is 15 mm or more. The method for manufacturing a semiconductor device according to claim 1 .

7. The width of the slope portion is 10% or more of the radius of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1 .

8. The semiconductor substrate has a diameter of 300 mm or more. The method for manufacturing a semiconductor device according to claim 1 .

9. In the grinding step, the semiconductor substrate is ground by tilting a grindstone with respect to a radial direction of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1 .

10. In the grinding step, the semiconductor substrate is ground by moving a grindstone from the end portion of the region to the center portion of the region. The method for manufacturing a semiconductor device according to claim 1 .

11. The diameter of the grinding wheel is greater than the radius of the region. The method for manufacturing a semiconductor device according to claim 9 or 10.

12. In the grinding step, the semiconductor substrate is ground by tilting a grindstone with respect to a circumferential direction of the semiconductor substrate; The diameter of the grinding wheel is 110% or more and 130% or less of the radius of the region. The method for manufacturing a semiconductor device according to claim 1 .

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