Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving ON resistance characteristics.SOLUTION: A semiconductor device comprises: a first semiconductor layer 2 of a first conductivity type; a second semiconductor layer 6 of the first conductivity type; a fifth semiconductor region 15 of the first conductivity type selectively provided in the second semiconductor layer 6, having an impurity concentration lower than that of the second semiconductor layer 6; a first semiconductor region 3 of a second conductivity type; a second semiconductor region 4 of the first conductivity type; a trench 5; a gate insulating film 7; a gate electrode 8; a third semiconductor region 9 of the second conductivity type; a fourth semiconductor region 1 of the second conductivity type; a first electrode 10; and a second electrode 11. For the fifth semiconductor region 15, one surface is in contact with the first semiconductor region 3, and the other surface is in contact with the third semiconductor region 9, and one lateral face is in contact with the gate insulating film 7.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, as a semiconductor device (hereinafter referred to as MOS type semiconductor device) with a MOS gate (insulated gate made of metal-oxide-semiconductor) structure used in a power device, a device having a trench gate structure in which a MOS gate is embedded in a trench formed in a semiconductor substrate is well known. In a MOS type semiconductor device with this trench gate structure, there is generally a trade-off between high breakdown voltage and low on-resistance. As a MOS type semiconductor device that improves this trade-off, a device has been proposed that includes a floating region of a conductivity type different from that of the drift layer, which is provided so as to surround the bottom (drain side end) of the trench in which the MOS gate is embedded (see, for example, Patent Document 1 below).

[0003] The structure of a conventional MOS type semiconductor device will be described. FIG. 9 is a cross-sectional view showing the structure of a main part of a conventional semiconductor device. FIG. 9 shows the structure of a unit cell (functional unit of an element) arranged in an active region through which current flows when in an on-state. FIG. 9 corresponds to FIG. 1 of Patent Document 1 listed below. As shown in FIG. 9, a conventional semiconductor device 100 has n - The first main surface of the drift layer 102 is provided with a MOS gate structure, and the second main surface is provided with an n + The MOS gate structure has a p - Type base region 103, n + The n-type source region 104, the trench 105, the deposited insulating layer 106, the gate insulating film 107, and the gate electrode 108. + The source region 104 is p - It is selectively provided inside the mold base region 103 .

[0004] The trench 105 has a depth of n + type source region 104 and p - through the n-type base region 103 -The deposited insulating layer 106 is embedded in the trench 105 on the drain side. The gate electrode 108 is provided on the source side of the deposited insulating layer 106 inside the trench 105. The gate electrode 108 is connected to the p-type drift layer 102 with a gate insulating film 107 provided on the side wall of the trench 105 in between. - type base region 103 and n + Opposite to the n-type source region 104. - A floating p-type diffusion region (hereinafter referred to as a p-type buried region) 109 is provided inside the drift layer 102. The bottom of the trench 105 is located inside the p-type buried region 109. Reference numerals 110 and 111 denote a source electrode and a drain electrode, respectively.

[0005] The conventional semiconductor device 100 has n - By providing a structure (hereinafter referred to as a floating structure) with a floating p-type buried region 109 inside the n-type drift layer 102, the following characteristics are obtained: - The inside of the p-type drift layer 102 - type base region 103 and n - A depletion layer (not shown) spreads from the pn junction 121 between the p-type drift layer 102 and the p-type buried region 109. When this depletion layer reaches the p-type buried region 109, the p-type buried region 109 is punched through, and the p - type base region 103 and n - The potential from the pn junction 121 between the n-type drift layer 102 and the p-type buried region 109 is fixed. - The p-type drift layer 102 includes a p-type buried region 109 and an n-type buried region 109. - A depletion layer (not shown) also spreads from the pn junction 122 between the drift layer 102 and the semiconductor layer 104 .

[0006] In this way p - type base region 103 and n - A depletion layer spreads from the pn junction 121 between the p-type buried region 109 and the n-type drift layer 102, and the electric field intensity peaks near the pn junction 121. -A depletion layer spreads from the pn junction 122 between the n-type drift layer 102 and the n-type drift layer 104, and a peak of the electric field strength is also formed near the pn junction 122. In other words, the peak of the electric field strength can be distributed to two locations. This reduces the maximum peak value of the electric field strength, and increases the breakdown voltage. Furthermore, since a high breakdown voltage can be ensured, - A low on-resistance can be achieved by increasing the impurity concentration in the type drift layer 102. Regarding the mechanism of such a floating structure, calculation results of the electric field strength distribution are disclosed in detail (see, for example, Patent Document 2 below).

[0007] For example, in a typical MOS semiconductor device used in an inverter circuit or the like, the drain voltage Vd is generally changed by controlling the on / off state of the semiconductor device using the gate voltage Vg. FIG. 10 is a characteristic diagram showing the voltage waveform of a conventional semiconductor device. Specifically, as shown in FIG. 10, in the on state (hereinafter referred to as the first state A) where a gate voltage Vg equal to or higher than the threshold voltage is applied, n - Since the depletion layer does not extend to the n-type drift layer, the drain voltage Vd is low and the device operates in a low on-resistance state. On the other hand, while the off state is maintained without applying the gate voltage Vg (hereinafter referred to as the second state B), - The depletion layer expands in the n-type drift layer (high on-resistance state), and the drain voltage Vd is maintained at a high level. In other words, the depletion layer expands to maintain the drain-source breakdown voltage. Then, by transitioning from the off state to the on state again (hereinafter referred to as the third state C), the width of the depletion layer that expanded in the second state B narrows, and the device again operates in a low on-resistance state. Thereafter, the second state B and the third state C are alternately repeated. In this way, in a normal MOS semiconductor device (a MOS semiconductor device that does not have a floating structure), in the second state B, - p inside the drift layer - Type base region and n - The depletion layer spreads from the pn junction between the ion-type drift layer and the p - Type base region and n -The width of the depletion layer extending from the pn junction with the type drift layer is p - Type base area to n - The supply of holes to the drift layer causes instantaneous narrowing.

[0008] However, in the conventional semiconductor device 100 with a floating structure shown in FIG. 9, it is difficult to return from a high on-resistance state to a low on-resistance state in the third state C compared to a normal MOS type semiconductor device. The reason for this is as follows. In the conventional semiconductor device 100, in the second state B, - type base region 103 and n - a pn junction 121 between the p-type buried region 109 and the n-type drift layer 102; - In the third state C, the depletion layer spreads from the pn junction 122 connected to the source electrode 110. - Although holes are supplied to the base region 103 from the outside, because the p-type buried region 109 is in a floating state, no holes are supplied to the p-type buried region 109 from the outside. Therefore, in the third state C, the supply of holes from the p-type buried region 109 itself is not enough to quickly narrow the depletion layer that has expanded toward the drain side of the p-type buried region 109. That is, the amount of holes required to narrow the depletion layer in the third state C is insufficient, and it takes time for the depletion layer that has expanded to the drain side of the p-type buried region 109 to narrow again. As a result, as shown by the dotted line in Figure 10, in the third state C, the drain voltage Vd gradually decreases and reaches its minimum value. Therefore, the device does not immediately return to a low on-resistance state, adversely affecting the transient on-resistance characteristics. In particular, when the chip size is large, the amount of holes required to narrow the depletion layer in the third state C increases, resulting in a delay in the hole supply. Generally, the chip size at which the on-resistance characteristics are adversely affected is several mm square or larger.

[0009] As another device of the conventional floating structure, a device is provided along the gate insulating film provided on the side wall of the trench and p - The p-type base region is connected to the floating p-type diffusion region (p-type buried region), and serves as a hole supply path to the floating p-type diffusion region when the transistor is on. -- An apparatus equipped with a mold diffusion region has been proposed (see, for example, Patent Document 3 listed below).

[0010] The structure shown in Patent Document 3 below will be described. FIG. 11 is a cross-sectional view showing the structure of another example of a conventional semiconductor device. FIG. 11 shows a cross-sectional structure of a gate electrode 108 embedded in a trench 105 having a linear planar shape, cut parallel to the longitudinal direction of the trench 105. FIG. 11 corresponds to FIG. 4 of Patent Document 3 below. A conventional semiconductor device 200 shown in FIG. 11 differs from the conventional semiconductor device 100 shown in FIG. 9 in that n - The inside of the p-type drift layer 102 -- The point is that the mold diffusion region 112 is provided. -- The p-type diffusion region 112 is provided along a portion of the sidewall of the trench 105 in the deposited insulating layer 106. - The p-type base region 103 and the p-type buried region 109 are connected.

[0011] p -- The n-type diffusion region 112 has a very low impurity concentration. - The depletion layer extending from the pn junction between the p-type buried region 109 and the p-type drift layer 102 creates an ultra-high resistance region. Therefore, in the off state, the p-type buried region 109 is in a floating state similar to the conventional semiconductor device 100 shown in FIG. 9 (Patent Documents 1 and 2 listed below). Therefore, similar to the floating structure described above, the drain-source breakdown voltage is maintained, and a high breakdown voltage can be achieved. On the other hand, in the on state, the p -- The p-type buried region 109 is fixed to the source potential by the p-type diffusion region 112, so that n - Holes are supplied to the type drift layer 102. Therefore, the amount of holes supplied in the on state can be increased.

[0012] In FIG. 11, reference numerals 115 to 119 respectively denote the trench, deposited insulating layer, gate insulating film, gate electrode, and p-type buried region of the termination structure 202. The trench 115, deposited insulating layer 116, gate insulating film 117, gate electrode 118, and p-type buried region 119 of the termination structure 202 have the same structures as the trench 105, deposited insulating layer 106, gate insulating film 107, gate electrode 108, and p-type buried region 109 of the active region 201. The gate electrode 118 is provided in the trench 115 closest to the active region 201, and the remaining trenches 115 are filled with the deposited insulating layer 116. The termination structure 202 surrounds the active region 201 and has n - This is a region that relaxes the electric field on the first main surface side of the type drift layer 102 and maintains the breakdown voltage. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-142243 [Patent Document 2] Japanese Patent Application Publication No. 9-191109 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-242852 Summary of the Invention [Problem to be solved by the invention]

[0014] However, although Patent Documents 1 and 2 can reduce the electric field strength near the bottom of trench 105, they do not describe preventing extraction of minority carriers (holes) in the on-state. Furthermore, even if Patent Documents 1 and 2 are applied to devices that utilize the conductivity modulation effect, such as insulated gate bipolar transistors (IGBTs), the conductivity modulation effect is not improved.

[0015] Also, p --The p-type diffusion region 112 is formed by obliquely implanting ions into the sidewall of the trench 105 and by performing epitaxial growth multiple times. This poses a problem of complex processes. Furthermore, in Patent Document 3, when applied to a device utilizing the conductivity modulation effect, such as an IGBT, holes are extracted from the p-type buried region 109, which is fixed to the source potential, in the on-state. This makes it difficult for conductivity modulation to occur, resulting in a problem of deteriorating on-resistance characteristics.

[0016] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device capable of improving the on-resistance characteristics. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A second semiconductor layer of a first conductivity type, having a higher impurity concentration than the first semiconductor layer, is provided on a first main surface side of a first semiconductor layer of a first conductivity type. A fifth semiconductor region of a first conductivity type, having a lower impurity concentration than the second semiconductor layer, is selectively provided inside the second semiconductor layer. A first semiconductor region of a second conductivity type is provided on a surface of the second semiconductor layer opposite to the first semiconductor layer. A second semiconductor region of a first conductivity type is selectively provided inside the first semiconductor region. A trench is provided that penetrates the second semiconductor region and the first semiconductor region and reaches the first semiconductor layer. A gate insulating film is provided inside the trench along the bottom and sidewalls of the trench. A gate electrode is provided inside the trench, inside the gate insulating film. A third semiconductor region of a second conductivity type is selectively provided inside the first semiconductor layer so as to surround the bottom of the trench. A fourth semiconductor region is provided on a second main surface side of the first semiconductor layer. A first electrode is provided electrically connected to the first semiconductor region and the second semiconductor region. A second electrode is provided electrically connected to the fourth semiconductor region. The fifth semiconductor region has one surface in contact with the first semiconductor region, the other surface in contact with the third semiconductor region, and one side surface in contact with the gate insulating film. The trench has a stripe shape, and the fifth semiconductor region is provided partially in the depth direction of the trench.

[0018] Moreover, in the semiconductor device according to the present invention, the fifth semiconductor region has the same impurity concentration as the first semiconductor layer.

[0019] Moreover, in the semiconductor device according to the present invention, the fifth semiconductor region has a lower impurity concentration than the first semiconductor layer.

[0020] Moreover, in the semiconductor device according to the present invention, a width of the fifth semiconductor region is narrower than a width of the second semiconductor layer.

[0021] Further, the semiconductor device according to the present invention is the above-mentioned invention. ,before The fifth semiconductor region is characterized in that a plurality of fifth semiconductor regions are provided partially in the depth direction of the trench.

[0022] According to the above-described invention, in the on-state, the p-type buried region (second conductivity type third semiconductor region) is in a floating state, so that minority carriers (holes) are not drawn from the p-type buried region to the emitter electrode (first electrode). Therefore, conductivity modulation is not hindered in devices that utilize the conductivity modulation effect, such as IGBTs. This makes it possible to prevent deterioration of the on-resistance characteristics. [Effects of the Invention]

[0023] The semiconductor device according to the present invention has the effect of improving the on-resistance characteristics. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 2 is a top view (part 1) of the AA' line in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. FIG. [Figure 3] 2 is a top view (part 2) of the semiconductor device according to the first embodiment taken along line AA' in FIG. 1; FIG. [Figure 4] 2 is a top view (part 3) of the semiconductor device according to the first embodiment taken along line AA' of FIG. 1, illustrating the structure of the semiconductor device according to the first embodiment. FIG. [Figure 5] FIG. 2 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment in an off state. [Figure 6] 3 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment in an on-state; FIG. [Figure 7] FIG. 4 is a cross-sectional view showing another structure of the semiconductor device according to the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the structure of a main part of a conventional semiconductor device. [Figure 10] FIG. 10 is a characteristic diagram showing a voltage waveform of a conventional semiconductor device. [Figure 11] FIG. 10 is a cross-sectional view showing the structure of another example of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0025] Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - appended to n or p indicate a higher or lower impurity concentration than layers or regions without these prefixes, respectively. In the following description of the embodiments and the accompanying drawings, similar components are given the same reference numerals, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0026] (Embodiment 1) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as a wide bandgap semiconductor will be described using a trench IGBT 50 as an example.

[0027] 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. As shown in FIG. 1, in the semiconductor device according to the first embodiment, n - A MOS gate structure having a trench gate structure is provided on the first main surface side of the p-type drift layer (first semiconductor layer of the first conductivity type) 2. The MOS gate structure has a p - n-type base region (first semiconductor region of second conductivity type) 3, + The trench IGBT 50 comprises an emitter region (second semiconductor region of the first conductivity type) 4, a trench 5, a gate insulating film 7, and a gate electrode 8. The trench 5 has a stripe shape, for example, as shown in Fig. 1. Fig. 1 shows only the active region of the trench IGBT 50, through which the main current flows.

[0028] n - The second main surface side of the drift layer 2 is + A second conductivity type collector layer (fourth semiconductor region of the second conductivity type) 1 is provided. + The collector layer 1 is an n - The diffusion region may be formed by, for example, ion implantation in the surface layer of the second main surface of the drift layer 2, or may be a p + It may be made of a starting substrate (semiconductor chip). + The collector layer 1 is p + When using a starting substrate of type n - The drift layer 2 is p + p type collector layer 1 + The epitaxial layer is deposited, for example, on the front surface of the starting substrate.

[0029] n -A high-concentration n-type layer (first conductivity type second semiconductor layer) 6 is provided on the first main surface side of the n-type drift layer 2. The high-concentration n-type layer 6 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The high-concentration n-type layer 6 is p - The n-type base region 3 is provided in a region sandwiched between the n-type base region 3 and a p-type buried region 9, which will be described later. - The impurity concentration is higher than that of the n-type drift layer 2. - The impurity concentration of the drift layer 2 is 1×10 14 / cm 3 More than 1×10 16 / cm 3 In this case, the impurity concentration of the high-concentration n-type layer 6 is, for example, 1×10 17 / cm 3 It is about the following.

[0030] The high-concentration n-type layer 6 is provided with an n-type insulating film 7 in a part thereof that is in contact with the gate insulating film 7 described later. - A first conductivity type region (fifth semiconductor region) 15 is provided. - The type region 15 is n - The impurity concentration is approximately the same as that of the n-type drift layer 2. - The n-type region 15 has the same thickness as the high-concentration n-type layer 6. Therefore, one surface is p - The other surface is in contact with the p-type base region 3 and the other surface is in contact with the p-type buried region 9 .

[0031] 2 to 4 are top views along the line AA′ in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. As shown in FIG. - The width of the n-type region 15 may be narrower than the width of the high-concentration n-type layer 6, or may be wider than the n-type region 15 as shown in FIG. - The width of the n-type region 15 may be the same as the width of the high-concentration n-type layer 6. - The n-type region 15 has a lower impurity concentration than the high-concentration n-type layer 6 and has a higher resistance. - The inversion layer of the n-type region 15 is formed in the area in contact with the gate insulating film 7. - The width of the n-type region 15 is preferably narrower than the width of the high-concentration n-type layer 6. FIGS. 2 and 3 show only one side of the gate insulating film 7.- The mold region 15 is provided symmetrically at the same position on the other side. - The mold region 15 may be provided asymmetrically. - The mold region 15 may be provided on only one side. - It is preferable that a plurality of mold regions 15 are provided partially in the depth direction (longitudinal direction) of the trench 5. - If there is only one type region 15, then n - Part of type region 15 and n - This is because the distance from the mold region 15 to the part farther away increases, resulting in a larger potential difference.

[0032] Fig. 5 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment in an off state. Fig. 6 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment in an on state. The off state is a state in which the semiconductor device does not operate, and is a state in which the gate voltage is at least 0 V or less (a state in which no gate voltage is applied to the gate electrode or a negative gate voltage is applied). The on state is a state in which the semiconductor device operates, and is a state in which the gate voltage is equal to or greater than a threshold voltage (gate voltage ≥ threshold voltage).

[0033] In the on-state, a positive gate voltage is applied to the gate electrode 8, and n - A channel electron inversion layer 12 is formed in the portion of the p-type region 15 that contacts the gate insulating film 7, and channel electrons are induced. - The p-type base region 3 and the p-type buried region 9 are not electrically connected directly to each other, and - The discharge of holes into the n-type base region 3 is suppressed. - This increases the hole density in the drift layer 2, increases the carrier density, and improves the on-resistance characteristics.

[0034] On the other hand, in the off state, n - A hole inversion layer 13 is formed in the portion of the doped region 15 that is in contact with the gate insulating film 7. This hole inversion layer 13 causes p -The n-type base region 3 and the p-type buried region 9 are electrically connected. Therefore, in the off state, the p-type buried region 9 is fixed to the emitter potential. - A hole inversion layer 13 is easily induced in the portion of the p-type region 15 that contacts the gate insulating film 7, and the p-type buried region 9 reaches the emitter potential even when the potential of the gate electrode 8 is near 0 V. By reaching the emitter potential more quickly than in the conventional structure during switching, a high electric field to the gate insulating film 7 is suppressed, the protective effect is improved, and a decrease in the breakdown voltage and a decrease in the reliability of the gate insulating film 7 can be suppressed.

[0035] Also, when in the off state, - In order to generate a hole inversion layer 13 in the portion of the n-type region 15 that contacts the gate insulating film 7, - The impurity concentration of the n-type drift layer 2, the thickness of the gate insulating film 7, and the work function of the gate electrode 8 are appropriately set. - The impurity concentration of the n-type region 15 is, for example, - The impurity concentration is the same as that of the type drift layer 2, and is set low enough to generate a hole inversion layer 13 (that is, to allow holes to exist) in the off state.

[0036] p - The p-type base region 3 is provided on the high-concentration n-type layer 6. - The base region 3 may be an epitaxial layer deposited on the high-concentration n-type layer 6, or may be a diffusion region formed in the surface layer of the high-concentration n-type layer 6 by, for example, ion implantation.

[0037] p - The lower the impurity concentration of the base region 3, the lower the threshold voltage. - It is preferable that the n-type inversion layer is low enough to prevent a channel (n-type inversion layer) from being formed (the n-type inversion layer is not turned on) in the portion of the n-type base region 3 facing the gate electrode 8. + The emitter region 4 is p - It is selectively provided inside the mold base region 3. +The emitter region 4 may be an epitaxial layer or a diffusion region formed by, for example, ion implantation. + The contact region 14 is p - It may be selectively provided inside the mold base region 3. + The p-type emitter region 4 is in contact with the gate insulating film 7. + The contact region 14 is provided at a position away from the gate insulating film 7. The trench 5 is + Type emitter region 4, p - The n-type base region 3 and the heavily doped n-type layer 6 are penetrated. - The drift layer 2 is reached.

[0038] p - In the type base region 3, p - Ion implantation may be performed on the portion of the base region 3 where the channel is to be formed. - A channel implantation layer 17 having a higher impurity concentration than the base region 3 is formed.

[0039] The gate electrode 8 is formed between the high-concentration n-type layer 6 and the n-type layer 7 with the gate insulating film 7 provided on the bottom and sidewall of the trench 5 sandwiched therebetween. - type area 15, p - Type base region 3, n + type emitter region 4, channel implantation layer 17 and n - The collector-side end of the gate electrode 8 faces the p-type drift layer 2. - The n-type base region 3 and the high-concentration n-type layer 6 are located closer to the collector than the pn junction 21. - The inside of the drift layer 2 is - A p-type diffusion region (p-type buried region (third semiconductor region of the second conductivity type)) 9 is selectively provided apart from the base region 3. The p-type buried region 9 is an n-type buried region that surrounds the bottom of the trench 5. - The p-type buried region 9 is buried inside the p-type drift layer 2 and faces the gate electrode 8 across the gate insulating film 7. That is, the bottom of the trench 5 is located inside the p-type buried region 9. The p-type buried region 9 is wider than the trench 5, and the surface on the emitter side is n -The n-type region 15 and the high-concentration n-type layer 6 are in contact with each other.

[0040] The p-type buried region 9 may extend along the inner wall of the trench 5 toward the emitter side, so as not to face the gate electrode 8 across the gate insulating film 7 provided on the trench sidewall. - The p-type buried region 9 has a function of alleviating the electric field applied to the p-type drift layer 2. The p-type buried region 9 may be a diffusion region formed by, for example, ion implantation. The impurity concentration of the p-type buried region 9 can be changed in various ways according to the design conditions, and may be high enough to prevent degeneration of the energy level (the Fermi level does not move into the valence band). For example, the impurity concentration of the p-type buried region 9 is high enough to prevent the entire p-type buried region 9 from being depleted even when a high voltage is applied to the collector, and may be, for example, n - The impurity concentration is set to be equal to or higher than that of the type drift layer 2.

[0041] The thickness of the gate insulating film 7 may be the same at the bottom and sidewall of the trench. - Type base region 3 and n + The p-type emitter region 4 is in contact with the p-type emitter region 4 and is electrically insulated from the gate electrode 8 by an interlayer insulating film (not shown). + When the contact region 14 is provided, the emitter electrode 10 is + type contact region 14 and n + The collector electrode (second electrode) 11 is in contact with the p-type emitter region 4. + The mold contacts the collector layer 1.

[0042] Although not particularly limited, for example, when the semiconductor device according to the first embodiment has a breakdown voltage of 13 kV, n + type emitter region 4 and p + The collector layer 1 has a sufficiently high impurity concentration (1×10 18 / cm 3 The thickness is about 0.1 μm or more. - The impurity concentration of the base region 3 depends on the thickness of the gate insulating film 7, but is generally 1×1015 / cm 3 More than 1×10 17 / cm 3 The following is the extent of the above. - The thickness of the n-type drift layer 2 is approximately 100 μm or more and 150 μm or less. - The impurity concentration of the drift layer 2 is in the range described above, and is preferably 5×10 14 / cm 3 The depth of the trench 5 is about 1 μm or more and 3 μm or less. The thickness of the gate insulating film 7 is about 50 nm or more and 200 nm or less. The impurity concentration of the p-type buried region 9 is 1×10 18 / cm 3 It is more than enough.

[0043] Next, the operation of the semiconductor device according to the first embodiment will be described. The emitter electrode 10 is either grounded or has a negative voltage applied to it (emitter potential≦0). The collector electrode 11 has a positive voltage applied to it (collector potential>0). In this state, p - Type base region 3 and n - The pn junction 21 between the n-type drift layer 2 and the n-type drift layer 2 is reverse biased. - Type base region 3 and n - A depletion layer (not shown) spreads inside the n-type drift layer 2, blocking the path (channel) of electrons, which are conduction carriers. At this time, when no gate voltage or a negative gate voltage (gate voltage≦0V) is applied to the gate electrode 8, no current flows between the emitter and collector. In other words, the off state is maintained. While the off state is maintained, n - A channel electron inversion layer 12 is formed in the portion of the p-type region 15 in contact with the gate insulating film 7. - The p-type base region 3 and the p-type buried region 9 are electrically connected. - The base (emitter) potential is fixed at approximately the same potential as the p-type base region 3, and the p-type buried region 9 and n - The pn junction 22 between the first and second drift layers 2 is also reverse biased.

[0044] On the other hand, when the voltage applied to the gate electrode 8 is set to the threshold voltage or higher (gate voltage≧threshold voltage), p - Type base region 3, n + Type emitter region 4 and n - A channel electron inversion layer 12 is formed along the gate insulating film 7 in the portion sandwiched between the n-type drift layer 2 and the n-type drift layer 2 (the portion facing the gate electrode 8). + type emitter region 4, channel electron inversion layer 12 and n - The n-type drift layer 2 serves as a path for electrons, which are conduction carriers. + n-type emitter region 4, n-type inversion layer and n - The electrons pass through the n-type drift layer 2 to the collector electrode 11, and a current flows between the emitter and the collector. This state is the on state. In the on state, - Since no hole inversion layer 13 is formed in the portion of the p-type region 15 in contact with the gate insulating film 7, the p-type buried region 9 is in a floating state. Then, by again applying a voltage to the gate electrode 8 that is at least 0 V or less (gate voltage≦0 V), the semiconductor device transitions from the on state to the off state. In this way, the on / off state of the semiconductor device is controlled by the voltage applied to the gate electrode 8.

[0045] Even when the gate voltage is greater than 0 and less than the threshold voltage (0<gate voltage<threshold voltage), the channel electron inversion layer 12 is not formed, just as when the gate voltage is 0V or less. However, in reality, after an external command value for off control (gate voltage<threshold voltage) is applied to the gate electrode 8, the semiconductor device according to the first embodiment is in a transition state until it stops operating and does not completely stop until the gate voltage becomes 0V. For this reason, in the above explanation, the state in which the gate voltage is at least 0V or less, at which the operation of the semiconductor device according to the first embodiment completely stops, is referred to as the off state. - The gate voltage at which the hole inversion layer 13 is formed in the p -If the gate voltage (i.e., threshold voltage) can be adjusted to be equal to the gate voltage when the channel electron inversion layer 12 is formed in the base region 3 (on state), the off state may be set when the gate voltage is less than the threshold voltage (gate voltage<threshold voltage).

[0046] 7 is a cross-sectional view showing another structure of the semiconductor device according to the first embodiment. As shown in FIG. 7, the semiconductor device according to the first embodiment may have inter-trench p-type buried regions 18 formed in the surface layer of the high-concentration n-type layer 6 between the trenches 5. The inter-trench p-type buried regions 18 are formed to the same depth as the p-type buried regions 9, and - The inter-trench p-type buried region 18 has the same potential as the n-type base region 3. - It has the function of reducing the electric field applied to the drift layer 2.

[0047] In the above description, a device utilizing the conductivity modulation effect such as an IGBT is used as an example, but the present invention may also be applied to an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). + Instead of type collector layer 1, n + A drain layer is provided, and an n + The emitter region 4, the emitter electrode 10 and the collector electrode 11 are n-type. + The semiconductor material of the semiconductor device according to the first embodiment may be a silicon (Si) semiconductor or a semiconductor having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor), such as a silicon carbide semiconductor.

[0048] In the case of MOSFET, p-type buried region 9 and p - In order to make the p-type buried region 9 and the n-type base region 3 have the same potential, a part of the p-type buried region 9 is extended to connect the p-type buried region 9 and the inter-trench p-type buried region 18. In the semiconductor device according to the first embodiment, -The p-type buried region 9 and the p-type region 15 are - Since the p-type buried region 9 and the base region 3 can be at the same potential, it is not necessary to connect the p-type buried region 9 to the inter-trench p-type buried region 18, and furthermore, it is not necessary to provide the inter-trench p-type buried region 18.

[0049] (Method of manufacturing a semiconductor device according to the first embodiment) Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. - n-type drift layer 2 - A p-type buried region 9 is formed on the front surface side of the n-type semiconductor substrate by ion implantation. - On the front surface of the drift layer 2, - The n-type layer is then epitaxially grown. - A high concentration n-type layer 6 is formed by ion implantation into the n-type layer. At this time, an ion implantation shielding mask is used to create a region where ions are not implanted, and n - The high concentration n-type layer 6 may be formed by epitaxial growth. - The n-type region 15 is formed by counter-doping a part of the high-concentration n-type layer 6 with p-type impurities. When providing the inter-trench p-type buried region 18, the inter-trench p-type buried region 18 is formed by ion implantation into the surface layer of the high-concentration n-type layer 6.

[0050] Next, p - The base region 3 is epitaxially grown. Next, a trench 5, a gate insulating film 7, and a gate electrode 8 are formed in this order to form a MOS gate. Next, in order to adjust the threshold voltage (Vth), a p - Ion implantation may be performed on a portion of the base region 3 where a channel is to be formed, to form a channel implantation layer 17. Next, p - Inside the base region 3, + Next, p-type emitter regions 4 are selectively formed by ion implantation of p-type impurities. - Inside the type base region 3, p + Mold contact regions 14 may be selectively formed.

[0051] Next, an interlayer insulating film such as a BPSG film is deposited so as to cover the gate electrode 8. Next, the interlayer insulating film is patterned to form contact holes, and n + type emitter region 4 and p + The n-type contact region 14 is exposed. Next, an n-type contact region 14 is deposited inside the contact hole by, for example, sputtering. + type emitter region 4 and p + An emitter electrode 10 is formed so as to contact the mold contact region 14 .

[0052] Next, n - The drift layer 2 is ground from the rear surface side until it reaches the thickness of the product to be used as a semiconductor device. - For example, p-type impurities are ion-implanted into the entire rear surface of the n-type drift layer 2. - The surface layer of the entire back surface of the drift layer 2 is p + A p-type collector layer 1 is formed. + The collector layer 1 is p + In this case, n - The drift layer 2 is p + p type collector layer 1 + The p-type starting substrate is then epitaxially deposited on the front surface of the substrate. + A collector electrode 11 is formed in contact with the collector layer 1. Thereafter, the semiconductor wafer is cut (diced) into individual chips, thereby completing the trench IGBT 50 shown in FIG.

[0053] As described above, according to the first embodiment, in the on-state, the p-type buried region is in a floating state, and therefore extraction of minority carriers (holes) from the p-type buried region to the emitter electrode does not occur. Therefore, conductivity modulation is not hindered in devices that utilize the conductivity modulation effect, such as IGBTs. This prevents deterioration of the on-resistance characteristics. In other words, the on-resistance characteristics can be improved compared to, for example, the case in Patent Document 3, in which the p-type buried region is fixed to the emitter potential in the on-state.

[0054] Furthermore, when the p-type buried region is in a floating state in the off state as in Patent Document 3, for example, depending on the potential state of the p-type buried region, the potential difference between the gate electrode and the p-type buried region may become large, and a high electric field may be concentrated at the bottom of the gate insulating film. On the other hand, according to the first embodiment, in the off state, the p-type buried region is in a floating state due to the hole inversion layer. - The p-type buried region is electrically connected to the n-type base region and fixed to the emitter potential (for example, ground). As a result, even if a high voltage is applied to the collector electrode, the potential difference between the gate electrode and the p-type buried region (the voltage applied to the bottom of the gate insulating film) is about the same as the gate voltage, so a high electric field does not concentrate at the bottom of the gate insulating film. In addition, by fixing the p-type buried region to the emitter potential, - The portion of the drift layer along the gate insulating film is also maintained at a potential close to the emitter potential, and the voltage applied to the gate insulating film is approximately the same as the gate voltage. Therefore, a high electric field is not concentrated on the gate insulating film. This improves the breakdown voltage characteristics compared to conventional devices, preventing malfunctions and dielectric breakdown. Furthermore, because a high electric field is not concentrated on the gate insulating film, the allowable upper limit of the collector voltage can be increased to a level that generates an electric field close to the maximum electric field strength of the semiconductor material. This allows, for example, using a wide bandgap semiconductor to achieve a high breakdown voltage close to the characteristic limit of the wide bandgap semiconductor material.

[0055] Furthermore, according to the first embodiment, in the off state, n -A hole inversion layer is formed in the surface layer of the p-type region. - Since the p-type base region and the p-type buried region can be electrically connected, for example, as in Patent Document 3, - This eliminates the need to form a diffusion region to connect the p-type base region and the p-type buried region, thereby simplifying the manufacturing process compared to conventional methods.

[0056] (Embodiment 2) 8 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. The silicon carbide semiconductor device according to the second embodiment has n - Instead of type region 15, ultra-low concentration n -- A mold area 16 is provided. -- The n-type region 16 is the same as that of the first embodiment. - The mold region 15 is provided in the same place as the n - This region has a lower impurity concentration than the type drift layer 2.

[0057] As in the first embodiment, when in the off state, n -- A channel electron inversion layer 12 is formed in the portion of the p-type region 16 that contacts the gate insulating film 7. - The n-type base region 3 and the p-type buried region 9 are electrically connected. -- By lowering the impurity concentration of the n-type region 16, the threshold value at which the hole inversion layer 13 is formed can be lowered. - By making the impurity concentration lower than that of the n-type region 15, the hole inversion layer 13 is easily induced, and -- By adjusting the impurity concentration of the p-type region 16, the p-type buried region 9 can be set to the emitter potential even when the potential of the gate electrode 8 is near 0 V. Therefore, in the second embodiment, the emitter potential is reached more quickly during switching than in the first embodiment, thereby suppressing a high electric field in the gate insulating film 7, improving the protective effect, and further suppressing a decrease in the breakdown voltage and a decrease in the reliability of the gate insulating film 7.

[0058] The semiconductor device according to the second embodiment can be formed in the same manner as the semiconductor device according to the first embodiment.-- The n-type region 16 can be formed by counter-doping a part of the high concentration n-type layer 6 with p-type impurities.

[0059] As described above, according to the second embodiment, in the on state, the p-type buried region is in a floating state, so that minority carriers (holes) are not drawn from the p-type buried region to the emitter electrode. -- A hole inversion layer is formed in the surface layer of the p-type region. - The n-type base region and the p-type buried region can be electrically connected. -- The n type region of the first embodiment - By making the impurity concentration lower than that of the type region, a hole inversion layer is more easily induced, and the emitter potential is reached more quickly during switching than in the first embodiment, thereby suppressing a high electric field in the gate insulating film, improving the protective effect, and further suppressing a decrease in the breakdown voltage and a decrease in the reliability of the gate insulating film.

[0060] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Furthermore, although each of the embodiments has been described in terms of an n-type as the first conductivity type and a p-type as the second conductivity type, the present invention is equally valid even if the first conductivity type is a p-type and the second conductivity type is an n-type. [Industrial Applicability]

[0061] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of symbols]

[0062] 1 p + Mold collector layer 2n - Mold drift layer 3 p - Type-based domain 4n+ Type emitter area 5. Trench 6 Highly concentrated n-type layer 7 Gate insulating film 8 gate electrode 9 p-type buried region 10 Emitter electrode 11 Collector electrode 12 Channel electron inversion layer 13 Hole inversion layer 14 p + Mold contact area 15n - type area 16n -- type area 17 Channel implantation layer 18 P-type buried region between trenches 21, 22 p-n junction 50 Trench IGBT

Claims

1. a second semiconductor layer of the first conductivity type provided on a first major surface side of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; a fifth semiconductor region of the first conductivity type selectively provided inside the second semiconductor layer and having a lower impurity concentration than the second semiconductor layer; a first semiconductor region of a second conductivity type provided on a surface of the second semiconductor layer opposite to the first semiconductor layer; a second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region; a trench that penetrates the second semiconductor region and the first semiconductor region and reaches the first semiconductor layer; a gate insulating film provided inside the trench along the bottom and sidewalls of the trench; a gate electrode provided inside the trench and on the inner side of the gate insulating film; a third semiconductor region of a second conductivity type selectively provided inside the first semiconductor layer so as to surround the bottom of the trench; a fourth semiconductor region provided on the second major surface side of the first semiconductor layer; a first electrode electrically connected to the first semiconductor region and the second semiconductor region; a second electrode electrically connected to the fourth semiconductor region; Equipped with the fifth semiconductor region has one surface in contact with the first semiconductor region, the other surface in contact with the third semiconductor region, and one side surface in contact with the gate insulating film; the trench is stripe-shaped; The semiconductor device is characterized in that the fifth semiconductor region is provided partially in the depth direction of the trench.

2. 2. The semiconductor device according to claim 1, wherein the fifth semiconductor region has the same impurity concentration as that of the first semiconductor layer.

3. 2. The semiconductor device according to claim 1, wherein the fifth semiconductor region has a lower impurity concentration than the first semiconductor layer.

4. 4. The semiconductor device according to claim 1, wherein the width of the fifth semiconductor region is narrower than the width of the second semiconductor layer.

5. A semiconductor device described in any one of claims 1 to 4, characterized in that the fifth semiconductor region is partially provided in multiple locations in the depth direction of the trench.

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