Nitride semiconductor device manufacturing method and nitride semiconductor device

Abstract

To provide a manufacturing method of a nitride semiconductor device and the nitride semiconductor device capable of forming a MOSFET with high mobility.SOLUTION: A manufacturing method of a nitride semiconductor device includes the steps of forming an AlxGa(1-x) N layer (0<x≤1) on a Mg-doped GaN layer, performing first heat treatment on the AlxGa(1-x) N layer (0<x≤1) and the GaN layer at a maximum temperature of 1100°C or higher in an atmosphere containing no hydrogen, reacting the AlxGa(1-x) N layer (0<x≤1) and the GaN layer to form a reaction layer of the AlxGa(1-x) N layer (0<x≤1) and the GaN layer, and removing, from the GaN layer, an unreacted AlxGa(1-x) N layer (0<x≤1) that has not reacted with the GaN layer in the first heat treatment.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] BACKGROUND ART Vertical MOSFETs using gallium nitride have been known for some time (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-188687 [Non-patent literature]

[0004] [Non-Patent Document 1] Y. Kajiwara et al, “Highly Reliable GaN-MOSFETs with High Channel Mobility Gate by Selective-Area Crystallization”, Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) September 13-18,2020 Summary of the Invention [Problem to be solved by the invention]

[0005] When forming a MOSFET on Mg-doped p-type GaN, silicon oxide (SiO2) or aluminum oxide (alumina; Al2O3) is generally used as the gate insulating film. In this case, the carrier mobility in the channel region of the MOSFET is estimated at 100 cm 2 / Vs. On the other hand, in the case of HEMT, it has been shown that the mobility is improved by forming AlN as an underlying film of the gate insulating film (see, for example, Non-Patent Document 1). However, this was the case where AlN was formed on undoped (non-doped) and thin GaN. When forming a MOSFET on GaN doped with Mg as a p-type impurity on a single crystal bulk, forming AlN on GaN makes it difficult for hydrogen in GaN to escape, inhibiting the activation of Mg, and thus the improvement in mobility has not been achieved.

[0006] The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of forming a MOSFET with high mobility.

Means for Solving the Problems

[0007] In order to solve the above problems, a method for manufacturing a nitride semiconductor device according to an aspect of the present invention includes a step of forming an AlxGa(1-x)N layer (0 < x ≤ 1) on a GaN layer doped with Mg, and performing a first heat treatment on the AlxGa(1-x)N layer (0 < x ≤ 1) and the GaN layer in an atmosphere not containing hydrogen at a maximum temperature of 1100°C or higher, reacting the AlxGa(1-x)N layer (0 < x ≤ 1) and the GaN layer with each other to form a reaction layer between the AlxGa(1-x)N layer (0 < x ≤ 1) and the GaN layer, and removing an unreacted AlxGa(1-x)N layer (0 < x ≤ 1) that did not react with the GaN layer in the first heat treatment from above the GaN layer.

[0008] A nitride semiconductor device according to an aspect of the present invention includes a p-type GaN layer doped with Mg and a gate insulating film provided on the GaN layer. The Mg concentration in the GaN layer is 1×10 17 cm -3 or more and 1×10 18 cm -3 or less. The gate insulating film is composed of a SiO2 film. There is an Al concentration peak where the Al concentration is maximum in the GaN layer and the gate insulating film between the GaN layer and the gate insulating film. [Effects of the Invention]

[0009] According to one aspect of the present invention, it is possible to provide a nitride semiconductor device manufacturing method that enables formation of a MOSFET with high mobility, and the nitride semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a diagram schematically showing the Al concentration peak in the range from the P-type GaN layer to the gate insulating film. [Figure 4A] FIG. 4A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4B] 4A to 4B are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4C] 4A to 4C are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4D] 4A to 4D are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4E] FIG. 4E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4F] 4F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4G] 4A to 4G are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 4H] 4A to 4H are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment in the order of steps. [Figure 5] FIG. 5 is a flowchart showing the manufacturing method of a GaN semiconductor device in order of steps. [Figure 6A] FIG. 6A is a graph showing the relationship between the gate voltage Vg and the electron mobility μ in the channel region of the lateral MOSFET according to the first embodiment of the present invention. [Figure 6B] FIG. 6B is a graph showing the relationship between the gate voltage Vg and the mobility μ of a lateral MOSFET according to a comparative example of the present invention. [Figure 7] FIG. 7 is a plan view showing a configuration example of a GaN semiconductor device according to the second embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the second embodiment. [Figure 9A] FIG. 9A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9B] FIG. 9B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9C] FIG. 9C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9D] FIG. 9D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9E] FIG. 9E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9F] 9F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9G] 9A to 9G are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 9H] 9A to 9H are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the second embodiment in the order of steps. [Figure 10] FIG. 10 is a plan view showing a configuration example of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the third embodiment. [Figure 12A] FIG. 12A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12B] FIG. 12B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12C] FIG. 12C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12D] FIG. 12D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12E] FIG. 12E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12F] FIG. 12F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 12G] FIG. 12G is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment in the order of steps. [Figure 13] FIG. 13 is a plan view showing a first modification of the layout of vertical MOSFETs. [Figure 14] FIG. 14 is a plan view showing a second modification of the vertical MOSFET arrangement. [Figure 15] FIG. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a fourth embodiment of the present invention. [Figure 16A] FIG. 16A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the fourth embodiment in the order of steps. [Figure 16B] FIG. 16B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the fourth embodiment in the order of steps. [Figure 16C] FIG. 16C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the fourth embodiment in the order of steps. [Figure 16D] FIG. 16D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the fourth embodiment in the order of steps. [Figure 17] FIG. 17 is a graph showing the results of comparing the breakdown voltage characteristics of the example of the present invention and the comparative example. [Figure 18A] FIG. 18A is a cross-sectional view showing a first modification of the method for manufacturing a GaN semiconductor device according to the fourth embodiment in the order of steps. [Figure 18B] FIG. 18B is a cross-sectional view showing the order of steps in the first modification of the method for manufacturing a GaN semiconductor device according to the fourth embodiment. [Figure 18C] FIG. 18C is a cross-sectional view showing the order of steps in a first modification of the method for manufacturing a GaN semiconductor device according to the fourth embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a second modification of the GaN semiconductor device according to the fourth embodiment. [Figure 20] FIG. 20 is a plan view showing a second modification of the GaN semiconductor device according to the fourth embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing a third modification of the GaN semiconductor device according to the fourth embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing a fourth modification of the GaN semiconductor device according to the fourth embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing a fifth modification of the GaN semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0012] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up." In the following description, + or - attached to P or N indicating the conductivity type of a semiconductor region means that the semiconductor region has a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if semiconductor regions are attached with the same P and P (or N and N), this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Embodiment 1> (Configuration example) FIG. 1 is a plan view showing an example of the configuration of a gallium nitride semiconductor device 1 according to a first embodiment of the present invention (one example of a "nitride semiconductor device" according to the present invention; hereinafter, referred to as a GaN semiconductor device). FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device 1 according to the first embodiment. Note that the insulating film 27 shown in FIG. 2 is omitted from FIG. 1. FIG. 2 also shows a cross section of the plan view shown in FIG. 1 taken along line X1-X'1 parallel to the X-axis direction. As shown in FIGS. 1 and 2, a GaN semiconductor device 1 according to the first embodiment includes a gallium nitride substrate (hereinafter referred to as GaN substrate) 10 and a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 20 provided on the GaN substrate 10.

[0014] The GaN substrate 10 includes, for example, a GaN single crystal substrate 11 and a P-type GaN layer 13 provided on the GaN single crystal substrate 11. The GaN single crystal substrate 11 is, for example, an N-type c-plane GaN single crystal substrate. The N-type impurities contained in the GaN single crystal substrate 11 are one or more of Si (silicon), O (oxygen), and Ge (germanium). For example, the GaN single crystal substrate 11 contains Si as an N-type impurity, and the impurity concentration of Si in the GaN single crystal substrate 11 is 5×10 17 cm -3 That's all.

[0015] The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2The GaN single crystal substrate 11 may be a low-dislocation freestanding substrate having a dislocation density of less than 1000 nm. When the GaN single crystal substrate 11 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 13 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low-dislocation freestanding substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, ion-implanted impurities can be prevented from diffusing deeply along dislocations during heat treatment.

[0016] The GaN layer 13 is a layer epitaxially grown on the surface of the GaN single crystal substrate 11, and contains Mg (magnesium) as a P-type impurity. Mg is doped during the epitaxial growth of the GaN layer 13. The Mg concentration in the GaN layer 13 is, for example, 1×10 17 cm -3 More than 1×10 18 cm -3 The thickness of GaN layer 13 is, for example, not less than 0.5 μm and not more than 1 μm. In GaN layer 13, the concentration of Mg, which is a P-type impurity, is higher than the concentration of N-type impurities such as Si. This makes the conductivity type of GaN layer 13 P-type.

[0017] The configuration of GaN substrate 10 is not limited to the above. For example, an N-type GaN layer may be provided between N-type GaN single crystal substrate 11 and P-type GaN layer 13. In this case, P-type GaN layer 13 may be formed on the N-type GaN layer by epitaxial growth. GaN substrate 10 may also be composed of only a Mg-doped P-type single crystal GaN layer. That is, GaN substrate 10 may be a Mg-doped P-type GaN single crystal substrate.

[0018] The lateral MOSFET 20 includes a gate insulating film 21 provided on a P-type GaN layer 13 doped with Mg, a gate electrode 22 provided on the gate insulating film 21, an N+ type source region 23 provided in the GaN layer 13, an N+ type drain region 24 provided in the GaN layer 13, a source electrode 25 provided above the GaN layer 13 and in contact with the source region 23, a drain electrode 26 provided above the GaN layer 13 and in contact with the drain region 24, and an insulating film 27 provided above the GaN layer 13 and covering the gate electrode 22. The gate insulating film 21 is, for example, a SiO2 film. Alternatively, the gate insulating film 21 may be a single-layer film including any one of an Al2O3 film, a SiON film, an AlSiO film, and an AlON film, or a multilayer film including one or more of a SiO2 film, an Al2O3 film, a SiON film, an AlSiO film, and an AlON film. The thickness of the gate insulating film 21 is, for example, 50 nm to 100 nm.

[0019] The gate electrode 22 is adjacent to the channel region via the gate insulating film 21. The gate electrode 22 is made of polysilicon doped with a metal such as Al, Ti, Ni, or W, or an impurity. The gate electrode 22 may also be made of a silicide such as WSi or NiSi. The source region 23 and the drain region 24 are provided in the GaN layer 13 below both sides of the gate electrode 22. The source region 23 and the drain region 24 are, for example, N+ type impurity diffusion layers. The source region 23 and the drain region 24 are doped with Si at a concentration of 1×10 as an N type impurity. 19 cm -3 5x10 or more 20 cm -3 Contains the following concentrations:

[0020] The source electrode 25 and the drain electrode 26 are made of Al or an Al-Si alloy, Ni, a Ni alloy, a Ti-Al alloy, a Ni-Au alloy, or the like. The source electrode 25 may have a barrier metal layer between it and the source region 23. The drain electrode 26 may have a barrier metal layer between it and the drain region 24. The barrier metal layer may be made of Ti (titanium). That is, the source electrode 25 and the drain electrode 26 may be a stack of a Ti layer and an Al layer, or a stack of a Ti layer and an Al-Si alloy layer. The source electrode 25 may also serve as a source pad (not shown), or may be an electrode provided separately from the source pad. The drain electrode 26 may also serve as a drain pad (not shown), or may be an electrode provided separately from the drain pad.

[0021] The insulating film 27 is made of, for example, a SiO2 film. The insulating film 27 has contact holes that open above the N+ type source region 23 and above the N+ type drain region 24. The source electrode 25 and the drain electrode 26 are connected to the source region 23 and the drain region 24, respectively, via the contact holes provided in the insulating film 27. The source electrode 25 may be directly connected to the P-type GaN layer 13, or may be indirectly connected via a P+ type region (for example, a P+ type region 29 shown in FIG. 15 described later) having a higher P-type concentration than the P-type GaN layer 13. For example, a contact hole that opens above the P-type GaN layer 13 is provided in the insulating film 27. The source electrode 25 is directly or indirectly connected to the P-type GaN layer 13 via this contact hole. As a result, the potential of the P-type GaN layer 13 may be fixed to the potential of the source electrode 25.

[0022] FIG. 3 is a diagram schematically illustrating an Al concentration peak in the range from the P-type GaN layer 13 to the gate insulating film 21. The Al composition distribution data shown in FIG. 3 can be obtained, for example, by line scanning of an EDX (Energy Dispersive X-ray spectroscopy) image of a TEM (Transmission Electron Microscope). Between the P-type GaN layer 13 and the gate insulating film 21, there exists a region having a higher Al concentration than at least the GaN layer 13. For example, when the gate insulating film 21 is made of an SiO film, as shown in FIG. 3, there exists an Al concentration peak between the P-type GaN layer 13 and the gate insulating film 21. This Al concentration peak is the region where the Al concentration is maximum in the P-type GaN layer 13 and the gate insulating film 21. This Al concentration peak occurs when a reaction layer (Al-containing layer) 31 containing a large amount of Al is formed during the heat treatment in step ST4 of FIG. 5 (described later).

[0023] For example, the reaction layer 31 contains crystalline AlGaN. While the reaction layer 31 can be detected as an Al concentration peak by EDX line scanning or the like, it is often difficult to detect it as an image by TEM or the like. This is because the reaction layer 31 is extremely thin (e.g., 0.25 nm to 7 nm). Also, it is difficult to delineate the boundary between the GaN layer 13 and the reaction layer 31 and the boundary between the reaction layer 31 and the gate insulating film 21. In FIG. 2, the boundary between the GaN layer 13 and the reaction layer 31 and the boundary between the reaction layer 31 and the gate insulating film 21 are shown by solid lines. In FIG. 3, these boundaries are shown by dashed lines. However, the boundary lines shown in FIGS. 2 and 3 are merely schematic.

[0024] For example, in a TEM image actually taken by the inventors, an Al concentration peak was present at the position where the GaN crystalline image and the SiO2 amorphous image switched places. Furthermore, in this TEM image, the Al concentration was distributed above and below this switching position in a range of one to two atomic layers in thickness, as shown in Figure 3. Because there is some error in measuring the distribution of Al concentration, even if the above boundary is defined in terms of Al concentration, it is difficult to clearly identify where the GaN layer 13 ends and the reaction layer 31 begins. In FIG. 2 and FIGS. 8 and 11 described later, the reaction layer 31 is intentionally depicted as a thick film relative to the gate insulating film 21 and the like in order to indicate the presence of the reaction layer 31.

[0025] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 1 will be described. Figures 4A to 4H are cross-sectional views showing the manufacturing method of GaN semiconductor device 1 according to embodiment 1 in the order of steps. Note that GaN single crystal substrate 11 shown in Figure 1 is omitted from Figures 4A to 4H. Figure 5 is a flowchart showing the manufacturing method of GaN semiconductor device 1 according to embodiment 1 in the order of steps.

[0026] GaN semiconductor device 1 is manufactured using various manufacturing equipment such as a resist coating equipment, an exposure equipment, an etching equipment, an ion implantation equipment, a heat treatment equipment, a film formation equipment, and a CMP (Chemical Mechanical Polishing) equipment. In FIG. 4A, the manufacturing equipment epitaxially grows a GaN layer 13' doped with Mg on a GaN single crystal substrate 11 (see FIG. 2) (step ST1 in FIG. 5). Mg is doped into GaN layer 13' during the epitaxial growth process. The thickness of GaN layer 13 is, for example, 0.5 μm or more and 1 μm or less. The Mg concentration in GaN layer 13' is, for example, 1×10 17 cm -3 More than 1×10 18 cm -3 The following is the result.

[0027] Next, the manufacturing apparatus performs heat treatment (an example of the "second heat treatment" of the present invention) on the entire substrate including the Mg-doped GaN layer 13' to remove hydrogen contained in the GaN layer 13' (step ST2 in FIG. 5). This heat treatment is performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2). Also, this heat treatment is preferably performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2) and not containing hydrogen (H2). The maximum temperature of this heat treatment is, for example, 650°C or higher and 850°C or lower.

[0028] Next, as shown in FIG. 4B, the manufacturing apparatus ion-implants N-type impurities into the regions where the source is formed (hereinafter referred to as the source formation region) 23' and the regions where the drain is formed (hereinafter referred to as the drain formation region) 24' in the GaN layer 13'. For example, the manufacturing apparatus forms a mask (not shown) on the GaN layer 13'. The mask is composed of a SiO2 film, an Al2O3 film, or a photoresist. The mask has a shape that opens above the source formation region 23' and the drain formation region 24' and covers other regions. The manufacturing apparatus ion-implants Si into the GaN layer 13' on which the mask is formed. By ion implantation, the Si concentration in the source formation region 23' and the drain formation region 24' is, for example, 1×10 19 cm -3 or more and 5×10 20 cm -3 or less. After ion implantation, the manufacturing apparatus removes the mask from the GaN layer 13.

[0029] Next, as shown in FIG. 4C, the manufacturing apparatus forms an AlxGa(1-x)N layer (0 < x ≦ 1) 30 on the GaN layer 13' (step ST3 in FIG. 5). The AlxGa(1-x)N layer 30 is formed by a thermal CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. The crystal structure of the AlxGa(1-x)N layer 30 is polycrystalline or amorphous. Next, the manufacturing equipment applies a heat treatment (an example of the "first heat treatment" of the present invention) to the entire substrate including the AlxGa(1-x)N layer 30 and the GaN layer 13' in a hydrogen-free atmosphere to react the AlxGa(1-x)N layer 30 and the GaN layer 13' with each other (step ST4 of FIG. 5). The maximum temperature of this heat treatment is, for example, 1100°C or higher and 1300°C or lower.

[0030] As shown in FIG. 4D , the heat treatment in step ST4 forms a reaction layer 31 at the interface between the AlxGa(1-x)N layer 30 and the GaN layer 13, the reaction layer 31 having a higher Al concentration than the GaN layer 13. Furthermore, this heat treatment activates the Mg doped into the GaN layer 13′, turning the GaN layer 13′ into a P-type GaN layer 13. Furthermore, this heat treatment activates the N-type impurities ion-implanted into the source formation region 23′ and the drain formation region 24′, turning the source formation region 23′ and the drain formation region 24′ into N+-type source region 23 and drain region 24. Furthermore, this heat treatment can repair, to a certain extent, defects in the source region 23 and the drain region 24 caused by the ion implantation of the N-type impurities.

[0031] Next, the manufacturing equipment removes the unreacted AlxGa(1-x)N layer 32 of the AlxGa(1-x)N layer 30 that did not react with the GaN layer 13' during the heat treatment in step ST4 from above the P-type GaN layer 13 (step ST5 in FIG. 5). The unreacted AlxGa(1-x)N layer 32 may be removed by, for example, wet etching using an alkaline solution or by surface polishing such as CMP. After the unreacted AlxGa(1-x)N layer 32 is removed, a reaction layer 31 remains on the GaN layer 13, as shown in FIG. 4E. Next, as shown in FIG. 4F, the manufacturing equipment forms a gate insulating film 21 by plasma CVD on the GaN layer 13 on which the reaction layer 31 remains (step ST6 in FIG. 5). Next, the manufacturing equipment partially etches the gate insulating film 21 and the reaction layer 31. As a result, as shown in FIG. 4G, the manufacturing equipment leaves the gate insulating film 21 and the reaction layer 31 in a region that will become the gate of the lateral MOSFET 20 and its periphery, and removes the gate insulating film 21 and the reaction layer 31 from other regions.

[0032] Next, as shown in FIG. 4H, the manufacturing equipment forms a metal film above GaN layer 13 and patterns the formed metal film to form gate electrode 22. The metal film that constitutes gate electrode 22 is formed by vapor deposition, sputtering, or the like. The metal film is patterned by dry etching or a lift-off method. Next, the manufacturing equipment forms an insulating film 27 (see FIG. 2) by plasma CVD or the like. Next, the manufacturing equipment partially etches the insulating film 27 to form contact holes. Next, the manufacturing equipment forms a source electrode 25 and a drain electrode 26 (see FIGS. 1 and 2). The metal film that constitutes the source electrode 25 and the drain electrode 26 is formed by vapor deposition, sputtering, or the like. The metal film is patterned by dry etching or a lift-off method. Through the above steps, the GaN semiconductor device 1 shown in FIGS. 1 and 2 is completed.

[0033] (mobility) FIG. 6A is a graph showing the relationship between the gate voltage Vg and the electron mobility μ in the channel region of the lateral MOSFET 20 according to the first embodiment of the present invention. FIG. 6B is a graph showing the relationship between the gate voltage Vg and the electron mobility μ in a lateral MOSFET according to a comparative example of the present invention. Both FIGS. 6A and 6B are the results of experiments conducted by the present inventors. In the comparative example, an AlxGa(1-x)N layer is not formed. Therefore, in the comparative example, a reaction layer between the GaN layer and the AlxGa(1-x)N layer is not formed between the GaN layer and the gate insulating film, and no Al concentration peak exists between the GaN layer and the gate insulating film.

[0034] As shown in FIG. 6B, the mobility μ of the comparative example was approximately 120 cm 2 In contrast, as shown in FIG. 6A, the mobility μ of the lateral MOSFET 20 according to the first embodiment was approximately 320 cm 2It was / Vs. From this result, it was confirmed that when an AlxGa(1-x)N layer 30 was formed on the GaN layer 13 and then heat-treated at 1100 °C or higher, the mobility μ of the lateral MOSFET 20 increased. This tendency for the mobility μ to increase is the same in the vertical MOSFET 20A according to Embodiment 2 described later and the vertical MOSFET 20B according to Embodiment 3 described later.

[0035] (Effect of Embodiment 1) The manufacturing method of the GaN semiconductor device 1 according to Embodiment 1 of the present invention includes a step of forming an AlxGa(1-x)N layer (0 < x ≤ 1) 30 on a Mg-doped GaN layer 13', a heat treatment (step ST4 in FIG. 5; an example of the "first heat treatment" of the present invention) in an atmosphere not containing hydrogen, with a maximum temperature of 1100 °C or higher, being applied to the AlxGa(1-x)N layer 30 and the GaN layer 13' to react the AlxGa(1-x)N layer 30 and the GaN layer 13' with each other to form a reaction layer 31 between the AlxGa(1-x)N layer 30 and the GaN layer 13', and a step of removing the unreacted AlxGa(1-x)N layer (0 < x ≤ 1) 32 that did not react with the GaN layer 13' in the first heat treatment from above the P-type GaN layer 13.

[0036] According to this, by the above-described first heat treatment, while removing hydrogen contained in the GaN layer 13', the Mg doped in the GaN layer 13' can be activated, and the conductivity type of the GaN layer 13' can be made P-type (that is, the P-type GaN layer 13 can be obtained). Also, by the above-described first heat treatment, a reaction layer 31 (for example, AlGaN) can be directly formed on the P-type GaN layer 13.

[0037] For example, because the underlying GaN layer 13' has a single crystal structure, AlGaN with good crystallinity is formed as the reaction layer 31 directly on the P-type GaN layer 13, resulting in an AlGaN / GaN junction with a good interface. Near the interface of the AlGaN / GaN junction, the crystal types of both materials are the same, resulting in lattice matching. This suppresses electron scattering near the interface of the AlGaN / GaN junction, lengthening the mean free path of electrons in the channel region of the lateral MOSFET 20. This allows the formation of a lateral MOSFET 20 with high mobility.

[0038] Furthermore, the maximum temperature of the first heat treatment is preferably 1100° C. or higher and 1300° C. or lower, which allows efficient removal of hydrogen from GaN layer 13′ and efficient activation of Mg doped in GaN layer 13′. The first heat treatment is preferably performed in an atmosphere that does not contain oxygen. The first heat treatment is preferably performed in an atmosphere that contains nitrogen. For example, the heat treatment is preferably performed in N gas that does not contain H and O. This makes it possible to remove hydrogen contained in the GaN layer 13' while suppressing oxidation of the GaN layer 13' and the AlxGa(1-x)N layer 30.

[0039] Furthermore, the step of removing the unreacted AlxGa(1-x)N layer 32 from the P-type GaN layer 13 is preferably performed by wet etching using an alkaline solution. This can prevent etching damage to the reaction layer 31. The crystallinity of the reaction layer 31 can be maintained at a good level. Furthermore, before forming the AlxGa(1-x)N layer 30, it is preferable to perform a heat treatment (step ST2 in FIG. 5; an example of the "second heat treatment" of the present invention) on the GaN layer 13' in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2) to remove hydrogen from the GaN layer 13'. This removes hydrogen from the GaN layer 13' both before and after forming the AlxGa(1-x)N layer 30. This further increases the removal rate of hydrogen from the GaN layer 13', and further increases the activation rate of Mg doped into the GaN layer 13'.

[0040] <Embodiment 2> In the above-described first embodiment, the present invention is described as being applied to a lateral MOSFET. However, the application of the present invention is not limited to a lateral MOSFET. For example, the present invention may be applied to a vertical MOSFET or a power device including a vertical MOSFET.

[0041] (Configuration example) FIG. 7 is a plan view showing a configuration example of a GaN semiconductor device 1A (an example of a "nitride semiconductor device" of the present invention) according to embodiment 2 of the present invention. FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device 1A according to embodiment 2. Note that source electrode 25 and insulating film 27 shown in FIG. 8 are omitted from FIG. 7. FIG. 8 also shows a cross section taken along line X2-X'2 of the plan view of FIG. 7.

[0042] 7 and 8, a GaN semiconductor device 1A includes a GaN substrate 10A and a plurality of vertical MOSFETs 20A provided on the GaN substrate 10A. In the GaN semiconductor device 1A, the vertical MOSFETs 20A are repeatedly provided in one direction (for example, the X-axis direction). Each vertical MOSFET 20A is a repeated unit structure, and these unit structures are arranged side by side in one direction (for example, the X-axis direction). For example, in the GaN semiconductor device 1A, vertical MOSFETs 20A that are elongated in the Y-axis direction are arranged side by side in the X-axis direction, and are arranged in a stripe pattern in a plan view. GaN substrate 10A is a GaN single crystal substrate. GaN substrate 10A includes, for example, an N+ type GaN single crystal substrate 11, an N-type first GaN layer 12 provided on GaN single crystal substrate 11, and a P-type GaN layer 13 (hereinafter, referred to as second GaN layer 13) provided on first GaN layer 12. The configuration of GaN single crystal substrate 11 is as described in the first embodiment.

[0043] The first GaN layer 12 is a layer epitaxially grown on the surface 11a of the GaN single crystal substrate 11, and contains Si or O as an N-type impurity. The Si or O is doped during the epitaxial growth of the first GaN layer 12. For example, the first GaN layer 12 contains Si as an N-type impurity at a concentration of 1×10 cm to 1×10 cm. The thickness of the first GaN layer is, for example, 5 μm to 20 μm. The second GaN layer 13 is epitaxially grown on the surface of the first GaN layer 12. In the second embodiment, the second GaN layer 13 also contains Mg as a P-type impurity. Mg is doped during the epitaxial growth of the GaN layer 13. For example, the second GaN layer 13 contains 1×10 17 cm -3 5x10 or more 18 cm -3 The GaN layer 13 is doped at the following concentration: The thickness of the GaN layer 13 is 0.5 μm or more and 1 μm or less.

[0044] 8, vertical MOSFET 20A has a trench gate structure. For example, GaN substrate 10A has trench H formed therein, which opens to the surface side of second GaN layer 13 and has first GaN layer 12 as its bottom surface. Gate insulating film 21 is formed to cover the bottom and side surfaces of trench H. The material constituting gate insulating film 21 is the same as that described in the first embodiment. The gate electrode 22 is formed so as to fill the trench H via the gate insulating film 21. The material forming the gate electrode 22 is the same as that described in the first embodiment. The N+ type source region 23 is the second GaN layer 13 and is provided on both sides of the trench H. The N type impurity contained in the source region 23 and its concentration are as described in the first embodiment.

[0045] The source electrode 25 is provided on the front surface side of the GaN substrate 10A. The source electrode 25 is in contact with the N+ type source region 23 and the P type GaN layer. The material constituting the source electrode 25 is the same as that described in the first embodiment. Drain electrode 26 is provided on the back surface side of GaN substrate 10A. Drain electrode 26 is in contact with back surface 11b of GaN single crystal substrate 11 constituting GaN substrate 10A. The material constituting drain electrode 26 is as described in the first embodiment. An insulating film 27 is provided on the P-type second GaN layer 13 and covers the gate electrode 22. A contact hole is provided in the insulating film 27, opening above the N+ type source region 23 and above the P-type second GaN layer 13. A source electrode 25 is connected to the source region 23 and the second GaN layer 13 via the contact hole provided in the insulating film 27. As a result, the potential of the GaN layer 13 is fixed to the potential of the source electrode 25.

[0046] Furthermore, in the vertical MOSFET 20A, a reaction layer 31 containing crystalline AlGaN exists between the second GaN layer 13, in which a channel is formed, and the gate insulating film 21. As a result, there exists a region between the second GaN layer 13 and the gate insulating film 21, which has a higher Al concentration than at least the second GaN layer 13. For example, when the gate insulating film 21 is made of an SiO2 film, an Al concentration peak exists between the P-type GaN layer 13 and the gate insulating film 21, as shown in FIG. 3. This Al concentration peak is the region where the Al concentration is maximum in the GaN layer 13 and the gate insulating film 21.

[0047] (Manufacturing method) Next, a method for manufacturing the GaN semiconductor device 1A will be described. FIGS. 9A to 9H are cross-sectional views illustrating the manufacturing method of the GaN semiconductor device 1A according to the second embodiment in the order of steps. FIGS. 9A to 9H illustrate the manufacturing method of one vertical MOSFET 20A among multiple vertical MOSFETs 20A repeatedly arranged in the X-axis direction in the order of steps. The GaN single crystal substrate 11 shown in FIG. 8 is not shown in FIGS. 9A to 9H. Like the GaN semiconductor device 1 according to embodiment 1, the GaN semiconductor device 1A according to embodiment 2 is also manufactured using various manufacturing equipment such as a resist coating apparatus, an exposure apparatus, an etching apparatus, an ion implantation apparatus, a heat treatment apparatus, a film formation apparatus, and a CMP apparatus.

[0048] 9A, the manufacturing equipment epitaxially grows a first GaN layer 12 of N-type doped with Si on a GaN single crystal substrate 11 (see FIG. 8), and then epitaxially grows a second GaN layer 13′ of Mg doped on the first GaN layer 12. The epitaxial growth of the first GaN layer 12 and the second GaN layer 13′ is performed continuously in the same chamber without being exposed to the atmosphere midway. Next, the manufacturing equipment applies a heat treatment (an example of the "second heat treatment" of the present invention) to the entire substrate including the Mg-doped second GaN layer 13' to remove hydrogen contained in the second GaN layer 13'. This heat treatment is performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2). Preferably, this heat treatment is performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2) but not hydrogen (H2). The maximum temperature of this heat treatment is, for example, 650°C or higher and 850°C or lower.

[0049] 9B, the manufacturing equipment ion-implants N-type impurities (e.g., Si) into the source formation region 23' in the second GaN layer 13'. By the ion implantation, the Si concentration in the source formation region 23' becomes, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 The following is the result. Next, as shown in FIG. 9C, the manufacturing apparatus partially etches the second GaN layer 13' and the first GaN layer 12' to form a trench H. The manufacturing apparatus forms the trench H deeper than the second GaN layer 13' that becomes the well region. The trench H penetrates the second GaN layer 13' and has the bottom surface of the first GaN layer 12.

[0050] Next, as shown in FIG. 9D, the manufacturing apparatus forms an AlxGa(1-x)N layer (0 < x ≤ 1) 30 on the second GaN layer 13'. Similar to Embodiment 1, in Embodiment 2 as well, the AlxGa(1-x)N layer 30 is formed by a thermal CVD method or an ALD method. The crystal structure of the AlxGa(1-x)N layer 30 is polycrystalline or amorphous. The bottom surface and side surfaces of the trench H are covered with the AlxGa(1-x)N layer (0 < x ≤ 1) 30. Next, the manufacturing apparatus performs a heat treatment on the entire substrate including the AlxGa(1-x)N layer 30 and the second GaN layer 13' in an atmosphere containing no hydrogen. Thereby, the AlxGa(1-x)N layer 30 and the second GaN layer 13' are reacted with each other at the surface of the second GaN layer 13' and the side surfaces of the trench H. Also, the AlxGa(1-x)N layer 30 and the first GaN layer 12 are reacted with each other at the bottom surface and the periphery of the trench H. The maximum temperature of this heat treatment is, for example, 1100°C or higher and 1300°C or lower.

[0051] By this heat treatment, as shown in FIG. 9E, a reaction layer 31 having an Al concentration higher than that of the second GaN layer 13 is formed at the interface between the AlxGa(1-x)N layer 30 and the second GaN layer 13. Also, a reaction layer 31 having an Al concentration higher than that of the first GaN layer 12 is formed at the interface between the AlxGa(1-x)N layer 30 and the first GaN layer 12. That is, a reaction layer 31 having a high Al concentration is formed on the bottom surface and side surfaces of the trench H and the surface of the second GaN layer 13. Furthermore, this heat treatment activates the Mg doped in second GaN layer 13', turning second GaN layer 13' into P-type second GaN layer 13. This heat treatment also activates the N-type impurity ions implanted into source formation region 23', turning source formation region 23' into N+-type source region 23. This heat treatment also makes it possible to recover, to a certain extent, defects in source region 23 that have occurred due to the ion implantation of N-type impurity.

[0052] Next, the manufacturing equipment removes the unreacted AlxGa(1-x)N layer 32 of the AlxGa(1-x)N layer 30 that did not react with the GaN layer 13' during the heat treatment from above the P-type GaN layer 13. The unreacted AlxGa(1-x)N layer 32 is removed by, for example, wet etching using an alkaline solution. This removes the unreacted AlxGa(1-x)N layer 32 not only from above the GaN layer 13 but also from within the trench H. After the unreacted AlxGa(1-x)N layer 32 is removed, a reaction layer 31 remains on the surface of the GaN layer 13 and on the bottom and side surfaces of the trench H, as shown in FIG. 9F.

[0053] Next, as shown in FIG. 9G, the manufacturing equipment forms a gate insulating film 21 by plasma CVD on the GaN layer 13 on which the reaction layer 31 remains. The bottom and side surfaces of the trench H are covered with the gate insulating film 21 via the reaction layer 31. Next, the manufacturing equipment partially etches the gate insulating film 21 and the reaction layer 31. As a result, as shown in FIG. 9H, the manufacturing equipment leaves the gate insulating film 21 and the reaction layer 31 in the region that will become the gate of the vertical MOSFET 20A and its periphery, and removes the gate insulating film 21 and the reaction layer 31 from other regions. Next, the manufacturing equipment forms a metal film above the GaN layer 13 and patterns the formed metal film to form the gate electrode 22. The metal film that constitutes the gate electrode 22 is formed by vapor deposition, sputtering, or the like. The metal film is patterned by dry etching or a lift-off method.

[0054] Next, the manufacturing equipment forms an insulating film 27 (see FIG. 8) by plasma CVD or the like. Next, the manufacturing equipment partially etches the insulating film 27 to form contact holes. Next, the manufacturing equipment forms a source electrode 25 (see FIG. 8) so as to fill the contact holes. The metal film that constitutes the source electrode 25 is formed by vapor deposition, sputtering, or the like. The metal film is patterned by dry etching or a lift-off method. Next, the manufacturing equipment forms drain electrode 26 (see FIG. 8) on rear surface 11b of GaN single crystal substrate 11. The metal film that constitutes drain electrode 26 is formed by vapor deposition, sputtering, or the like. Through the above steps, GaN semiconductor device 1A shown in FIGS. 7 and 8 is completed.

[0055] (Effects of the second embodiment) Similar to the first embodiment, the method for manufacturing GaN semiconductor device 1A according to the second embodiment of the present invention includes the steps of forming an AlxGa(1-x)N layer 30 on an Mg-doped GaN layer 13′, subjecting AlxGa(1-x)N layer 30 and GaN layer 13′ to a heat treatment in a hydrogen-free atmosphere at a maximum temperature of 1100°C or higher (step ST4 in FIG. 5; an example of the “first heat treatment” according to the present invention) to form a reaction layer 31, and removing unreacted AlxGa(1-x)N layer 32 from the P-type GaN layer 13. According to this, the first heat treatment can remove hydrogen contained in GaN layer 13' while activating Mg doped in GaN layer 13', thereby changing the conductivity type of GaN layer 13' to P-type. Furthermore, the first heat treatment can directly form reaction layer 31 (e.g., AlGaN) on P-type GaN layer 13.

[0056] For example, because the underlying GaN layer 13' has a single-crystal structure, AlGaN with good crystallinity can be formed directly on the P-type GaN layer 13 as the reaction layer 31, resulting in an AlGaN / GaN junction with a good interface. The lattice constants of both materials near the AlGaN / GaN junction interface are identical or nearly identical. This suppresses electron scattering near the AlGaN / GaN junction interface, lengthening the mean free path of electrons in the channel region of the vertical MOSFET 20A. This allows for the formation of a vertical MOSFET 20A with a trench gate structure and high mobility.

[0057] <Embodiment 3> The present invention may be applied to a vertical MOSFET with a planar structure.

[0058] (Configuration example) FIG. 10 is a plan view showing a configuration example of GaN semiconductor device 1B (an example of the "nitride semiconductor device" of the present invention) according to embodiment 3 of the present invention. FIG. 11 is a cross-sectional view showing a configuration example of GaN semiconductor device 1B according to embodiment 3. Note that source electrode 25 and insulating film 27 shown in FIG. 11 are omitted from FIG. 10. FIG. 11 also shows a cross section taken along line X3-X'3 of the plan view of FIG. 10. 10 and 11, a GaN semiconductor device 1A includes a GaN substrate 10A and a plurality of vertical MOSFETs 20B provided on the GaN substrate 10A. In the GaN semiconductor device 1B, the vertical MOSFETs 20B are repeatedly provided in one direction (for example, the X-axis direction). Each vertical MOSFET 20B is a repeated unit structure, and these unit structures are arranged side by side in one direction (for example, the X-axis direction). For example, in the GaN semiconductor device 1B, vertical MOSFETs 20B that are elongated in the Y-axis direction are arranged side by side in the X-axis direction, and are arranged in a striped pattern in a plan view.

[0059] 11, the vertical MOSFET 20B has a planar structure. For example, the vertical MOSFET 20B has a gate electrode 22 provided on a flat gate insulating film 21. The vertical MOSFET 20B also has a structure in which a P-type second GaN layer 13 and an N+-type source region 23 are disposed doubly on the surface side of an N-type first GaN layer 12. Because of this structure, the vertical MOSFET 20B may be called a vertical MOSFET with a DMOS structure.

[0060] As shown in FIG. 11 , the vertical MOSFET 20B has an N-type region 28 provided in the P-type second GaN layer 13 and the N-type first GaN layer 12. The N-type region 28 is part of the drift region and may also be called a JFET region. The drift region functions as a current path between the N+ type GaN single crystal substrate 11 and a channel formed in the P-type second GaN layer 13. The N-type region 28 has a higher concentration of N-type impurities and a lower electrical resistance than other drift regions (e.g., the first GaN layer 12). The provision of the N-type region 28 can reduce the on-resistance of the vertical MOSFET 20B.

[0061] In vertical MOSFET 20B, a reaction layer 31 containing crystalline AlGaN exists between second GaN layer 13, where a channel is formed, and gate insulating film 21. This creates a region between second GaN layer 13 and gate insulating film 21 where the Al concentration is maximum in second GaN layer 13. For example, if gate insulating film 21 is made of a SiO film, an Al concentration peak exists between P-type GaN layer 13 and gate insulating film 21, as shown in FIG.

[0062] (Manufacturing method) Next, a method for manufacturing the GaN semiconductor device 1B will be described. FIGS. 12A to 12G are cross-sectional views illustrating the manufacturing method of the GaN semiconductor device 1B according to the third embodiment in the order of steps. FIGS. 12A to 12G illustrate the manufacturing method of one vertical MOSFET 20B among multiple vertical MOSFETs 20B repeatedly arranged in the X-axis direction in the order of steps. The GaN single crystal substrate 11 shown in FIG. 11 is omitted from FIGS. 12A to 12G. 12A, the manufacturing equipment epitaxially grows a Si-doped N-type first GaN layer 12 on a GaN single crystal substrate 11 (see FIG. 12), and then epitaxially grows a Mg-doped second GaN layer 13′ on first GaN layer 12. The epitaxial growth of first GaN layer 12 and second GaN layer 13′ is performed continuously in the same chamber without being exposed to the atmosphere midway.

[0063] Next, the manufacturing equipment applies a heat treatment (an example of the "second heat treatment" of the present invention) to the entire substrate including the Mg-doped second GaN layer 13' to remove hydrogen contained in the second GaN layer 13'. This heat treatment is performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2). Preferably, this heat treatment is performed in an atmosphere containing at least one of nitrogen (N2) and oxygen (O2) but not hydrogen (H2). The maximum temperature of this heat treatment is, for example, 650°C or higher and 850°C or lower. Next, the manufacturing equipment ions-implants N-type impurities (e.g., Si, O, or Ge) into a region 28' in second GaN layer 13' where N-type region 28 will be formed (hereinafter referred to as N-type formation region). This ion implantation makes the N-type impurity concentration in N-type formation region 28' higher than the N-type impurity concentration in first GaN layer 12.

[0064] Next, as shown in FIG. 12B, the manufacturing equipment ions-implants N-type impurities (for example, Si) into source formation regions 23' in second GaN layer 13'. Next, as shown in FIG. 12C, the manufacturing apparatus forms an AlxGa(1-x)N layer (0 < x ≦ 1) 30 on the second GaN layer 13'. Similar to Embodiments 1 and 2, in Embodiment 3 as well, the AlxGa(1-x)N layer 30 is formed by a thermal CVD method or an ALD method. The crystal structure of the AlxGa(1-x)N layer 30 is polycrystalline or amorphous. The surface of the second GaN layer 13' is covered with the AlxGa(1-x)N layer (0 < x ≦ 1) 30.

[0065] Next, the manufacturing apparatus performs heat treatment on the entire substrate including the AlxGa(1-x)N layer 30 and the second GaN layer 13' in an atmosphere not containing hydrogen, causing the AlxGa(1-x)N layer 30 and the second GaN layer 13' to react with each other. The maximum temperature of this heat treatment is, for example, 1100°C or higher and 1300°C or lower. By this heat treatment, as shown in FIG. 12D, a reaction layer 31 with a higher Al concentration than the second GaN layer 13 is formed at the interface between the AlxGa(1-x)N layer 30 and the second GaN layer 13.

[0066] Also, by this heat treatment, Mg doped in the second GaN layer 13' is activated, and the second GaN layer 13' becomes a P-type second GaN layer 13. Also, by this heat treatment, N-type impurities ion-implanted in the N-type formation region 28' and N-type impurities ion-implanted in the source formation region 23' are activated, the N-type formation region 28' becomes the N-type region 28, and the source formation region 23' becomes the N+-type source region 23. Also, by this heat treatment, defects generated by ion implantation of N-type impurities in the N-type region 28 and the source region 23 can be recovered to some extent.

[0067] The subsequent steps are the same as in Embodiment 2. For example, the manufacturing apparatus removes the unreacted AlxGa(1-x)N layer 32 that did not react with the GaN layer 13' in the above heat treatment from the P-type GaN layer 13. The removal of the unreacted AlxGa(1-x)N layer 32 is performed, for example, by wet etching using an alkaline solution. After removing the unreacted AlxGa(1-x)N layer 32, as shown in FIG. 12E, the reaction layer 31 remains on the surface of the GaN layer 13.

[0068] 12F, the manufacturing equipment forms a gate insulating film 21 by plasma CVD on the GaN layer 13 on which the reaction layer 31 remains. Next, the manufacturing equipment partially etches the gate insulating film 21 and the reaction layer 31. As a result, as shown in FIG. 12G, the manufacturing equipment leaves the gate insulating film 21 and the reaction layer 31 in the region that will become the gate of the vertical MOSFET 20A and its periphery, and removes the gate insulating film 21 and the reaction layer 31 from other regions.

[0069] Next, the manufacturing equipment forms gate electrode 22 above GaN layer 13. Next, the manufacturing equipment forms insulating film 27 (see FIG. 11). Next, the manufacturing equipment partially etches insulating film 27 to form contact holes. Next, the manufacturing equipment forms source electrode 25 (see FIG. 11) so as to fill the contact holes. Next, the manufacturing equipment forms drain electrode 26 (see FIG. 11) on back surface 11b of GaN single crystal substrate 11. Through the above steps, GaN semiconductor device 1B shown in FIGS. 10 and 11 is completed.

[0070] (Effects of the third embodiment) The method for manufacturing a GaN semiconductor device 1B according to the third embodiment of the present invention includes the same steps as those of the second embodiment. In the third embodiment, as in the second embodiment, the first heat treatment at a maximum temperature of 1100°C or higher can activate the Mg doped in the GaN layer 13′ while removing hydrogen contained in the GaN layer 13′, thereby converting the conductivity type of the GaN layer 13′ to P-type. Furthermore, the first heat treatment can directly form a reaction layer 31 (e.g., AlGaN) on the P-type GaN layer 13. In the third embodiment, as in the second embodiment, AlGaN with good crystallinity can be formed as the reaction layer 31 directly on the P-type GaN layer 13, resulting in an AlGaN / GaN junction with a good interface. This allows a vertical MOSFET 20B with a planar structure and high mobility to be formed.

[0071] <Modification> In the above-described first to third embodiments, a heat treatment (an example of the "second heat treatment" of the present invention) is performed to remove hydrogen contained in the GaN layer after epitaxial growth of the Mg-doped GaN layer (second GaN layer). However, in the embodiments of the present invention, the second heat treatment may be omitted. Even in this case, by performing a heat treatment (an example of the "first heat treatment" of the present invention) to react the AlxGa(1-x)N layer and the GaN layer (second GaN layer) with each other, it is possible to remove hydrogen from the GaN layer (second GaN layer) to some extent and promote activation of the Mg doped in the GaN layer (second GaN layer).

[0072] In the above-described first to third embodiments, the GaN layer (second GaN layer) is doped with Mg during epitaxial growth. However, the method of Mg doping is not limited to this in the embodiments of the present invention. The Mg doping may be performed by ion implantation of Mg after epitaxial growth of an undoped GaN layer (second GaN layer). Even in such a case, by performing at least the first heat treatment described above, hydrogen in the GaN layer (second GaN layer) can be removed, and activation of the doped Mg can be promoted. In the above-described second embodiment, the vertical MOSFETs 20A are arranged in a stripe pattern in a plan view. In the above-described third embodiment, the vertical MOSFETs 20B are arranged in a stripe pattern in a plan view. However, in the second and third embodiments of the present invention, the arrangement of the vertical MOSFETs is not limited to the stripe pattern.

[0073] FIG. 13 is a plan view showing a first variation of the layout of the vertical MOSFET 20A. As shown in FIG. 13, the N+ type source region 23 and the P-type second GaN layer 13 of the vertical MOSFET 20A may be formed in a square shape in plan view. The source region 23 and the second GaN layer 13, each formed in a square shape in plan view, may be arranged side by side at regular intervals in the X-axis direction and the Y-axis direction. Cutting the plan view shown in FIG. 13 along line X4-X'4 results in a cross section like that shown in FIG. 8. Even with this configuration, the same effects as those of the second embodiment can be achieved. The square layout shown in FIG. 13 may also be applied to the vertical MOSFET 20B according to the third embodiment.

[0074] FIG. 14 is a plan view showing a second variation of the vertical MOSFET 20A. As shown in FIG. 14, the N+ type source region 23 and the P-type second GaN layer 13 of the vertical MOSFET 20A may be formed in a hexagonal shape in plan view. The source region 23 and the second GaN layer 13 formed in a hexagonal shape in plan view may be arranged side by side at regular intervals in the X-axis direction and the Y-axis direction, respectively. Cutting the plan view shown in FIG. 14 along line X5-X'5 results in a cross section like that shown in FIG. 8. Even with this configuration, the same effects as those of the second embodiment can be achieved. The hexagonal arrangement shown in FIG. 14 may also be applied to the vertical MOSFET 20B according to the third embodiment.

[0075] <Embodiment 4> A GaN semiconductor device according to an embodiment of the present invention may include an active region through which current flows when the MOSFET is in an on-state, and a non-active region that surrounds the active region in a plan view in the thickness direction (e.g., the Z-axis direction) of the GaN semiconductor device. The non-active region may have the function of preventing electric field concentration in the active region by expanding a depletion layer generated in the active region to the non-active region. A structure in the non-active region that has the function of preventing electric field concentration is also called a breakdown voltage structure.

[0076] Here, the inventors have found that when the present invention is applied to a GaN semiconductor device having a breakdown voltage structure, there is a possibility that surface leakage in the off state (i.e., during breakdown voltage) may increase. This is thought to be because, if a reaction layer exists between the GaN substrate and the insulating film (e.g., field insulating film) covering the GaN substrate in the inactive region, the interface between the GaN substrate and the insulating film becomes an AlN / GaN heterojunction, generating carriers that become a source of leakage. Therefore, in the embodiment of the present invention, the reaction layer may be left between the GaN substrate and the gate insulating film, and removed from other regions.

[0077] (Configuration example) Fig. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device 1C according to Embodiment 4 of the present invention. As shown in Fig. 15, GaN semiconductor device 1C includes a GaN substrate 10A, multiple vertical MOSFETs 20C provided in an active region R1 of GaN substrate 10A, a breakdown voltage structure 40 provided in an inactive region R2 of GaN substrate 10A, and a field insulating film 61 provided on the inactive region R2 of GaN substrate 10A. Field insulating film 61 is made of, for example, SiO2.

[0078] The vertical MOSFET 20C is a vertical MOSFET with a planar structure and a DMOS structure, similar to the vertical MOSFET 20B shown in Figures 10 and 11. The GaN semiconductor device 1C has a structure in which one vertical MOSFET 20C (unit structure) is repeatedly provided in one direction (for example, the X-axis direction), similar to the GaN semiconductor device 1B shown in Figures 10 and 11.

[0079] GaN semiconductor device 1C also has a plurality of guard ring structures 41 spaced apart from one another as breakdown voltage structure 40. Guard ring structure 41 is a structure in which a plurality of thin P-type layers surround active region R1 in a ring shape. Alternatively, breakdown voltage structure 40 may have a single guard ring structure 41 surrounding active region R1 in a ring shape, rather than multiple guard ring structures. Guard ring structure 41 may be a P-type layer with the same concentration and depth as P-type second GaN layer 13, or may be a separate P-type layer with a different concentration and depth from P-type second GaN layer 13. For example, guard ring structure 41 may be a P+ type layer with a higher P-type concentration than P-type second GaN layer 13. GaN semiconductor device 1C has guard ring structure 41, which makes it easier for the depletion layer in the off state to spread to the outer peripheral edge of first GaN layer 12. This allows GaN semiconductor device 1C to have an improved breakdown voltage compared to a device without guard ring structure 41.

[0080] In the vertical MOSFET 20C, after the reaction layer 31 is formed on the GaN substrate 10A, the reaction layer 31 is left in the region where the gate insulating film 21 is to be formed, and is removed from other regions. For example, in FIG. 15 , the region directly below the gate insulating film 21 corresponds to the region where the gate insulating film 21 is to be formed. As a result, the maximum Al concentration at the interface between the GaN substrate 10A and the insulating film other than the gate insulating film 21 is lower than the Al concentration peak present between the GaN substrate 10A and the gate insulating film 21.

[0081] For example, in the non-active region R2, the reaction layer 31 is removed from the entire area on the GaN substrate 10A. As a result, the maximum Al concentration at the interface between the field insulating film 61 formed after the removal of the reaction layer 31 and the GaN substrate 10A is lower than the Al concentration peak between the gate insulating film 21 and the GaN substrate 10A. At the interface between the field insulating film 61 and the GaN substrate 10A, there is no AlN / GaN heterojunction, and no carriers are generated by the AlN / GaN heterojunction.

[0082] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 1C will be described. FIGS. 16A to 16D are cross-sectional views showing the manufacturing method of GaN semiconductor device 1C according to embodiment 4 in the order of steps. In FIG. 16A, the manufacturing method is the same as that of GaN semiconductor device 1B described in embodiment 3, for example, up to the step of forming reaction layer 31. The thickness of reaction layer 31 is, for example, 1 nm or more and 5 nm or less. Note that P-type guard ring structure 41 is formed in advance by ion implantation, activation heat treatment, and the like, before forming reaction layer 31.

[0083] Next, as shown in FIG. 16B, the manufacturing equipment forms a mask 71 on the GaN substrate 10A. The mask 71 is made of an SiO2 film, an Al2O3 film, or a photoresist. The mask 71 has a shape that covers the region where the gate insulating film 21 (see FIG. 15) is to be formed and exposes the other regions. Next, the manufacturing equipment removes the reaction layer 31 exposed from the mask 71 by dry etching. As a result, as shown in FIG. 16C, the reaction layer 31 remains in the region where the gate insulating film 21 is to be formed and is removed from the other regions. After the reaction layer 31 has been partially removed in this manner, the manufacturing equipment removes the mask 71 from the GaN substrate 10A.

[0084] Next, the manufacturing equipment forms an insulating film on GaN substrate 10A and partially etches this insulating film to form gate insulating film 21 on reaction layer 31, as shown in Fig. 16D. Gate insulating film 21 is, for example, a silicon oxide film (SiO2 film), and its thickness is not less than 50 nm and not more than 200 nm. Next, the manufacturing equipment forms a conductive film on GaN substrate 10A on which gate insulating film 21 has been formed, and partially etches this conductive film to form gate electrode 22 and source electrode 25. The manufacturing equipment may form source electrode 25 simultaneously with gate electrode 22, or may form source electrode 25 in a step separate from that for gate electrode 22.

[0085] The gate electrode 22 and the source electrode 25 may be a single layer film containing, for example, any one of titanium (Ti), titanium nitride (TiN), aluminum (Al), nickel (Ni), tungsten (W), tungsten silicide (W-Si), and polysilicon (Poly-Si), or a laminated film containing any one or more of these. Also, around the time of the process of forming gate electrode 22, the manufacturing equipment forms field insulating film 61 on inactive region R2 (see FIG. 15) of GaN substrate 10A. Field insulating film 61 is, for example, a SiO2 film, and its thickness is not less than 400 nm and not more than 1000 nm. Through the above processes, GaN semiconductor device 1C shown in FIG. 15 is completed.

[0086] (Effects of the fourth embodiment) The method for manufacturing GaN semiconductor device 1C according to embodiment 4 of the present invention further includes the step of partially removing reaction layer 31 before forming gate insulating film 21. In the step of partially removing reaction layer 31, reaction layer 31 is left in the region where gate insulating film 21 is to be formed, and reaction layer 31 is removed from regions other than the planned region. This allows the maximum Al concentration at the interface between GaN substrate 10A and an insulating film other than gate insulating film to be lower than the Al concentration peak present between GaN substrate 10A and gate insulating film .

[0087] For example, the maximum Al concentration at the interface between the field insulating film 61 in the non-active region R2 and the GaN substrate 10A can be set to a value lower than the Al concentration peak that exists between the gate insulating film 21 in the active region R1 and the GaN substrate 10A. At the interface between the GaN substrate 10A and the field insulating film 61, there is no AlN / GaN heterojunction, and no carriers are generated by the AlN / GaN heterojunction, so surface leakage at the time of breakdown voltage can be suppressed.

[0088] 17 is a graph showing the results of comparing the breakdown voltage characteristics of the example of the present invention and the comparative example. In FIG. 17, the vertical axis represents the voltage (V) applied between the drain and source in the off state (when the breakdown voltage is applied), and the vertical axis represents the current density (A / cm 2 ) is shown. The example of FIG. 17 has a configuration similar to that of the GaN semiconductor device 1C shown in FIG. 15. In the example of FIG. 17, a process for partially removing the reaction layer 31 is performed. Therefore, in the example, the reaction layer 31 does not exist between the GaN substrate 10A and the field insulating film 61. In contrast, in the comparative example of FIG. 17, a process for partially removing the reaction layer 31 is not performed. Therefore, in the comparative example, the reaction layer 31 exists between the GaN substrate 10A and the field insulating film 61. In the example and the comparative example of FIG. 17, the donor element concentration Nd of the N-type first GaN layer 12 (see FIG. 15), which is the drift layer, is the same value, 2×10 16 cm -3 is. As shown in FIG. 17, it was confirmed that the example had a smaller leakage current and a higher breakdown voltage than the comparative example.

[0089] (Variation 1) In the above-described fourth embodiment, the portion of the reaction layer 31 formed in the region other than the region where the gate insulating film 21 is to be formed is removed by dry etching. However, in the embodiments of the present invention, the method for partially removing the reaction layer 31 is not limited to dry etching. For example, the reaction layer 31 may be partially removed by sacrificial oxidation. 18A to 18C are cross-sectional views showing the process sequence of another method (variation 1) for manufacturing GaN semiconductor device 1C according to embodiment 4. In Fig. 18A, the steps up to the step of forming reaction layer 31 are the same as the method for manufacturing GaN semiconductor device 1B described in embodiment 3, for example. In this modification 1, after the reaction layer 31 is formed, the manufacturing equipment forms an oxidation-resistant mask 73 on the reaction layer 31. The oxidation-resistant mask 73 has a shape that covers a region where the gate insulating film 21 (see FIG. 15) is to be formed and exposes other regions. The material that forms the oxidation-resistant mask 73 is, for example, SiO2.

[0090] Next, the manufacturing equipment thermally oxidizes the GaN substrate 10A on which the oxidation-resistant mask 73 has been formed. This thermal oxidation oxidizes the portion of the reaction layer 31 exposed from the oxidation-resistant mask 73 and the vicinity of the surface of the GaN substrate 10A located directly below this portion, forming a sacrificial oxide film 75 as shown in FIG. 18B. The sacrificial oxide film 75 is made of, for example, gallium oxide (GaO). Next, the manufacturing equipment removes the sacrificial oxide film 75 by wet etching. As a result, the reaction layer 31 is partially removed as shown in FIG. 18C. Thereafter, the manufacturing equipment removes the oxidation-resistant mask 73 from the GaN substrate 10A.

[0091] The subsequent steps are the same as those described with reference to Figures 16C and 16D. Even with this method, reaction layer 31 can be partially removed, and GaN semiconductor device 1C shown in Figure 15 can be manufactured. Furthermore, because sacrificial oxide film 75 is removed by wet etching, etching damage to the surface of GaN substrate 10A underlying sacrificial oxide film 75 can be suppressed.

[0092] (Variation 2) In the above-described fourth embodiment, the GaN semiconductor device 1C may have a multilayer wiring structure. FIG. 19 is a cross-sectional view showing another configuration example (variation 2) of the GaN semiconductor device 1C according to the fourth embodiment. FIG. 20 is a plan view showing variation 2 of the GaN semiconductor device 1C according to the fourth embodiment. In variation 2, the reaction layer 31 is also present between the GaN substrate 10A and the gate insulating film 21 in the active region, but is not present in the non-active region R2. As a result, the maximum Al concentration at the interface 50 between the field insulating film 61 and the GaN substrate 10A in the non-active region R2 is lower than the Al concentration peak present between the gate insulating film 21 and the GaN substrate 10A in the active region R1. This makes it possible to suppress surface leakage at a breakdown voltage.

[0093] 19, in this modification 2, an interlayer insulating film 63 is provided on the GaN substrate 10A, and the gate electrode 22 is covered with the interlayer insulating film 63. A source pad 25P connected to the source electrode 25 is provided on the interlayer insulating film 63. In the active region, the source pad 25P is disposed above the gate electrode 22 with the interlayer insulating film 63 interposed therebetween. This allows the source pad 25P to be disposed in the active region, and as shown in Fig. 20, the gate wiring 22L connected to the gate electrode 22 and the gate pad 22P connected to the gate electrode 22 via the gate wiring 22L can be disposed on the interlayer insulating film 63. This improves the degree of freedom in layout regarding the routing of wiring and the arrangement of the source pad 25P and the gate pad 22P. Furthermore, since the source pad 25P and the gate pad 22P can be disposed in the active region, this can contribute to the miniaturization of the GaN substrate 10A.

[0094] 19, in the non-active region R2, the gate insulating film 21 is disposed on the field insulating film 61. This structure can be realized by removing the reaction layer 31 from the non-active region R2, forming the field insulating film 61 in the non-active region R2, and then simultaneously forming the gate insulating film 21 on the reaction layer 31 in the active region R1 and on the field insulating film 61 in the non-active region R2 in the same process. In this structure, the insulating film covering the guard ring structure 41 is a thick film that includes three films (layers): the field insulating film 61, the gate insulating film 21, and the interlayer insulating film 63. This makes it possible to keep the parasitic capacitance between the wiring or the like and the GaN substrate 10A in the non-active region R2 small, even when the wiring or the like is disposed on the interlayer insulating film 63 in the non-active region R2.

[0095] (Variation 3) In the above fourth embodiment, it has been described that the GaN semiconductor device 1C has the guard ring structure 41 as the breakdown voltage structure 40. However, the breakdown voltage structure 40 is not limited to the guard ring structure 41. The breakdown voltage structure 40 may have a JTE (Junction Termination Extension) structure.

[0096] 21 is a cross-sectional view showing yet another configuration example (Variation 3) of GaN semiconductor device 1C according to Embodiment 4. In Variation 3, reaction layer 31 is also present between GaN substrate 10A and gate insulating film 21 in the active region, but is not present in non-active region R2. As a result, the maximum Al concentration at interface 50 between field insulating film 61 and GaN substrate 10A in non-active region R2 is lower than the Al concentration peak present between gate insulating film 21 and GaN substrate 10A in active region R1. This makes it possible to suppress surface leakage at high breakdown voltages.

[0097] 21, the breakdown voltage structure 40 has a JTE structure 43. The JTE structure 43 is formed of a P-type layer that is in contact with the P-type second GaN layer 13 and that is arranged to surround the active region R1 in a plan view from the Z-axis direction. GaN semiconductor device 1C has JTE structure 43, which makes it easier for the depletion layer in the off state to spread to the outer edge of first GaN layer 12. This allows GaN semiconductor device 1C to have an improved breakdown voltage compared to a device without JTE structure 43.

[0098] (Variation 4) In the above-described fourth embodiment, the MOS transistor included in the GaN semiconductor device 1C is not limited to the vertical MOSFET 20C having a planar structure. Fig. 22 is a cross-sectional view showing yet another configuration example (variation 4) of the GaN semiconductor device 1C according to the fourth embodiment. As shown in Fig. 22, the GaN semiconductor device 1C includes a vertical MOSFET 20D having a trench gate structure. In this fourth modification, too, reaction layer 31 exists between GaN substrate 10A and gate insulating film 21 in the active region, but does not exist in non-active region R2. As a result, the maximum Al concentration at interface 50 between field insulating film 61 and GaN substrate 10A in non-active region R2 is lower than the Al concentration peak that exists between gate insulating film 21 and GaN substrate 10A in active region R1. This makes it possible to suppress surface leakage at high breakdown voltage.

[0099] (Variation 5) Fig. 23 is a cross-sectional view showing yet another configuration example (Modification 5) of GaN semiconductor device 1C according to Embodiment 4. As shown in Fig. 23, GaN semiconductor device 1C may have the configurations of both Modification 3 and Modification 4. That is, GaN semiconductor device 1C may have a JTE structure 43 and a vertical MOSFET 20D with a trench gate structure. In this modification 5, too, reaction layer 31 exists between GaN substrate 10A and gate insulating film 21 in the active region, but does not exist in non-active region R2. As a result, the maximum Al concentration at interface 50 between field insulating film 61 and GaN substrate 10A in non-active region R2 is lower than the Al concentration peak that exists between gate insulating film 21 and GaN substrate 10A in active region R1. This makes it possible to suppress surface leakage at high breakdown voltages.

[0100] <Other embodiments> As described above, the present invention has been described with reference to embodiments and modifications. However, the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. It goes without saying that the present invention also encompasses various embodiments not described herein. Various omissions, substitutions, and / or modifications of components may be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely illustrative and not limiting, and other effects may also be present. The technical scope of the present invention is defined solely by the specific aspects of the invention as defined in the claims that are appropriate from the above description. [Explanation of symbols]

[0101] 1, 1A, 1B, 1C GaN semiconductor device 10, 10A GaN substrate 11 GaN single crystal substrate 11a surface 11b Back side 12 1st GaN layer 13 GaN layer (2nd GaN layer) 20 Horizontal MOSFET 20A, 20B, 20C, 20D vertical MOSFET 21 Gate insulating film 22 gate electrode 22L Gate wiring 22P gate pad 23 Source Region 23´ Source formation region 24 Drain region 24´ Drain formation region 25 Source electrode 25P Sauce Pad 26 Drain electrode 27 Insulating film 28 N-type region 29 P+ type region 28´ N-type formation area 30 AlxGa(1-x)N layer (0 <x≦1)31 Reaction layer 32 Unreacted AlxGa(1-x)N layer (0 <x≦1)40 Pressure-resistant structure 41 Guard ring structure 43 JTE structure 50 Interface 61 Field insulating film 63 Interlayer insulating film 71 Mask 73 Anti-oxidation mask 75 Sacrificial oxide film H Trench R1 active region R2 Inactive region

Claims

1. forming an AlxGa(1-x)N layer (0<x≦1) on the Mg-doped GaN layer; a step of subjecting the AlxGa(1-x)N layer (0<x≦1) and the GaN layer to a first heat treatment at a maximum temperature of 1100°C or higher in a hydrogen-free atmosphere to react the AlxGa(1-x)N layer (0<x≦1) and the GaN layer with each other, thereby forming a reaction layer of the AlxGa(1-x)N layer (0<x≦1) and the GaN layer; removing an unreacted AlxGa(1-x)N layer (0<x≦1) that did not react with the GaN layer in the first heat treatment from above the GaN layer.

2. 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said first heat treatment activates Mg doped into said GaN layer.

3. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the maximum temperature of said first heat treatment is 1100°C or higher and 1300°C or lower.

4. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the first heat treatment is performed in an atmosphere containing no oxygen.

5. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the first heat treatment is performed in an atmosphere containing nitrogen.

6. 6. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the step of removing the unreacted AlxGa(1-x)N layer (0<x≦1) from the GaN layer is performed by wet etching using an alkaline solution.

7. 7. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of: before forming the AlxGa(1-x)N layer (0<x≦1), performing a second heat treatment on the GaN layer in an atmosphere containing at least one of nitrogen and oxygen to remove hydrogen contained in the GaN layer.

8. The method for manufacturing a nitride semiconductor device according to claim 7 , wherein the maximum temperature of said second heat treatment is 650° C. or more and 850° C. or less.

9. 9. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of forming a gate insulating film on the GaN layer after removing the unreacted AlxGa(1-x)N layer (0<x≦1).

10. The gate insulating film is made of SiO ２ Membrane, Al ２ O ３ 10. The method for manufacturing a nitride semiconductor device according to claim 9, wherein the nitride semiconductor device comprises at least one of a nitride film, a SiON film, an AlSiO film, and an AlON film.

11. before forming the gate insulating film, further comprising a step of partially removing the reaction layer; In the step of partially removing the reaction layer, The method for manufacturing a nitride semiconductor device according to claim 9 , wherein the reaction layer is left in a region where the gate insulating film is to be formed, and the reaction layer is removed from regions other than the region where the gate insulating film is to be formed.

12. In the step of partially removing the reaction layer, The reaction layer is removed by dry etching the portion formed in the region other than the predetermined region. The method for manufacturing a nitride semiconductor device according to claim 11 , further comprising removing the nitride semiconductor layer.

13. In the step of partially removing the reaction layer, The method for manufacturing a nitride semiconductor device according to claim 11 , further comprising the steps of thermally oxidizing a portion of the reaction layer formed in a region other than the planned region to form a sacrificial oxide film, and removing the sacrificial oxide film by wet etching.

14. 14. The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the step of forming the AlxGa(1-x)N layer (0<x≦1), the AlxGa(1-x)N layer is formed by a thermal CVD method or an ALD method.

15. A semiconductor device comprising: an active region; and a breakdown withstanding structure region surrounding the active region in a plan view, In the active region, a first GaN layer of P-type doped with Mg; a gate insulating film provided on the first GaN layer; The Mg concentration in the first GaN layer is 1×10 １７ cm －３ 1x10 or more １８ cm －３ is as follows: an Al concentration peak exists between the first GaN layer and the gate insulating film, at which the Al concentration is maximum in the first GaN layer and the gate insulating film; In the pressure-resistant structural region, a second GaN layer of P-type doped with Mg; a field insulating film provided on the second GaN layer; a maximum value of the Al concentration at the interface between the second GaN layer and the field insulating film is lower than the Al concentration peak.

16. A nitride semiconductor device as described in Claim 15, wherein the P-type impurity concentration of the second GaN layer is the same as the P-type impurity concentration of the first GaN layer.

17. 17. The nitride semiconductor device according to claim 15, wherein the thickness of the Al-containing layer present between the first GaN layer and the gate insulating film is not less than 0.25 nm and not more than 7 nm.

18. The gate insulating film is made of SiO ２ The nitride semiconductor device according to claim 15, which is formed of a film.

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