Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing voltage drop.SOLUTION: A semiconductor device is formed so that, a relational expression (1) is satisfied between L1i, S1i in a first guard ring of the semiconductor device and L2i, S2in a second guard ring and a distance ΔXi from an outer end of an i-1-th first guard ring in a substrate plane direction, counting from the first guard ring closest to the cell area toward an outside in the plane direction of the substrate to an outer end of an i-1th second guard ring in the substrate plane direction, counting from the second guard ring closest to the cell area toward the outside in the plane direction of the substrate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, as described in Patent Document 1, a semiconductor device including a plurality of first guard rings and a plurality of second guard rings has been known. The first guard rings are provided at positions exposed on a first main surface of a substrate and surround an element region. The second guard rings are spaced apart from the first guard rings in the thickness direction of the substrate and surround the element region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-12966 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device of Patent Document 1, the dimensional design of the first and second guard rings does not take into account the relative positions of the first and second guard rings, making it impossible to suppress a resulting decrease in breakdown voltage. Specifically, in the semiconductor device of Patent Document 1, when the semiconductor device is turned off, when the drift region between the first guard rings is projected in the thickness direction of the substrate, the projected drift region overlaps the drift region between the second guard rings. As a result, when the semiconductor device is turned off, equipotential lines pass through the drift region between the second guard rings and enter the drift region between the first guard rings that overlaps the drift region. This results in locations in the drift region where the curvature of the equipotential lines is high. This causes electric field concentration in those locations, reducing the breakdown voltage of the semiconductor device.

[0005] An object of the present disclosure is to provide a semiconductor device that suppresses a decrease in breakdown voltage. [Means for solving the problem]

[0006] The invention of claim 1 is a semiconductor device comprising: a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a drift layer (12) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the front surface side of the drift layer; a second electrode (34) formed on the back surface side of the substrate and through which a current flows between the first electrode and the second electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; and a front-side guard ring (41, 42, 43, 44) formed in the drift layer and extending in the thickness direction of the substrate. and a plurality of backside guard rings (51, 52, 53, 54) of a second conductivity type that are arranged at a position away from the front side guard ring on the back side of the substrate and surround the cell region, the front side guard ring and the back side guard ring are aligned in the surface direction of the substrate, the front side guard ring and the back side guard ring that are closer to the cell region are referred to as first guard rings, and the front side guard ring and the back side guard ring that are different from the first guard ring are referred to as second guard rings, where i is a natural number and the width of the i-th first guard ring counted from the first guard ring that is closest to the cell region toward the outside in the surface direction of the substrate is L1. i The distance between the i-1th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S1 i The width of the ith second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 i The distance between the i-1th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S2 iThe distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, to the outer edge of the i-1th second guard ring in the surface direction of the substrate, counting from the second guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, is defined as ΔX i Then, the front and rear guard rings are formed so that the relation (1) holds. Or, S1 i and S2 i increases as i increases, and when α and β are real numbers greater than 1, the front guard ring and the back guard ring are formed so that the relation (2) holds. It is a semiconductor device. The invention of claim 2 is a semiconductor device comprising: a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a drift layer (12) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the front surface side of the drift layer; a second electrode (34) formed on the back surface side of the substrate and through which a current flows between the first electrode and the second electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; and a plurality of backside guard rings (51, 52, 53, 54) of a second conductivity type that are arranged at a position away from the guard rings on the backside of the substrate and surround the cell region, the frontside guard rings and the backside guard rings are aligned in the surface direction of the substrate, the frontside guard ring and the backside guard ring that is closer to the cell region is referred to as a first guard ring, and the frontside guard ring and the backside guard ring that is different from the first guard ring is referred to as a second guard ring, where i is a natural number and the width of the i-th first guard ring counted from the first guard ring that is closest to the cell region toward the outside in the surface direction of the substrate is referred to as L1. i The distance between the i-1th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S1 i The width of the ith second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 i The distance between the i-1th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S2 i The distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, to the outer edge of the i-1th second guard ring in the surface direction of the substrate, counting from the second guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, is defined as ΔX i Then, the front guard ring and the back guard ring are formed so that the relation (3) holds, and S1 i and S2 i increases as i increases, and where α is a real number greater than 1 and c is a predetermined distance, the front guard ring and the back guard ring are formed in a semiconductor device such that the relational expression (4) holds. Furthermore, the invention of claim 3 is a semiconductor device comprising: a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a drift layer (12) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the front surface side of the drift layer; a second electrode (34) formed on the back surface side of the substrate and through which a current flows between the first electrode and the second electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; and a plurality of backside guard rings (51, 52, 53, 54) of a second conductivity type that are arranged at a position away from the frontside guard rings on the backside of the substrate and surround the cell region, the frontside guard rings and the backside guard rings are aligned in the surface direction of the substrate, the frontside guard ring and the backside guard ring that is closer to the cell region is referred to as a first guard ring, and the frontside guard ring and the backside guard ring that is different from the first guard ring is referred to as a second guard ring, where i is a natural number and the width of the ith first guard ring counted from the first guard ring that is closest to the cell region toward the outside in the surface direction of the substrate is L1. i The distance between the i-1th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S1 i The width of the ith second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 i The distance between the i-1th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S2 i The distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, to the outer edge of the i-1th second guard ring in the surface direction of the substrate, counting from the second guard ring that is closest to the cell region toward the outer side of the surface direction of the substrate, is defined as ΔX i Then, the front guard ring and the back guard ring are formed so that the relation (5) holds, and S1 i and S2 i increases as i increases, and if a predetermined distance is K, the front guard ring and the back guard ring are formed in a semiconductor device such that the relational expression (6) holds.

number

number

number

number

number

number

[0007] As a result, when the drift layer between the first guard rings is projected in the thickness direction of the substrate, the projected drift layer overlaps with the second guard ring. Furthermore, when the drift layer between the second guard rings is projected in the thickness direction of the substrate, the projected drift layer overlaps with the first guard ring. This prevents equipotential lines from penetrating, smoothing the equipotential lines. This prevents the occurrence of locations in the drift layer where the curvature of the equipotential lines is high. This prevents electric field concentration, thereby preventing a decrease in the breakdown voltage of the semiconductor device.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a top view layout diagram of the semiconductor device according to the first to fourth embodiments. [Figure 2] Cross-sectional view of line II-II in Figure 1. [Figure 3] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device. [Figure 4] 4A to 4C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 3. [Figure 5] 5A to 5C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 4. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 5. [Figure 7] FIG. 10 is a cross-sectional view illustrating equipotential lines in a semiconductor device according to a comparative example. [Figure 8] FIG. 10 is a cross-sectional view of the semiconductor device when L2i is equal to the value of the left side of the relational expression (1). [Figure 9] FIG. 10 is a cross-sectional view of the semiconductor device when L2i is equal to the value of the right side of the relational expression (1). [Figure 10]FIG. 10 is a cross-sectional view illustrating equipotential lines in a semiconductor device. [Figure 11] FIG. 10 is a diagram showing the relationship between the distance from the lower first outer end of the semiconductor device and the strength of the electric field. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals, and description thereof will be omitted.

[0011] (First embodiment) The semiconductor device 1 of this embodiment is used, for example, to drive electronic devices for vehicles. Here, the semiconductor device 1 is a SiC semiconductor device in which an inversion MOSFET with a trench gate structure is formed.

[0012] Specifically, as shown in FIGS. 1 and 2, the semiconductor device 1 has n + Mold substrate 10, n - type layer 12, p-type base region 14, n + The semiconductor device 1 includes a p-type source region 16, a p-type contact region 18, and a p-type hole extraction layer 20. The semiconductor device 1 also includes a gate trench 22, a gate insulating film 24, a gate electrode 26, an interlayer insulating film 30, a source electrode 32, and a drain electrode 34. The semiconductor device 1 also includes an upper first FLR region 41, an upper second FLR region 42, an upper third FLR region 43, an upper fourth FLR region 44, a lower first FLR region 51, a lower second FLR region 52, a lower third FLR region 53, and a lower fourth FLR region 54. FLR stands for Field Limiting Ring.

[0013] n + The mold substrate 10 is made of SiC and has a rectangular shape. + The n-type impurity concentration of the substrate 10 is, for example, 1.0×10 19 / cm 3 Furthermore, n + The surface of the mold substrate 10 is, for example, a (0001) Si surface. + The off-direction of the substrate 10 is, for example, the <11-20> direction. The n-type impurity is, for example, nitrogen or phosphorus.

[0014] Here, the region in which the MOSFET is formed in the semiconductor device 1 is referred to as a cell region RC, and the region surrounding this cell region RC is referred to as a peripheral region RG.

[0015] n - The n-type layer 12 corresponds to the drift layer, and is formed in the cell region RC and the peripheral region RG. + The silicon carbide (SiC) is formed on the surface of the mold substrate 10. - The n-type impurity concentration of the n-type layer 12 is n + The n-type impurity concentration of the substrate 10 is lower than that of the substrate 10, for example, 5.0×10 15 ~2.0×10 16 / cm 3 is.

[0016] The p-type base region 14 is formed in the cell region RC by - The surface layer of the mold layer 12 is made of SiC. The p-type impurity concentration of the p-type base region 14 is, for example, 2.0×10 17 / cm 3 The thickness of the p-type base region 14 is, for example, 300 nm. The p-type impurity is, for example, aluminum or boron.

[0017] n + The p-type source region 16 is formed in the surface layer of the p-type base region 14. + The n-type impurity concentration of the n-type source region 16 is + The n-type impurity concentration is higher than that of the n-type substrate 10. + The n-type impurity concentration in the surface layer of the source region 16 is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 Also, n+ The thickness of the source region 16 is, for example, 500 nm.

[0018] The p-type contact region 18 is formed in the surface layer of the p-type base region 14. The p-type contact region 18 is also formed by two n + The p-type contact region 18 is sandwiched between the p-type source region 16. Furthermore, the p-type impurity concentration of the p-type contact region 18 is higher than the p-type impurity concentration of the p-type base region .

[0019] The p-type hole extraction layer 20 is formed on the surface of the p-type base region 14 on the peripheral region RG side of the cell region RC. The p-type impurity concentration of the p-type hole extraction layer 20 is, for example, the same as the p-type impurity concentration of the p-type contact region 18 and higher than the p-type impurity concentration of the p-type base region 14.

[0020] The gate trench 22 extends in one direction, for example, the vertical direction of the paper in FIG. 1. The gate trench 22 is also formed between the p-type base region 14 and the n-type base region 15. + The n-type source region 16 is penetrated. - The gate trench 22 has a width of, for example, 800 nm and a depth of, for example, 1000 nm. The side surfaces of the gate trench 22 are in contact with the p-type base region 14 and the n-type + The portion of the p-type base region 14 that contacts the side surface of the gate trench 22 is the n-type source region 16 when the MOSFET is in operation. + type source region 16 and n - This forms a channel region connecting with the mold layer 12 .

[0021] The gate insulating film 24 has electrical insulation properties. The gate insulating film 24 is formed on the inner wall surface of the gate trench 22, including the channel region. The gate insulating film 24 is formed, for example, by thermally oxidizing the inner wall surface of the gate trench 22 or by using a CVD method. The thickness of the gate insulating film 24 is, for example, 100 nm.

[0022] The gate electrode 26 is made of doped Poly-Si and is formed on the surface of the gate insulating film 24. This forms a trench gate structure with one longitudinal direction.

[0023] The interlayer insulating film 30 has electrical insulating properties. - Part of mold layer 12, n + It is formed on the surfaces of a part of the type source region 16, the gate insulating film 24, and the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44, which will be described later.

[0024] The source electrode 32 corresponds to the first electrode and is made of a plurality of metals, for example, metals such as Ni / Al. The source electrode 32 is connected to the n-type semiconductor layer 31 through a contact hole formed in the interlayer insulating film 30. + The n-type source region 16, the p-type contact region 18, and the p-type hole extraction layer 20 are electrically connected to the n-type source region 16, the p-type contact region 18, and the p-type hole extraction layer 20. + The portion of the source electrode 32 that contacts the p-type source region 16 is made of a metal that can make ohmic contact with the n-type SiC. The portion of the source electrode 32 that contacts the p-type contact region 18 and the p-type hole extracting layer 20 is made of a metal that can make ohmic contact with the p-type SiC.

[0025] The drain electrode 34 corresponds to the second electrode, and in the cell region RC and the peripheral region RG, + It is formed on the back side of the mold substrate 10.

[0026] The upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 correspond to a plurality of front-side guard rings of the second conductivity type, and in the outer circumferential region RG, - It is formed on the surface of the mold layer 12. +The cross section of the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 in the planar direction of the mold substrate 10, i.e., the upper surface layout, is a rectangle with rounded corners. + The upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 are each rectangular in shape in the thickness direction of the mold substrate 10. The p-type impurity concentrations of the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 are the same as the p-type impurity concentration of the p-type base region 14, for example, 2.0×10 17 / cm 3 Furthermore, the thickness of upper first FLR region 41, upper second FLR region 42, upper third FLR region 43, and upper fourth FLR region 44 is, for example, 800 nm.

[0027] The upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 are spaced apart from one another and are arranged in order with the cell region RC at the center, as follows: + They are arranged from the inside to the outside in the surface direction of mold substrate 10. That is, among upper first FLR region 41, upper second FLR region 42, upper third FLR region 43, and upper fourth FLR region 44, upper first FLR region 41 is arranged at a position closest to cell region RC. Furthermore, upper second FLR region 42 and upper first FLR region 41 are n - The mold layer 12 is sandwiched between the upper third FLR region 43 and the upper second FLR region 42, and the upper third FLR region 43 is disposed adjacent to the upper first FLR region 41. - The mold layer 12 is sandwiched between the upper fourth FLR region 44 and the upper third FLR region 43, and the upper fourth FLR region 44 is disposed adjacent to the upper second FLR region 42. - The mold layer 12 is sandwiched between the mold layer 12 and the upper third FLR region 43 .

[0028] The lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 correspond to a plurality of backside guard rings of the second conductivity type, and in the outer circumferential region RG, - The first FLR region 51, the second FLR region 52, the third FLR region 53, and the fourth FLR region 54 are formed in the mold layer 12. + In the thickness direction of the substrate 10, the n-type + The lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 are arranged on the rear surface side of the mold substrate 10. Furthermore, the upper surface layout of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 is a square with rounded corners. + The lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 are each rectangular in shape in the thickness direction of the mold substrate 10. Furthermore, the p-type impurity concentrations of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 are, for example, 1.0×10 17 ~1.0×10 19 / cm 3 The thickness of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 is, for example, 800 nm.

[0029] The lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 are spaced apart from one another and are arranged in order with the cell region RC at the center, as follows: + They are arranged from the inside to the outside in the surface direction of mold substrate 10. That is, among lower first to fourth FLR regions 51 to 54, lower first FLR region 51 is arranged in a position closest to cell region RC and in a position corresponding to upper first FLR region 41. Furthermore, lower second FLR region 52 is arranged in n-th order with lower first FLR region 51. - The mold layer 12 is sandwiched between the lower third FLR region 53 and the lower second FLR region 52, and the lower third FLR region 53 is disposed adjacent to the lower first FLR region 51. -The mold layer 12 is sandwiched between the lower fourth FLR region 54 and the lower third FLR region 53, and the lower fourth FLR region 54 is disposed adjacent to the lower second FLR region 52. - The mold layer 12 is sandwiched between the mold layer 12 and the lower third FLR region 53 .

[0030] Here, the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 that are closer to the cell region RC are referred to as first guard rings. Furthermore, the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 that are different from the first guard rings are referred to as second guard rings. Note that here, since the lower first outer end 511 is located closer to the cell region RC than the upper first outer end 411, the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 correspond to the first guard rings. Furthermore, the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 correspond to the second guard rings.

[0031] In addition, i is a natural number between 1 and 4. Furthermore, the first guard rings closest to the cell region RC are numbered n. + The width of the i-th first guard ring counted outward in the surface direction of the mold substrate 10 is L1 i The first guard ring is the one closest to the cell region RC. + The distance between the (i-1)th and i-th first guard rings counted outward in the surface direction of the mold substrate 10 is defined as S1 i Among the second guard rings, the second guard ring closest to the cell region RC is n + The width of the ith second guard ring counted outward in the surface direction of the mold substrate 10 is defined as L2 i Among the second guard rings, the second guard ring closest to the cell region RC is n + The distance between the (i-1)th and i-th second guard rings counted outward in the surface direction of the mold substrate 10 is defined as S2 i The first guard ring is the one closest to the cell region RC. +Counting from the outer edge of the i-1th first guard ring in the surface direction of the mold substrate 10 toward the outer side of the substrate, the number of second guard rings is n. + The distance from the mold substrate 10 to the outer edge of the (i-1)th second guard ring in the surface direction of the substrate is defined as ΔX i Let's say.

[0032] The upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expression (1) holds. The upper part of the following relational expression (1) means that the first guard rings are closer to the cell region RC than the second guard rings. The lower part of the following relational expression (1) means that the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the second guard rings. - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 is formed between the first guard rings. - It overlaps with the mold layer 12. The meaning of the configuration in which the lower part of the following relational expression (1) is satisfied will be described later.

[0033]

number

[0034] Furthermore, as an example of a configuration in which the above-mentioned relational expression (1) is established, the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 have the following configuration. Specifically, when the interval between the FLR regions is n + The thickness of the guard rings increases from the inside to the outside in the surface direction of the mold substrate 10. - Passing through the center of the mold layer 12 + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the other guard ring.

[0035] For the purpose of this description, n of the upper first FLR regions 41 + The end on the outer side in the surface direction of the mold substrate 10 is defined as the upper first outer end 411. + The end on the outer side in the surface direction of the mold substrate 10 is defined as the upper second outer end 421. + The end on the outer side in the surface direction of the mold substrate 10 is defined as the upper third outer end 431. + The end on the outer side in the surface direction of the mold substrate 10 is defined as the upper fourth outer end 441. + The end on the inner side in the surface direction of the mold substrate 10 is defined as the upper first inner end 412. + The end on the inner side in the surface direction of the mold substrate 10 is defined as the upper second inner end 422. + The end on the inner side in the surface direction of the mold substrate 10 is defined as the upper third inner end 432. + The end on the inner side in the surface direction of the mold substrate 10 is defined as an upper fourth inner end 442 .

[0036] Furthermore, the distance from the upper first outer end 411 to the upper second inner end 422 is defined as the upper first interval Su1. The distance from the upper second outer end 421 to the upper third inner end 432 is defined as the upper second interval Su2. The distance from the upper third outer end 431 to the upper fourth inner end 442 is defined as the upper third interval Su3. The distance from the upper second inner end 422 to the upper second outer end 421 is defined as the upper first region distance Lu1. The distance from the upper third inner end 432 to the upper third outer end 431 is defined as the upper second region distance Lu2. The distance from the upper fourth inner end 442 to the upper fourth outer end 441 is defined as the upper third region distance Lu3.

[0037] Furthermore, n of the lower first FLR regions 51 + The end on the outer side in the surface direction of the mold substrate 10 is defined as a lower first outer end 511. + The end on the outer side in the surface direction of the mold substrate 10 is defined as a lower second outer end 521. + The end on the outer side in the surface direction of the mold substrate 10 is defined as a lower third outer end 531.+ The end on the outer side in the surface direction of the mold substrate 10 is defined as a lower fourth outer end 541. + The end on the inner side in the surface direction of the mold substrate 10 is defined as the lower first inner end 512. + The end on the inner side in the surface direction of the mold substrate 10 is defined as a lower second inner end 522. + The end on the inner side in the surface direction of the mold substrate 10 is defined as a lower third inner end 532. + The end on the inner side in the surface direction of the mold substrate 10 is defined as a lower fourth inner end 542 .

[0038] Furthermore, the distance from the lower first outer end 511 to the lower second inner end 522 is defined as the lower first distance Sd1. The distance from the lower second outer end 521 to the lower third inner end 532 is defined as the lower second distance Sd2. The distance from the lower third outer end 531 to the lower fourth inner end 542 is defined as the lower third distance Sd3. The distance from the lower second inner end 522 to the lower second outer end 521 is defined as the lower first region distance Ld1. The distance from the lower third inner end 532 to the lower third outer end 531 is defined as the lower second region distance Ld2. The distance from the lower fourth inner end 542 to the lower fourth outer end 541 is defined as the lower third region distance Ld3.

[0039] Furthermore, the distance from the lower first outer end 511 to the upper first outer end 411 is defined as the first difference ΔXr1. The distance from the lower second outer end 521 to the upper second outer end 421 is defined as the second difference ΔXr2. The distance from the lower third outer end 531 to the upper third outer end 431 is defined as the third difference ΔXr3.

[0040] The lower first outer end 511 is located closer to the cell region RC than the upper first outer end 411. The upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expressions (2-1) to (2-8) hold. In the following relational expressions (2-1) to (2-4), ΔS is a predetermined distance greater than 0. ΔS is set by experiments, simulations, etc. In the following relational expressions (2-5) to (2-8), K is a predetermined distance. K is set by experiments, simulations, etc. so that the sum of each interval and the distance from the inner end to the outer end of each FLR is constant.

[0041]

number

[0042] In addition, here, the upper first FLR region 41 to n + The i-th FLR region toward the outside in the surface direction of the mold substrate 10 is defined as the upper (i+1)th FLR region. + The outer end of the mold substrate 10 in the surface direction is defined as the upper i-th outer end. + The end on the inner side in the surface direction of the mold substrate 10 is defined as the upper i-th inner end. The distance from the upper i-th outer end to the upper i+1-th inner end is defined as the upper i-th interval Su i The distance from the upper i-th inner end to the upper i-th outer end is the upper i-th region distance Lu i The distance from the lower i-th outer end to the lower i+1-th inner end is the lower i-th interval Sd i The distance from the lower i-th inner end to the lower i+1-th outer end is the lower i-th region distance Ld i The distance from the bottom i-th outer edge to the top i-th outer edge is the i-th difference ΔXr i In this case, since the upper first to fourth FLR regions 41 to 44 correspond to the second guard ring, the upper i-th region distance Lu i is L2 i Also, the upper i-th interval Su i is S2 iFurthermore, since the lower first to fourth FLR regions 51 to 54 correspond to the first guard ring, the lower i-th region distance Ld i is L1 i Also, the lower i-th interval Sd i is S1 i Corresponds to.

[0043] In this case, the following relational expressions (3-1) to (3-6) are established from the above relational expressions (2-1) to (2-8).

[0044]

number

[0045] Furthermore, according to the above relational expression (3-1), as i increases, the lower i-th interval Sd i Therefore, since the lower third interval Sd3 is larger than the lower second interval Sd2, and the lower second interval Sd2 is larger than the lower first interval Sd1, the interval between the lower FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0046] Furthermore, according to the above relational expression (3-3), as i increases, the upper i-th interval Su i Therefore, since the upper third interval Su3 is larger than the upper second interval Su2, and the upper second interval Su2 is larger than the upper first interval Su1, the interval between the upper FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0047] Furthermore, according to the above relational expression (3-6), the line passing through the center between the upper first outer end 411 and the upper second inner end 422 and n + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower second FLR region 52. Furthermore, the center line passes through the center between the upper second outer end 421 and the upper third inner end 432. +The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower third FLR region 53. It also passes through the center between the upper third outer end 431 and the upper fourth inner end 442. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower fourth FLR region 54. Furthermore, the center line passes through the center between the lower first outer end 511 and the lower second inner end 522. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper first FLR region 41. It also passes through the center between the lower second outer end 521 and the lower third inner end 532. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper second FLR region 42. Furthermore, the center line passes through the center between the lower third outer end 531 and the lower fourth inner end 542. + A center line extending in the thickness direction of mold substrate 10 passes through the center of upper third FLR region 43.

[0048] The semiconductor device 1 is configured as described above. Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 3 to 6. Note that Figures 3 to 6 only show the outer periphery region RG, and do not show the cell region RC.

[0049] As shown in Figure 3, the n + On the surface of the substrate 10 - The lower layer of the n-type layer 12 is then formed by ion implantation of p-type impurities, as shown in FIG. - Lower first to fourth FLR regions 51 to 54 are formed in the surface layer portion of the lower layer portion of the mold layer 12. Thereafter, as shown in FIG. - On the surface of the lower layer portion of the mold layer 12 and on the surfaces of the lower first to fourth FLR regions 51 to 54, n - The upper layer of the n-type layer 12 is then formed by ion implantation of p-type impurities, as shown in FIG. - In the surface layer portion of the upper layer portion of the mold layer 12, the upper first to fourth FLR regions 41 to 44 are formed, and the p-type base region 14 is also formed. +After the n-type source region 16 is formed, the p-type contact region 18 and the p-type hole extracting layer 20 are formed by ion implantation of p-type impurities. In this embodiment, the p-type base region 14 is formed simultaneously with the formation of the upper first to fourth FLR regions 41 to 44. However, the p-type base region 14 may be formed in a separate process from the process in which the upper first to fourth FLR regions 41 to 44 are formed. - The n-type impurity concentration in the lower portion of the dopant layer 12 is n - The n-type impurity concentration is the same as that of the upper layer of the n-type layer 12. - The n-type impurity concentration in the upper portion of the mold layer 12 may be different from that in the upper portion of the mold layer 12 .

[0050] Furthermore, the gate trench 22 is formed by RIE using a mask, i.e., anisotropic etching such as reactive ion etching. Thereafter, the gate insulating film 24 is formed by thermal oxidation or CVD method or the like. The gate insulating film 24 covers the inner wall surface of the gate trench 22 and the n-type insulating film. + The gate insulating film 24 covers the p-type source region 16. Then, after forming polysilicon doped with p-type or n-type impurities by CVD or the like, this is etched back, leaving at least the polysilicon in the gate trench 22, thereby forming the gate electrode 26. Furthermore, an interlayer insulating film 30 is formed by CVD or the like, and the gate insulating film 24 and the gate electrode 26 are covered with the interlayer insulating film 30. Furthermore, after forming a mask (not shown) on the surface of the interlayer insulating film 30, portions of the mask located between the gate electrodes 26, i.e., portions corresponding to the p-type contact regions 18 and their vicinity, are opened. At the same time, portions of the mask corresponding to the p-type hole extraction layer 20 are also opened. Thereafter, the interlayer insulating film 30 is patterned using the mask, thereby forming the n-type hole extraction layer 20. + Contact holes are formed to expose the n-type source region 16, the p-type contact region 18, and the p-type hole extracting layer 20. Then, the electrode material is patterned to form the source electrode 32. Finally, the n + Steps such as forming a drain electrode 34 on the back surface of the mold substrate 10 are then carried out.

[0051] The semiconductor device 1 is manufactured as described above. In the semiconductor device 1 manufactured in this manner, when the MOSFET is turned on, the voltage applied to the gate electrode 26 is controlled. At this time, a channel region is formed in the surface portion of the p-type base region 14 located on the side surface of the gate trench 22. As a result, the n + type source region 16, a channel region and an n - Current flows between source electrode 32 and drain electrode 34 through type layer 12 .

[0052] Furthermore, when avalanche breakdown occurs in the cell region RC and the peripheral region RG, the generated holes are extracted to the source electrode 32 through the p-type hole extracting layer 20. This restricts the flow of holes into the cell region RC, thereby suppressing element breakdown.

[0053] This suppresses a decrease in the breakdown voltage of the semiconductor device 1. Hereinafter, the suppression of this decrease in the breakdown voltage will be described.

[0054] Here, to explain the suppression of breakdown voltage reduction by semiconductor device 1, a comparative first guard ring 91 and a comparative second guard ring 92 described in Patent Document 1 and Japanese Patent No. 6139356 will be described as comparative examples. Note that in the comparative example, the front-side guard ring or the back-side guard ring whose outer edge in the surface direction of the substrate is closer to cell region RC is also referred to as the first guard ring. Furthermore, the front-side guard ring or the back-side guard ring different from the first guard ring is referred to as the second guard ring. Furthermore, in the comparative example, because the front-side guard ring and the back-side guard ring are formed at the same position in the thickness direction of the substrate, for convenience, the front-side guard ring is referred to as comparative first guard ring 91, and the back-side guard ring is referred to as comparative second guard ring 92.

[0055] In this comparative example, as shown in FIG. 7, when the comparative semiconductor device 90 is turned off, the comparative n - When the mold layer is projected in the thickness direction of the substrate, the projected comparative n- The mold layer is a comparative n between the comparative second guard rings 92. - That is, both comparison n - Thus, when the comparative semiconductor device 90 is turned off, the equipotential lines are formed between the two comparative n-type layers aligned on a straight line extending in the thickness direction of the substrate. - In other words, when the comparative semiconductor device 90 is turned off, the equipotential lines pass through the comparative n - Through the type layer, the comparison - The comparative n between the comparative first guard rings 91 overlapping the mold layer. - Therefore, the comparative n - In the mold layer, there are portions where the curvature of the equipotential lines becomes high, and therefore electric field concentration occurs at those portions, resulting in a decrease in breakdown voltage.

[0056] In contrast to this, in semiconductor device 1 of this embodiment, upper first to fourth FLR regions 41 to 44 and lower first to fourth FLR regions 51 to 54 are formed so that the above relational expression (1) holds.

[0057] Here, the meaning of the configuration in which the lower part of the above relational expression (1) is established will be explained. For example, L2 i is equal to the value of the left side of the lower part of the above relational expression (1). In this case, as shown in FIG. 8, - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The outer edge of the mold layer 12 overlaps with the outer edge of the i-th second guard ring. i becomes smaller than the value of the left side of the lower part of the above relational expression (1), the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 is formed between the second guard rings. - It overlaps with the mold layer 12. Therefore, L2 iis larger than the value of the left side of the lower part of the above relational expression (1), so that the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the second guard ring.

[0058] Furthermore, L2 i is equal to the value of the right side of the lower part of the above relational expression (1). In this case, as shown in FIG. 9, - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The outer edge of the mold layer 12 overlaps with the outer edge of the (i+1)th first guard ring. i When is larger than the value of the right side of the lower part of the above relational expression (1), the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 is formed between the first guard rings. - It overlaps with the mold layer 12. Therefore, L2 i is smaller than the value of the right side of the lower part of the above relational expression (1), so that the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the first guard ring.

[0059] Therefore, L2 i When is larger than the value of the left side of the lower part of the above relational expression (1), the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the second guard ring. i becomes smaller than the value of the right-hand side of the lower part of the above relational expression (1), the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n -The mold layer 12 overlaps with the first guard ring. As a result, as shown in FIG. 10, the equipotential lines are prevented from penetrating, and the equipotential lines are smoothed. - This prevents the occurrence of locations where the curvature of the equipotential lines is high within the mold layer 12. This prevents the occurrence of electric field concentration, thereby preventing a decrease in the breakdown voltage of the semiconductor device 1.

[0060] In addition, in the semiconductor device 1, according to the above relational expression (1), S1 i and S2 i can be optimally designed to be small, thereby shortening the outer periphery of the first guard ring and the second guard ring. i and L2 i By adjusting the above, the above relational expression (1) that suppresses a decrease in the breakdown voltage of the semiconductor device 1 is satisfied, and therefore the design of the semiconductor device 1 becomes easier.

[0061] The semiconductor device 1 also provides the following effects.

[0062] [1] In the semiconductor device 1, the lower first outer end 511 is located closer to the cell region RC than the upper first outer end 411. As a result, the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 correspond to the first guard ring. Also, the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 correspond to the second guard ring.

[0063] Here, the equipotential lines extend from the cell region RC toward the outer periphery region RG, and in the outer periphery region RG, n + The equipotential lines extend from the rear surface side to the front surface side of the mold substrate 10. Therefore, in the semiconductor device 1, the equipotential lines are formed along the n-th and (i+1)-th first guard rings. - n between the i-th and (i+1)-th second guard rings via the mold layer 12 - The mold layer 12 becomes smooth because it is easy to penetrate into the mold layer 12. -This prevents the occurrence of locations where the curvature of the equipotential lines is high within the mold layer 12. This prevents the occurrence of electric field concentration, thereby preventing a decrease in the breakdown voltage of the semiconductor device 1.

[0064] [2] Since the semiconductor device 1 includes the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54, the number of first guard rings is equal to the number of second guard rings. This makes it possible to reduce the strength of the electric field and eliminate excess FLR regions that do not contribute to the breakdown voltage. + Since the mold substrate 10 can be made smaller, the semiconductor device 1 can be made smaller.

[0065] [3] The upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expression (4) is established. As a result, the sum of the width and spacing of the i-th first guard ring can be set to be the same as the sum of the width and spacing of the i-th second guard ring, so that L1 i , S1 i , L2 i , S2 i Therefore, it is necessary to set S1 so that the above relation (1) is satisfied. i , S2 i , ΔX i and L2 i Since it becomes easier to make adjustments such as the above, the design of the semiconductor device 1 becomes easier.

[0066]

number

[0067] [4]S1 i and S2 i increases as i increases. Thus, the spacing between the first guard rings and the spacing between the second guard rings increases as n + In this case, when the semiconductor device 1 is turned off, n +As one moves from the inside to the outside in the surface direction of the mold substrate 10, the potential within the adjacent gap becomes less affected, and the potential within the gap approaches the potential of the drain electrode 34. Therefore, as shown in FIG. 11 , the electric field strength within the gap increases compared to when the spacing between the first guard rings and the spacing between the second guard rings are constant. This increases the area enclosed by the line showing the relationship between the electric field, which indicates the breakdown voltage, and the distance from the lower first outer end 511. Therefore, the breakdown voltage is improved while optimizing the spacing between the first guard rings and the spacing between the second guard rings. In FIG. 11 , the relationship between the lower first outer end 511 and the electric field strength in the semiconductor device 1 is indicated by a solid line. Furthermore, the relationship between the lower first outer end 511 and the electric field strength when the spacing between the first guard rings and the spacing between the second guard rings is constant is indicated by a dashed line.

[0068] [5] The upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expression (5) is established. This allows the sum of the width and spacing of the i-th first guard ring and the sum of the width and spacing of the i-th second guard ring to be set to K, so that L1 i , S1 i , L2 i , S2 i Therefore, it is necessary to set S1 so that the above relation (1) is satisfied. i , S2 i , ΔX i and L2 i Since it becomes easier to make adjustments such as the above, the design of the semiconductor device 1 becomes easier.

[0069]

number

[0070] [6] The upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expression (6) is established. As a result, the n -Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the centers of the lower first to fourth FLR regions 51 to 54. - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the centers of the upper first to fourth FLR regions 41 to 44. Therefore, the n - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the center of the second guard rings. - Mold layer 12 + When projected in the thickness direction of the mold substrate 10, the projected n - The mold layer 12 overlaps the center of the first guard rings. - The mold layer 12 and its n - The n between the mold layer 12 and the adjacent second guard rings - This makes it easier for the mold layer 12 to separate from the i-th and (i+1)-th first guard rings. - The n-th second guard ring between the (i-1)th and the i-th second guard rings located on the cell region RC side via the mold layer 12 - The inclusion of the metal in the mold layer 12 is suppressed. - This prevents the occurrence of locations where the curvature of the equipotential lines is high within the mold layer 12. This prevents the occurrence of electric field concentration, thereby preventing a decrease in the breakdown voltage of the semiconductor device 1.

[0071]

number

[0072] (Second embodiment) The second embodiment differs from the first embodiment in the arrangement of the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54. Other than this, the second embodiment is similar to the first embodiment.

[0073] Specifically, the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relational expressions (7-1) to (7-6) hold, instead of the above relational expressions (3-1) to (3-6). In the following relational expression (7-1), α is a real number greater than 1. α is set by experiment, simulation, etc., so as to obtain the lower i-th interval Sdi that satisfies the above relational expression (1). In the following relational expression (7-3), β is a real number greater than 1. β is set by experiment, simulation, etc., so as to obtain the upper i-th interval Sui that satisfies the above relational expression (1).

[0074]

number

[0075] Furthermore, according to the above relational expression (7-1), as i increases, the lower i-th interval Sd i increases exponentially. Therefore, since the lower third interval Sd3 is larger than the lower second interval Sd2, and the lower second interval Sd2 is larger than the lower first interval Sd1, the interval between the lower FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0076] Furthermore, according to the above relation (7-3), as i increases, the upper i-th interval Su i increases exponentially. Therefore, the upper third interval Su3 is larger than the upper second interval Su2, and the upper second interval Su2 is larger than the upper first interval Su1, so the interval between the upper FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0077] Furthermore, according to the above relational expression (7-6), similarly to the first embodiment, the distance n passes through the center between the upper first outer end 411 and the upper second inner end 422. +The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower second FLR region 52. The center line passes through the center between the upper second outer end 421 and the upper third inner end 432. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower third FLR region 53. The center line passes through the center between the upper third outer end 431 and the upper fourth inner end 442. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower fourth FLR region 54. The center line passes through the center between the lower first outer end 511 and the lower second inner end 522. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper first FLR region 41. The center line passes through the center between the lower second outer end 521 and the lower third inner end 532. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper second FLR region 42. The center line passes through the center between the lower third outer end 531 and the lower fourth inner end 542. + A center line extending in the thickness direction of mold substrate 10 passes through the center of upper third FLR region 43.

[0078] As described above, the semiconductor device 1 of the second embodiment is configured. The second embodiment also achieves the same effects as the first embodiment. In the second embodiment, as i increases, the lower i-th distance Sd i and the upper i-th interval Su i increases exponentially. This causes the lower i-th interval Sd i and the upper i-th interval Su i Since it is easy to set, it is easy to design the semiconductor device 1 that satisfies the above relational expression (1).

[0079] (Third embodiment) The third embodiment differs from the second embodiment in the arrangement of the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54. Other than this, the third embodiment is similar to the second embodiment.

[0080] Specifically, the upper first to fourth FLR regions 41 to 44 and the lower first to fourth FLR regions 51 to 54 are formed so that the following relations (8-1) to (8-6) hold, instead of the above relations (3-1) to (3-6). In the following relation (8-3), c is a predetermined distance. Furthermore, c is set by experiment, simulation, or the like to become the upper ith interval Sui that satisfies the above relation (1).

[0081]

number

[0082] Furthermore, according to the above relational expression (8-1), similarly to the second embodiment, the lower third interval Sd3 is larger than the lower second interval Sd2, and the lower second interval Sd2 is larger than the lower first interval Sd1. Therefore, the interval between the lower FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0083] Furthermore, according to the above relational expression (8-3), the lower third interval Sd3 is larger than the lower second interval Sd2, and therefore the upper third interval Su3 is larger than the upper second interval Su2. Also, the lower second interval Sd2 is larger than the lower first interval Sd1, and therefore the upper second interval Su2 is larger than the upper first interval Su1. Therefore, since the upper third interval Su3 is larger than the upper second interval Su2 and the upper second interval Su2 is larger than the upper first interval Su1, the interval between the upper FLR regions is n + The size increases from the inside to the outside in the surface direction of the mold substrate 10.

[0084] Furthermore, according to the above relational expression (8-6), similarly to the first and second embodiments, the line passing through the center between the upper first outer end 411 and the upper second inner end 422 and n + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower second FLR region 52. The center line passes through the center between the upper second outer end 421 and the upper third inner end 432. +The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower third FLR region 53. The center line passes through the center between the upper third outer end 431 and the upper fourth inner end 442. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the lower fourth FLR region 54. The center line passes through the center between the lower first outer end 511 and the lower second inner end 522. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper first FLR region 41. The center line passes through the center between the lower second outer end 521 and the lower third inner end 532. + The center line extending in the thickness direction of the mold substrate 10 passes through the center of the upper second FLR region 42. The center line passes through the center between the lower third outer end 531 and the lower fourth inner end 542. + A center line extending in the thickness direction of mold substrate 10 passes through the center of upper third FLR region 43.

[0085] As described above, the semiconductor device 1 of the third embodiment is configured. The third embodiment also achieves the same effects as the second embodiment. In the third embodiment, the lower i-th spacing Sd i By adding c to the upper i-th interval Su i is set, the upper i-th interval Su i Therefore, it is easy to design the semiconductor device 1 that satisfies the above relational expression (1).

[0086] (Fourth embodiment) In the fourth embodiment, the semiconductor device 1 includes a plurality of deep layers 36. The rest is the same as in the first embodiment. The deep layers 36 are sometimes called electric field relaxation layers.

[0087] As shown in FIG. 12, the deep layer 36 is formed in the cell region RC by n - The deep layer 36 is formed in the mold layer 12. + In the thickness direction of the substrate 10, the n-type +The deep layer 36 is disposed on the back surface side of the semiconductor substrate 10. Furthermore, the deep layer 36 is connected to the source electrode 32 via a coupling layer (not shown). The deep layer 36 is not limited to being connected to the source electrode 32 via a coupling layer (not shown), but may be connected to the p-type base region 14, as shown in FIG. 13, and thus connected to the source electrode 32 via the p-type base region 14.

[0088] The deep layer 36 extends in the longitudinal direction of the trench gate structure. + The cross section of the deep layer 36 in the thickness direction of the mold substrate 10 is rectangular. + The cross section of the deep layer 36 in the thickness direction of the mold substrate 10 is not limited to a rectangular shape, but may be, for example, a circular shape.

[0089] The p-type impurity concentration of the deep layer 36 is, for example, 1.0×10, similar to the p-type impurity concentrations of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54. 17 ~1.0×10 19 / cm 3 Furthermore, the thickness of the deep layer 36 is, for example, 800 nm, as are the thicknesses of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54.

[0090] The deep layer 36 is formed at the same time that the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 are formed by ion implantation.

[0091] The semiconductor device 1 of the fourth embodiment is configured as described above. The fourth embodiment also achieves the same effects as the first embodiment. Furthermore, in the fourth embodiment, the semiconductor device 1 includes a deep layer 36. The deep layer 36 prevents an electric field from penetrating into the bottom of the gate trench 22 even when a high voltage is applied when the MOSFET is turned off. This reduces electric field concentration at the bottom of the gate trench 22. This prevents breakdown of the gate insulating film 24.

[0092] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, it goes without saying that the elements constituting the embodiments in the above-described embodiments are not necessarily essential unless they are specifically stated as essential or are considered to be clearly essential in principle.

[0093] In each of the above embodiments, SiC is used as the semiconductor material, but the semiconductor material is not limited to SiC and may be Si or the like.

[0094] In each of the above embodiments, the MOSFET has a trench gate structure. However, the MOSFET is not limited to having a trench gate structure and may have a planar gate structure. Also, in each of the above embodiments, the MOSFET is an n-channel MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type. However, the MOSFET is not limited to being an n-channel MOSFET and may be a p-channel MOSFET in which the conductivity types of the respective components are inverted.

[0095] In the above embodiments, a MOSFET is used as an example of a semiconductor element, but the semiconductor element is not limited to a MOSFET and may be another element such as an IGBT.

[0096] In each of the above embodiments, the n of the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 + The cross section in the plane direction of mold substrate 10, i.e., the top surface layout, has a rectangular shape with rounded corners. However, the top surface layout of upper first FLR region 41, upper second FLR region 42, upper third FLR region 43, and upper fourth FLR region 44 may have other shapes, for example, a circular shape. Also, n along the radial direction centered on cell region RC + The cross sections of the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 in the thickness direction of the mold substrate 10 are rectangular, but are not limited to this and may be other shapes, for example, circular.

[0097] In the above-described embodiments, the upper surface layout of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 is a rectangle with rounded corners. However, the upper surface layout of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 may be another shape, for example, a circle. In addition, the n FLR regions 51, 52, 53, and 54 may be arranged in a radial direction with the cell region RC as the center. + The cross sections of the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 in the thickness direction of the mold substrate 10 are rectangular, but are not limited to this and may be other shapes, for example, circular.

[0098] In each of the above embodiments, the lower first outer end 511 is located closer to the cell region RC than the upper first outer end 411. However, the lower first outer end 511 is not limited to being located closer to the cell region RC than the upper first outer end 411. The upper first outer end 411 may be located closer to the cell region RC than the lower first outer end 511. In this case, the upper first FLR region 41, the upper second FLR region 42, the upper third FLR region 43, and the upper fourth FLR region 44 correspond to the first guard ring. Furthermore, the lower first FLR region 51, the lower second FLR region 52, the lower third FLR region 53, and the lower fourth FLR region 54 correspond to the second guard ring.

[0099] In each of the above embodiments, the number of upper FLR regions is the same as the number of lower FLR regions, but the number of upper FLR regions is not limited to being the same as the number of lower FLR regions and may be different from the number of lower FLR regions.

[0100] In each of the above embodiments, since the number of FLR regions on both the upper and lower sides is four, i is a natural number from 1 to 4. However, i is not limited to being a natural number from 1 to 4. It is sufficient that n is a natural number of 2 or more, and i is a natural number from 1 to n. In other words, it is sufficient that the number of FLR regions on both the upper and lower sides is 2 or more.

[0101] The above embodiments may be combined as appropriate.

[0102] When indicating the crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification. [Explanation of symbols]

[0103] 10n + Mold board 12n - mold layer 32 Source electrode 34 Drain electrode 41, 42, 43, 44 upper FLR area 51, 52, 53, 54 lower FLR area

Claims

1. A semiconductor device, a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the rear surface side of the substrate, through which a current flows between the second electrode and the first electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; a plurality of second conductivity type back-side guard rings (51, 52, 53, 54) formed in the drift layer, arranged at positions spaced apart from the front-side guard ring on the back side of the substrate in the thickness direction of the substrate, and surrounding the cell region; Equipped with the front-side guard ring and the back-side guard ring are aligned in a surface direction of the substrate, one of the front-side guard ring and the back-side guard ring that is closer to the cell region is designated as a first guard ring; one of the front-side guard ring and the back-side guard ring that is different from the first guard ring is designated as a second guard ring; Let i be a natural number, The width of the i-th first guard ring counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as L1 ｉ year, The distance between the i-1th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S1 ｉ year, The width of the ith second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 ｉ year, The distance between the i-1th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate is defined as S2 ｉ year, The distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring closest to the cell region toward the outer side in the surface direction of the substrate, to the outer edge of the i-1th second guard ring in the surface direction of the substrate, counting from the second guard ring closest to the cell region toward the outer side in the surface direction of the substrate, is defined as ΔX ｉ Then, The front side guard ring and the back side guard ring are [Equation 1] The relationship (1) is formed so that The S1 i and the S2 i increase as the i increases, Let α and β be real numbers greater than 1. The front side guard ring and the back side guard ring are [Equation 2] The semiconductor device is formed so that the following relational expression (2) holds true.

2. A semiconductor device, a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the rear surface side of the substrate, through which a current flows between the second electrode and the first electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; a plurality of second conductivity type back-side guard rings (51, 52, 53, 54) formed in the drift layer, arranged at positions spaced apart from the front-side guard ring on the back side of the substrate in the thickness direction of the substrate, and surrounding the cell region; Equipped with the front-side guard ring and the back-side guard ring are aligned in a surface direction of the substrate, one of the front-side guard ring and the back-side guard ring that is closer to the cell region is designated as a first guard ring; one of the front-side guard ring and the back-side guard ring that is different from the first guard ring is designated as a second guard ring; Let i be a natural number, L1 i denotes a width of the i-th first guard ring counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate, S1 i denotes a distance between the (i-1)th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate, and the width of the i-th second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 i ; S2 i denotes the distance between the (i-1)th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate; Let ΔX i be the distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring that is closest to the cell region outward in the surface direction of the substrate, to the outer edge of the i-1th second guard ring, counting from the second guard ring that is closest to the cell region outward in the surface direction of the substrate, The front side guard ring and the back side guard ring are [Equation 3] The relationship (3) is established. The S1 i and the S2 i increase as the i increases, Let α be a real number greater than 1, If the predetermined distance is c, then The front side guard ring and the back side guard ring are [Equation 4] The semiconductor device is formed so that the following relational expression (4) is satisfied.

3. A semiconductor device, a substrate (10) having a cell region (RC) in which a semiconductor element is formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the rear surface side of the substrate, through which a current flows between the second electrode and the first electrode when the semiconductor element is turned on; a plurality of front-side guard rings (41, 42, 43, 44) of a second conductivity type formed in the drift layer and surrounding the cell region; a plurality of second conductivity type back-side guard rings (51, 52, 53, 54) formed in the drift layer, arranged at positions spaced apart from the front-side guard ring on the back side of the substrate in the thickness direction of the substrate, and surrounding the cell region; Equipped with the front-side guard ring and the back-side guard ring are aligned in a surface direction of the substrate, one of the front-side guard ring and the back-side guard ring that is closer to the cell region is designated as a first guard ring; one of the front-side guard ring and the back-side guard ring that is different from the first guard ring is designated as a second guard ring; Let i be a natural number, L1 i denotes a width of the i-th first guard ring counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate, S1 i denotes a distance between the (i-1)th and i-th first guard rings counted from the first guard ring closest to the cell region toward the outside in the surface direction of the substrate, and the width of the i-th second guard ring, counting from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate, is defined as L2 i ; S2 i denotes the distance between the (i-1)th and i-th second guard rings counted from the second guard ring closest to the cell region toward the outside in the surface direction of the substrate; Let ΔX i be the distance from the outer edge of the i-1th first guard ring in the surface direction of the substrate, counting from the first guard ring that is closest to the cell region outward in the surface direction of the substrate, to the outer edge of the i-1th second guard ring, counting from the second guard ring that is closest to the cell region outward in the surface direction of the substrate, The front side guard ring and the back side guard ring are [Equation 5] The formula (5) is formed so that the following relation holds true: The S1 i and the S2 i increase as the i increases, If the predetermined distance is K, then The front side guard ring and the back side guard ring are [Equation 6] The semiconductor device is formed so that the following relational expression (6) is satisfied.

4. 4. A semiconductor device according to claim 1, wherein the outer end (511) of the rear guard ring closest to the cell region in the surface direction of the substrate is located closer to the cell region than the outer end (411) of the front guard ring closest to the cell region in the surface direction of the substrate.

5. 5. The semiconductor device according to claim 1, wherein the number of the front-side guard rings is equal to the number of the back-side guard rings.

6. The front side guard ring and the back side guard ring are [Equation 7] 6. The semiconductor device according to claim 1, wherein the semiconductor device is formed so that the following relational expression (7) is satisfied:

7. Let K be the predetermined distance, The front side guard ring and the back side guard ring are [Equation 8] 7. The semiconductor device according to claim 1, wherein the semiconductor device is formed so that the following relational expression (8) is satisfied:

8. Let K be the predetermined distance, The front side guard ring and the back side guard ring are [Equation 9] 7. The semiconductor device according to claim 1, wherein the semiconductor device is formed so that the following relational expression (9) is satisfied:

Images