Silicon carbide semiconductor device

Abstract

To provide a silicon-carbide semiconductor device capable of achieving both relaxation of an electric field intensity and suppression of a crack.SOLUTION: A silicon-carbide semiconductor device comprises a silicon-carbide substrate having a first principal surface, a first insulation film provided on the first principal surface, a second insulation film provided on the first insulation film and having a higher density than the first insulation film, and a third insulation film provided on the second insulation film and having a smaller dielectric constant than the second insulation film. The silicon-carbide substrate comprises an element region in which a plurality of semiconductor elements are formed, and a termination region including one or two or more annular protection regions provided around the element region when viewed from a direction perpendicular to the first principal surface. The protection region is termination bonding expansion or a guard ring. When viewed from the direction perpendicular to the first principal surface, the third insulation film comprises a first region overlapping an edge on the element region separation side of the protection region and a second region adjacent to the first region above the termination region. A first thickness of the first region is greater than a second thickness of the second region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] Silicon carbide semiconductor devices have been disclosed in which a silicon nitride film is formed on one main surface of a silicon carbide substrate to reduce the electric field strength in a termination region (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2011 / 027523 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-15482 Summary of the Invention [Problem to be solved by the invention]

[0004] As silicon carbide semiconductor devices are used at higher voltages, they require higher breakdown voltages. Although the electric field strength in the termination region can be increased by thickening the silicon nitride film, the thick silicon nitride film is prone to cracking.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can simultaneously alleviate electric field strength and suppress cracks. [Means for solving the problem]

[0006] a second insulating film provided on the first insulating film and having a higher density than the first insulating film; and a third insulating film provided on the second insulating film and having a lower dielectric constant than the second insulating film; the silicon carbide substrate has an element region in which a plurality of semiconductor elements are formed, and a termination region including one or more annular protective regions provided around the element region when viewed from a direction perpendicular to the first main surface, the protective regions being termination junction extensions or guard rings; and the third insulating film has, above the termination region when viewed from a direction perpendicular to the first main surface, a first region overlapping an edge of the protective region away from the element region and a second region adjacent to the first region, and a first thickness of the first region is greater than a second thickness of the second region. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to achieve both reduction of electric field strength and suppression of cracks. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing a silicon carbide semiconductor device in accordance with the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 7] FIG. 7 is a fifth cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 11] FIG. 11 is a ninth cross-sectional view illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 10) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a silicon carbide semiconductor device in accordance with the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the crystallographic descriptions in this specification and drawings, individual directions are represented by [ ], collective directions by < >, individual planes by ( ), and collective planes by {}. Furthermore, while a negative index in crystallographic terms is usually represented by placing a "-" (bar) above the number, in this specification a negative sign is placed before the number.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface, a first insulating film provided on the first main surface, a second insulating film provided on the first insulating film, the second insulating film having a higher density than the first insulating film, and a third insulating film provided on the second insulating film, the third insulating film having a lower dielectric constant than the second insulating film, wherein the silicon carbide substrate has an element region in which a plurality of semiconductor elements are formed, and a termination region including one or more annular protection regions provided around the element region when viewed from a direction perpendicular to the first main surface, the protection regions being termination junction extensions or guard rings, wherein the third insulating film has, above the termination region, a first region overlapping an edge of the protection region away from the element region and a second region adjacent to the first region when viewed from a direction perpendicular to the first main surface,

[0012] The density of the second insulating film is higher than the density of the first insulating film, and the relative dielectric constant of the third insulating film is lower than the relative dielectric constant of the second insulating film. The third insulating film has a first region and a second region, and when viewed from a direction perpendicular to the first main surface, the first region overlaps with an edge of the protection region on a side away from the element region, and the first thickness of the first region is greater than the second thickness of the second region. This reduces the electric field strength on the surface of the third insulating film while suppressing cracks.

[0013] [2] In [1], the first insulating film may contain silicon and oxygen, the second insulating film may be a silicon nitride film, and the third insulating film may be a polyimide film. In this case, the first insulating film, the second insulating film, and the third insulating film are easy to form, and good passivation performance is easy to obtain.

[0014] [3] In [1] or [2], the first thickness may be 1.5 times or more the second thickness, which makes it easier to both alleviate the electric field strength and suppress cracks.

[0015] [4] In [1] to [3], the thickness of the second insulating film may be 0.1 μm or more and 1.0 μm or less. If the second insulating film is too thin, it may be difficult to alleviate the electric field strength, and if the second insulating film is too thick, it may be difficult to suppress cracks.

[0016] [5] In [1] to [4], the first thickness may be 6.0 μm or more and 20.0 μm or less. If the first thickness is too small, it may be difficult to alleviate the electric field strength, and if the first thickness is too large, it may be difficult to suppress cracks.

[0017] [6] In any of [1] to [5], the second thickness may be 3.0 μm or more and 10.0 μm or less. If the second thickness is too small, it may be difficult to alleviate the electric field strength, and if the second thickness is too large, it may be difficult to suppress cracks.

[0018] [7] In any of [1] to [6], the thickness of the third insulating film above the element region may be 3.0 μm or more and 10.0 μm or less. If the third thickness is too small above the element region, it may be difficult to alleviate the electric field strength, and if the third thickness is too large, it may be difficult to suppress cracks.

[0019] [8] In any of [1] to [7], the first region may be provided at each edge of the protective region, which makes it easier to both alleviate the electric field strength and suppress cracks.

[0020] [9] In any of [1] to [7], the first region may be provided across the edges of two or more of the protective regions. In cases where the width of the protective region is narrow, even if the first region is provided across the edges of two or more protective regions, it is possible to achieve both relaxation of the electric field strength and prevention of cracks.

[0021] [Embodiments of the present disclosure] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. Note that, in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0022] (First embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOSFET (silicon carbide semiconductor device). FIG. 1 is a top view showing the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0023] As shown in Figures 1 to 4, the silicon carbide semiconductor device 100 according to the first embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, a source electrode 60, a drain electrode 70, an interlayer insulating film 83, a barrier metal film 84, a first passivation film 32, and a second passivation film 33.

[0024] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type). A semiconductor element is formed on the silicon carbide substrate 10.

[0025] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0026] The MOSFET 100 has an element region 6 and a termination region 7 provided around the element region 6 when viewed in a plan view perpendicular to the first main surface 1.

[0027] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, a first contact region 14, a second contact region 15, a shield region 16, a first buried junction termination extension (JTE) region 21, and a second JTE region 22. The body region 12, the source region 13, the first contact region 14, the second contact region 15, and the shield region 16 are provided in the element region 6. The first JTE region 21 and the second JTE region 22 are provided in the termination region 7. The drift region 11 is provided across the element region 6 and the termination region 7.

[0028] Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 is located closer to first main surface 1 than silicon carbide single crystal substrate 50. Drift region 11 may be continuous with silicon carbide single crystal substrate 50. Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 may include a current diffusion region near the surface on the first main surface 1 side.

[0029] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The body region 12 is located closer to the first main surface 1 than the drift region 11. The drift region 11 is located closer to the second main surface 2 than the body region 12. The body region 12 is in contact with the drift region 11.

[0030] The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. The source region 13 is located closer to the first main surface 1 than the body region 12. The body region 12 is located closer to the second main surface 2 than the source region 13. The source region 13 is in contact with the body region 12. The source region 13 constitutes the first main surface 1. The source region 13 is covered with a gate insulating film 81. The source region 13 is in direct contact with the gate insulating film 81.

[0031] The first contact region 14 penetrates the source region 13 and contacts the body region 12. The first contact region 14 constitutes the first main surface 1. The first contact region 14 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the first contact region 14 is higher than the effective concentration of the p-type impurities in the body region 12, for example.

[0032] The shield region 16 is provided on the drift region 11 near the termination region 7 of the element region 6. For example, when viewed in a plan view perpendicular to the first main surface 1, the shield region 16 has a ring-shaped planar shape. The shield region 16 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the shield region 16 is, for example, 1.0×10 18 cm -3 ~4.0×10 18 cm -3 The shield region 16 is located closer to the first main surface 1 than the drift region 11. The drift region 11 is located closer to the second main surface 2 than the shield region 16. The shield region 16 is in contact with the drift region 11. A part of the shield region 16 may constitute the first main surface 1.

[0033] The second contact region 15 is provided on the shield region 16. The second contact region 15 constitutes the first main surface 1. The edge of the second contact region 15 on the termination region 7 side may be located more inward than the edge of the shield region 16 on the termination region 7 side. The second contact region 15 contains p-type impurities such as aluminum, and has p-type conductivity. The effective concentration of the p-type impurities in the second contact region 15 is higher than the effective concentration of the p-type impurities in the shield region 16, for example. The effective concentration of the p-type impurities in the second contact region 15 may be approximately the same as the effective concentration of the p-type impurities in the first contact region 14. The effective concentration of the p-type impurities in the second contact region 15 is, for example, 1.0×10 19 cm -3 ~4.0×10 19 cm -3 That's about it.

[0034] The first JTE region 21 contacts the shield region 16 in a direction parallel to the first main surface 1. For example, when viewed in a plane perpendicular to the first main surface 1, the first JTE region 21 has an annular planar shape. The first JTE region 21 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the first JTE region 21 is lower than the effective concentration of the p-type impurities in the shield region 16, for example. The effective concentration of the p-type impurities in the first JTE region 21 is, for example, 6.0×1017 cm -3 ~9.0×10 17 cm -3 The first JTE region 21 constitutes the first main surface 1. The first JTE region 21 is an example of a protective region.

[0035] The second JTE region 22 contacts the first JTE region 21 in a direction parallel to the first main surface 1. For example, when viewed in a plane perpendicular to the first main surface 1, the second JTE region 22 has an annular planar shape. The first JTE region 21 is located between the shield region 16 and the second JTE region 22. The lower end surface of the second JTE region 22 is, for example, closer to the first main surface 1 than the lower end surface of the first JTE region 21. The lower end surface of the second JTE region 22 may be flush with the lower end surface of the first JTE region 21. The second JTE region 22 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the second JTE region 22 is lower than the effective concentration of the p-type impurities in the first JTE region 21. The effective concentration of the p-type impurities in the second JTE region 22 is, for example, 1.0 × 10 17 cm -3 ~4.0×10 17 cm -3 The second JTE region 22 constitutes the first main surface 1. The second JTE region 22 is another example of a protective region.

[0036] The first main surface 1 has a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates part of the source region 13, the body region 12, and the drift region 11. The bottom surface 4 is continuous with the side surface 3. The source region 13, the body region 12, and the drift region 11 are in contact with the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0037] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 contacts the source region 13, the first contact region 14, the second contact region 15, the shield region 16, the first JTE region 21, and the second JTE region 22 at the first main surface 1.

[0038] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0039] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0040] A contact hole 86 is formed in the interlayer insulating film 83 and the gate insulating film 81. Through the contact hole 86, the source region 13, the first contact region 14, and the second contact region 15 are exposed from the interlayer insulating film 83 and the gate insulating film 81. The gate insulating film 81 and the interlayer insulating film 83 constitute an insulating film 31. The insulating film 31 is an example of a first insulating film.

[0041] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0042] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source pad electrode 62. The contact electrode 61 may be in contact with the source region 13, the first contact region 14, and the second contact region 15 on the first main surface 1. The contact electrode 61 may be made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing, for example, titanium, aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13, the first contact region 14, and the second contact region 15. The source pad electrode 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source pad electrode 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source pad electrode 62 is made of a material containing, for example, aluminum.

[0043] The first passivation film 32 covers the source pad electrode 62 and the interlayer insulating film 83. The first passivation film 32 is provided on the source pad electrode 62 and the interlayer insulating film 83. The first passivation film 32 is in contact with the source pad electrode 62 and the interlayer insulating film 83. The density of the first passivation film 32 is higher than the density of the insulating film 31. The first passivation film 32 is made of a material containing silicon nitride, for example. The first passivation film 32 may be a silicon nitride film. A first opening 34 is formed in the first passivation film 32, exposing a portion of the upper surface of the source pad electrode 62. The first passivation film 32 is an example of a second insulating film.

[0044] The second passivation film 33 covers the first passivation film 32. The second passivation film 33 is provided on the first passivation film 32. The second passivation film 33 is in contact with the first passivation film 32. The relative dielectric constant of the second passivation film 33 is lower than the relative dielectric constant of the first passivation film 32. The second passivation film 33 is made of a material containing polyimide, for example. The second passivation film 33 may be a polyimide film. A second opening 35 is formed in the second passivation film 33, exposing a portion of the upper surface of the source pad electrode 62. The second opening 35 is connected to the first opening 34. The second passivation film 33 is an example of a third insulating film.

[0045] The second passivation film 33 has a convex region 36A, a convex region 36B, a concave region 37A, a concave region 37B, and a concave region 37C. In a plan view, the convex region 36A, the convex region 36B, the concave region 37A, the concave region 37B, and the concave region 37C are arranged in an annular shape. In a plan view, the convex region 36A overlaps with an edge 21E of the first JTE region 21 on the side away from the element region 6, and the convex region 36B overlaps with an edge 22E of the second JTE region 22 on the side away from the element region 6.

[0046] In a plan view, the convex region 36A is on the element region 6 side of the convex region 36B. Also, in a plan view, the recessed region 37A is on the element region 6 side of the convex region 36A, the recessed region 37B is between the convex region 36A and the convex region 36B, and the recessed region 37C is on the side of the convex region 36B away from the element region 6. In a plan view, the convex region 36A is between the recessed region 37A and the recessed region 37B, and the convex region 36B is between the recessed region 37B and the recessed region 37C. The convex region 36A is adjacent to the recessed region 37A, the recessed region 37B is adjacent to the convex region 36A, the convex region 36B is adjacent to the recessed region 37B, and the recessed region 37C is adjacent to the convex region 36B. The convex region 36A and the convex region 36B are examples of first regions. The recessed regions 37A, 37B, and 37C are examples of the second region.

[0047] The first thickness T1 of the convex regions 36A and 36B is greater than the second thickness T2 of the concave regions 37A, 37B, and 37C. The first thickness T1 is, for example, 1.5 times or more the second thickness T2. For example, the first thickness T1 is approximately 6.0 μm to 20.0 μm, and the second thickness T2 is approximately 3.0 μm to 10.0 μm.

[0048] The dimension (width) of the convex region 36A in the direction perpendicular to the boundary between the nearest element region 6 and termination region 7 is, for example, approximately 5.0 μm to 10.0 μm. In plan view, it is preferable that the edge 21E of the first JTE region 21 overlaps with the center in the width direction of the convex region 36A, and it is preferable that the edge 22E of the second JTE region 22 overlaps with the center in the width direction of the convex region 36B.

[0049] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0050] Between silicon carbide single crystal substrate 50 and drift region 11, a buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided.

[0051] Next, a method for manufacturing the silicon carbide semiconductor device (MOSFET 100) according to the first embodiment will be described. Figures 3 to 12 are cross-sectional views illustrating the method for manufacturing MOSFET 100 according to the first embodiment. Like Figure 2, Figures 3 to 12 correspond to cross-sectional views taken along line II-II in Figure 1.

[0052] First, as shown in Fig. 3, a silicon carbide single crystal substrate 50 is prepared. For example, the silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by sublimation. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0053] Next, as also shown in Figure 3, an epitaxial layer is formed as drift region 11. For example, drift region 11 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into drift region 11. Drift region 11 has n-type conductivity.

[0054] 4, body region 12, source region 13, first contact region 14, second contact region 15, shield region 16, first JTE region 21, and second JTE region 22 are formed. For example, these regions are formed by ion implantation of n-type or p-type impurities using a mask layer (not shown) having openings over the regions to be formed.

[0055] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0056] Next, as shown in FIG. 5 , a gate trench 5 is formed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1. Using the mask layer, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF) or a mixed gas of SF and oxygen (O) as a reactive gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0057] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask layer formed on the first main surface 1 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 800°C or higher and 900°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0058] By the thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is formed by the source region 13, the body region 12, and the drift region 11. The bottom surface 4 is formed by the drift region 11. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0059] Next, as shown in FIG. 6 , a gate insulating film 81 is formed. The thickness of the gate insulating film 81 is, for example, 50 nm or more and 70 nm or less. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 is formed in contact with the source region 13, the body region 12, the drift region 11, the first contact region 14, the second contact region 15, the shield region 16, the first JTE region 21, and the second JTE region 22. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or more and 1400° C. or less. As a result, the gate insulating film 81 is formed in contact with the first main surface 1, the side surface 3, and the bottom surface 4. Note that when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a portion of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0060] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is maintained, for example, under conditions of 1100°C or higher and 1400°C or lower for about one hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0061] After the NO annealing, Ar annealing may be performed using argon (Ar) as the atmospheric gas. The heating temperature of the Ar annealing is, for example, equal to or higher than the heating temperature of the NO annealing. The Ar annealing time is, for example, about one hour. This further suppresses the formation of interface states in the interface region between the gate insulating film 81 and the body region 12. Note that, instead of Ar gas, other inert gases such as nitrogen gas may be used as the atmospheric gas.

[0062] 7, a gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed to face each of the source region 13, the body region 12, and the drift region 11.

[0063] Next, as shown in FIG. 8, an interlayer insulating film 83 is formed. The thickness of the interlayer insulating film 83 is, for example, 300 nm or more and 1000 nm or less. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5. In this way, the insulating film 31 including the gate insulating film 81 and the interlayer insulating film 83 is formed.

[0064] 8, contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81. In the contact holes 86, the source region 13, the first contact region 14, and the second contact region 15 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0065] 9, a barrier metal film 84, a contact electrode 61, and a source pad electrode 62 are formed. For example, the barrier metal film 84 is formed to cover the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is made of a material containing titanium nitride, for example. The barrier metal film 84 is formed by film formation using a sputtering method and RIE, for example.

[0066] In forming the contact electrode 61, first, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1, the metal film being in contact with the first contact region 14 or the second contact region 15. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing nickel. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 reacts with silicon contained in the silicon carbide substrate 10 and is converted into silicide, thereby forming the contact electrode 61 that forms an ohmic junction with the first contact region 14 or the second contact region 15. The thickness of the contact electrode 61 is, for example, 10 nm or higher and 100 nm or lower.

[0067] In forming the source pad electrode 62, first, a metal film (not shown) for the source pad electrode 62 is formed. Specifically, the metal film for the source pad electrode 62 is formed so as to cover the contact electrode 61 and the barrier metal film 84. The thickness of the metal film for the source pad electrode 62, for example, the thickness of the field insulating film 88, is, for example, 3000 nm to 5000 nm. The metal film for the source pad electrode 62 is formed by, for example, a sputtering method. The metal film for the source pad electrode 62 is made of, for example, a material containing aluminum. Next, a mask layer (not shown) is formed on the metal film for the source pad electrode 62 to cover the region where the source pad electrode 62 is to be formed. Using the mask layer, a portion of the metal film for the source pad electrode 62 is removed by etching. As an etching method, for example, RIE can be used. In this way, the source electrode 60 having the contact electrode 61 and the source pad electrode 62 is formed. Next, the mask layer is removed from the source pad electrode 62.

[0068] 10, a first passivation film 32 is formed. The thickness of the first passivation film 32 is, for example, 100 nm or more and 800 nm or less. Specifically, the first passivation film 32 is formed to cover the source pad electrode 62. The first passivation film 32 is made of a material containing, for example, silicon nitride. Next, a first opening 34 is formed in the first passivation film 32.

[0069] Next, as shown in FIG. 11, an insulating film 33X that will become part of the second passivation film 33 is formed. The insulating film 33X is formed on the first passivation film 32. The insulating film 33X is formed in a region overlapping the edge 21E of the first JTE region 21 and a region overlapping the edge 22E of the second JTE region 22 in a plan view. That is, the insulating film 33X is formed in a region where the convex region 36A is to be formed and a region where the convex region 36B is to be formed. The insulating film 33X has a thickness that is approximately half the first thickness T1 of the convex regions 36A and 36B to be formed. For example, the thickness of the insulating film 33X is approximately 3.0 μm to 10.0 μm. The insulating film 33X is made of a material containing, for example, polyimide. The insulating film 33X is formed, for example, by applying a photosensitive material, developing it, and exposing it to light.

[0070] Next, as shown in FIG. 12, a second passivation film 33, which includes an insulating film 33X in part, is formed on the first passivation film 32. The second passivation film 33 includes a convex region 36A and a convex region 36B in the region where the insulating film 33X was formed. The second passivation film 33 also includes a concave region 37A on the element region 6 side of the convex region 36A, a concave region 37B between the convex region 36A and the convex region 36B, and a concave region 37C on the side of the convex region 36B away from the element region 6. For example, the first thickness T1 of the convex region 36A and the convex region 36B is approximately 6.0 μm to 20.0 μm, and the second thickness T2 of the concave region 37A, the concave region 37B, and the concave region 37C is approximately 3.0 μm to 10.0 μm. The second passivation film 33 is made of a material including, for example, polyimide. The second passivation film 33 is formed by, for example, applying a photosensitive material, developing it, and exposing it to light. A second opening 35 connected to the first opening 34 is formed in the second passivation film 33.

[0071] Next, as also shown in FIG. 12 , the drain electrode 70 is formed. For example, a metal film (not shown) for the drain electrode 70 is formed in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing nickel. Next, alloying annealing is performed. The metal film for the drain electrode 70 is held at a temperature of 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the metal film for the drain electrode 70 reacts with the silicon contained in the silicon carbide substrate 10 to be silicided, thereby forming the drain electrode 70 in ohmic contact with the silicon carbide single crystal substrate 50. The alloying annealing between the formation of the metal film for the contact electrode 61 and the formation of the metal film 62A for the source pad electrode 62 may be omitted, and the metal film for the contact electrode 61 may be silicided by annealing after the formation of the metal film for the drain electrode 70.

[0072] In this way, the MOSFET 100 according to the embodiment is completed.

[0073] Next, the effects of the MOSFET according to this embodiment will be described.

[0074] In the MOSFET 100 according to this embodiment, the density of the first passivation film 32 is higher than the density of the insulating film 31. This makes it possible to prevent moisture from entering from the outside. Furthermore, the relative dielectric constant of the second passivation film 33 is lower than the relative dielectric constant of the first passivation film 32. This reduces the electric field strength on the surface of the second passivation film 33, making it easier to prevent fluctuations in characteristics due to the adhesion of metal ions. The relative dielectric constant of polyimide is approximately 3.0 to 3.5, and the relative dielectric constant of silicon nitride is approximately 7.3 to 10.0.

[0075] Furthermore, second passivation film 33 has convex regions 36A and 36B. This reduces the electric field strength on the surface of second passivation film 33 above edges 21E and 22E, where the electric field tends to be strong. If second passivation film 33 were thick overall, cracks might easily occur in second passivation film 33 due to thermal stress during operation, but because second passivation film 33 has concave regions 37A, 37B, and 37C, cracks can be suppressed.

[0076] In this way, according to the first embodiment, it is possible to achieve both reduction in electric field strength and prevention of cracks. In particular, since the convex regions 36A and 36B are provided at the edges 21E and 22E, it is easy to achieve both reduction in electric field strength and prevention of cracks.

[0077] The materials of the insulating film 31, the first passivation film 32, and the second passivation film 33 are not particularly limited, but it is preferable that the insulating film 31 contains silicon and oxygen, the first passivation film 32 is a silicon nitride film, and the second passivation film 33 is a polyimide film. This is because these films are easy to form and provide good passivation performance. The insulating film 31 is made of, for example, silicon dioxide or silicon oxynitride. The insulating film 31 may be doped with phosphorus, or may be doped with phosphorus and boron.

[0078] The first thickness T1 is preferably 1.5 times or more, more preferably 1.7 times or more, and even more preferably 2.0 times or more, the second thickness T2. If this ratio is too low, it may be difficult to achieve both mitigation of electric field strength and suppression of cracks. Note that, if the surfaces of the convex regions 36A and 36B are not flat, the first thickness T1 of the convex regions 36A and 36B is the thickness at their respective thickest portions. Furthermore, if the surfaces of the concave regions 37A, 37B, and 37C are not flat, the second thickness T2 of the concave regions 37A, 37B, and 37C is the thickness at their respective thinnest portions.

[0079] The first thickness T1 is preferably 6.0 μm or more and 20.0 μm or less, more preferably 8.0 μm or more and 18.0 μm or less, and even more preferably 10.0 μm or more and 16.0 μm or less. If the convex regions 36A and 36B are too thin, it may be difficult to alleviate the electric field strength, and if the convex regions 36A and 36B are too thick, it may be difficult to suppress cracks.

[0080] The second thickness T2 is preferably 3.0 μm or more and 10.0 μm or less, more preferably 4.0 μm or more and 9.0 μm or less, and even more preferably 5.0 μm or more and 18.0 μm or less. If the recessed regions 37A, 37B, and 37C are too thin, it may be difficult to alleviate the electric field strength, and if the recessed regions 37A, 37B, and 37C are too thick, it may be difficult to suppress cracks.

[0081] The thickness T3 of the second passivation film 33 above the element region 6 is preferably 3.0 μm to 10.0 μm, more preferably 4.0 μm to 9.0 μm, and even more preferably 5.0 μm to 18.0 μm. This is because the second passivation film 33 is easily formed when the thickness T3 is approximately the same as the thicknesses of the recessed regions 37A, 37B, and 37C. Furthermore, even above the element region 6, if the second passivation film 33 is too thin, it may be difficult to alleviate the electric field strength, and if the second passivation film 33 is too thick, it may be difficult to suppress cracks.

[0082] The thickness of the first passivation film 32 is preferably 0.1 μm to 1.0 μm, more preferably 0.2 μm to 0.9 μm, and even more preferably 0.3 μm to 0.8 μm. If the first passivation film 32 is too thin, it may be difficult to alleviate the electric field strength, and if the first passivation film 32 is too thick, it may be difficult to suppress cracks.

[0083] (Second embodiment) A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the second passivation film 33. Fig. 13 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment. Like Fig. 2, Fig. 13 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

[0084] 13 , in a silicon carbide semiconductor device 200 according to the second embodiment, a second passivation film 33 has a convex region 36C instead of convex regions 36A, 36B, and concave regions 37B. In plan view, convex region 36C overlaps with edge 21E of first JTE region 21 and edge 22E of second JTE region 22. That is, convex region 36C is provided across edge 21E of first JTE region 21 and edge 22E of second JTE region 22. In plan view, convex region 36C overlaps with the entire second JTE region 22.

[0085] The other configurations are the same as those in the first embodiment.

[0086] The second embodiment can also achieve both reduction in electric field intensity and suppression of cracks, similar to the first embodiment. The second embodiment is particularly effective when the distance between the edge 21E and the edge 22E is small.

[0087] (Third embodiment) A third embodiment will now be described. The third embodiment differs from the first embodiment mainly in the configurations of the protection region and second passivation film 33. Fig. 14 is a cross-sectional view showing a silicon carbide semiconductor device according to the third embodiment. Like Fig. 2, Fig. 14 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

[0088] As shown in FIG. 14 , in a silicon carbide semiconductor device 300 according to the third embodiment, a first guard ring (GR) region 23, a second GR region 24, and a third GR region 25 are provided instead of the second JTE region 22. The first GR region 23, the second GR region 24, and the third GR region 25 are provided in the termination region 7. For example, when viewed in a plan view from a direction perpendicular to the first main surface 1, the first GR region 23, the second GR region 24, and the third GR region 25 have annular planar shapes. In plan view, the second GR region 24 is located on the element region 6 side of the third GR region 25, and the first GR region 23 is located on the element region 6 side of the second GR region 24. The first GR region 23, the second GR region 24, and the third GR region 25 are spaced apart from one another.

[0089] The first GR region 23 contacts the first JTE region 21 in a direction parallel to the first main surface 1. The first JTE region 21 is located between the shield region 16 and the first GR region 23. The lower end surfaces of the first GR region 23, the second GR region 24, and the third GR region 25 are, for example, closer to the first main surface 1 than the lower end surface of the first JTE region 21. The first GR region 23, the second GR region 24, and the third GR region 25 contain p-type impurities such as aluminum, and have p-type conductivity. The effective concentration of the p-type impurity in the first GR region 23, the second GR region 24, and the third GR region 25 is lower than the effective concentration of the p-type impurity in the first JTE region 21. The effective concentration of the p-type impurity in the first GR region 23, the second GR region 24, and the third GR region 25 is, for example, 5×10 16 cm -3 ~1×10 18 cm -3 The effective concentrations of p-type impurities in the first GR region 23, the second GR region 24, and the third GR region 25 may be equal to each other. The first GR region 23, the second GR region 24, and the third GR region 25 constitute the first main surface 1. The first GR region 23, the second GR region 24, and the third GR region 25 are another example of a protection region.

[0090] Furthermore, the second passivation film 33 has a convex region 36D instead of the convex region 36A, the convex region 36B, and the concave region 37B. In plan view, the convex region 36D overlaps with the edge 21E of the first JTE region 21, the edge 23E of the first GR region 23 on the side away from the element region 6, the edge 24E of the second GR region 24 on the side away from the element region 6, and the edge 25E of the third GR region 25 on the side away from the element region 6. In other words, the convex region 36D is provided across the edge 21E of the first JTE region 21, the edge 23E of the first GR region 23, the edge 24E of the second GR region 24, and the edge 25E of the third GR region 25. In plan view, the convex region 36D overlaps with the entire first GR region 23, the second GR region 24, and the third GR region 25.

[0091] The other configurations are the same as those in the first embodiment.

[0092] The third embodiment can also achieve both reduction in electric field strength and suppression of cracks, similar to the first embodiment. The third embodiment is particularly effective when the distance between edge 21E and edge 23E, the distance between edge 23E and edge 24E, and the distance between edge 24E and edge 25E are small.

[0093] In the third embodiment, a convex region may be provided for each of the edges 21E, 23E, 24E, and 25E.

[0094] In each embodiment, a JTE region is provided in the termination region, but a GR region may be provided without a JTE region. Also, the number of JTE regions and GR regions is not particularly limited.

[0095] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0096] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 6 Element Area 7 Termination area 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 14 First contact area 15 Second contact area 16 Shield Area 21 1st JTE area 21E, 22E, 23E, 24E, 25E edge 22 2nd JTE Area 23 1st GR area 24 2nd GR area 25 3rd GR area 31 insulating film 32 First passivation film 33 Second passivation film 33X insulating film 34 First Opening 35 Second opening 36A, 36B, 36C, 36D convex area 37A, 37B, 37C concave area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source pad electrode 62A Metal film 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 86 Contact Hole 88 Field insulating film 100, 200, 300 MOSFET (Silicon Carbide Semiconductor Device)

Claims

1. a silicon carbide substrate having a first main surface; a first insulating film provided on the first main surface; a second insulating film provided on the first insulating film and having a density higher than that of the first insulating film; a third insulating film provided on the second insulating film and having a dielectric constant smaller than that of the second insulating film; and The silicon carbide substrate is an element region in which a plurality of semiconductor elements are formed; a termination region including one or more annular protection regions provided around the element region when viewed from a direction perpendicular to the first main surface; and the protective region is a termination junction extension or guard ring; When viewed from a direction perpendicular to the first main surface, the third insulating film has, above the termination region, a first region overlapping an edge of the protection region on a side away from the element region; a second region adjacent to the first region; and a first thickness of the first region greater than a second thickness of the second region;

2. the first insulating film contains silicon and oxygen; the second insulating film is a silicon nitride film, The silicon carbide semiconductor device according to claim 1 , wherein the third insulating film is a polyimide film.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein the first thickness is at least 1.5 times the second thickness.

4. 4 . The silicon carbide semiconductor device according to claim 1 , wherein the second insulating film has a thickness of not less than 0.1 μm and not more than 1.0 μm.

5. The silicon carbide semiconductor device according to claim 1 , wherein the first thickness is not less than 6.0 μm and not more than 20.0 μm.

6. The silicon carbide semiconductor device according to claim 1 , wherein the second thickness is not less than 3.0 μm and not more than 10.0 μm.

7. 7 . The silicon carbide semiconductor device according to claim 1 , wherein the third insulating film has a thickness above the element region of not less than 3.0 μm and not more than 10.0 μm.

8. The silicon carbide semiconductor device according to claim 1 , wherein the first region is provided at each edge of the protection region.

9. The silicon carbide semiconductor device according to claim 1 , wherein the first region is provided across the edges of two or more of the protection regions.

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