Processing device and electronic system including same

Abstract

To provide a processing device, and an electronic device having the same.SOLUTION: A bit cell circuit and a processing device are disclosed, the bit cell circuit comprising: a first variable resistor, a second variable resistor connected to the first variable resistor in parallel, a first switch serially connected to the first variable resistor and configured to switch application of a voltage or current to the first variable resistor, and a second switch serially connected to the second variable resistor and configured to perform switching operation for applying the voltage or current to the second variable resistor complementarily with the first switch.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an apparatus for performing processing and an electronic system including the same. [Background technology]

[0002] A neural network device can perform a multiply-accumulate (MAC) operation, which involves repeated multiplication and addition. A neural network repeatedly performs a MAC operation at a specific node, which involves multiplying the output of a node in a previous layer by the weight mapped to that node, and adding the resulting value. The neural network then applies an activation function to the resulting value of the MAC operation. To achieve this, a memory access operation may be performed at a desired time, loading appropriate inputs and weights. Instead of using a commonly known digital computer to process a neural network, various approaches have been attempted to perform neural network operations, such as a MAC operation, using other hardware architectures. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a processing device and an electronic system including the same that improve the reliability and power efficiency of analog operations, and other technical problems can be inferred from the embodiments described below. [Means for solving the problem]

[0004] In one embodiment, the bit cell circuit includes: a first variable resistor, which is a resistive memory element whose resistance value is set by switching between different resistance states; a second variable resistor, which is a resistive memory element connected in parallel with the first variable resistor and set to a resistance value complementary to that of the first variable resistor; a first switch connected in series with the first variable resistor and switching application of the voltage or the current to the first variable resistor; and a second switch connected in series with the second variable resistor and performing a switching operation to apply the voltage or the current to the second variable resistor in a complementary manner to the first switch.

[0005] In addition, the first variable resistor is set to one of a first resistance value and a second resistance value, and the second variable resistor is set to the second resistance value when the first variable resistor is set to the first resistance value, and is set to the first resistance value when the first variable resistor is set to the second resistance value.

[0006] Furthermore, the resistance values of the first variable resistor and the second variable resistor are set to values corresponding to weights for a MAC (multiply and accumulate) operation of a neural network.

[0007] The first switch and the second switch perform complementary ON / OFF operations according to an input value applied to the bit cell circuit for the MAC operation of the neural network.

[0008] Furthermore, the resistance value of the bit cell circuit is the same as the resistance value of the first variable resistor when the first switch is closed by applying a first input value, and is also the same as the resistance value of the second variable resistor when the second switch is closed by applying a second input value.

[0009] Furthermore, the resistance value of the bit cell circuit is set to a first resistance value corresponding to a first weight when the first variable resistor is set to a first resistance value corresponding to a first weight, and when the first input value is applied to the bit cell circuit, the bit cell circuit has the first resistance value.1 The variable resistor is set to a second resistance value corresponding to a second weight, and the bit cell circuit is 1 When an input value is applied, the resistor has the second resistance value, 2 The variable resistor The aforementioned No. 1 Corresponding to weight The aforementioned No. 1 a resistance value set to said bit cell circuit; No. 2 When an input value is applied, the second variable resistor has the second resistance value. The aforementioned No. 2 Corresponding to weight The aforementioned No. 2 When the second input value is applied to the bit cell circuit, 1 It has a resistance value.

[0010] The bit cell circuit has a resistance value corresponding to the result of an XNOR (exclusive-NOR) operation between an input value applied to the bit cell circuit and a weight set in the bit cell circuit.

[0011] In addition, the first variable resistor and the first switch connected in series are connected in parallel with the second variable resistor and the second switch connected in series, one end of the first variable resistor and one end of the second variable resistor are commonly connected to a first bit data line, and one end of the first switch and one end of the second switch are commonly connected to a second bit data line.

[0012] At least one of one end of the variable resistor commonly connected to the first bit data line and one end of the switch commonly connected to the second bit data line is connected to another bit cell circuit.

[0013] The first variable resistor and the second variable resistor are also magnetic tunnel junction (MTJ) elements.

[0014] In another embodiment, the bit cell circuit includes a pair of variable resistors, which are resistive memory elements configured to have different resistance values and connected in parallel, and a pair of switches connected in series with each of the variable resistors to complementarily switch the application of the voltage or the current to each of the variable resistors.

[0015] In yet another embodiment, a processing device includes a bit cell array having a plurality of bit cells, each including a pair of variable resistors and a pair of switches, wherein at least one of the plurality of bit cells includes: a first variable resistor, which is a resistive memory element whose resistance value is set by switching between different resistance states; a second variable resistor, which is a resistive memory element connected in parallel with the first variable resistor and set to a resistance value complementary to that of the first variable resistor; a first switch, which is connected in series with the first variable resistor and switches application of the voltage or the current to the first variable resistor; and a second switch, which is connected in series with the second variable resistor and performs a switching operation to apply the voltage or the current to the second variable resistor in a complementary manner to the first switch.

[0016] The plurality of bit cells form the bit cell array including a plurality of bit cell lines, each of which includes serially connected bit cells among the bit cells.

[0017] In addition, a first bit cell line among the bit cell lines processes a MAC operation performed at a first node among a plurality of nodes of the neural network, and the pair of variable resistors included in each bit cell of the first bit cell line are set to a resistance value corresponding to a weight for the MAC operation performed at the first node.

[0018] In addition, one of the pair of switches included in each of the bit cells is closed and the other switch is opened according to the input value of the MAC operation performed at the first node.

[0019] Furthermore, the result of the MAC operation at the first node corresponds to the value of the voltage drop of the first bit cell line caused by a predetermined value of current applied to the first bit cell line when the setting of the resistance value corresponding to the weight and the switching operation of the switch corresponding to the input value are completed.

[0020] Also, the voltage drop value of the first bit cell line corresponds to the sum of the voltage drops occurring in the bit cells included in the first bit cell line.

[0021] The device further includes a pair of bit data lines connected between at least one or more of the bit cells to set the resistance values of the pair of variable resistors and applying a voltage or current to both ends of at least one of the bit cells.

[0022] The processing device is also a device that performs in-memory processing.

[0023] In yet another embodiment, a processing device including a bit cell array includes a plurality of bit cells; a pair of bit data lines connected between at least one or more of the bit cells and applying a voltage or current to both ends of at least one of the bit cells; at least one bit cell of the plurality of bit cells is configured to have different resistance values by being switched between different resistance states; a pair of variable resistors that are resistive memory elements connected in parallel; and a pair of switches connected in series with each of the variable resistors and switching the application of the voltage or current to each of the variable resistors in a complementary manner. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a diagram for explaining a biological neuron and its operation. [Figure 2] 1 is a diagram for explaining an example of a neural network. [Figure 3] 1 is a diagram illustrating a circuit diagram of a bit cell used in a processing device. [Figure 4A] 4 is a diagram illustrating the structure and operation of a variable resistor applied to the bit cell of FIG. 3; [Figure 4B] 4 is a diagram illustrating the structure and operation of a variable resistor applied to the bit cell of FIG. 3; [Figure 5A] 10 is a diagram illustrating another example of a neural network. [Figure 5B] 5B is a diagram illustrating one embodiment of a processing device capable of performing the operations required by the neural network of FIG. 5A. [Figure 6] 5B is a diagram illustrating another embodiment of a processing device capable of performing the operations required by the neural network of FIG. 5A. [Figure 7] 5C is a diagram illustrating a connection relationship between a variable resistor and a switch in the embodiment of FIG. 5B. [Figure 8] 8 is a horizontal cross-sectional view illustrating the variable resistance layer of FIG. 7 in further detail. [Figure 9A] FIG. 1 is a vertical cross-sectional view taken along line XX'. [Figure 9B] 9 is a vertical cross-sectional view taken along line YY′ in FIG. 8. [Figure 10] FIG. 2 is a plan view of the active layer of the processing device. [Figure 11] FIG. 9B is a plan view of the seventh metal layer of the processing device of FIG. 9A. [Figure 12] 5B is a diagram illustrating another embodiment of a processing device, which has a different connection structure between a switch and a variable resistor from that of the processing device of FIG. 5B. [Figure 13] 13 is a diagram for explaining the connection relationship between the variable resistor and the switch in the embodiment of FIG. 12; [Figure 14] FIG. 1 is a chip block diagram of a processing device according to an example. [Figure 15] FIG. 1 is a block diagram illustrating an electronic system according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0025] Various embodiments will now be described with reference to the accompanying drawings. The terms used to describe the present embodiments are not intended to limit the scope of the present invention to a particular embodiment, and various modifications, equivalents, and / or alternatives to the particular embodiment are also encompassed within the scope of the present invention. Throughout the description of the drawings, like reference numerals may be used to refer to like elements. A singular expression may include a plural expression unless the context clearly dictates otherwise. Expressions such as "A or B" or "A and / or B" may include all possible combinations of the listed items. Terms such as "first" and "second" may modify the relevant element regardless of order or importance, and are used only to distinguish one element from other elements, not to limit the relevant element.

[0026] In the description of the present embodiment, when a part is said to be connected to another part, this does not only mean that they are directly connected to each other, but also means that they are connected via other components in between. Furthermore, when a part is said to "comprise" a component, this does not mean that it excludes other components, but that it may further include other components, unless otherwise specified. However, the term "comprise" should not be interpreted as necessarily including all of the various components or steps described in the specification.

[0027] The embodiments described below relate to the technical field of processing devices (e.g., neuromorphic processors, neural processors, etc.), and detailed descriptions of matters well known to those skilled in the art will be omitted.

[0028] In this embodiment, the processing device may include analog circuits for performing multiplication and addition operations, unlike a typical digital computer that uses a common data bus to communicate information. In other words, the processing device may perform in-memory processing or internal processing. Therefore, the processing device may be referred to by various terms, such as an in-memory processing device, a PIM (Processor in memory), or an FIM (Function in memory).

[0029] FIG. 1 is a diagram for explaining a biological neuron and its operation.

[0030] Referring to Figure 1, a biological neuron 10 refers to a cell present in the human nervous system and is one of the fundamental biological computational entities. The human brain contains approximately 100 billion biological neurons and 100 trillion interconnections between them.

[0031] A biological neuron 10 is a single cell that includes a nucleus and a neuron cell body that contains various organelles, including mitochondria, numerous dendrites that emanate from the neuron cell body, and an axon that terminates in many branching extensions.

[0032] Generally, the axon functions to transmit signals from one neuron to another, and the dendrites function to receive signals from another neuron. For example, when different neurons are connected to each other, a signal transmitted through one neuron's axon is received by the dendrites of the other neuron. Signals are transmitted between neurons through specialized connections called synapses, and various neurons are connected to each other to form a neural network. Based on the synapse, a neuron that secretes neurotransmitters is also called a presynaptic neuron, and a neuron that receives information transmitted via neurotransmitters is also called a post-synaptic neuron.

[0033] The human brain can learn and memorize vast amounts of information by transmitting and processing various signals through a neural network formed by interconnecting such a large number of neurons. Various attempts have been made to develop processing or computer devices that can efficiently process vast amounts of information by replicating such biological neural networks.

[0034] FIG. 2 is a diagram for explaining an example of a neural network.

[0035] Referring to Figure 2, neural network 20 is an example of an artificial neural network that mimics the aforementioned biological neural network and also corresponds to a deep neural network (DNN). For ease of explanation, neural network 20 is illustrated as including two hidden layers, but may include a variety of numbers of hidden layers. Also, in Figure 2, neural network 20 is illustrated as including a separate input layer 21 for receiving input data, but input data may be input directly to the hidden layer.

[0036] In the neural network 20, artificial nodes in layers other than the output layer may be connected to artificial nodes in the next layer via links for transmitting output signals. A value obtained by multiplying the node value of an artificial node included in a previous layer by a weight assigned to each link may be input to one artificial node via these links. The node value of the previous layer corresponds to an axon value, and the weight corresponds to a synaptic weight. The weight is also referred to as a parameter of the neural network 20. Activation functions include sigmoid, hyperbolic tangent (Tanh), and rectified linear unit (ReLU), and nonlinearity may be formed in the neural network 20 by the activation functions.

[0037] The output of any one node 22 included in such a neural network 20 can be expressed as in Equation 1 below.

[0038]

number

[0039] FIG. 3 is a circuit diagram illustrating one embodiment of a bitcell for use in a processing device, with reference to which the structure and operation of the bitcell will be explained.

[0040] The bitcell BC (bitcell) in Figure 3 may be a circuit configuration included in a processing device for implementing a neuromorphic processor, a neural processor, etc. The processing device may be, for example, an in-memory processing unit that stores data in a memory (such as a resistive memory element) and uses the stored data when an operation is required.

[0041] The bit cell BC consists of a pair of variable resistors R a ,R b , variable resistor R a ,R b A pair of switches S connected in series to a ,S b , and the first bit data line BLD a and the second bit data line BLD b Switches S connected to BDLa ,S BDLb However, the circuit configuration of the bit cell BC shown in FIG. 3 is merely an example, and the bit cell BC may be realized by an equivalent circuit using other circuit elements.

[0042] A pair of variable resistors R a ,R b are resistance elements that can be set to different resistance values, and the variable resistor R a ,R bThe resistance value of each variable resistor R can be determined by the weight applied to the bit cell BC. a ,R b can have one of two resistance values, for example, 20Ω or 5Ω. Assuming that the weights that can be applied to the bit cell BC are "-1 or 1", when a weight "1" is applied to the bit cell BC, the first variable resistor R a is set to 20 Ω, and the second variable resistor R b On the other hand, when a weight "-1" is applied to the bit cell BC, the first variable resistor R a is set to 5 Ω, and the second variable resistor R b can be set to 20 Ω. a ,R b The resistance value of the variable resistor R a ,R b The resistors can be set to have complementary resistance values different from each other.

[0043] Specifically, the variable resistor R a ,R b The resistive memory element may be a resistive memory element. The resistive memory element can have multiple resistance states and can be switched between different resistance states depending on a voltage or current applied across the resistive memory element. The resistive memory element may have a single-layer structure or a multi-layer structure including, for example, a transition metal oxide, a metal oxide such as a perovskite-based material, a phase-change material such as a chalcogenide-based material, a ferroelectric material, or a ferromagnetic material. The operation of the resistive memory element to change from a high resistance state to a low resistance state may be referred to as a set operation, and the operation of the resistive memory element to change from a low resistance state to a high resistance state may be referred to as a reset operation.

[0044] Variable resistor R a ,R bFirst, connect both ends of the variable resistor to be changed to the first bit data line BDL a and the second bit data line BDL b Connect to the first variable resistor R a For example, the first variable resistor R a One end of the variable resistor R a The upper end of the upper bit data line switch S BDLb via the second bit data line BDL b and the first variable resistor R a The other end of the variable resistor R a The lower end of the first switch S a and the lower bit data line switch S BDLa and the first bit data line BDL a can be connected to

[0045] Upper bit data line switch S BDLb may be a switch not included in the bit cell BC of FIG. 3. For example, the upper bit data line switch S BDLb is a switch included in a bit cell (not shown) adjacent to bit cell BC in FIG. 3, or is an independent switch not included in any other bit cell.

[0046] First variable resistor R a However, the bit data line BDL a ,BDL b When the second switch S is connected to the first variable resistor Ra, a set operation or a reset operation for the first variable resistor Ra can be performed by controlling the voltage across the first variable resistor Ra or the current flowing through the first variable resistor Ra via the bit data lines BDLa and BDLb. b and the bit data line switches S on both ends of the bit cell BC. BDLa ,S BDLb When the second variable resistor R b However, the bit data line BDL a ,BDL b is connected to the second variable resistor Rb A set or reset operation can be performed on the .

[0047] Variable resistor R a ,R b The voltage and / or current applied to change the resistance of the variable resistor R a ,R b In other words, the resistance of the variable resistor R a ,R b Depending on the voltage and / or current applied to read the resistance of the variable resistor R a ,R b The resistance value of the resistor will not change.

[0048] Variable resistor R a ,R b A pair of switches S connected in series with a ,S b The switch S can perform an ON / OFF operation depending on the input applied to the bit cell BC. a ,S b can operate in a complementary manner so that when one is closed, the other is opened. For example, assuming that the inputs that can be applied to the bit cell BC are "-1 or 1", when an input "1" is applied, the first switch S a is closed, and the second switch S b is open, and when input "-1" is applied, the first switch S a is opened, and the second switch S b can be designed to be closed.

[0049] According to the operation method of the variable resistor and the switch described above, the resistance measured at both ends of the bit cell BC may vary depending on the wait and input applied to the bit cell BC in Figure 3. The relationship between the wait, input, and the resistance at both ends of the bit cell BC is summarized in Table 1 below.

[0050] [Table 1] Referring to Table 1, when the product of the input and the weight is 1, the resistance of the bit cell BC is 20Ω, and when the product of the input and the weight is -1, the resistance of the bit cell BC is 5Ω. In other words, by measuring the resistance of the bit cell BC or measuring the voltage drop of the bit cell BC due to a constant current, the product of the input applied to the bit cell BC and the weight can be determined. By utilizing such characteristics of the bit cell BC, a processing device (e.g., a neuromorphic processor) that calculates the sum of the products of the input and the weight can be implemented.

[0051] 4A and 4B are diagrams illustrating the structure and operation of variable resistors applicable to the bit cell BC of Fig. 3. The variable resistors Ra and Rb are implemented using magnetic tunnel junction (MTJ) elements, and their resistance value changes depending on the magnitude and direction of current (or voltage). They can also have non-volatile characteristics, in which the resistance value is maintained even when the input current (or voltage) is cut off.

[0052] 4A and 4B, a magnetic tunnel junction (MTJ) element includes a pinned layer L3, a free layer L1, and a tunnel layer L2 therebetween. The magnetization direction of the pinned layer L3 is fixed, and the magnetization direction of the free layer L1 can be made the same as or different from the magnetization direction of the pinned layer L3 according to conditions.

[0053] FIG. 4A illustrates a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of a magnetic tunnel junction (MTJ) element are parallel. When the magnetization directions are parallel, the magnetic tunnel junction (MTJ) element can have a low resistance value, for example, a resistance of 5 Ω. FIG. 4B illustrates a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of the magnetic tunnel junction (MTJ) element are anti-parallel. When the magnetization directions are anti-parallel, the magnetic tunnel junction (MTJ) element can have a high resistance value, for example, a resistance of 20 Ω. Therefore, the resistance value of the variable resistor can be changed by changing the magnetization direction of the free layer L1.

[0054] The magnetization direction of the free layer L1 can be changed by electrical / magnetic factors provided externally and / or internally of the resistive memory cell. The free layer L1 may include a material having a changeable magnetization direction, such as a ferromagnetic material. Examples of the free layer L1 include CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O 12 , and / or combinations thereof.

[0055] The tunnel layer L2 may have a thickness less than the spin diffusion distance and may include a non-magnetic material, such as magnesium (Mg), titanium (Ti), aluminum (Al), oxides of magnesium zinc (MgZn) and magnesium boron (MgB), titanium (Ti), vanadium (V), and / or combinations thereof.

[0056] The pinned layer L3 may have its magnetization direction fixed by an antiferromagnetic layer. The pinned layer L3 may be made of a ferromagnetic material, such as CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O 12 and / or combinations thereof, and may further include an antiferromagnetic layer and / or a synthetic antiferromagnetic layer to fix the magnetization direction. The antiferromagnetic layer may include an anti-ferromagnetic material such as PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, Cr, and / or combinations thereof. The synthetic antiferromagnetic layer may include Cu, Ru, Ir, and / or combinations thereof.

[0057] Figure 5A is a diagram illustrating a neural network including a first layer having three nodes and a second layer having two nodes, and Figure 5B is a diagram illustrating an example circuit diagram of a processing device implemented using the bit cell of Figure 3 to perform the operations required in the second layer of the neural network of Figure 5A.

[0058] Referring to FIG. 5A, in the first node a1 of the second layer L2, inputs x1, x2, x3 provided from the nodes of the first layer L1 and weights w 11 ,w 21 ,w 31 At the second node a2 in the second layer L2, the inputs x1, x2, and x3 provided from the nodes in the first layer L1 and the weight w are multiplied three times, and then the MAC operation is performed to add up the multiplication results, as shown in the following formula 3. 12 ,w 22 ,w 32 Then, a MAC operation is performed in which three multiplication operations are performed by multiplying each of the above by 1 and 2, and the resulting multiplication values are added together.

[0059]

number

[0060]

number

[0061] The processing device 100 of FIG. 5B includes three serially connected bit cells BC 11 ,BC 12 ,BC 13 a first bit cell line BCL1 including three serially connected bit cells BC 21 ,BC 22 ,BC 23 The first bit cell line BCL1 performs the operation of Equation 2 required from the first node a1 of FIG. 5A, and the second bit cell line BCL2 performs the operation of Equation 3 required from the second node a2.

[0062] A constant current I is applied to each bit cell line BCL1, BCL2, and the bit cell BC 11 ,BC 12 ,BC 13 ,BC 21 ,BC 22 ,BC 23 The sum of the voltage drops that occur in each bit cell is 11 ,BC 12 ,BC 13 ,BC 21 ,BC 22 ,BC 23 The sum of the products of the weights applied to each and the input is derived. In the following, an example will be described in which the inputs and weights are as shown in Table 2 below.

[0063] [Table 2] According to the weights in Table 2, the variable resistor R included in the processing device 100 of FIG. 5B 11a ,R 11b ,R 12a ,R 12b ,…,R 23a ,R 23b can be set as shown in Table 3 below. By inputting Table 2, each variable resistor R 11a ,…,R 23b and a switch S connected in series 11a ,S 11b ,S 12a ,S 12b ,…,S 23a ,S 23b The open / closed state can be set as shown in Table 4 below.

[0064] [Table 3]

[0065] [Table 4] When a current of 1 A is supplied to the first bit cell line BCL1 and the second bit cell line BCL2 configured as shown in Tables 3 and 4, a current flows through the variable resistor included in each bit cell whose switch is closed, causing a voltage drop. At this time, if the voltage is measured at the upper ends of the first bit cell line BCL1 and the second bit cell line BCL2, the measured voltage may correspond to the sum of the voltage drops occurring in each bit cell. The bit cell BC included in the first bit cell line BCL1 11 ,BC 12 ,BC 13 The voltage drop occurring in the second bit cell line BCL2 is as shown in Table 5 below. 21 ,BC 22 ,BC 23 The voltage drop that occurs is as shown in Table 6 below.

[0066] [Table 5]

[0067] [Table 6] The voltage drop of 45V in the first bit cell line BCL1 and the voltage drop of 15V in the second bit cell line BCL2 may represent the MAC operation result of the weights applied to the bit cells included in each bit cell line and the input. The relationship between the voltage drop and the MAC operation result can be shown as an example in Table 7 below.

[0068] [Table 7] Referring to Table 7, since the voltage drop in the first bit cell line BCL1 is measured to be 45V, it can be seen that the sum of the products of the inputs applied to the first bit cell line BCL1 and the weight is 1. Also, since the voltage drop in the second bit cell line BCL2 is measured to be 15V, it can be seen that the sum of the products of the inputs applied to the second bit cell line BCL2 and the weight is -3.

[0069] 5B, each of the bit cell lines BCL1 and BCL2 is illustrated as including three bit cells, but the number of bit cells included in one bit cell line may be various numbers greater than or equal to 1. For example, one bit cell line may include 64 to 256 bit cells.

[0070] Although processing device 100 is illustrated in Figure 5B as including only two bit cell lines, processing device 100 may include any number of bit cell lines greater than one, such as 64 to 128 bit cell lines.

[0071] Meanwhile, a structure in which a plurality of bit cell lines, each including a plurality of bit cells, are arranged is also called a bit cell array.

[0072] 5B may be an in-memory processing device that stores values corresponding to weights in a memory element configured with a variable resistor and performs calculations using the values stored in the memory element. Unlike a von Neumann architecture in which the memory and calculation unit are separated, the in-memory processing device may have improved data transmission speed and power consumption.

[0073] In the embodiment of Figure 5B, a processing device is described in which a constant current I is applied to serially connected bit cells, and an operation result corresponding to the sum of products is derived from the voltage drop occurring on the bit cell lines. However, the bit cell BC structure of Figure 3 can also be applied to processing devices of other types.

[0074] 6 is a diagram illustrating another embodiment of a processing device capable of performing the operations required by the neural network of FIG. 5A. Referring to FIG. 6, unlike FIG. 5B, a capacitor BCL is connected to the lower end of each of the serially connected bit cell lines BCL1 and BCL2. C1 ,BCL C2 That is, according to another embodiment, after applying a voltage V to each of the bit cell lines BCL1 and BCL2, each capacitor BCL C1 ,BCL C2 The processing unit 200 may be implemented using a time-to-digital converter (TDC) method, which measures the time it takes for the voltage of a transistor to rise to a specific value.

[0075] 7 to 15 are diagrams illustrating the layout of a processing device implemented using the bit cell BC of Fig. 3. Hereinafter, the structure of the processing device will be described with reference to Figs. 7 to 15.

[0076] 7 is a diagram illustrating a connection structure between a variable resistor and a switch in a bit cell included in a processing device according to an embodiment, and conceptually illustrates a cross-sectional view of a processing device including an active layer, a variable resistance layer, and a metal layer, using the first bit cell line BCL1 of FIG.

[0077] Referring to Figure 7, switch S 11a ,S 12a ,S 13b The active layer L100, on which the metal wiring and the variable resistance R are formed, the first metal layer M100 to the sixth metal layer M600, and the variable resistance layer L200 are laminated in this order. 11a ,R 12a ,R 13b The positional relationship between the active layer L100 and the variable resistance layer L200 is determined by the order of the steps of fabricating the above.

[0078] The active layer L100 is the switch S in FIG. 11a ,S 12a ,S 13b The layer on which the switch S is formed is formed through a transistor formation process on the silicon wafer. 11a ,S 12a ,S 13b For convenience of explanation, the active layer L100 may be a layer in which the switch S included in the first bit cell line BCL1 of FIG. 11a ,S 11b ,S 12a ,S 12b ,S 13a ,S 13b ,S1,S 11 ,S 12 ,S 13 Among them, the switch S on the path of the current I flowing through the first bit cell line BCL1 is selected by the input and wait of Table 2. 11a ,S 12a ,S 13b Only the remaining switches S in FIG. 11b ,S 12b ,S 13a ,S1,S 11,S 12 ,S 13 5B is in an open state, and the current I applied to the first bit cell line BCL1 does not flow, and is not shown in FIG. 7. However, the remaining switches S in FIG. 5B, which are not shown in FIG. 7, 11b ,S 12b ,S 13a ,S1,S 11 ,S 12 ,S 13 are also formed in the active layer L100, except that the switch S 11a ,S 12a ,S 13b may be located at other positions in the horizontal direction.

[0079] The variable resistance layer L200 corresponds to the variable resistance R 11a ,R 12a ,R 13b etc., and via V 11 ,V 12 ,V 13 A seventh metal layer M700 is located above the variable resistance layer L200, and a sixth metal layer M600 is located below the variable resistance layer L200.

[0080] Variable resistor R 11a ,R 12a ,R 13b The variable resistors R may be formed vertically from the variable resistance layer L200 so that one end of each variable resistor is connected to the seventh metal layer M700 and the other end is connected to the sixth metal layer M600. In the following, the vertically formed variable resistors R 11a ,R 12a ,R 13b The end of the variable resistor R on the seventh metal layer M700 side is the upper end of the variable resistor, and the end of the variable resistor R on the sixth metal layer M600 side is the lower end of the variable resistor. 11a ,R 12a ,R 13b The current flowing through the variable resistors can flow from the upper end to the lower end or from the lower end to the upper end.

[0081] The variable resistance layer L200 of FIG. 7 includes the variable resistance R included in the first bit cell line BCL1 of FIG. 5B. 11a ,R 11b ,R 12a ,R 12b ,R 13a ,R 13b Among them, the variable resistor R on the path where the current flows due to the input and wait in Table 2 above 11a ,R 12a ,R 13b However, even though not shown in FIG. 7, the remaining variable resistors R 11b ,R 12b ,R 13a is also formed in the variable resistance layer L200, except that the variable resistance R 11a ,R 12a ,R 13b may be located at other positions in the horizontal direction.

[0082] Via V 11 ,V 12 ,V 13 The via V penetrates the variable resistance layer L200 and electrically connects the seventh metal layer M700 and the sixth metal layer M600. 11 ,V 12 ,V 13 The variable resistor R of each bit cell is connected via 11a ,R 11b ,R 12a ,R 12b ,R 13a ,R 13b are connected in series, and this connection structure will be explained in more detail below.

[0083] The first metal layer M100 to the seventh metal layer M700 are variable resistors R 11a ,R 12a ,R 13b And so on, switch S 11a ,S 12a ,S 13b Wiring to connect these, and switch S 11a ,S 12a ,S 13b It can be a layer on which conductive wiring such as wiring for transmitting ON / OFF signals is formed.

[0084] As shown in FIG. 11a ,S 12a ,S 13b and variable resistor R 11a ,R 12a ,R 13b The third bit cell BC1 arranged at the end (bottom) of the first bit cell line BCL1 is connected to the third bit cell BC2. 13 Switch S included in 13b Except for switch S 11a ,S 12a Each end is electrically connected to a different variable resistor.

[0085] Second bit cell BC 12 The first switch S 12a For example, switch S 12a One end of the second bit cell BC 12 The first variable resistor R 12a and switch S 12a The other end of the third bit cell BC 13 The second variable resistor R 13b More specifically, the switch S 12a One end of the variable resistor R 12a The switch S 12a The other end of the via V 12 Through the variable resistor R 13b As described above, the active layer L100 is located below the variable resistance layer L200, so that the switch S 12a variable resistor R 13b The second bit cell BC penetrates the variable resistance layer L200 to connect to the upper end of the 12 Via V 12 Referring to FIG. 5B, the second bit cell BC 12 Via V 12 The position connected by the second bit cell BC 12 and the third bit cell BC 13 In other words, the second bit cell BC 12 and the third bit cell BC13 To connect to the variable resistor at 12 Similarly, the first bit cell BC in FIG. 11 Via V 11 is the first bit cell BC 11 and the second bit cell BC 12 In other words, by using vias in this way, the variable resistors in each bit cell can be connected in series.

[0086] FIG. 8 is a horizontal cross-sectional view illustrating the variable resistance layer L200 of FIG. 7 in further detail.

[0087] 8, the variable resistance layer L200 includes four bit cell lines, each including three bit cells. In FIG. 5B, only the first bit cell line BCL1 and the second bit cell line BCL2 are shown. Compared to FIG. 5B, FIG. 8 illustrates four more bit cell lines, including the third bit cell line BCL3 and the fourth bit cell line BCL4, to show the layout structure of the variable resistors and vias. Because the first bit cell line BCL1 and the third bit cell line BCL3 have the same structure, and the second bit cell line BCL2 and the fourth bit cell line BCL4 have the same structure, the variable resistors and vias of the third bit cell line BCL3 and the fourth bit cell line BCL4 will be described without separate reference numerals.

[0088] 8, each bit cell further includes an inactive variable resistor in addition to the variable resistor and the via. 11 For example, the first bit cell BC 11 is the variable resistor R in Figure 5B. 11a ,R 11b and Via V 11 In addition, there are nine inactive variable resistors R i It further includes:

[0089] Inactive variable resistor R i is the variable resistor R11a ,R 11b Unlike the switch S in Figure 5B, it is a variable resistor that is not used for processing. 11a ,S 11b It is not electrically connected to the variable resistor R 11a ,R 11b etc. are inactive variable resistors R i To distinguish it from the inactive variable resistor R, it is also called an active variable resistor. i is an active variable resistor R with uniform electrical characteristics 11a ,R 11b Specifically, due to manufacturing process issues, a variable resistor formed at a position surrounded by other variable resistors can exhibit relatively uniform electrical characteristics compared to variable resistors formed at the edges, and only the highly reliable centrally located variable resistor is used in processing, while the remaining variable resistors can be left as unused inactive variable resistors.

[0090] The four bit cells BC in Figure 8 11 ,BC 12 ,BC 21 ,BC 22 The variable resistors included in each bit cell are used as an example. Each bit cell has 11 variable resistors, and four bit cells BC 11 ,BC 12 ,BC 21 ,BC 22 A total of 44 variable resistors are formed in each bit cell. The active variable resistor is located in the center of the bit cell and is surrounded by other variable resistors. That is, four bit cells BC 11 ,BC 12 ,BC 21 ,BC 22 In this case, 36 inactive variable resistors R i Eight variable resistors R arranged in a position surrounded by 11a ,R 11b ,R 12a ,R 12b ,R 21a ,R 21b ,R 22a ,R 22b corresponds to the active variable resistor.

[0091] Referring to FIG. 8, via V 11 ,V 12 7, each of which is formed in the variable resistance layer L200 in a structure penetrating the variable resistance layer L200 and can be used to connect the upper end of a variable resistance to a switch. 11 ,V 12 The first bit cell BC1 of the first bit cell line BCL1 in FIG. 11 For example, near the bottom right corner, there is an active variable resistor R 11a ,R 11b and inactive variable resistor R i is arranged, and Via V 11 is the variable resistor R 11a ,R 11b ,R i The marker may be located near the upper left corner, which is a position sufficiently spaced apart from the marker.

[0092] According to the above arrangement of FIG. 8, via V 11 ,V 12 and the active variable resistor R 11a ,R 11b The minimum distance d1 between the via V 11 ,V 12 and the inactive variable resistor R i The minimum distance between the via V and the ground plane is d2. 11 ,V 12 and the active variable resistor R 11a ,R 11b The minimum distance d1 between the via V and the 11 ,V 12 and the inactive variable resistor R i The minimum distance d2 between the first and second electrodes may be, for example, 0.30 μm to 0.60 μm.

[0093] Variable resistor R 11a ,R 11b ,R i The minimum distance d3 between the via V 11 ,V 12 and the active variable resistor R 11a ,R11b The minimum distance d1 between 11 ,V 12 and the inactive variable resistor R i The distance d2 between the via V and the via hole 11 may be set to, for example, 0.10 μm to 0.40 μm. 11 ,V 12 The minimum distance d4 between adjacent vias is 11 ,V 12 and the active variable resistor R 11a ,R 11b The minimum distance d1 between the 11 ,V 12 and the inactive variable resistor R i The distance d2 may be shorter than the minimum distance d2 between the first and second electrodes, and may be, for example, 0.10 μm to 0.40 μm.

[0094] In adjacent (or neighboring) bit cells, the arrangement of the variable resistors and / or vias may be vertically symmetrical and / or horizontally symmetrical with respect to the boundary line between the adjacent (or neighboring) bit cells. For example, in the first bit cell BC 11 The variable resistor R 11a ,R 11b ,R i and Via V 11 The arrangement of adjacent bit cells BC 11 ,BC 12 Based on the boundary line between the second bit cell BC 12 The variable resistor R 12a ,R 12b ,R i and Via V 12 Similarly, the arrangement of the first bit cell BC of the first bit cell line BCL1 may be vertically symmetrical. 11 The variable resistor R 11a ,R 11b ,R i and Via V 11 The arrangement of adjacent bit cells BC 11 ,BC 21 Based on the boundary line between the first bit cell BC 21 The variable resistor R 21a ,R 21b ,R iand the arrangement of vias may be symmetrical.

[0095] 9A is a vertical cross-sectional view taken along line XX' in FIG. 8, and FIG. 9B is a vertical cross-sectional view taken along line YY' in FIG.

[0096] 9A and 9B, the processing device 100 includes a plurality of switches S 11a ,S 11b The active layer L100 and the variable resistor R 11a ,R 11b etc. and Via V 11 ,V 12 and the like, as well as a plurality of metal layers M100, M200, M300, M400, M500, M600, and M700.

[0097] The active layer L100 is a bit cell (e.g., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 ) included in the switch (e.g., S 11a , S 11b For example, in FIG. 9A, a part of the switch S 11a ,S 11b Although only the switch S is shown, other switches not shown may also be formed in the active layer L100. The active layer L100 may be a silicon-based semiconductor layer. 11a ,S 11b The specific structure will be described below with reference to FIG.

[0098] The plurality of metal layers M100, M200, M300, M400, M500, M600, and M700 form an active variable resistor R 11a ,R 11b And so on, switch S 11a ,S 11b Wiring to connect the above, switch S 11a ,S 11bFor example, the metal layers M100, M200, M300, M400, M500, and M600 may be connected to each other through vias, and the active variable resistor R 11a The bottom end of the switch S 11a Drain S 11aD Even if the active variable resistor R 11a Drain S 11aD Although the path connecting to the switch S is not shown in either FIG. 9A or FIG. 9B, a connection path can be provided through various designs. For example, the third metal layer M300 is 11a ,S 11b The fourth metal layer M400 includes wiring for transmitting ON / OFF signals to the bit data lines BDL of FIG. 1a ,BDL 1b The seventh metal layer M700 may also include vias V 11 ,V 12 and the active variable resistor R 12a ,R 13b and a wiring connecting the upper end of the first electrode to the upper end of the second electrode.

[0099] FIG. 10 is a plan view of the active layer L100 of FIG. 9A.

[0100] Referring to FIG. 10, bit cell BC of FIG. 5B 11 ,BC 12 ,BC 21 ,BC 22 Switch S included in 11a ,S 11b ,S 11 In FIG. 10, the first bit cell BC1 of the first bit cell line BCL1 is 11 The three switches S 11a ,S 11b ,S 11 As an example, the structure of the active layer L100 will be described in detail.

[0101] Switch S included in active layer L100 11a ,S 11b ,S 11The first switch S may be a metal oxide semiconductor field effect transistor (MOSFET) transistor including a source, a drain, and a gate. A switch implemented by a MOSFET transistor can operate in such a way that when a gate voltage (above a threshold voltage) is applied to the gate, the switch is turned on and the source and drain are electrically connected, and when no gate voltage is applied, the switch is turned off and the source and drain are electrically disconnected. For example, the first switch S 11a Gate S 11aG When a gate voltage is applied, the first switch S 11a is turned on, and the first switch S 11a Source S 11CS1 and the first switch S 11a Drain S 11aD In FIG. 10, the first switch S 11a and the second switch S 11b Source S 11CS1 The bit data line switch S 11 is two gates S 11Ga ,S 11Gb , 2 drain S 11Da ,S 11Db , and common source S 11CS2 The bit data line switch S 11 By using two transistors that receive the same signal, the switch S in the active layer L100 can operate just like one transistor. 11a ,S 11b ,S 11 etc. can be connected to the first metal layer M100 in the indicated region L110.

[0102] FIG. 11 is a plan view of the seventh metal layer M700 of FIG. 9A.

[0103] Referring to FIG. 11, a seventh metal layer M700 is stacked on the variable resistance layer L200, and a via V 11 ,V12 and the active variable resistor R 11a ,R 11b For example, a wiring may be provided to connect the upper end of the first bit cell BC 11 Via V 11 is connected to the second bit cell BC via the wiring M750 of the seventh metal layer M700. 12 Active variable resistor R 12a ,R 12b can be connected to the upper end of the

[0104] 7, the first bit cell BC 11 Active variable resistor R 11a ,R 11b The current I flows from the top to the bottom of each layer through the metal layers M100 to M600, down to the active layer L100, and through the switch S 11a ,S 11b Then, the current I passes through the metal layers M100 to M600 and the via V11, and then through the wiring M750 of the first metal layer M700 to the second bit cell BC 12 Active variable resistor R 12a ,R 12b can flow to the top end of each.

[0105] Metal layers M100, M200, M500, and M600 may also provide the necessary wiring for electrical connection between the aforementioned components, with insulating layers being disposed between the metal layers M100 to M600.

[0106] In the above embodiment, the variable resistance layer L200 is connected to one via V for each bit cell. 11 ,V 12 However, the number of vias included in a bit cell line may be greater or less than the number of bit cells. For example, a bit cell line may have one via for every two adjacent (or neighboring) bit cells.

[0107] FIG. 12 is a diagram showing an embodiment of a processing device including a bit cell with a different structure than that of FIG. 5B.

[0108] Referring to FIG. 12, the processing device 300 detects whether the current I flowing through the bit cell line BCL1 is equal to or greater than the resistance of a variable resistor R 11a or R 13b For example, switch S 11a or S 13b The bit cell BC' is arranged to flow through the 11 ,BC' 13 Includes:

[0109] The first bit cell BC' of FIG. 11 The structure is shown in FIG. 5B as the first bit cell BC 11 In comparison, the first bit cell BC in FIG. 11 The current I flowing through the first variable resistor R 11a through the first switch S 11a 12. Meanwhile, the first bit cell BC' of FIG. 11 The current I flowing through the first switch S 11a through the first variable resistor R 11a That is, the first bit cell BC' in FIG. 11 and the first bit cell BC in FIG. 5B. 11 In this structure, the direction of the current I is the reference, and the switch S 11a ,S 11b and variable resistor R 11a ,R 11b The positions are opposite to each other.

[0110] The processing device 300 includes a first bit cell BC' 11 Like, switch S 11a ,S 11b and variable resistor R 11a ,R 11b and the second bit cell BC of FIG. 5B. 12 Like, switch S 12a ,S 12b and variable resistor R 12a ,R 12bIn other words, the processing device 300 has a first bit cell BC' in which the positions of the switch and the variable resistor are reversed. 11 Between the third bit cell BC'13 and the second bit cell BC'13, the positions of the switch and the variable resistor are not reversed. 12 can be distributed.

[0111] According to the circuit configuration of the processing device 300 of FIG. 12, the current I flowing through the bit cell line BCL1 is 11 ,V 12 As such, current can flow through the bit cell line BCL1 without passing through the via formed in the variable resistance layer L200. The connection relationship between the variable resistance and the switch will be described in more detail with reference to FIG.

[0112] FIG. 13 shows a schematic cross section of the active layer, variable resistance layer, and metal layer of the processing device of FIG.

[0113] Referring to FIG. 13, the current I flowing through the first bit cell line BCL1 is 11 In this case, the first switch S 11a through the first variable resistor R 11a The first variable resistor R 11a and the second bit cell BC 12 The first variable resistor R 12a 7, one end (top end) of the first variable resistor R 11a The current I that passed through the second bit cell BC 12 The first variable resistor R 12a The bit data line switches S1 and S 11 ,S 12 ,S 13 is closed only when a wait is applied, and is otherwise kept open. Therefore, after applying a wait, the bit data line BDL 1a ,BDL 1bNo current I flows through the first bit cell line BCL1 from the second bit cell BC 12 The first variable resistor R 12a The current I passing through the switch S 12a ,S 13b through the third bit cell BC 13 The second variable resistor R 13b As described above, in FIG. 13, the current I flowing through the first bit cell line BCL1 can flow through the via V formed in the variable resistance layer L200. 11 ,V 13 It can flow without going through.

[0114] Via V in Figure 13 11 ,V 13 is the variable resistor R 11a ,R 12a For example, the second variable resistor R 12a In the process of changing the resistance value of the first via V 11 The method of changing the resistance value of the variable resistor when applying a weight to a bit cell has been described above with reference to the bit cell BC in FIG. 3. Referring again to FIG. 12, the second variable resistor R 12a To change the resistance of the second variable resistor R 12a Both ends of the first bit data line BDL 1a and the second bit data line BDL 1b Specifically, the second variable resistor R 12a The upper end of the first bit data line switch S 11 via the second bit data line BDL 1b and a second variable resistor R 12a The bottom end of the second bit cell BC 12 The first switch S 12a and the second bit data line switch S 12 via the first bit data line BDL 1a Referring to FIG. 13, the second variable resistor R 12a The top end of the first via V 11 via the first bit data line switch S 11In other words, as shown in FIG. 11 ,V 13 It can be seen that each provides a path connecting a certain variable resistor and a certain bit data line switch.

[0115] Comparing the number of vias formed in the variable resistance layer L200 of the bit cell in Fig. 13 with that of the bit cell in Fig. 7, each bit cell is shown to include one via in Fig. 7, while one via is shown for every two bit cells in Fig. 13. Specifically, the first bit cell BC' in Fig. 13 11 and the second bit cell BC 12 is one via V 11 The bit cell line BCL1 in FIG. 13 may include only the first bit cell BC' 11 and the third bit cell BC' 13 As shown in the example, a structure in which vias are formed in odd-numbered bit cells is illustrated, but a structure including vias formed in the variable resistance layers of even-numbered bit cells is also possible.

[0116] FIG. 14 is a chip block diagram of a processing device according to one embodiment.

[0117] 14, a processing device 700 includes a bit cell array 710, a controller 720, a row decoder 730, a column decoder 740, a wait driver 750, a current source controller 760, a data buffer 770, and a voltage measuring device 780. The processing device 700 shown in FIG. 14 includes components related to the above-described embodiments. However, the processing device 700 is not limited thereto, and may further include other general-purpose components in addition to the components shown in FIG.

[0118] The controller 720 can decode instructions necessary to drive and operate the processing device 700. For example, the controller 720 decodes instructions such as setting weights, checking weight settings, applying inputs, and measuring voltages, and transmits signals to the components necessary to carry out those instructions.

[0119] The bit cell array 710 may be an array of bit cells composed of the variable resistors and switches described above, where the variable resistors may be magnetic tunnel junction (MTJ) elements having magnetic material.

[0120] The row decoder 730 receives a row address and an input signal and applies an input value to the bit cell array 710. The row decoder 730 includes a digital-to-analog converter (DAC) (or an analog-to-digital converter (ADC)) and applies a driving voltage to a switch connected in series with a variable resistor based on the input value. The row decoder 730 can also change the resistance value of a variable resistor included in a bit cell in the bit cell array 710 and apply a driving voltage to an associated switch so that a target variable resistor can be selected.

[0121] The column decoder 740 receives a column address and a wait setting signal and applies a voltage / current to a variable resistor. The column decoder 740 selects a bit cell line for which voltage measurement is required and a wait line connected to a bit cell for which wait setting is required.

[0122] When setting a wait, the wait driver 750 can transmit wait data to a bit cell selected by the row decoder 730 and the column decoder 740. The wait driver 750 can set a wait and check the set wait by driving a wait line connected to the column decoder 740 based on data received from the data buffer 770. The wait driver 750 may include a current source that applies a check current to the wait line to check whether a desired resistance value is set in the variable resistor.

[0123] The current source controller 760 receives signals from the controller 720 and drives the current sources to apply current to the bit cell lines.

[0124] The voltage measurer 780 measures the voltage of the bit cell line or a capacitor connected to one end of the bit cell line and stores the measured value in an external memory (not shown). The voltage measurer 780 may include an ADC that outputs the measured value as a digital value.

[0125] FIG. 15 is a block diagram illustrating an electronic system according to an example.

[0126] 15, electronic system 800 can analyze input data using a neural network device 830 including a processing device, extract useful information, make situational decisions based on the extracted information, and control the configuration of an electronic device in which electronic system 800 is installed. For example, electronic system 800 can be applied to robotic devices such as drones and advanced driver assistance systems (ADAS), smart televisions, smartphones, medical devices, mobile devices, video display devices, measurement devices, and Internet of Things (IoT) devices, and can also be installed in various other electronic devices.

[0127] The electronic system 800 may include a processing unit 810, a random access memory (RAM) 820, a memory 840, a sensor module 850, and a communication module (Tx / Rx module) 860 in addition to the neural network device 830. The electronic system 800 may further include an input / output module, a security module, a power control device, etc. Part of the hardware configuration of the electronic system 800 may be mounted on a semiconductor chip. The neural network device 830 may be an on-chip implementation of the processing device of the above-described embodiments, or may be a device that includes the processing device of the above-described embodiments as a part thereof.

[0128] The processing unit 810 may control the overall operation of the electronic system 800. The processing unit 810 may be a central processing unit (CPU) and may include one processor core (single core) or multiple processor cores (multi-core). The processing unit 810 may process and execute programs and / or data stored in the memory 840, and may control the functions of the neural network device 830 by executing the programs stored in the memory 840. The processing unit 810 may be embodied as a graphics processing unit (GPU), an application processor (AP), etc., in addition to a CPU.

[0129] The RAM 820 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 840 may be temporarily stored in the RAM 820 by a control code or boot code of the processing unit 810. The RAM 820 may be implemented by a memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0130] The neural network device 830 performs neural network operations based on received input data and generates an information signal based on the results of the operations. The neural network device 830 may include the processing device described in the above embodiment. The neural network may include, but is not limited to, a convolutional neural network (CNN), a recurrent neural network (RNN), deep belief networks, restricted Boltzmann machines, etc. The neural network device 830 may correspond to a dedicated hardware accelerator for neural networks.

[0131] The information signal may include various types of recognition signals, such as a voice recognition signal, an object recognition signal, a video recognition signal, and a biometric recognition signal. For example, the neural network device 830 may receive frame data included in a video stream as input data and generate a recognition signal related to an object included in an image represented by the frame data. Depending on the type or function of the electronic device in which the electronic system 800 is installed, the neural network device 830 may receive various types of input data and generate a recognition signal based on the input data.

[0132] The memory 840 is a storage location for storing data, and can store an operating system (OS), various programs, and various data. The memory 840 may include volatile memory or nonvolatile memory. The nonvolatile memory includes read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FeRAM). The volatile memory includes dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Memory 840 may include, for example, a hard disk drive (HDD), a solid static drive (SSD), a compact flash (CF), a secure digital (SD), a micro-SD (micro secure digital), a mini-SD (mini secure digital), an extreme digital (xD), or a memory stick.

[0133] The sensor module 850 can collect information about the surroundings of an electronic device in which the electronic system 800 is installed. The sensor module 850 can sense or receive signals (e.g., video signals, audio signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device and convert the sensed or received signals into data. To this end, the sensor module 850 can be any of a variety of sensing devices, such as a microphone, an imaging device, an image sensor, a LIDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, or a touch sensor.

[0134] The sensor module 850 can provide the converted data as input data to the neural network device 830. For example, the sensor module 850 can include an image sensor to capture an image of the external environment of the electronic device, generate a video stream, and sequentially provide successive data frames of the video stream as input data to the neural network device 830. However, without being limited thereto, the sensor module 850 can provide various types of data to the neural network device 830.

[0135] The communication module 860 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 860 may include a communication interface connectable to a wired local area network (LAN), a wireless local area network (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or a mobile cellular network such as 3G (3rd generation), 4G (4th generation), LTE (long term evolution), or 5G (5th generation).

[0136] The electronic system 800 may further include a processor, a memory device for storing and executing program data, permanent storage such as a disk drive, a communication port for communicating with external devices, and user interface devices such as a touch panel, keys, buttons, etc. Methods embodied by software modules or algorithms may be stored on a computer-readable recording medium as computer-readable code or program instructions executable on a processor.

[0137] The above-described embodiments are merely examples and are not intended to limit the technical scope in any way. For the sake of brevity, descriptions of well-known electronic configurations, control systems, software, and other functional aspects have been omitted. Furthermore, wire connections or connecting members between components shown in the drawings are illustrative of functional connections and / or physical or circuit connections, and an actual device may be embodied by various alternative or additional functional connections, physical connections, or circuit connections.

[0138] Those skilled in the art in the art to which the above-described embodiments relate will understand that the above-described embodiments may be embodied in modified forms without departing from the essential characteristics thereof. The description of the present embodiments should be considered from an explanatory perspective, not a limiting perspective. The scope of the claims is defined in the appended claims, not the above description, and all differences within the scope of the claims should be construed as being within the scope of the claims. [Explanation of symbols]

[0139] 10 Biological Neurons 20 Neural Networks 21 Input Layer 22 nodes 100,200,300,700 Processing Devices 710-bit cell array 720 Controller 730 Row Decoder 740 column decoder 750 Weight Driver 760 Current Source Controller 770 Data Buffer 800 Electronic Systems 810 Processing Unit 820 RAM 830 Neural Network Device 840 memory 850 Sensor Module 860 Communication Module

Claims

1. In the bit cell circuit, a first variable resistor that is a resistive memory element whose resistance value is set by being switched between different resistance states; a second variable resistor, which is a resistive memory element connected in parallel with the first variable resistor, and which is set to a resistance value complementary to a resistance value of the first variable resistor; a first switch connected in series with the first variable resistor to switch application of a voltage or a current to the first variable resistor; a second switch connected in series to the second variable resistor and performing a switching operation to apply a voltage or a current to the second variable resistor in a complementary manner to the first switch; The first variable resistor and the first switch connected in series are connected in parallel with the second variable resistor and the second switch connected in series, one end of the first variable resistor and one end of the second variable resistor are commonly connected to a first bit data line; a bit cell circuit, wherein one end of the first switch and one end of the second switch are commonly connected to a second bit data line;

2. the first variable resistor is set to one of a first resistance value and a second resistance value; The second variable resistor is 2. The bit cell circuit of claim 1, wherein when the first variable resistor is set to the first resistance value, the bit cell circuit is set to the second resistance value, and when the first variable resistor is set to the second resistance value, the bit cell circuit is set to the first resistance value.

3. The resistance values of the first variable resistor and the second variable resistor are 3. The bit cell circuit according to claim 1, wherein the bit cell is set to a value corresponding to a weight for a MAC (multiply and accumulate) operation of a neural network.

4. The first switch and the second switch are 4. The bit cell circuit according to claim 1, wherein the bit cell circuit performs complementary opening and closing (ON / OFF) operations depending on an input value applied to the bit cell circuit for MAC operation of a neural network.

5. The resistance value of the bit cell circuit is 5. The bit cell circuit of claim 4, wherein when the first switch is closed by application of a first input value, the resistance is the same as the first variable resistor, and when the second switch is closed by application of a second input value, the resistance is the same as the second variable resistor.

6. The resistance value of the bit cell circuit is the first variable resistor is set to a first resistance value corresponding to a first weight, and when a first input value is applied to the bit cell circuit, the bit cell circuit has the first resistance value; the first variable resistor is set to a second resistance value corresponding to a second weight, and when the first input value is applied to the bit cell circuit, the bit cell circuit has the second resistance value; the second variable resistor is set to the first resistance value corresponding to the first weight, and when a second input value is applied to the bit cell circuit, the second variable resistor has the second resistance value; 5. The bit cell circuit of claim 4, wherein the second variable resistor is set to the second resistance value corresponding to the second weight, and has the first resistance value when the second input value is applied to the bit cell circuit.

7. The bit cell circuit 5. The bit cell circuit according to claim 4, having a resistance value corresponding to the result of an XNOR (exclusive-NOR) operation between an input value applied to the bit cell circuit and a weight set in the bit cell circuit.

8. 2. The bit cell circuit of claim 1, wherein at least one of the first and second variable resistors commonly connected to the first bit data line and the first and second switches commonly connected to the second bit data line is connected to another bit cell circuit.

9. The bit cell circuit of claim 1 , wherein the first variable resistor and the second variable resistor are magnetic tunnel junction (MTJ) elements.

10. In the bit cell circuit, a pair of variable resistors, each of which is a resistive memory element configured to have a different resistance value and connected in parallel; a pair of switches connected in series with each of the variable resistors, for complementary switching of application of voltage or current to each of the variable resistors; a first variable resistor of the pair of variable resistors and a first switch of the pair of switches connected in series is connected in parallel with a second variable resistor of the pair of variable resistors and a second switch of the pair of switches connected in series; one end of the first variable resistor and one end of the second variable resistor are commonly connected to a first bit data line; a bit cell circuit, wherein one end of the first switch and one end of the second switch are commonly connected to a second bit data line;

11. In the processing device, a bit cell array having a plurality of bit cells each including a pair of variable resistors and a pair of switches; At least one bit cell of the plurality of bit cells a first variable resistor that is a resistive memory element whose resistance value is set by being switched between different resistance states; a second variable resistor, which is a resistive memory element connected in parallel with the first variable resistor, and which is set to a resistance value complementary to a resistance value of the first variable resistor; a first switch connected in series with the first variable resistor to switch application of a voltage or a current to the first variable resistor; a second switch connected in series to the second variable resistor and performing a switching operation for applying a voltage or a current to the second variable resistor in a complementary manner to the first switch; a pair of bit data lines connected between at least one of the bit cells and applying a voltage or current to both ends of the at least one of the bit cells to set the resistance value of the pair of variable resistors.

12. the plurality of bit cells form the bit cell array including a plurality of bit cell lines; 12. The processing device of claim 11, wherein each of the bit cell lines includes serially connected bit cells among the bit cells.

13. a first bit cell line among the plurality of bit cell lines processes a MAC (multiply and accumulate) operation performed at a first node among a plurality of nodes of a neural network; 13. The processing device of claim 12, wherein the pair of variable resistors included in each bit cell of the first bit cell line are set to a resistance value corresponding to a weight for a MAC operation performed at the first node.

14. The pair of switches included in each of the bit cells are 14. The processing device according to claim 13, wherein one switch is closed and the other switch is opened depending on an input value of the MAC operation performed at the first node.

15. The result of the MAC operation at the first node is 15. The processing device of claim 14, wherein the value corresponds to a voltage drop across the first bit cell line caused by a predetermined value of current applied to the first bit cell line when the setting of the resistance value corresponding to the weight and the switching operation of the switch corresponding to the input value are completed.

16. The value of the voltage drop on the first bit cell line is 16. The processing device of claim 15, wherein the voltage drop corresponds to the sum of the values of the voltage drops occurring in each of the bit cells included in the first bit cell line.

17. 17. The processing device according to claim 11, wherein the processing device is a device that performs in-memory processing.

18. In a processing device including a bit cell array, a plurality of bit cells; a pair of bit data lines; At least one bit cell of the plurality of bit cells a pair of variable resistors, which are resistive memory elements connected in parallel and configured to have different resistance values by being switched between different resistance states; a pair of switches connected in series with each of the variable resistors, for complementary switching of application of voltage or current to each of the variable resistors; The pair of bit data lines are coupled between one or more of the at least one bit cell and configured to apply a voltage or current across the one or more bit cells to set the resistance value of the pair of variable resistors.

Images