Semiconductor device and semiconductor package

Abstract

To provide a semiconductor device and a semiconductor package capable of suppressing breakage of the device.SOLUTION: A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a gate electrode, a third semiconductor region of the second conductivity type, a conductive part, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, a sixth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region includes a first region and a second region. The second semiconductor region and the third semiconductor region are provided on the first region. The gate electrode is provided on the second semiconductor region. The third semiconductor region is separated from the second semiconductor region. The conductive part is provided on the third semiconductor region. The fourth semiconductor region is provided on the second region so as to be in contact with the third semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The sixth semiconductor region has an impurity concentration of the first conductivity type higher than that of the first semiconductor region, being in contact with the third semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a semiconductor package. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, for example. There is a demand for technology that can prevent breakdown of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-82848 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor package that can suppress damage to the device. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a gate electrode, a third semiconductor region of the second conductivity type, a conductive portion, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, a sixth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The first semiconductor region includes a first region and a second region provided on the first region. The second semiconductor region is provided on the first region. The gate electrode is provided on the second semiconductor region via a gate insulating layer. The third semiconductor region is provided on the first region. The third semiconductor region is separated from the second semiconductor region via the second region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The conductive portion is provided on the third semiconductor region via an insulating layer. The fourth semiconductor region is provided on the second region and contacts the third semiconductor region. The fifth semiconductor region is provided on a portion of the fourth semiconductor region. The sixth semiconductor region has a higher impurity concentration of the first conductivity type than the first semiconductor region and contacts the third semiconductor region. The second electrode is provided on the fourth semiconductor region and the fifth semiconductor region and is electrically connected to the fourth semiconductor region and the fifth semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a part of a semiconductor device according to a first embodiment. [Figure 2] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 3] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a reference example. [Figure 6]FIG. 1 is a plan view showing a part of a semiconductor device according to a first embodiment. [Figure 7] FIG. 1 is a plan view showing a part of a semiconductor device according to a first embodiment. [Figure 8] FIG. 4 is a schematic diagram showing a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 9] FIG. 10 is a schematic diagram showing a part of a semiconductor device according to a second modification of the first embodiment. [Figure 10] FIG. 10 is a schematic view showing a part of a semiconductor device according to a third modified example of the first embodiment. [Figure 11] FIG. 10 is a schematic view showing a part of a semiconductor device according to a fourth modification of the first embodiment. [Figure 12] FIG. 10 is a schematic view showing a part of a semiconductor device according to a fifth modification of the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a sixth modification of the first embodiment. [Figure 14] 14 is a cross-sectional view taken along A1-A2 in FIG. 13. [Figure 15] FIG. 13 is a cross-sectional view showing a part of a semiconductor device according to a seventh modification of the first embodiment. [Figure 16] FIG. 13 is a cross-sectional view showing a part of a semiconductor device according to a seventh modification of the first embodiment. [Figure 17] 17 is a cross-sectional view taken along A1-A2 in FIGS. 15 and 16. FIG. [Figure 18] FIG. 13 is a schematic diagram showing the operation of the semiconductor device according to the seventh modification of the first embodiment. [Figure 19] FIG. 13 is a plan view showing a part of a semiconductor device according to an eighth modification of the first embodiment. [Figure 20] FIG. 13 is a plan view showing a part of a semiconductor device according to an eighth modification of the first embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a second embodiment. [Figure 22] FIG. 10 is a plan view showing a part of a semiconductor device according to a second embodiment. [Figure 23] FIG. 10 is a plan view showing a part of a semiconductor device according to a second embodiment. [Figure 24]FIG. 10 is a plan view showing a part of a semiconductor package according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing a part of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a MOSFET. As shown in FIG. - type (first conductivity type) drift region 1 (first semiconductor region), p + type (second conductivity type) semiconductor region 2 (second semiconductor region), p + a p-type semiconductor region 3 (third semiconductor region), a p-type base region 4 (fourth semiconductor region), + source region 5 (fifth semiconductor region), n+ Semiconductor region 6 (sixth semiconductor region), n + shaped drain region 8, p + The semiconductor device includes a contact region 9, a gate electrode 10, a conductive portion 20, a drain electrode 31 (first electrode), and a source electrode 32 (second electrode).

[0009] The embodiment will be described using an XYZ Cartesian coordinate system. - The direction toward the drift region 1 is the Z direction (first direction). The direction perpendicular to the Z direction is the X direction (second direction). The direction perpendicular to the X and Z directions is the Y direction (third direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - This is a direction based on the relative positional relationship with the shape drift region 1 and is unrelated to the direction of gravity.

[0010] The drain electrode 31 is provided on the bottom surface of the semiconductor device 100. + The drain region 8 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. - The drift region 1 is n + The n-type drain region 8 is provided on the n-type drain region 8. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 8 is lower than that of the n-type impurity concentration of the n-type drain region 8. - The drift region 1 is n + The semiconductor layer 1 is electrically connected to the drain electrode 31 via the drain region 8 .

[0011] n - The drift region 1 includes a first region 1a and a second region 1b. The second region 1b is partially disposed on the first region 1a. + Semiconductor region 2 and p + The semiconductor region 3 is provided on the first region 1a. + Semiconductor region 2 and p +The semiconductor regions 3 are spaced apart from each other in the X direction via the second regions 1b. + Semiconductor region 2, second region 1b (n - part of the drift region 1), p + The semiconductor regions 3 are arranged side by side in this order.

[0012] The gate electrode 10 is connected to the p + The conductive portion 20 is provided on the semiconductor region 2 via an insulating layer 21. + The semiconductor region 3 is provided on the substrate. + A portion of the semiconductor region 3 is provided around the lower portion of the conductive portion 20 along the XY plane.

[0013] The p-type base region 4 is - The p-type base region 4 is formed on the p-type drift region 1. + Apart from the semiconductor region 2, + The semiconductor region 3 is in contact with the p + The potential of the p-type semiconductor region 3 is substantially the same as the potential of the p-type base region 4. For example, + Semiconductor region 2 and p + The p-type impurity concentration of each of the p-type semiconductor regions 3 is higher than the p-type impurity concentration of the p-type base region 4. + The p-type source region 5 is provided on a part of the p-type base region 4. + The p-type contact region 9 is provided on another part of the p-type base region 4. + The p-type impurity concentration of the p-type contact region 9 is higher than the p-type impurity concentration of the p-type base region 4 .

[0014] The gate electrode 10 faces the p-type base region 4 in the X direction via the gate insulating layer 11. In the illustrated example, the gate electrode 10 faces the second region 1b and the n-type base region 4 in the X direction via the gate insulating layer 11. + The conductive portion 20 also faces the p-type source region 5 through the insulating layer 21 in the X direction. + p-type semiconductor region 3, p-type base region 4, and p +The contact area 9 faces the substrate 1 .

[0015] n + The semiconductor region 6 is p + Apart from the semiconductor region 2, + In the illustrated example, n + The semiconductor region 6 is p + The electrodes are provided directly below both ends of the semiconductor region 3 in the X direction.

[0016] The source electrode 32 is + Shape source region 5 and p + shaped contact region 9, + Shape source region 5 and p + The p-type base region 4 is electrically connected to the p-type contact region 9. + The gate electrode 10 is electrically connected to the source electrode 32 via a contact region 9. The gate electrode 10 and the conductive portion 20 are electrically isolated from the source electrode 32 by a gate insulating layer 11 and an insulating layer 21, respectively.

[0017] The conductive portion 20 is electrically connected to the gate electrode 10. The potential of the conductive portion 20 may be floating, which reduces the gate-drain capacitance Cgd and the feedback capacitance of the semiconductor device 100. Alternatively, the conductive portion 20 may be electrically connected to the source electrode 32.

[0018] Second area 1b, p + Semiconductor region 2, p + p-type semiconductor region 3, p-type base region 4, n + Shape source area 5, p + The contact region 9, gate electrode 10, and conductive portion 20 each extend in the Y direction, and a plurality of them are provided in the X direction. For example, the gate electrodes 10 and the conductive portions 20 are provided alternately in the X direction. When the conductive portion 20 is electrically connected to the source electrode 32, the end of the conductive portion 20 in the Y direction is pulled upward and electrically connected to the source electrode 32.

[0019] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 31 relative to the source electrode 32, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 4, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 32 to the drain electrode 31. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 4 disappears, turning the semiconductor device 100 off.

[0020] An example of the material of each component of the semiconductor device 100 will be described. n - Shape drift region 1, p + Semiconductor region 2, p + p-type semiconductor region 3, p-type base region 4, n + Shape source region 5, n + Semiconductor area 6, n + shaped drain region 8, and p + The contact region 9 includes a semiconductor material. The semiconductor material may be silicon carbide. The semiconductor material may be silicon, gallium nitride, or gallium arsenide. The n-type impurity may be arsenic, phosphorus, or antimony. The p-type impurity may be boron.

[0021] The gate insulating layer 11 and the insulating layer 21 include an insulating material. For example, the gate insulating layer 11 and the insulating layer 21 include silicon oxide, silicon nitride, or silicon oxynitride. The gate electrode 10 and the conductive portion 20 include a conductive material such as polysilicon. The gate electrode 10 and the conductive portion 20 may be doped with n-type or p-type impurities. The drain electrode 31 and the source electrode 32 include a metal such as titanium, tungsten, or aluminum.

[0022] 2 to 4 are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. An example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. +A semiconductor substrate including a semiconductor layer 8x is prepared. + On the semiconductor layer 8x, n is epitaxially grown. - A semiconductor layer 1x is formed. - An n-type semiconductor layer 1y is formed on the n-type semiconductor layer 1x by epitaxial growth. - As shown in FIG. 2(a), the n-type semiconductor layer 1y has a higher n-type impurity concentration than the n-type semiconductor layer 1x. + A shaped semiconductor region 6x is formed.

[0023] P-type impurity ions are implanted into the n-type semiconductor layer 1y, + shaped semiconductor regions 2x and p + As shown in FIG. 2(b), p-type impurities and n-type impurities are ion-implanted sequentially into the upper surface of the n-type semiconductor layer 1y to form p-type semiconductor regions 4x and n-type semiconductor regions 3x. + Semiconductor region 5x and p + A shaped semiconductor region 9x is formed.

[0024] By reactive ion etching (RIE), p-type semiconductor regions 4x and n + A trench T1 passing through the p-type semiconductor region 5x and the p-type semiconductor region 4x and p + A trench T2 is formed through the semiconductor region 9x, and an insulating layer 11x is formed along the inner surfaces of the trenches T1 and T2 by thermal oxidation, as shown in FIG.

[0025] A conductive layer filling trenches T1 and T2 is formed on insulating layer 11x by chemical vapor deposition (CVD). The upper surface of the conductive layer is recessed by chemical dry etching (CDE). As a result, as shown in FIG. 3(b), a conductive layer 10x is formed inside trench T1, and a conductive layer 20x is formed inside trench T2.

[0026] An insulating layer 11y is formed to cover the conductive layers 10x and 20x. Part of the insulating layer 11x and part of the insulating layer 11y are removed by RIE, and n + Semiconductor regions 5x and p+ 4(a), an insulating layer 11x and a metal layer 32x are formed on the insulating layer 11x.

[0027] n + The semiconductor layer 8x is then grown to a predetermined thickness. + The bottom surface of the semiconductor layer 8x is ground. + A metal layer 31x is formed under the conductive semiconductor layer 8x. Through the above steps, the semiconductor device 100 shown in FIG.

[0028] n shown in Figure 4(b) - The semiconductor layer 1x is the n-type semiconductor layer shown in FIG. - The n-type semiconductor layer 1y corresponds to the first region 1a of the n-type drift region 1. The n-type semiconductor layer 1y corresponds to the second region 1b. + shaped semiconductor regions 2x and p + The semiconductor regions 3x are p + Semiconductor region 2 and p + The p-type semiconductor region 4x corresponds to the p-type base region 4. + The semiconductor region 5x is n + corresponds to the source region 5. + The semiconductor region 6x is n + corresponds to the semiconductor region 6. + The semiconductor layer 8x is n + corresponding to the drain region 8. + The semiconductor region 9x is p + The metal layer 31x corresponds to the drain electrode 31. The metal layer 32x corresponds to the source electrode 32. The conductive layer 10x corresponds to the gate electrode 10. The conductive layer 20x corresponds to the conductive portion 20. The metal layer 31x corresponds to the drain electrode 31. The metal layer 32x corresponds to the source electrode 32.

[0029] The semiconductor device 100 according to the first embodiment can be manufactured by a manufacturing method other than the example shown in the drawings. For example, the n-type semiconductor layer 1y may be formed by epitaxial growth multiple times. + shaped semiconductor regions 2x and p +P-type impurities are ion-implanted into the region corresponding to the p-type semiconductor region 3x. + The bottom of the semiconductor region 3x is p + The p-type semiconductor region is formed by the same ion implantation as the p-type semiconductor region 2x. + The upper portion of the semiconductor region 3x may be formed by ion implantation through the trench T2. The specific ion implantation method may be appropriately selected from a method of implanting ions from a direction tilted with respect to the normal direction of the semiconductor substrate surface, a method of implanting ions at a high acceleration, and the like.

[0030] The advantages of the first embodiment will be described. FIG. 5 is a cross-sectional view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in FIG. + Semiconductor region 3, conductive portion 20, n + In the semiconductor device 100r, a p-type semiconductor region 6 is not provided under the gate electrode 10. + The n-type semiconductor region 2 is provided. - Shape drift region 1 and p + Avalanche breakdown is more likely to occur between the gate insulating layer 11 and the bottom semiconductor region 2, and it is possible to suppress the occurrence of avalanche breakdown at the bottom of the gate electrode 10. As a result, dielectric breakdown of the gate insulating layer 11 is less likely to occur.

[0031] In the semiconductor device 100r, n - Shape drift region 1 and any p + Avalanche breakdown may occur intensively between the gate electrode 10 and the semiconductor region 2. This generates a large amount of holes and electrons. The generated holes attack the gate insulating layer 11, causing a short circuit between the gate electrode 10, the drain electrode 31, and the source electrode 32. This destroys the semiconductor device 100r.

[0032] In the semiconductor device 100, p + n-shaped semiconductor region 3 + A semiconductor region 6 is provided. + The n-type impurity concentration of the n-type semiconductor region 6 is -The n-type impurity concentration of the n-type drift region 1 is higher than that of the n-type drift region 2. Therefore, when the semiconductor device 100 withstands a voltage, + Semiconductor region 3 and n + The electric field strength in the vicinity of the pn junction with the semiconductor region 6 is - Shape drift region 1 and p + The electric field strength is higher than that in the vicinity of the pn junction between the semiconductor region 2 and the p + Semiconductor region 3 and n + Avalanche breakdown occurs between the n-type semiconductor region 6 and the n-type semiconductor region 7. - Shape drift region 1 and p + This can suppress the occurrence of avalanche breakdown between the semiconductor region 2 and the gate electrode 1.

[0033] When avalanche breakdown occurs, a large amount of holes and electrons are generated. The holes are discharged to the source electrode 32 through the p-type base region 4. The electrons are discharged to the n - Shape drift region 1 and n + The semiconductor device 100 is configured such that the p + The p-type semiconductor region 3 is in contact with the p-type base region 4. + The electrical resistance for holes between the p-type semiconductor region 3 and the p-type base region 4 is + The electrical resistance to holes between the p-type semiconductor region 2 and the p-type base region 4 is lower than that between the p-type semiconductor region 2 and the p-type base region 4. + Semiconductor region 3 and n + When avalanche breakdown occurs between the p-type semiconductor region 6 and the gate insulating layer 11, holes tend to flow into the p-type base region 4. This prevents the gate insulating layer 11 from being destroyed by avalanche breakdown. This prevents the semiconductor device 100 from being destroyed, improving the reliability of the semiconductor device 100.

[0034] The n-type impurity concentration of the second region 1b is preferably higher than the n-type impurity concentration of the first region 1a. The second region 1b is aligned with the gate electrode 10 in the X direction and is more easily depleted than the first region 1a. By having the n-type impurity concentration higher in the second region 1b than in the first region 1a, it is possible to reduce the on-resistance of the semiconductor device 100 while suppressing a decrease in the breakdown voltage of the semiconductor device 100.

[0035] n+ The higher the n-type impurity concentration of the n-type semiconductor region 6, the + Semiconductor region 3 and n + Avalanche breakdown is likely to occur between the n-type semiconductor region 6. + If the n-type impurity concentration of the n-type semiconductor region 6 is too high, + The n-type impurities may diffuse from the n-type semiconductor region 6 to other semiconductor regions, which may reduce the breakdown voltage of the semiconductor device 100. + The n-type impurity concentration of the semiconductor region 6 is 1.0×10 17 atom / cm 3 higher than 1.0×10 18 atom / cm 3 It is preferable that it is lower than p + The p-type impurity concentration of the semiconductor region 3 is set to 1000 ppm or less in order to suppress the diffusion of the p-type impurity and to sufficiently reduce the electric field strength below the conductive portion 20. . 0×10 17 atom / cm 3 higher than 1.0×10 19 atom / cm 3 It is preferable that it is lower than

[0036] An example of a preferable impurity concentration for each of the other semiconductor regions is as follows: - The n-type impurity concentration of the drift region 1 is 1.0×10 15 atom / cm 3 Higher than 5.0 × 10 16 atom / cm 3 Lower than p + The p-type impurity concentration of the semiconductor region 2 is 1 . 0×10 18 atom / cm 3 higher than 1.0×10 19 atom / cm 3 The p-type impurity concentration of the p-type base region 4 is lower than 1.0×10 16 atom / cm 3 Higher than 5.0 × 10 18 atom / cm 3 Lower than n + The n-type impurity concentration of the source region 5 is 5.0×10 18atom / cm 3 Higher than 5.0 × 10 20 atom / cm 3 Lower than n + The n-type impurity concentration of the n-type drain region 8 is 1.0×10 18 atom / cm 3 higher than 1.0×10 20 atom / cm 3 Lower than p + The p-type impurity concentration of the contact region 9 is 1.0×10 18 atom / cm 3 higher than 1.0×10 20 atom / cm 3 Lower than.

[0037] 6(a), 6(b), 7(a), and 7(b) are plan views showing a part of the semiconductor device according to the first embodiment. 6(a) and 6(b) correspond to the A1-A2 cross section of FIG. 1. As shown in FIG. 6(a), n + The semiconductor region 6 is p + 6(b), the plurality of n + The semiconductor regions 6 may be arranged apart from each other in the Y direction.

[0038] The structure shown in FIG. 6(a) allows avalanche breakdown to occur more uniformly in the Y direction than the structure shown in FIG. 6(b). As a result, n - Shape drift region 1 and p + The occurrence of avalanche breakdown between the semiconductor region 2 is further suppressed.

[0039] 7(a) and 7(b) correspond to the B1-B2 cross section of Fig. 1. In the XY plane, the number of gate electrodes 10 per unit area may be the same as or different from the number of conductive portions 20 per unit area.

[0040] The semiconductor device 100 includes a first structural portion 101 shown in FIG. 7(a), for example. In the first structural portion 101, two or more conductive portions 20 and one gate electrode 10 are alternately provided in the X direction. The number of conductive portions 20 per unit area is greater than the number of gate electrodes 10 per unit area. By providing the first structural portion 101, p + Semiconductor region 3 and n + This makes it easier for avalanche breakdown to occur between the semiconductor region 6 and the gate electrode 1.

[0041] The semiconductor device 100 may include a second structural portion 102 shown in FIG. 7(b). In the second structural portion 102, two or more gate electrodes 10 and one conductive portion 20 are alternately provided in the X direction. The number of gate electrodes 10 per unit area is greater than the number of conductive portions 20 per unit area. By providing the second structural portion 102, the channel density in the on state can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0042] The cross-sectional structure taken along line C1-C2 in Fig. 7(a) and the cross-sectional structure taken along line D1-D2 in Fig. 7(b) are similar to the cross-sectional structure shown in Fig. 1. The semiconductor device 100 may include only the first structural portion 101 or the second structural portion 102, or may include both the first structural portion 101 and the second structural portion 102.

[0043] FIG. 8 is a schematic diagram showing a part of a semiconductor device according to a first modification of the first embodiment. In the semiconductor device 110 according to the first modification, as shown in FIG. + The position of the lower end of the semiconductor region 6 in the Z direction is p + The position of the lower end of the semiconductor region 3 in the Z direction is the same as that of the lower end of the semiconductor region 3. + The semiconductor region 6 is p + The n-type semiconductor region 3 is located on both sides in the X direction of the n-type semiconductor region 3. + The semiconductor region 6 is the n-type semiconductor region of the semiconductor device 100. + The semiconductor region 6 is longer in the Z direction.

[0044] FIG. 9 is a schematic diagram showing a part of a semiconductor device according to a second modification of the first embodiment. In the semiconductor device 120 according to the second modification, as shown in FIG. + The bottom end of the semiconductor region 6 is p + The semiconductor region 3 is located above the lower end of the n + The semiconductor region 6 is p + The conductive portions 20 are located on both sides of the semiconductor region 3 in the X direction. + The semiconductor regions 6 are located between each other.

[0045] Fig. 10 is a schematic diagram showing a part of a semiconductor device according to a third modified example of the first embodiment. Fig. 11 is a schematic diagram showing a part of a semiconductor device according to a fourth modified example of the first embodiment. In the semiconductor devices 130 and 140 according to the third and fourth modifications, as shown in FIGS. 10 and 11, n + The semiconductor region 6 is separated from the first region 1a in the Z direction by + In the semiconductor device 130 shown in FIG. + The length of the semiconductor region 6 in the X direction is p + In the semiconductor device 140 shown in FIG. + The length of the semiconductor region 6 in the X direction is p + The length of the semiconductor region 3 in the X direction is shorter than that of the semiconductor region 3 .

[0046] In any of the semiconductor devices shown in FIGS. + n-shaped semiconductor region 3 + A p-type semiconductor region 6 is provided. + The p-type semiconductor region 3 is in contact with the p-type base region 4. This makes it possible to suppress destruction of the semiconductor device due to avalanche breakdown.

[0047] More preferably, n + As shown in FIGS. 8, 10, and 11, the semiconductor region 6 is + The semiconductor region 3 is in contact with at least a portion of the lower end thereof. + Near the bottom of the semiconductor region 3,+ The electric field strength is higher than that in the upper part of the semiconductor region 3. + Semiconductor region 6 is p + By contacting at least a part of the lower end of the semiconductor region 3, + Semiconductor region 3 and n + Avalanche breakdown occurs more easily between the semiconductor region 6. - Shape drift region 1 and p + The occurrence of avalanche breakdown between the semiconductor region 2 is further suppressed.

[0048] In particular, as shown in FIGS. 8 and 10, n + The semiconductor region 6 is p + It is preferable that the electrode contacts the lower end of the end portion of the semiconductor region 3 in the X direction. The electric field strength is highest at the lower end. + Semiconductor region 6 is p + By contacting the lower end of the end of the semiconductor region 3 in the X direction, + Semiconductor region 3 and n + Avalanche breakdown is more likely to occur between the semiconductor region 6. - Shape drift region 1 and p + The occurrence of avalanche breakdown between the semiconductor region 2 is further suppressed.

[0049] FIG. 12 is a schematic diagram showing a part of a semiconductor device according to a fifth modification of the first embodiment. In the semiconductor device 150 according to the fifth modification, as shown in FIG. + The p-type semiconductor region 3 includes a first portion 3a and a second portion 3b. The second portion 3b is provided on the first portion 3a. The second portion 3b is located between the first portion 3a and the conductive portion 20. The p-type impurity concentration of the first portion 3a is higher than the p-type impurity concentration of the second portion 3b.

[0050] Similarly, p + The p-type semiconductor region 2 includes a portion 2a and a portion 2b. The portion 2b is provided on the portion 2a. The portion 2b is located between the portion 2a and the gate electrode 10. The p-type impurity concentration of the portion 2a is higher than the p-type impurity concentration of the portion 2b.

[0051] At a position away from the conductive portion 20, p + By providing the first portion 3a of the semiconductor region 3, the electric field strength in the vicinity of the insulating layer 21 can be reduced, thereby suppressing the occurrence of dielectric breakdown of the insulating layer 21. Similarly, the p + The provision of the portion 2a of the semiconductor region 2 reduces the electric field strength in the vicinity of the gate insulating layer 11. This makes it possible to suppress the occurrence of dielectric breakdown in the gate insulating layer 11.

[0052] n + The semiconductor region 6 is preferably in contact with the first portion 3a. In the illustrated example, the n-type semiconductor region 6 is provided at the lower end of the end portion in the X direction of the first portion 3a. + The semiconductor region 6 is in contact with the + The semiconductor region 6 is in contact with the first portion 3a, so that p + Semiconductor region 3 and n + The electric field strength in the vicinity of the pn junction with the semiconductor region 6 can be further increased. + Semiconductor region 3 and n + Avalanche breakdown is more likely to occur between the semiconductor region 6 and the gate electrode 1.

[0053] In order to suppress the diffusion of the p-type impurity while increasing the electric field strength, the p-type impurity concentration of the first portion 3a is set to 1.0×10 19 atom / cm 3 higher than 1.0×10 20 atom / cm 3 The p-type impurity concentration of the second portion 3b is preferably lower than 1.0×10 17 atom / cm 3 higher than 1.0×10 18 atom / cm 3 It is preferable that it is lower than

[0054] Alternatively, the p-type impurity concentration of the first portion 3a is 1.0×10 17 atom / cm 3 Higher than 1.0×10 18 atom / cm 3and the p-type impurity concentration of the second portion 3b is lower than 1.0×10 18 atom / cm 3 Higher than 1.0×10 19 atom / cm 3 When the p-type impurity concentration of the first portion 3a is lower than the p-type impurity concentration of the second portion 3b, n - This reduces the electric field strength near the pn junction between the drift region 1 and the first portion 3a, thereby improving the breakdown voltage of the semiconductor device 150.

[0055] Fig. 13 is a cross-sectional view showing a part of a semiconductor device according to a sixth modified example of the first embodiment. Fig. 14 is a cross-sectional view taken along A1-A2 in Fig. 13. Fig. 13 corresponds to a cross-sectional view taken along B1-B2 in Fig. 14. The semiconductor device 160 according to the sixth modification is p + The semiconductor device further includes a semiconductor connection region 7 (seventh semiconductor region). + The connecting region 7 has a width of p + Semiconductor region 2 and p + shaped semiconductor region 3, and + Semiconductor region 2 and p + The semiconductor region 3 is in contact with the + By the shape connection area 7, p + The semiconductor region 2 is p + The p + The potential of the semiconductor region 2 is p + The potential of the p-type semiconductor region 3 and the potential of the p-type base region 4 are substantially the same. + The p-type impurity concentration of the p-type connection region 7 is p + Semiconductor region 2 and p + The p-type impurity concentration of each of the p-type semiconductor regions 3 is equal to that of the p-type semiconductor region 3. + The p-type impurity concentration of the p-type connection region 7 is p + Semiconductor region 2 and p + The p-type impurity concentrations of the p-type semiconductor regions 3 may be different from each other.

[0056] As shown in Figure 14, p + Semiconductor region 2 and p +The semiconductor region 3 extends in the Y direction. + Semiconductor region 2 and p + Between the semiconductor region 3, p + The connecting region 7 is aligned with the second region 1b in the Y direction. + The n-shaped connection regions 7 are alternately arranged in the Y direction. + The semiconductor regions 6 are aligned with the plurality of second regions 1b in the X direction.

[0057] p + The length L1 of the shaped connection region 7 in the Y direction is shorter than the length L2 of the second region 1b in the Y direction. + The potential of the semiconductor region 2 can be stabilized.

[0058] The cross-sectional structure taken along the line C1-C2 in FIG. 14 is the same as the cross-sectional structure shown in FIG. + Semiconductor region 3 and n + Avalanche breakdown is likely to occur between the n-type semiconductor region 6, and the semiconductor device 160 can be prevented from being destroyed. - Shape drift region 1 and p + Even if avalanche breakdown occurs between the semiconductor region 2 and the p + Shape connection area 7 and p + Holes can be efficiently discharged via the semiconductor region 3. Therefore, compared to the semiconductor device 100, the semiconductor device 160 can be more effectively prevented from being destroyed by avalanche breakdown.

[0059] Figures 15 and 16 are cross-sectional views showing a part of a semiconductor device according to a seventh modification of the first embodiment. Figure 17 is a cross-sectional view taken along A1-A2 in Figures 15 and 16. Figures 15 and 16 correspond to the B1-B2 and C1-C2 cross-sectional views in Figure 17, respectively. In the semiconductor device 170 according to the seventh modification, as shown in FIG. +The p-type semiconductor region 3 includes a second portion 3b to a fourth portion 3d. The third portion 3c is provided on a part of the second portion 3b. The fourth portion 3d is provided between the third portion 3c and the conductive portion 20 in the X direction. The third portion 3c and the fourth portion 3d contact the p-type base region 4. In the illustrated example, the conductive portion 20 and a pair of fourth portions 3d are located between the pair of third portions 3c. The conductive portion 20 is located between the pair of fourth portions 3d.

[0060] The p-type impurity concentration of the fourth portion 3d is lower than the p-type impurity concentrations of the second portion 3b and the third portion 3c. The difference between the p-type impurity concentration of the fourth portion 3d and the p-type impurity concentration of the p-type base region 4 is smaller than the difference between the p-type impurity concentration of the third portion 3c and the p-type impurity concentration of the p-type base region 4.

[0061] 16, the third portion 3c and the fourth portion 3d are not provided in the XZ cross section of a part of the semiconductor device 170. In this cross section, the conductive portion 20 is connected to the n-type base region 4 between the second portion 3b and the p-type base region 4 via the insulating layer 21. - It faces the shaped drift region 1.

[0062] 17, the third portions 3c are arranged apart from one another along the Y direction. The fourth portions 3d are located between the conductive portions 20 and the third portions 3c, respectively.

[0063] FIG. 18 is a schematic diagram showing the operation of the semiconductor device according to the seventh modification of the first embodiment. In the semiconductor device 170, the conductive portion 20 is electrically connected to the gate electrode 10. When the semiconductor device 170 is in an on-state, as shown in FIG. 18, a channel ch is formed in the fourth portion 3d in addition to the p-type base region 4. As shown by arrow A, some electrons pass from the channel in the p-type base region 4 through the channel ch in the fourth portion 3d, and then - The electrons flow into the drift region 1.

[0064] According to the seventh modification, when the semiconductor device 170 is in an on-state, a current can flow not only around the gate electrode 10 but also around the conductive portion 20. In particular, p + A channel can be formed in the fourth portion 3d of the p-type semiconductor region 3, allowing a current to flow. This allows the on-resistance of the semiconductor device 170 to be reduced compared to the semiconductor device 100. In addition, the second portion 3b is electrically connected to the p-type base region 4 by the third portion 3c, which has a higher p-type impurity concentration than the fourth portion 3d. Therefore, by providing the fourth portion 3d, + Therefore, an increase in the electrical resistance to holes between the p-type semiconductor region 3 and the p-type base region 4 can be suppressed.

[0065] 19 and 20 are plan views showing a part of a semiconductor device according to an eighth modification of the first embodiment. 19 and 20, in the semiconductor devices 180a and 180b according to the eighth modification, the width W1 of the gate electrode 10 and the width W2 of the conductive portion 20 are different from each other. The width is the length in the X direction.

[0066] 19, the width W2 is narrower than the width W1. Because the width W1 is narrower, the number of gate electrodes 10 per unit area can be increased compared to when the widths W1 and W2 are the same. This allows the on-resistance of the semiconductor device 180a to be further reduced compared to the semiconductor device 100.

[0067] In the semiconductor device 180b shown in FIG. 20, the width W2 is larger than the width W1. As the width W2 increases, + The width of the semiconductor region 3 also becomes wider. + Electric field concentration occurs at the lower ends of both sides of the semiconductor region 3 in the X direction. + If the width of the semiconductor region 3 is narrow, the electric field distribution around one bottom end will affect the electric field distribution around the other bottom end. The electric field strengths at both bottom ends will increase each other, resulting in an excessive increase in the electric field strength. + By increasing the width of the semiconductor region 3, it is possible to suppress an increase in the electric field intensity at both bottom ends, thereby improving the breakdown voltage of the semiconductor device 180b.

[0068] (Second embodiment) FIG. 21 is a cross-sectional view showing a part of the semiconductor device according to the second embodiment. 21, the semiconductor device 200 according to the second embodiment further includes a Schottky barrier diode (SBD) 40 compared to the semiconductor device 100 according to the first embodiment. In the semiconductor device 200, the source electrode 32 includes a protrusion 32a extending downward. The protrusion 32a is located between the p-type base region 4 and the p + The protrusion 32a is aligned with the n-type contact region 9 and is in contact with these semiconductor regions. - The protrusion 32a contacts the second region 1b of the drift region 1. The second region 1b and the protrusion 32a form the SBD 40.

[0069] The source electrode 32 includes titanium, platinum, vanadium, or the like to form the SBD 40. The source electrode 32 may also include a stacked film of titanium and aluminum.

[0070] The semiconductor device 200 includes, in addition to the SBD 40, - The semiconductor device 200 has a PN diode consisting of a p-type drift region 1 and a p-type base region 4. When a positive voltage is applied to the source electrode 32 with respect to the drain electrode 31, a current flows through the PN diode, and the characteristics of the semiconductor device 200 change. For example, crystal defects in the semiconductor region increase, causing the on-resistance of the semiconductor device 200 to fluctuate.

[0071] The SBD 40 has a lower on-state voltage than a PN diode. Therefore, in the semiconductor device 200, when a positive voltage is applied to the source electrode 32 relative to the drain electrode 31, a current flows through the SBD 40, thereby reducing the current flowing through the PN diode. This suppresses an increase in crystal defects and suppresses fluctuations in the on-state resistance of the semiconductor device 200. As a result, the reliability of the semiconductor device 200 can be improved.

[0072] 22 and 23 are plan views showing a part of the semiconductor device according to the second embodiment. For example, as shown in FIG. 22, a conductive portion 20 is provided between the gate electrode 10 and the SBD 40 in the X direction. The SBD 40 is located between the conductive portions 20. This arrangement allows for a longer distance D1 (first distance) in the X direction between the SBD 40 and the gate electrode 10 adjacent to the SBD 40 in the X direction compared to the structure shown in FIG. 23 (described later). When the semiconductor device 200 is in the on state, a current flows near the gate electrode 10, generating heat. Increasing the distance D1 can prevent the temperature of the SBD 40 from rising due to this heat generation. As a result, deterioration of the Schottky electrode (protrusion 32a) can be suppressed.

[0073] As shown in FIG. 23, the gate electrode 10 may be provided between the conductive portion 20 and the SBD 40 in the X direction. The SBD 40 is located between the gate electrodes 10. This arrangement allows for a longer distance D2 (second distance) in the X direction between the SBD 40 and the conductive portion 20 adjacent to the SBD 40 in the X direction compared to the structure shown in FIG. 22. When avalanche breakdown occurs in the semiconductor device 200, a current flows near the conductive portion 20, generating heat. Increasing the distance D2 can prevent the temperature of the SBD 40 from rising due to this heat generation. As a result, deterioration of the Schottky electrode (protrusion 32a) can be suppressed.

[0074] (Third embodiment) FIG. 24 is a plan view showing a part of the semiconductor package according to the third embodiment. 24, a semiconductor package 300 according to the third embodiment includes a semiconductor device 100, a drain terminal 51 (first terminal), a source terminal 52 (second terminal), and a gate terminal 53 (third terminal). The semiconductor device 100 includes a plurality of source electrodes 32 and a gate pad 33.

[0075] The plurality of source electrodes 32 are provided at a distance from one another on the top surface of the semiconductor device 100. The gate pad 33 is spaced apart from the plurality of source electrodes 32. The gate pad 33 is electrically isolated from the plurality of source electrodes 32 and electrically connected to the gate electrode 10. The gate pad 33 may further be electrically connected to the conductive portion 20.

[0076] The drain terminal 51 includes a mounting portion 51a. The mounting portion 51a is plate-shaped and extends along the XY plane. The drain electrode 31 of the semiconductor device 100 is mounted on the mounting portion 51a and is electrically connected to the drain terminal 51. The source terminal 52 is electrically connected to the source electrode 32 via a wiring 52a. The gate terminal 53 is electrically connected to the gate pad 33 via a wiring 53a.

[0077] The drain terminal 51, the source terminal 52, and the gate terminal 53 contain a metal such as copper, iron, or nickel. The wirings 52a and 53a are made of copper wire, aluminum ribbon, Al-Cu wire, Al-Cu ribbon, or the like, and are formed by wire bonding. The wirings 52a and 53a may each be part of a lead frame.

[0078] The semiconductor device 100 includes a first structural portion 101 and a second structural portion 102. In the first structural portion 101, 7 As shown in (a), the number of conductive portions 20 per unit area is greater than the number of gate electrodes 10 per unit area. 7 As shown in (b), the number of gate electrodes 10 per unit area is greater than the number of conductive portions 20 per unit area.

[0079] The wiring 52a is located directly above the first structural portion 101. In other words, one end of the wiring 52a contacts the source electrode 32 directly above the first structural portion 101. The number of wirings 52a located directly above the first structural portion 101 is greater than the number of wirings 52a located directly above the second structural portion 102. When the wiring 52a is located directly above the first structural portion 101, the electrical resistance between the wiring 52a and the first structural portion 101 can be reduced compared to when the wiring 52a is located directly above the second structural portion 102.

[0080] Avalanche breakdown is more likely to occur in the first structural portion 101 than in the second structural portion 102. When avalanche breakdown occurs, a large number of electrons and holes are generated in the first structural portion 101. The wiring 52a is located directly above the first structural portion 101, which makes it easier for holes to flow to the wiring 52a. As a result, damage to the semiconductor device 100 due to avalanche breakdown can be suppressed, and the reliability of the semiconductor package 300 can be improved. Furthermore, since the semiconductor device 100 includes the second structural portion 102, an increase in on-resistance caused by the provision of the first structural portion 101 can be suppressed.

[0081] The structures according to the above-described embodiments and examples can be combined as appropriate. For example, the cross-sectional structures of the first structural portion 101 and the second structural portion 102 shown in Fig. 7(a) and Fig. 7(b) may have the same structure as any of the semiconductor devices 110 to 170. In any of the semiconductor devices 110 to 140, p + The semiconductor region 3 may include a first portion 3a and a second portion 3b. + In any of the semiconductor devices 110 to 160, similarly to the semiconductor device 170, a p +The semiconductor region 3 may include the second portion 3b to the fourth portion 3d. The semiconductor devices 110 to 170, 180a, or 180b may be provided with an SBD 40, similar to the semiconductor device 200. The semiconductor device 110 to 170, 180a, 180b, or 200 may be provided in the semiconductor package 300 instead of the semiconductor device 100. In this case, the semiconductor device 110 to 170, 180a, 180b, or 200 includes a first structural portion 101 in which the number of conductive portions 20 per unit area is greater than the number of gate electrodes 10 per unit area.

[0082] In the embodiments described above, the relative levels of impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative levels of carrier concentration between each semiconductor region can also be confirmed using SCM. The impurity concentration in each semiconductor region can be measured using secondary ion mass spectrometry (SIMS).

[0083] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0084] 1:n - Shape drift region, 1a: first region, 1b: second region, 2: p + shaped semiconductor region, 2a,2b:part, 3:p +type semiconductor region, 3a: first part, 3b: second part, 3c: third part, 3d: fourth part, 4: p-type base region, 5: n + Shape source area, 6:n + Semiconductor area, 7:p + Shape connection area, 8:n + Shape drain region, 9:p + shaped contact region, 10: gate electrode, 11: gate insulating layer, 20: conductive portion, 31: drain electrode, 32: source electrode, 32a: protrusion, 33: gate pad, 40: Schottky barrier diode, 51: drain terminal, 51a: mounting portion, 52: source terminal, 52a: wiring, 53: gate terminal, 53a: wiring, 100, 100r: semiconductor device, 101: first structural portion, 102: second structural portion, 110 to 170, 180a, 180b, 200: semiconductor device, 300: semiconductor package, A: arrow, T1, T2: trench

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, electrically connected to the first electrode, and including a first region and a second region provided on the first region; a second semiconductor region of a second conductivity type provided on the first region; a gate electrode provided on the second semiconductor region via a gate insulating layer; a third semiconductor region of a second conductivity type provided on the first region and spaced apart from the second semiconductor region via the second region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a conductive portion provided on the third semiconductor region via an insulating layer; a fourth semiconductor region of the second conductivity type provided on the second region and in contact with the third semiconductor region; a fifth semiconductor region of the first conductivity type provided on a portion of the fourth semiconductor region; a sixth semiconductor region of the first conductivity type having a higher impurity concentration of the first conductivity type than the first semiconductor region and in contact with the third semiconductor region; a second electrode provided on the fourth semiconductor region and the fifth semiconductor region and electrically connected to the fourth semiconductor region and the fifth semiconductor region; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the second region has a higher impurity concentration of the first conductivity type than the first region.

3. The semiconductor device according to claim 1 , wherein the sixth semiconductor region is in contact with at least a part of a lower end of the third semiconductor region.

4. the third semiconductor region includes a first portion and a second portion provided on the first portion; a part of the second portion is located between the first portion and the conductive portion in the first direction, 4. The semiconductor device according to claim 1, wherein the concentration of the impurity of the second conductivity type in said first portion is higher than the concentration of the impurity of the second conductivity type in said second portion.

5. a seventh semiconductor region of the second conductivity type provided between the second semiconductor region and the third semiconductor region; 5. The semiconductor device according to claim 1, wherein said seventh semiconductor region is aligned with said second region in a third direction perpendicular to said first direction and said second direction.

6. The third semiconductor region is A second part; and a third portion provided on a portion of the second portion; a fourth portion provided on another part of the second portion and positioned between the conductive portion and the third portion in the second direction; Including, 6. The semiconductor device according to claim 1, wherein the fourth portion has a lower impurity concentration of the second conductivity type than the third portion.

7. 7. The semiconductor device according to claim 6, wherein a plurality of said third portions and a plurality of said fourth portions are provided in a third direction perpendicular to said first direction and said second direction.

8. A semiconductor device according to any one of claims 1 to 7; a first terminal electrically connected to the first electrode; a second terminal electrically connected to the second electrode; a wiring that electrically connects the second electrode and the second terminal; a third terminal electrically connected to the gate electrode; Equipped with the semiconductor device includes a first structure portion in which the number of the conductive portions per unit area is greater than the number of the gate electrodes per unit area, The wiring is located directly above the first structure.

9. The wiring is provided in plurality, the semiconductor device further includes a second structure portion in which the number of the gate electrodes per unit area is greater than the number of the conductive portions per unit area, 9. The semiconductor package according to claim 8, wherein the number of the wirings located directly above the first structural portion is greater than the number of the wirings located directly above the second structural portion.

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