Semiconductor device, semiconductor device manufacturing method, and electronic device

Abstract

To provide a semiconductor element capable of suppressing characteristic deterioration due to Si segregated in a boundary face between a substrate and a semiconductor layer.SOLUTION: A semiconductor element 1 comprises a substrate 10, and a semiconductor layer 20 disposed over a surface 10a of the substrate 10. The semiconductor layer 20 comprises a boundary layer 21 in contact with the surface 10a of the substrate 10 and containing a Si compensation chemical element such as Fe for compensating segregation of Si, and F at a boundary face. The Si compensation chemical element contained in the boundary layer 21 is contained at a higher concentration than Si segregated on the boundary face, and compensates the segregation of Si. F contained in the boundary layer 21 terminates dangling bond in the surface 10a of the substrate 10, and reduces the amount of Si in the boundary face to reduce the necessary amount of the Si compensation chemical element to be contained at a higher concentration than F. This allows the Si compensation chemical element at a relatively low concentration to compensate the segregation of Si. As a result, the degradation of a pressure resistance and the like due to the segregation of Si in the boundary face is suppressed, and the deterioration of current collapse due to the addition of the Si compensate chemical element is suppressed, so that characteristic deterioration of the semiconductor element 1 due to the segregation of Si in the boundary face is effectively suppressed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] An electronic device using a group III nitride semiconductor is known. For example, the device includes a semi-insulating group III nitride substrate and a group III nitride stack thereon, and the peak silicon concentration at the interface between the substrate and the stack is 1×10 20 cm -3 The carrier density at the interface is less than 5×10 16 cm -3 The following electronic device is known: With regard to this electronic device, a technique is known in which a gallium nitride-based semiconductor layer forming an interface between a group III nitride stack and a semi-insulating group III nitride substrate contains iron at a concentration equal to or greater than one-tenth of the peak silicon concentration at the interface.

[0003] Also known is a Group III nitride semiconductor epitaxial wafer that includes an iron-doped Group III nitride semiconductor substrate and a Group III nitride semiconductor layer directly thereon, in which iron is doped near the interface between the Group III nitride semiconductor layer and the Group III nitride semiconductor substrate by diffusion from the Group III nitride semiconductor substrate. 15 cm -3 As described above, a technique is known in which the iron concentration is set to at least three times the silicon concentration throughout the entire region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-21362 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-136658 Summary of the Invention [Problem to be solved by the invention]

[0005] When a semiconductor layer for forming electronic elements such as transistors is provided on a substrate, silicon may segregate at the interface between the substrate and the semiconductor layer. For example, when a semiconductor layer is provided on a substrate to which silicon has adhered due to exposure to air, silicon segregates at the interface. The segregation of silicon at the interface between the substrate and the semiconductor layer may degrade the characteristics of electronic elements such as transistors formed on the semiconductor layer, such as by reducing the breakdown voltage.

[0006] A technique for compensating for silicon segregation at the interface between the substrate and the semiconductor layer by adding elements such as iron is known. However, if the concentration of the added element such as iron is too low, the silicon is not sufficiently compensated, and there is a risk that characteristic degradation such as a decrease in breakdown voltage cannot be suppressed. On the other hand, if the concentration of the added element such as iron is too high, there is a risk that the element will cause deterioration in characteristics such as an increase in current collapse and a resultant decrease in output power.

[0007] In one aspect, the present invention aims to provide a semiconductor device capable of suppressing deterioration of characteristics caused by silicon at the interface between a substrate and a semiconductor layer. [Means for solving the problem]

[0008] In one embodiment, the present invention includes a substrate and a semiconductor layer provided on a first surface of the substrate, the semiconductor layer having an interface layer containing an element that compensates for silicon and fluorine at an interface with the first surface of the substrate, and a concentration of the silicon in the interface layer being lower than a concentration of the element in the interface layer. the semiconductor layer includes an initial layer provided on the side of the interface layer opposite to the substrate side, an electron transit layer provided on the side of the initial layer opposite to the interface layer side, and an electron supply layer provided on the side of the electron transit layer opposite to the initial layer side, and the element is contained in the substrate, the interface layer, and the initial layer. A semiconductor device is provided.

[0009] In another aspect, a method for manufacturing the semiconductor device described above ,half An electronic device is provided that includes a conductor device. [Effects of the Invention]

[0010] In one aspect, it is possible to realize a semiconductor device that can suppress deterioration of characteristics caused by silicon at the interface between the substrate and the semiconductor layer. [Brief explanation of the drawings]

[0011] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 2] 5A to 5C are diagrams illustrating the effects obtained by the interface layer according to the first embodiment. [Figure 3] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 4] 10A to 10C are diagrams (part 1) illustrating an example of a method for forming a semiconductor device according to a second embodiment. [Figure 5] 10A to 10C are diagrams (part 2) illustrating an example of a method for forming a semiconductor device according to a second embodiment. [Figure 6] 10A to 10C are views (part 3) illustrating an example of a method for forming a semiconductor device according to a second embodiment. [Figure 7] 10A to 10C are diagrams (part 4) illustrating an example of a method for forming a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a diagram illustrating an example of the relationship between the Fe concentration and characteristics of the interface layer according to the second embodiment. [Figure 9] FIG. 10 is a diagram illustrating an example of the relationship between the depth of a semiconductor layer and the concentration of Fe according to the second embodiment. [Figure 10] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a diagram illustrating an example of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a diagram illustrating an example of a semiconductor device according to a fifth embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of a semiconductor device according to a sixth embodiment. [Figure 14]13A to 13C are diagrams illustrating an example of a semiconductor package according to a seventh embodiment. [Figure 15] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to an eighth embodiment. [Figure 16] FIG. 13 is a diagram illustrating an example of a power supply device according to a ninth embodiment. [Figure 17] FIG. 20 is a diagram illustrating an example of an amplifier according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] One type of semiconductor device is known to use nitride semiconductors. Taking advantage of characteristics such as a high saturated electron velocity and a wide band gap, nitride semiconductor devices are being developed as high-voltage, high-power devices. Many reports have been published on nitride semiconductor semiconductor devices, including field-effect transistors (FETs), such as high-electron mobility transistors (HEMTs). One known HEMT uses an aluminum gallium nitride (AlGaN) layer as an electron supply layer (also referred to as a barrier layer) and a gallium nitride (GaN) layer as an electron transit layer (also referred to as a channel layer). In such HEMTs, spontaneous polarization in the AlGaN layer and piezoelectric polarization generated in the AlGaN layer due to strain caused by the difference in lattice constant between the AlGaN layer and the GaN layer generate a high-concentration two-dimensional electron gas (2DEG) in the GaN layer near the junction interface with the AlGaN layer, thereby achieving a high-power device. For this reason, HEMTs using GaN-based nitride semiconductors are expected to be used in applications such as high-power amplifiers for communications.

[0013] In forming a HEMT, a semiconductor layer including the above-described electron transit layer and electron supply layer is formed on a predetermined substrate using a metal-organic chemical vapor deposition (MOCVD) method or the like. Known techniques for forming the semiconductor layer on a substrate include a silicon carbide (SiC) substrate and a silicon (Si) substrate. Another known technique involves using a GaN substrate for forming the semiconductor layer. When a GaN-based nitride semiconductor is used for the semiconductor layer, using a GaN substrate as the substrate reduces crystal defects in the semiconductor layer formed on the substrate compared to using a heterogeneous substrate such as a SiC substrate or a Si substrate. Reducing crystal defects in the semiconductor layer formed on the substrate reduces current collapse in the HEMT formed on the semiconductor layer. Therefore, using a GaN substrate as the substrate is expected to be an effective method for improving the output characteristics of HEMTs and amplifiers to which they are applied.

[0014] However, when a GaN substrate is used as the substrate and a GaN-based nitride semiconductor is provided on the substrate as the semiconductor layer, current collapse is suppressed, but Si is easily segregated at the interface between the substrate and the semiconductor layer. For example, if a substrate before the semiconductor layer is provided is exposed to air, Si adheres to the surface of the substrate. When a semiconductor layer is provided on the Si-adhered substrate, Si segregates at the interface between the substrate and the semiconductor layer. The segregation of Si at the interface between the substrate and the semiconductor layer causes parasitic loss. For example, the segregated Si at the interface between the substrate and the semiconductor layer can function as a carrier (donor), resulting in low resistance at the interface and potentially degrading the characteristics of the HEMT, such as reducing the breakdown voltage of the HEMT formed in the semiconductor layer.

[0015] Such Si segregation can occur not only in GaN substrates but also in interfaces between various substrates, such as SiC substrates and Si substrates, and semiconductor layers provided thereon.Furthermore, Si segregation can occur not only in GaN-based nitride semiconductors but also in interfaces between semiconductor layers using various semiconductors, such as GaAs (gallium arsenide) and InP (indium phosphide), and various substrates on which they are provided.

[0016] One method proposed to suppress the effects of Si segregation at the interface between the substrate and the semiconductor layer is to provide a relatively thick, high-resistivity buffer layer on the substrate, approximately 10 μm thick. However, forming a thick buffer layer takes a relatively long time, making it difficult to adopt from the perspective of mass production.

[0017] Another method proposed is to add elements such as Fe (iron) and C (carbon) to compensate for the Si segregated at the interface between the substrate and the semiconductor layer. However, if the concentration of the added element, such as Fe, is too low compared to the concentration of Si segregated at the interface, the Si is not sufficiently compensated, making it difficult to prevent deterioration of the HEMT's characteristics, such as a decrease in its breakdown voltage. In response to this, a relatively high concentration (e.g., 1×10) of an element, such as Fe, can be added to sufficiently compensate for the Si segregated at the interface. 19 cm -3 However, if the concentration of the element is too high, the element may cause a deterioration in current collapse, which may result in a decrease in the output power of the HEMT and other degradation of its characteristics.

[0018] In view of the above, a semiconductor device is realized that can suppress characteristic degradation caused by Si at the interface between the substrate and the semiconductor layer formed thereon, using a method as shown in the following embodiment.

[0019] [First embodiment] Fig. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device according to the first embodiment.

[0020] 1 is an example of a HEMT, and includes a substrate 10, a semiconductor layer 20, a gate electrode 30, a source electrode 40, and a drain electrode 50. The substrate 10 may be, for example, a semiconductor substrate. As an example, the substrate 10 may be a GaN substrate. Alternatively, the substrate 10 may be a SiC substrate, a Si substrate, an AlN (aluminum nitride) substrate, an AlGaN substrate, or the like. The substrate 10 may have a single-layer structure of one type of substrate, or a stacked structure of two or more types of substrates.

[0021] The substrate 10 may be a base substrate having a semiconductor layer thereon, such as a GaN layer, a SiC layer, a Si layer, an AlN layer, an AlGaN layer, etc. In this case, the base substrate may be a GaN substrate, a SiC substrate, a Si substrate, an AlN substrate, an AlGaN substrate, or other substrates such as a sapphire substrate or a diamond substrate.

[0022] The substrate 10 (or the semiconductor layer when the semiconductor layer is provided on the base substrate) contains an element that compensates for Si (hereinafter referred to as "Si compensation element"). Examples of the Si compensation element in the substrate 10 include Fe, C, and Mn (manganese). The substrate 10 may contain one type of Si compensation element, or two or more types of Si compensation elements. The concentration of the Si compensation element contained in the substrate 10 is, for example, 1×10 18 cm -3 It is set to the above.

[0023] Before the semiconductor layer 20 is provided on one surface 10a of the substrate 10 (the surface 10a of the semiconductor layer in the case where a semiconductor layer is provided on a base substrate), as described below, Si attached to the surface 10a is removed and dangling bonds on the surface 10a are terminated with F (fluorine). By terminating the dangling bonds on the surface 10a of the substrate 10 with F, the amount of Si that will subsequently attach to the surface 10a, i.e., the amount of Si that will contaminate the surface 10a, is reduced. For example, when F is not introduced into the surface 10a of the substrate 10, the amount of Si that will subsequently adhere to the surface 10a is reduced. 19 cm -3 The Si deposited at a concentration of the order of 10 17 cm -3The concentration is reduced to a concentration on the order of .

[0024] A semiconductor layer 20 is provided on one surface 10a of the substrate 10 as described above. The semiconductor layer 20 includes an interface layer 21, an initial layer 22, an electron transit layer 23, and an electron supply layer 24. The semiconductor layer 20 is obtained by sequentially growing the interface layer 21, the initial layer 22, the electron transit layer 23, and the electron supply layer 24 on the surface 10a of the substrate 10 by, for example, MOCVD.

[0025] The interface layer 21 is provided at the interface between the semiconductor layer 20 and the surface 10a of the substrate 10. The interface layer 21 is provided between the surface 10a of the substrate 10 and the initial layer 22 of the semiconductor layer 20. For example, when the initial layer 22 is grown on the surface 10a of the substrate 10 by MOCVD, the interface layer 21 is formed on the surface 10a of the substrate 10 in an early stage of growth. Following the formation of the interface layer 21, the growth of the initial layer 22 further progresses, thereby forming the initial layer 22. The interface layer 21 and the initial layer 22 are made of nitride semiconductors such as AlN, GaN, and AlGaN. The interface layer 21 may have a single-layer structure of one type of nitride semiconductor or a stacked structure of two or more types of nitride semiconductors. The initial layer 22 may have a single-layer structure of one type of nitride semiconductor or a stacked structure of two or more types of nitride semiconductors.

[0026] Here, the interface layer 21 contains Si compensation element and F. The Si compensation element in the interface layer 21 may be, for example, Fe, C, or Mn. The interface layer 21 may contain one type of Si compensation element, or two or more types of Si compensation elements. The concentration of the Si compensation element contained in the interface layer 21 is set to be higher than the concentration of Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. However, the concentration of the Si compensation element contained in the interface layer 21 is set to be, for example, 5×10 18 cm -3 It is preferable to set it as follows:

[0027] The interface layer 21 containing the Si compensation element is formed, for example, by adding the Si compensation element at least in the initial stage of growth when the initial layer 22 is grown on the surface 10a of the substrate 10 by MOCVD. The Si compensation element in the interface layer 21 may include one present on the surface 10a of the substrate 10, one diffused from the substrate 10, one in the initial layer 22 grown with the addition of the Si compensation element, or one diffused from the initial layer 22.

[0028] The F in the interface layer 21 includes F introduced to terminate dangling bonds on the surface 10a of the substrate 10 before providing the semiconductor layer 20 (the interface layer 21). An initial layer 22 is grown on the surface 10a of the substrate 10 by MOCVD, and the interface layer 21 containing F is formed in the initial stage of growth.

[0029] The Si compensation element may be contained in the initial layer 22 in addition to the interface layer 21. Examples of the Si compensation element used in the initial layer 22 include Fe, C, and Mn. The initial layer 22 may contain one type of Si compensation element, or two or more types of Si compensation elements. The initial layer 22 containing the Si compensation element is formed by adding the Si compensation element when growing the initial layer 22 on the surface 10a of the substrate 10 by MOCVD.

[0030] The Si compensation element in the initial layer 22 does not necessarily need to be uniformly contained in the initial layer 22. For example, the Si compensation element in the initial layer 22 may be distributed so that it is contained in a region near the interface layer 21 but not in a region near the electron transit layer 23. Furthermore, the initial layer 22 may have a region in which the concentration of the Si compensation element increases in the direction from the interface layer 21 side toward the electron transit layer 23 side, all or part of the region near the interface layer 21. Various distributions of the Si compensation element in the initial layer 22 are achieved by adjusting the amount of Si compensation element added when the initial layer 22 is grown on the surface 10a of the substrate 10 by MOCVD.

[0031] The electron transit layer 23 is provided on a surface 22a of the initial layer 22 opposite to the interface layer 21 or the substrate 10. The electron transit layer 23 is made of a nitride semiconductor such as GaN or AlGaN. The electron transit layer 23 may have a single-layer structure made of one type of nitride semiconductor, or a stacked structure made of two or more types of nitride semiconductors. For example, the electron transit layer 23 is made of i-type GaN.

[0032] The electron supply layer 24 is provided on a surface 23a of the electron transit layer 23 opposite to the initial layer 22. The electron supply layer 24 is made of a nitride semiconductor such as AlGaN, InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), AlN, or ScAlN (scandium aluminum nitride). The electron supply layer 24 may have a single-layer structure of one type of nitride semiconductor, or a stacked structure of two or more types of nitride semiconductors.

[0033] A 2DEG 1a is generated in the electron transit layer 23 near the junction interface with the electron supply layer 24. The electron transit layer 23 and the electron supply layer 24 are made of nitride semiconductors in such a combination that a 2DEG 1a is generated in the electron transit layer 23.

[0034] Although not shown, a spacer layer made of a nitride semiconductor such as AlN or AlGaN may be provided between the electron transit layer 23 and the electron supply layer 24. A cap layer made of a nitride semiconductor such as GaN may be provided on a surface 24a of the electron supply layer 24 opposite to the electron transit layer 23. The semiconductor layer 20 may include such a spacer layer and cap layer in addition to the interface layer 21, initial layer 22, electron transit layer 23, and electron supply layer 24 described above.

[0035] The gate electrode 30 is provided on the surface 20a side of the semiconductor layer 20 (the surface 24a of the electron supply layer 24 in the example of FIG. 1). The gate electrode 30 is made of a metal such as Ni (nickel) or Au (gold). The gate electrode 30 is provided so as to function as a Schottky electrode. A gate insulating film (not shown) made of an oxide, nitride, oxynitride, or the like may be interposed between the gate electrode 30 and the surface 20a of the semiconductor layer 20.

[0036] The source electrode 40 and the drain electrode 50 are provided on the surface 20a side of the semiconductor layer 20 so as to sandwich the gate electrode 30. The source electrode 40 and the drain electrode 50 are made of a metal such as Ti (titanium) or Al (aluminum). The source electrode 40 and the drain electrode 50 are provided to function as ohmic electrodes. As long as the source electrode 40 and the drain electrode 50 function as ohmic electrodes, they may be connected to the electron supply layer 24 or may penetrate the electron supply layer 24 and be connected to the electron transit layer 23. A regrowth layer using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided as a contact layer in the electron supply layer 24 or the electron transit layer 23 to which the source electrode 40 and the drain electrode 50 are connected.

[0037] When the semiconductor device 1 is in operation, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel through which carrier electrons are transported is formed in the electron transit layer 23 between the source electrode 40 and the drain electrode 50, and the semiconductor device 1 achieves a transistor function.

[0038] As described above, in the semiconductor device 1, the semiconductor layer 20 provided on the surface 10a of the substrate 10 has an interface with the surface 10a of the substrate 10, and the interface layer 21 containing a Si compensation element and F is provided thereat. The Si compensation element in the interface layer 21 is contained at a concentration higher than the concentration of Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the Si compensation element in the interface layer 21, suppressing the function of the segregated Si as a carrier (donor), thereby suppressing a decrease in the breakdown voltage of the semiconductor device 1 and suppressing signal propagation to the interface.

[0039] The interface layer 21 contains F in addition to the Si compensation element. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. The F contained in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10, thereby reducing the amount of Si segregating at the interface between the surface 10a and the semiconductor layer 20. Therefore, the amount of Si compensation element contained in the interface layer 21, i.e., the amount of Si compensation element contained at a concentration higher than the concentration of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, is reduced. For example, when the concentration of the Si compensation element in the interface layer 21 is 5×10 18 cm -3 Therefore, it is not necessary to add an excessive amount of Si compensation element to the semiconductor layer 20 and the interface between the semiconductor layer 20 and the surface 10a of the substrate 10, and the amount of Si compensation element in the semiconductor layer 20 is reduced, thereby suppressing the deterioration of current collapse due to the Si compensation element and the resulting decrease in output of the semiconductor device 1. In the semiconductor device 1, Si at the interface is compensated for with a relatively low concentration of Si compensation element.

[0040] By providing an interface layer 21 containing a Si compensation element and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1 is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0041] Furthermore, in the semiconductor device 1, a region in which the concentration of the Si compensation element increases in the direction from the interface layer 21 toward the electron transit layer 23 may be provided in all or part of the region of the initial layer 22 in the semiconductor layer 20 near the interface layer 21. Providing such a region effectively prevents carriers or signals from the electron transit layer 23 from propagating to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0042] In the semiconductor device 1, the provision of the interface layer 21 containing a Si compensation element and F suppresses the effects of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. To suppress the effects of Si segregating at the interface, it is not necessary to provide a relatively thick, high-resistance buffer layer, such as one with a thickness of approximately 10 μm, on the substrate 10. In the semiconductor device 1, the provision of the interface layer 21 makes it possible to suppress the effects of Si segregating at the interface even if the thickness of the semiconductor layer 20 (the total thickness of all layers included in the semiconductor layer 20) is, for example, 5 μm or less. In this way, in the semiconductor device 1, it is not necessary to increase the thickness of the semiconductor layer 20, and therefore the time required to form the semiconductor layer 20 is not lengthened, thereby improving mass productivity.

[0043] Next, the results of evaluating the effects of the interface layer 21 described above will be described. FIG. 2 is a diagram illustrating the effect obtained by the interface layer according to the first embodiment. For comparison, Fig. 2(A) shows an example of the distribution of Si concentration and carrier density when F is not contained in the interface layer 21 of the semiconductor device 1 ("F-free"), and Fig. 2(B) shows an example of the distribution of Si concentration and carrier density when F is contained in the interface layer 21 of the semiconductor device 1 ("F-containing"). Here, a GaN substrate is used as the substrate 10, and Fe is used as the Si compensation element.

[0044] As shown in FIG. 2(A), when the interface layer 21 does not contain F, the peak concentration of 5×10 19 cm -3Relatively high concentrations of Si, such as this, are segregated. The Fe concentration of the Si compensation element contained in the substrate 10 used for evaluation is 2×10 18 cm -3 or so. Therefore, when F is not contained in the interface layer 21, at the interface between the substrate 10 and the semiconductor layer 20, since the relationship of Si concentration > Fe concentration exists, carrier accumulation due to excess Si occurs.

[0045] In contrast, as shown in Fig. 2(B), when F is contained in the interface layer 21, the Si at the interface between the substrate 10 and the semiconductor layer 20 is reduced to 8×10 17 cm -3 at the peak concentration. Therefore, when F is contained in the interface layer 21, at the interface between the substrate 10 and the semiconductor layer 20, since the relationship of Si concentration < Fe concentration exists, carrier accumulation due to Si can be suppressed.

[0046] Even when F is not contained in the interface layer 21, it is considered possible to compensate for the Si at the interface by adding a high concentration of a Si compensation element such as Fe to the interface between the substrate 10 and the semiconductor layer 20. However, as a result of intensive studies, when more than 5×10 18 cm -3 of the Si compensation element is added, the current collapse phenomenon becomes prominent, and the possibility of deterioration of the output characteristics increases. By containing F in the interface layer 21, it becomes possible to suppress the amount of Si adhering to the substrate 10, suppress the amount of Si segregating at the interface between the substrate 10 and the semiconductor layer 20, and suppress the amount of the Si compensation element added to compensate for that Si. Therefore, it becomes possible to suppress carrier accumulation due to Si segregating at the interface with a relatively low concentration of the Si compensation element added.

[0047] As an example, in the evaluation of the output characteristics in the 2.45 GHz band, the power load efficiency when F was not contained in the interface layer 21 was 70%, whereas it was confirmed that the power load efficiency when F was contained in the interface layer 21 improved up to 80%.

[0048] [Second Embodiment] Fig. 3 is a diagram illustrating an example of a semiconductor device according to the second embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device according to the second embodiment.

[0049] 3 is an example of a HEMT, and includes a substrate 10, a semiconductor layer 20, a gate electrode 30, a source electrode 40, a drain electrode 50, and a passivation layer 60.

[0050] The substrate 10 of the semiconductor device 1A is, for example, a GaN substrate. The substrate 10 contains, for example, Fe, which is a Si compensation element. The concentration of the Si compensation element in the substrate 10 is, for example, 1×10 18 cm -3 The above is set. Before the semiconductor layer 20 is provided, F is introduced into the surface 10a of the substrate 10 to terminate dangling bonds on the surface 10a. This reduces the amount of Si adhering to the surface 10a compared to when the surface 10a is not terminated with F.

[0051] The semiconductor layer 20 of the semiconductor device 1A includes an interface layer 21, an initial layer 22, an electron transit layer 23, an electron supply layer 24, and a cap layer 25. The semiconductor layer 20 is obtained by sequentially growing the interface layer 21, the initial layer 22, the electron transit layer 23, the electron supply layer 24, and the cap layer 25 on the surface 10a of the substrate 10 by, for example, MOCVD.

[0052] The interface layer 21 and the initial layer 22 of the semiconductor device 1A are made of nitride semiconductors such as AlN, GaN, and AlGaN. The electron transit layer 23 of the semiconductor device 1A is provided on a surface 22a of the initial layer 22 opposite to the interface layer 21 or the substrate 10. The electron transit layer 23 is made of, for example, i-type GaN. The electron supply layer 24 of the semiconductor device 1A is provided on a surface 23a of the electron transit layer 23 opposite to the initial layer 22. The electron supply layer 24 is made of nitride semiconductors such as AlGaN, InAlN, InAlGaN, AlN, and ScAlN. In the semiconductor device 1A, a 2DEG 1a is formed near the junction interface between the electron transit layer 23 and the electron supply layer 24. The cap layer 25 of the semiconductor device 1A is provided on a surface 24a of the electron supply layer 24 opposite to the electron transit layer 23. The cap layer 25 is made of a nitride semiconductor such as GaN, AlN, or AlGaN.

[0053] In the semiconductor device 1A, the interface layer 21, the initial layer 22, the electron transit layer 23, the electron supply layer 24, and the cap layer 25 of the semiconductor layer 20 may each have a single layer structure of one type of nitride semiconductor, or a stacked structure of two or more types of nitride semiconductors.

[0054] Furthermore, although not shown here, a spacer layer having a single layer structure or a multilayer structure made of a nitride semiconductor such as AlN or AlGaN may be provided between the electron transit layer 23 and the electron supply layer 24 of the semiconductor device 1A.

[0055] The thickness of the semiconductor layer 20 of the semiconductor device 1A (the total thickness of all layers included in the semiconductor layer 20) is set to, for example, 5 μm or less. In the semiconductor device 1A, the interface layer 21 is provided at the interface between the semiconductor layer 20 and the surface 10a of the substrate 10. An initial layer 22 is provided on the side of the interface layer 21 opposite the substrate 10 side. The interface layer 21 and the initial layer 22 of the semiconductor device 1A contain a Si compensation element, for example, Fe. The interface layer 21 is formed when the initial layer 22 is grown on the surface 10a of the substrate 10 using an MOCVD method. By adding Fe, the Si compensation element, when growing the initial layer 22 using an MOCVD method, the interface layer 21 containing Fe is formed in the initial stage of growth, and as the growth of the initial layer 22 progresses further following the formation of the interface layer 21, the initial layer 22 containing Fe is formed.

[0056] In the semiconductor device 1A, the concentration of Fe, a Si compensation element, contained in the interface layer 21 is set to be higher than the concentration of Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. The Fe contained in the interface layer 21 may include Fe that is present on the surface 10a of the substrate 10, Fe that diffuses from the substrate 10, Fe that is in the initial layer 22 grown with Fe added, or Fe that diffuses from the initial layer 22. The initial layer 22 may have a region in which the concentration of Fe increases in a direction from the interface layer 21 side toward the electron transit layer 23 side, in all or part of a region near the interface layer 21.

[0057] The interface layer 21 of the semiconductor device 1A contains Fe as a Si compensation element, as well as F introduced to terminate dangling bonds on the surface 10a of the substrate 10. F reduces the amount of Si adhering to the surface 10a of the substrate 10, and reduces the amount of Si segregating at the interface between the surface 10a and the semiconductor layer 20. Therefore, the concentration of Fe as a Si compensation element contained in the interface layer 21 is set to a relatively low concentration, for example, 5×10 18 cm -3 It can be reduced to the following.

[0058] As described above, in the semiconductor device 1A, the substrate 10, the interface layer 21, and the initial layer 22 contain Fe, which is a Si compensation element, and the interface layer 21 further contains F, which suppresses adhesion and segregation of Si. For convenience, in Fig. 3, the inclusion of Fe in the substrate 10 is represented by [Fe], the inclusion of Fe and F in the interface layer 21 is represented by [Fe,F], and the inclusion of Fe in the initial layer 22 is represented by [Fe].

[0059] In the semiconductor device 1A, a gate electrode 30, a source electrode 40, a drain electrode 50, and a passivation layer 60 are provided on the surface 20a (surface 25a of the cap layer 25 in the example of FIG. 3) side of the semiconductor layer 20 having the above-described configuration.

[0060] The gate electrode 30 is provided on the surface 20a side of the semiconductor layer 20. The gate electrode 30 is made of a metal such as Ni or Au. The gate electrode 30 is provided so as to function as a Schottky electrode. A gate insulating film (not shown) made of an oxide, nitride, oxynitride, or the like may be interposed between the gate electrode 30 and the surface 20a of the semiconductor layer 20.

[0061] The source electrode 40 and the drain electrode 50 are provided on the surface 20a side of the semiconductor layer 20 so as to sandwich the gate electrode 30. The source electrode 40 and the drain electrode 50 are made of a metal such as Ti or Al. The source electrode 40 and the drain electrode 50 are provided to function as ohmic electrodes. As long as the source electrode 40 and the drain electrode 50 function as ohmic electrodes, they may be connected to the cap layer 25, may be connected to the electron supply layer 24 through the cap layer 25, or may be connected to the electron transit layer 23 through the cap layer 25 and the electron supply layer 24. A regrowth layer using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided as a contact layer in the portion of the cap layer 25, the electron supply layer 24, or the electron transit layer 23 to which the source electrode 40 and the drain electrode 50 are connected.

[0062] 3, the semiconductor device 1A employs a so-called asymmetric structure in which the distance between the gate electrode 30 and the drain electrode 50 is wider than the distance between the gate electrode 30 and the source electrode 40. By employing the asymmetric structure, the electric field between the gate electrode 30 and the drain electrode 50 is alleviated and the breakdown voltage is improved.

[0063] The passivation layer 60 is provided on the surface 20a side of the semiconductor layer 20 so as to cover at least the surface 20a of the semiconductor layer 20 between the gate electrode 30 and the source electrode 40 and the drain electrode 50. The passivation layer 60 is made of an insulating layer such as SiN (silicon nitride).

[0064] When the semiconductor device 1A is in operation, a predetermined voltage is supplied between the source electrode 40 and the drain electrode 50, and a predetermined gate voltage is supplied to the gate electrode 30. A channel through which carrier electrons are transported is formed in the electron transit layer 23 between the source electrode 40 and the drain electrode 50, thereby realizing the transistor function of the semiconductor device 1A.

[0065] In the semiconductor device 1A, an interface layer 21 containing Fe and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The Fe content of the interface layer 21 is higher than the Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the Fe of the interface layer 21, and a decrease in the breakdown voltage of the semiconductor device 1A and signal propagation to the interface can be suppressed.

[0066] The interface layer 21 of the semiconductor device 1A contains F in addition to Fe. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. This reduces the amount of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, and allows the amount of Fe contained at a higher concentration than the Si segregating at the interface to be suppressed. This eliminates the need to add excessive amounts of Fe to the semiconductor layer 20 and its interface with the surface 10a of the substrate 10. A relatively low concentration of Fe can suppress deterioration of current collapse and the resulting decrease in output power of the semiconductor device 1A. In the semiconductor device 1A, the relatively low concentration of Fe can compensate for the Si at the interface. Furthermore, the semiconductor layer 20 does not need to include a thick, high-resistance buffer layer.

[0067] By providing an interface layer 21 containing Fe and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1A is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0068] Next, a method for forming the semiconductor device 1A having the above-described configuration will be described. 4 to 7 are diagrams illustrating an example of a method for forming a semiconductor device according to the second embodiment. Figures 4(A), 4(B), 5(A), 5(B), 6(A), 6(B), 7(A), and 7(B) each show a schematic cross-sectional view of a main part of each step in forming a semiconductor device according to the second embodiment. Each step will be described below in order.

[0069] FIG. 4(A) is a schematic cross-sectional view of a main part of an example of a preparation step for the substrate 10. In FIG. First, as shown in FIG. 4A, a substrate 10 is prepared. In this example, a GaN substrate (a GaN freestanding substrate) is prepared as the substrate 10. Fe, which is a Si compensation element, is added to the substrate 10. For example, the addition of Fe to the substrate 10 increases the Si content by 1×10 18 cm -3 The iron content is above 100%.

[0070] FIG. 4(B) is a schematic cross-sectional view of a main part of an example of an F introduction process for the substrate 10. After the substrate 10 is prepared, as shown in FIG. 4(B), a process for introducing F into the surface 10a of the prepared substrate 10 is performed. In this process, the surface 10a of the substrate 10 is exposed to an F-containing environment 70. The process for exposing the surface 10a of the substrate 10 to the F-containing environment 70 may be, for example, a wet chemical process in which the surface 10a is immersed in an F-containing solution such as HF (hydrogen fluoride). The wet chemical process may be performed by dropping or spraying the F-containing solution onto the surface 10a of the substrate 10. Alternatively, the process for exposing the surface 10a of the substrate 10 to the F-containing environment 70 may be, for example, a dry chemical process in which an F-containing gas such as SF6 (sulfur hexafluoride) or CF4 (carbon tetrafluoride) is converted into plasma and irradiated onto the surface 10a of the substrate 10.

[0071] By the treatment of exposing the substrate 10 to such an environment 70 containing F, F is introduced into the surface 10a of the substrate 10 so that dangling bonds on the surface 10a are terminated with F. By terminating the dangling bonds on the surface 10a of the substrate 10 with F, the amount of Si that adheres to the surface 10a, i.e., the amount of Si that contaminates the surface 10a, is reduced compared to when the surface 10a is not terminated with F.

[0072] FIG. 5(A) is a schematic cross-sectional view of a main part of an example of a process for forming the interface layer 21 and the initial layer 22. In FIG. After F is introduced into the surface 10a of the substrate 10, as shown in FIG. 5(A), a predetermined nitride semiconductor is grown on the surface 10a of the substrate 10 into which F has been introduced using an MOCVD method, thereby forming an interface layer 21 and an initial layer 22. The interface layer 21 and the initial layer 22 contain Fe, which is a Si compensation element. The initial layer 22 is grown on the surface 10a of the substrate 10 into which F has been introduced using an MOCVD method, and Fe, which is a Si compensation element, is added during this growth. In the early stage of growth of this initial layer 22, the interface layer 21 containing Fe is formed on the surface 10a of the substrate 10. Following the formation of the interface layer 21, the growth of the initial layer 22 further progresses, thereby forming the initial layer 22 containing Fe on the interface layer 21.

[0073] The amount of Fe added during the growth of the interface layer 21 is set so that the concentration of Fe contained in the interface layer 21 is higher than that of Si that adheres to the surface 10a of the substrate 10 and segregates at the interface with the surface 10a. The Fe contained in the interface layer 21 may include Fe present on the surface 10a of the substrate 10, Fe diffused from the substrate 10, Fe in the initial layer 22 grown with Fe added, or Fe diffused from the initial layer 22. The formed interface layer 21 contains F introduced into the surface 10a of the substrate 10 in addition to Fe. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. Therefore, the amount of Si segregating at the interface with the surface 10a of the substrate 10 is reduced, and the amount of Fe added during the growth of the interface layer 21 is reduced so that the Fe contained therein is higher in concentration than that of Si segregating at the interface.

[0074] The amount of Fe added during growth of the initial layer 22 can be adjusted to allow the initial layer 22 to contain Fe with a distribution. For example, the Fe in the initial layer 22 may be distributed so that it is contained in a region near the interface layer 21 and not in a region near the surface 22a of the initial layer 22. Furthermore, the initial layer 22 may have a region in which the concentration of Fe increases in a direction from the interface layer 21 side toward the surface 22a of the initial layer 22, in all or part of the region near the interface layer 21.

[0075] In this way, Fe is added to the surface 10a of the substrate 10 to which Fe has been added and F has been introduced into the surface 10a, and a nitride semiconductor is grown on the surface 10a, forming a layered structure of an interface layer 21 containing Fe and F and an initial layer 22 containing Fe.

[0076] FIG. 5B is a schematic cross-sectional view of a main part of an example of a process for forming the electron transit layer 23, the electron supply layer 24, and the cap layer 25. After the interface layer 21 and the initial layer 22 are formed, as shown in FIG. 5B , a predetermined nitride semiconductor is grown on the surface 22a of the formed initial layer 22 using MOCVD to form the electron transit layer 23. A predetermined nitride semiconductor is grown on the surface 23a of the formed electron transit layer 23 using MOCVD to form the electron supply layer 24. A 2DEG 1a is generated in the electron transit layer 23 near the junction interface with the electron supply layer 24. A predetermined nitride semiconductor is grown on the surface 24a of the formed electron supply layer 24 using MOCVD to form the cap layer 25. This forms the semiconductor layer 20 having a layered structure in which the interface layer 21, the initial layer 22, the electron transit layer 23, the electron supply layer 24, and the cap layer 25 are stacked in this order. The semiconductor layer 20 may further include other layers, such as a spacer layer, provided between the electron transit layer 23 and the electron supply layer 24.

[0077] After the semiconductor layer 20 is formed, an isolation region (not shown) is formed. For example, first, a resist pattern (not shown) having openings in regions where the isolation regions will be formed is formed by photolithography. Then, using the formed resist pattern as a mask, Ar (argon) ions are implanted into the nitride semiconductor in the openings, thereby forming the isolation regions. The isolation regions may be formed by removing the nitride semiconductor in the openings of the resist pattern by dry etching such as reactive ion etching (RIE) using a Cl (chlorine)-based gas. After the isolation regions are formed, the resist pattern used as a mask is removed using an organic solvent or the like.

[0078] FIG. 6A is a schematic cross-sectional view of a main part of an example of a process for forming the source electrode 40 and the drain electrode 50. In FIG. After the semiconductor layer 20 and the element isolation region (not shown) are formed, the source electrode 40 and the drain electrode 50 are formed as shown in FIG. 6A. For example, first, a resist pattern (not shown) having openings in the regions where the source electrode 40 and the drain electrode 50 are to be formed is formed by photolithography. Next, a metal is deposited on the resist pattern and in the openings by vacuum deposition. For example, Ti is deposited to a thickness of 2 nm to 50 nm, and Al is deposited thereon to a thickness of 100 nm to 300 nm. After the metal deposition, the resist pattern is removed together with the deposited metal by lift-off. This forms the source electrode 40 and the drain electrode 50. Then, a heat treatment (alloying treatment) is performed in a nitrogen atmosphere at 500°C to 900°C to establish ohmic contact between the source electrode 40 and the drain electrode 50.

[0079] FIG. 6B is a schematic cross-sectional view of a main part of an example of a process for forming the passivation layer 60. In FIG. 6(B), after the source electrode 40 and the drain electrode 50 are formed, a passivation layer 60 is formed so as to cover the surface 20a of the semiconductor layer 20 on which the source electrode 40 and the drain electrode 50 are formed. The passivation layer 60 may be formed so as to cover the source electrode 40 and the drain electrode 50 together with the surface 20a of the semiconductor layer 20. For example, the passivation layer 60 is formed of SiN having a thickness of 5 nm to 100 nm using a plasma CVD (Chemical Vapor Deposition) method.

[0080] FIG. 7A is a schematic cross-sectional view of a main part of an example of a step of forming an opening in the passivation layer 60. In FIG. 7(A), the passivation layer 60 is removed from the region where the gate electrode 30 is to be formed, forming an opening 60a. For example, a resist pattern (not shown) having an opening in the region where the gate electrode 30 is to be formed is formed using photolithography, and the passivation layer 60 exposed from the opening of the resist pattern is removed by dry etching such as RIE. As a result, the passivation layer 60 having the opening 60a is formed in the region where the gate electrode 30 is to be formed.

[0081] FIG. 7B is a schematic cross-sectional view of a main part of an example of a process for forming the gate electrode 30. In FIG. After the passivation layer 60 having the opening 60a is formed, the gate electrode 30 is formed as shown in FIG. 7(B). For example, first, a resist pattern (not shown) having an opening in a region where the gate electrode 30 is to be formed and which encompasses the opening 60a of the passivation layer 60 is formed by photolithography. Next, a metal is evaporated onto the resist pattern and into the opening by vacuum evaporation. For example, Ni is evaporated to a thickness of 5 nm to 30 nm, and Au is evaporated thereon to a thickness of 100 nm to 300 nm. After the metal evaporation, the resist pattern is removed together with the evaporated metal by lift-off. This results in the gate electrode 30 being formed in the opening 60a of the passivation layer 60 and on the passivation layer 60 outside it. After the gate electrode 30 is formed, a heat treatment may be performed.

[0082] Through the steps described above, the semiconductor device 1A shown in FIG. 7(B) and FIG. 3 is formed. In the semiconductor device 1A, an interface layer 21 containing Fe and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The Fe content in the interface layer 21 is higher than the Si segregated at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. Therefore, the Fe in the interface layer 21 sufficiently compensates for the Si segregated at the interface, suppressing a decrease in the breakdown voltage of the semiconductor device 1A and suppressing signal propagation to the interface. The interface layer 21 of the semiconductor device 1A contains F in addition to Fe. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10 and reduces the amount of Si segregated at the interface. Therefore, the amount of Fe contained is kept higher than the Si segregated at the interface, and a relatively low concentration of Fe can suppress deterioration of current collapse and the resulting decrease in output power of the semiconductor device 1A. In the semiconductor device 1A, the Si at the interface can be compensated for by a relatively low concentration of Fe. The interface layer 21 enables the semiconductor device 1A to effectively suppress characteristic degradation caused by Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0083] Here, the Fe concentration in the interface layer 21 is 5×10 18 cm -3 It is preferable to set it as follows: FIG. 8 is a diagram illustrating an example of the relationship between the Fe concentration and characteristics of the interface layer according to the second embodiment.

[0084] For example, the concentration of Si segregated at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is set to N Si As shown in FIG. 8, the Fe concentration in the interface layer 21 is set to be equal to the Si concentration N Si If the Fe concentration in the interface layer 21 is greater than or equal to the Si concentration N Si It is believed that a certain level or more of breakdown voltage characteristics can be obtained even if the concentration of Fe in the interface layer 21 is 1 / 10 or more of the concentration of Si at the interface. Si In order to obtain a certain level or more of breakdown voltage characteristics, the Fe concentration in the interface layer 21 is set to be equal to or higher than the Si concentration N SiIt is considered that the value should be 1 / 10 or more of the above.

[0085] However, the Fe concentration in the interface layer 21 is 5×10 18 cm -3 If the Fe concentration in the interface layer 21 exceeds 5×10, the current collapse phenomenon becomes significant, the current collapse characteristics deteriorate, and the possibility of causing deterioration in the output characteristics increases. 18 cm -3 In order to realize RF characteristics and breakdown voltage characteristics at a certain level or higher and further suppress the deterioration of current collapse characteristics, the Fe concentration of the interface layer 21 is preferably set to be less than the Si concentration N Si Above and 5 x 10 18 cm -3 It is more preferable to set the following:

[0086] Furthermore, the initial layer 22 of the semiconductor layer 20 can have a distribution in the Fe concentration. FIG. 9 is a diagram illustrating an example of the relationship between the depth of the semiconductor layer and the Fe concentration according to the second embodiment.

[0087] 9 , the semiconductor layer 20 may have a region AR in the vicinity of an interface layer 21 (interface) between the surface 10a of the substrate 10 and the semiconductor layer 20, where the concentration of Fe increases in a direction from the interface side toward the surface 20a (front surface) of the semiconductor layer 20. Such a region AR can be provided in the initial layer 22, for example, by adjusting the amount of Fe added during growth of the initial layer 22 using an MOCVD method. Providing such a region AR effectively suppresses propagation of carriers or signals from the electron transit layer 23 side to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0088] The region AR can be provided, for example, in the entire region near the interface layer 21 in the initial layer 22 of the semiconductor layer 20. In addition, the region AR can be selectively provided in a part of the region near the interface layer 21 in the initial layer 22 of the semiconductor layer 20. For example, the region AR can be provided in the region near the interface layer 21 in the initial layer 22 of the semiconductor layer 20, in a region directly below the gate electrode 30, directly below the gap between the gate electrode 30 and the source electrode 40, directly below the gap between the gate electrode 30 and the drain electrode 50, etc.

[0089] The semiconductor device 1A according to the second embodiment has been described above. In the above description of the semiconductor device 1A according to the second embodiment, an example was shown in which the substrate 10, the interface layer 21, and the initial layer 22 contain Fe as a Si compensation element. Alternatively, the substrate 10, the interface layer 21, and the initial layer 22 of the semiconductor device 1A may further contain other elements, such as C or Mn, in addition to Fe as a Si compensation element. However, in the semiconductor device 1A, the Si compensation element contained in the substrate 10 has the highest integrated concentration of Fe, the Si compensation element contained in the interface layer 21 has the highest integrated concentration of Fe, and the Si compensation element contained in the initial layer 22 has the highest integrated concentration of Fe. Even with this configuration, the Si compensation element mainly composed of Fe contained in the substrate 10, the interface layer 21, and the initial layer 22 can compensate for Si segregated at the interface between the substrate 10 and the semiconductor layer 20. Furthermore, the F contained in the interface layer 21 reduces the amount of Si segregated at the interface, thereby reducing the amount of the Fe-based Si compensation element added. This allows the Si segregated at the interface to be compensated for by a relatively low concentration of Si compensating element. Even with this configuration, the concentration of the Si compensating element in the interface layer 21 can be set to be less than the concentration N of Si at the interface, as in the example of FIG. Si Above and 5 x 10 18 cm -3 9, a region in the vicinity of the interface layer 21 between the surface 10a of the substrate 10 and the semiconductor layer 20 can be provided in which the concentration of the Si compensation element increases in the direction from the interface side toward the surface 20a of the semiconductor layer 20.

[0090] [Third embodiment] Fig. 10 is a diagram illustrating an example of a semiconductor device according to the third embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of the semiconductor device according to the third embodiment.

[0091] 10 is an example of a HEMT. The semiconductor device 1B has a configuration in which C is contained as a Si compensation element in the substrate 10, the interface layer 21, and the initial layer 22. In this respect, the semiconductor device 1B differs from the semiconductor device 1A described in the second embodiment, which has a configuration in which Fe is contained as a Si compensation element in the substrate 10, the interface layer 21, and the initial layer 22.

[0092] In the semiconductor device 1B, C is added to the surface 10a of the substrate 10, which contains C as a Si compensation element and has F introduced into the surface 10a, by MOCVD to form an interface layer 21 and an initial layer 22. The C contained in the interface layer 21 may include C present on the surface 10a of the substrate 10, C diffused from the substrate 10, C in the initial layer 22 grown by adding C, or C diffused from the initial layer 22.

[0093] In the semiconductor device 1B, the substrate 10, the interface layer 21, and the initial layer 22 contain C as a Si compensation element, and the interface layer 21 further contains F to suppress adhesion and segregation of Si. For convenience, in Fig. 10, the inclusion of C in the substrate 10 is represented by [C], the inclusion of C and F in the interface layer 21 is represented by [C, F], and the inclusion of C in the initial layer 22 is represented by [C].

[0094] Other configurations and manufacturing methods of the semiconductor device 1B can be the same as those described above for the semiconductor device 1A. In the semiconductor device 1B, an interface layer 21 containing C and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The C content of the interface layer 21 is higher than the Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the C in the interface layer 21, and it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 1B and the propagation of signals to the interface. However, from the viewpoint of suppressing current collapse, the concentration of C in the interface layer 21 should be 5×10 18 cm -3 It is preferable to set it as follows:

[0095] The interface layer 21 of the semiconductor device 1B contains F in addition to C. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. This reduces the amount of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, and reduces the amount of C contained at a higher concentration than the Si segregating at the interface. This eliminates the need to add excessive amounts of C to the semiconductor layer 20 and its interface with the surface 10a of the substrate 10, and a relatively low concentration of C can suppress deterioration of current collapse and the resulting decrease in output of the semiconductor device 1B. In the semiconductor device 1B, the Si at the interface can be compensated for with a relatively low concentration of C.

[0096] By providing an interface layer 21 containing C and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1B is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0097] 9, the semiconductor device 1B may have a region in which the concentration of C increases in the direction from the interface layer 21 toward the electron transit layer 23 in the entire or part of the region of the initial layer 22 in the semiconductor layer 20 near the interface layer 21. Providing such a region effectively prevents carriers or signals from the electron transit layer 23 from propagating to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0098] In the semiconductor device 1B, the provision of the interface layer 21 containing C and F suppresses the effects of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. There is no need to provide a thick, high-resistance buffer layer to suppress the effects of Si segregating at the interface. In the semiconductor device 1B, the provision of the interface layer 21 suppresses the effects of Si segregating at the interface even if the total thickness of the semiconductor layer 20 is, for example, 5 μm or less, and therefore the time required to form the semiconductor layer 20 is prevented from increasing, thereby improving mass productivity.

[0099] Here, an example has been shown in which the substrate 10, interface layer 21, and initial layer 22 of the semiconductor device 1B contain C as the Si compensation element. However, the substrate 10, interface layer 21, and initial layer 22 may further contain other elements, such as Fe or Mn, as the Si compensation element in addition to C. However, in the semiconductor device 1B, the Si compensation element contained in the substrate 10 has the highest integrated concentration of C, the Si compensation element contained in the interface layer 21 has the highest integrated concentration of C, and the Si compensation element contained in the initial layer 22 has the highest integrated concentration of C. Even with this configuration, the Si compensation element mainly composed of C contained in the substrate 10, interface layer 21, and initial layer 22 can compensate for Si segregated at the interface between the substrate 10 and the semiconductor layer 20. Furthermore, the F contained in the interface layer 21 reduces the amount of Si segregated at the interface, thereby reducing the amount of the Si compensation element mainly composed of C. This allows for compensation for Si segregated at the interface with a relatively low concentration of the Si compensation element. Even with such a configuration, the concentration of the Si compensation element in the interface layer 21 can be adjusted to the concentration N Si Above and 5 x 10 18 cm -3 9, a region in the vicinity of the interface layer 21 between the surface 10a of the substrate 10 and the semiconductor layer 20 can be provided in which the concentration of the Si compensation element increases in the direction from the interface side toward the surface 20a of the semiconductor layer 20.

[0100] [Fourth embodiment] Fig. 11 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of a semiconductor device according to the fourth embodiment.

[0101] 11 is an example of a HEMT. The semiconductor device 1C has a configuration in which the substrate 10 contains C as a Si compensation element, the initial layer 22 contains Fe as a Si compensation element, and the interface layer 21 contains C and Fe as Si compensation elements. In having such a configuration, the semiconductor device 1C differs from the semiconductor device 1A described in the second embodiment above, which has a configuration in which the substrate 10, the interface layer 21, and the initial layer 22 contain Fe as a Si compensation element.

[0102] In the semiconductor device 1C, an interface layer 21 and an initial layer 22 are formed by adding Fe to the surface 10a of a substrate 10 that contains C as a Si compensation element and has F introduced into the surface 10a, using an MOCVD method. C may be added during the formation of the interface layer 21, i.e., in the initial stage of growth of the initial layer 22. The C contained in the interface layer 21 may include C present on the surface 10a of the substrate 10, C diffused from the substrate 10, C in the initial layer 22 grown with the addition of C, or C diffused from the initial layer 22.

[0103] In the semiconductor device 1C, the substrate 10 contains C as a Si compensation element, the initial layer 22 contains Fe as a Si compensation element, the interface layer 21 contains C and Fe as Si compensation elements, and the interface layer 21 further contains F to suppress adhesion and segregation of Si. For convenience, in Fig. 11, the inclusion of C in the substrate 10 is represented by [C], the inclusion of C, Fe, and F in the interface layer 21 is represented by [C,Fe,F], and the inclusion of Fe in the initial layer 22 is represented by [Fe].

[0104] Other configurations and manufacturing methods of the semiconductor device 1C can be the same as those described for the semiconductor device 1A. In the semiconductor device 1C, an interface layer 21 containing C, Fe, and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The C and Fe in the interface layer 21 are contained at a higher concentration than the Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the C and Fe in the interface layer 21, and a decrease in the breakdown voltage of the semiconductor device 1C and signal propagation to the interface can be suppressed. However, from the viewpoint of suppressing current collapse, the total concentration of C and Fe in the interface layer 21 should be less than 5×10 18 cm -3 It is preferable to set it as follows:

[0105] The interface layer 21 of the semiconductor device 1C contains F in addition to C and Fe. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. This reduces the amount of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, and allows the amounts of C and Fe contained to be higher than the Si segregating at the interface to be suppressed. This eliminates the need to add excessive amounts of C and Fe to the semiconductor layer 20 and its interface with the surface 10a of the substrate 10. A deterioration in current collapse and a resulting decrease in output power of the semiconductor device 1C can be suppressed with relatively low concentrations of C and Fe in the semiconductor device 1C. In the semiconductor device 1C, the Si at the interface can be compensated for with relatively low concentrations of C and Fe.

[0106] By providing an interface layer 21 containing C, Fe, and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1C is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0107] 9, the semiconductor device 1C may have a region in which the concentration of the Si compensation element (e.g., Fe) increases in the direction from the interface layer 21 toward the electron transit layer 23 in the entire or part of the region of the initial layer 22 in the semiconductor layer 20 near the interface layer 21. Providing such a region effectively prevents carriers or signals from the electron transit layer 23 from propagating to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0108] In the semiconductor device 1C, the provision of the interface layer 21 containing C, Fe, and F suppresses the effects of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. There is no need to provide a thick, high-resistance buffer layer to suppress the effects of Si segregating at the interface. In the semiconductor device 1C, the provision of the interface layer 21 suppresses the effects of Si segregating at the interface even if the total thickness of the semiconductor layer 20 is, for example, 5 μm or less, and the time required to form the semiconductor layer 20 is prevented from increasing, thereby improving mass productivity.

[0109] Here, an example is shown in which the substrate 10 of the semiconductor device 1C contains C as the Si compensation element, the initial layer 22 contains Fe as the Si compensation element, and the interface layer 21 contains C and Fe as the Si compensation elements. Alternatively, the substrate 10 may further contain other elements such as Fe and Mn in addition to C as the Si compensation element. The initial layer 22 may further contain other elements such as C and Mn in addition to Fe as the Si compensation element. The interface layer 21 may further contain other elements such as Mn in addition to C and Fe as the Si compensation element. However, in the semiconductor device 1C, the substrate 10 contains the Si compensation element with the highest integrated concentration of C, the initial layer 22 contains the Si compensation element with the highest integrated concentration of Fe, and the interface layer 21 contains the Si compensation elements with the highest integrated concentrations of C and Fe. Even with this configuration, the Si segregated at the interface between the substrate 10 and the semiconductor layer 20 can be compensated for by the Si compensation element mainly composed of C contained in the substrate 10, the Si compensation element mainly composed of Fe contained in the initial layer 22, and the Si compensation element mainly composed of C and Fe contained in the interface layer 21. Furthermore, the amount of Si segregated at the interface can be reduced by the F contained in the interface layer 21, and the amount of Si compensation element added can be suppressed. This makes it possible to compensate for the Si segregated at the interface with a relatively low concentration of Si compensation element. Furthermore, even with this configuration, it is possible to compensate for the Si segregated at the interface with the concentration of the Si compensation element in the interface layer 21, as in the example of FIG. 8, by adjusting the concentration of the Si compensation element in the interface layer 21 to the concentration N of Si at the interface. Si Above and 5 x 10 18 cm -39, a region in the vicinity of the interface layer 21 between the surface 10a of the substrate 10 and the semiconductor layer 20 can be provided in which the concentration of the Si compensation element increases in the direction from the interface side toward the surface 20a of the semiconductor layer 20.

[0110] [Fifth embodiment] Fig. 12 is a diagram illustrating an example of a semiconductor device according to the fifth embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of a semiconductor device according to the fifth embodiment.

[0111] 12 is an example of a HEMT. The semiconductor device 1D has a configuration in which the substrate 10 contains Fe as a Si compensation element, the initial layer 22 contains C as a Si compensation element, and the interface layer 21 contains Fe and C as Si compensation elements. In having such a configuration, the semiconductor device 1D differs from the semiconductor device 1A described in the second embodiment above, which has a configuration in which the substrate 10, the interface layer 21, and the initial layer 22 contain Fe as a Si compensation element.

[0112] In the semiconductor device 1D, an interface layer 21 and an initial layer 22 are formed by adding C to the surface 10a of a substrate 10 that contains Fe as a Si compensation element and has F introduced into the surface 10a, using an MOCVD method. Fe may be added during the formation of the interface layer 21, that is, in the initial stage of growth of the initial layer 22. The Fe contained in the interface layer 21 may include Fe present on the surface 10a of the substrate 10, Fe diffused from the substrate 10, Fe in the initial layer 22 grown with the addition of Fe, or Fe diffused from the initial layer 22.

[0113] In the semiconductor device 1D, the substrate 10 contains Fe as a Si compensation element, the initial layer 22 contains C as a Si compensation element, the interface layer 21 contains Fe and C as Si compensation elements, and the interface layer 21 further contains F to suppress adhesion and segregation of Si. For convenience, in Fig. 12, the inclusion of Fe in the substrate 10 is represented by [Fe], the inclusion of Fe, C, and F in the interface layer 21 is represented by [Fe, C, F], and the inclusion of C in the initial layer 22 is represented by [C].

[0114] Other configurations and manufacturing methods of the semiconductor device 1D can be the same as those described for the semiconductor device 1A. In the semiconductor device 1D, an interface layer 21 containing Fe, C, and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The Fe and C in the interface layer 21 are contained at a higher concentration than the Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the Fe and C in the interface layer 21, and a decrease in the breakdown voltage of the semiconductor device 1D and signal propagation to the interface can be suppressed. However, from the viewpoint of suppressing current collapse, the total concentration of Fe and C in the interface layer 21 should be less than 5×10 18 cm -3 It is preferable to set it as follows:

[0115] The interface layer 21 of the semiconductor device 1D contains F in addition to Fe and C. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. This reduces the amount of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, and allows the amounts of Fe and C to be contained at higher concentrations than the Si segregating at the interface to be suppressed. This eliminates the need to add excessive amounts of Fe and C to the semiconductor layer 20 and its interface with the surface 10a of the substrate 10, and allows relatively low concentrations of Fe and C to suppress deterioration of current collapse and the resulting decrease in output of the semiconductor device 1D. In the semiconductor device 1D, the relatively low concentrations of Fe and C can compensate for Si at the interface.

[0116] By providing an interface layer 21 containing Fe, C, and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1D is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0117] 9, the semiconductor device 1D may have a region in which the concentration of a Si compensation element (e.g., C) increases in the direction from the interface layer 21 toward the electron transit layer 23 in the entire or part of the region of the initial layer 22 in the semiconductor layer 20 near the interface layer 21. Providing such a region effectively prevents carriers or signals from the electron transit layer 23 from propagating to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0118] In the semiconductor device 1D, the provision of the interface layer 21 containing Fe, C, and F suppresses the effects of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. There is no need to provide a thick, high-resistance buffer layer to suppress the effects of Si segregating at the interface. In the semiconductor device 1D, the provision of the interface layer 21 suppresses the effects of Si segregating at the interface even if the total thickness of the semiconductor layer 20 is, for example, 5 μm or less, and the time required to form the semiconductor layer 20 is prevented from increasing, thereby improving mass productivity.

[0119] Here, an example is shown in which the substrate 10 of the semiconductor device 1D contains Fe as a Si compensation element, the initial layer 22 contains C as a Si compensation element, and the interface layer 21 contains Fe and C as Si compensation elements. Alternatively, the substrate 10 may further contain other elements such as C or Mn in addition to Fe as a Si compensation element. The initial layer 22 may further contain other elements such as Fe or Mn in addition to C as a Si compensation element. The interface layer 21 may further contain other elements such as Mn in addition to Fe and C as a Si compensation element. However, in the semiconductor device 1D, the substrate 10 contains the Si compensation element with the highest integrated concentration of Fe, the initial layer 22 contains the Si compensation element with the highest integrated concentration of C, and the interface layer 21 contains the Si compensation element with the highest integrated concentrations of Fe and C. Even with this configuration, the Si segregated at the interface between the substrate 10 and the semiconductor layer 20 can be compensated for by the Si compensation element mainly composed of Fe contained in the substrate 10, the Si compensation element mainly composed of C contained in the initial layer 22, and the Si compensation element mainly composed of Fe and C contained in the interface layer 21. Furthermore, the amount of Si segregated at the interface can be reduced by the F contained in the interface layer 21, and the amount of Si compensation element added can be suppressed. This makes it possible to compensate for the Si segregated at the interface with a relatively low concentration of Si compensation element. Furthermore, even with this configuration, it is possible to compensate for the Si segregated at the interface with the concentration of the Si compensation element in the interface layer 21, as in the example of FIG. 8, by adjusting the concentration of the Si compensation element in the interface layer 21 to the concentration N of Si at the interface. Si Above and 5 x 10 18 cm -3 9, a region in the vicinity of the interface layer 21 between the surface 10a of the substrate 10 and the semiconductor layer 20 can be provided in which the concentration of the Si compensation element increases in the direction from the interface side toward the surface 20a of the semiconductor layer 20.

[0120] [Sixth embodiment] Fig. 13 is a diagram illustrating an example of a semiconductor device according to the sixth embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of a semiconductor device according to the sixth embodiment.

[0121] 13 is an example of a HEMT. The semiconductor device 1E has a configuration in which the substrate 10 contains Mn as a Si compensation element, the initial layer 22 contains Fe as a Si compensation element, and the interface layer 21 contains Mn and Fe as Si compensation elements. In having such a configuration, the semiconductor device 1E differs from the semiconductor device 1A described in the second embodiment above, which has a configuration in which the substrate 10, the interface layer 21, and the initial layer 22 contain Fe as a Si compensation element.

[0122] In the semiconductor device 1E, an interface layer 21 and an initial layer 22 are formed by adding Fe to the surface 10a of a substrate 10 that contains Mn as a Si compensation element and has F introduced into the surface 10a, using an MOCVD method. Mn may be added when the interface layer 21 is formed, that is, in the initial stage of growth of the initial layer 22. The Mn contained in the interface layer 21 may include Mn present on the surface 10a of the substrate 10, Mn diffused from the substrate 10, Mn in the initial layer 22 grown with the addition of Mn, or Mn diffused from the initial layer 22.

[0123] In the semiconductor device 1E, the substrate 10 contains Mn as a Si compensation element, the initial layer 22 contains Fe as a Si compensation element, the interface layer 21 contains Mn and Fe as Si compensation elements, and the interface layer 21 further contains F to suppress adhesion and segregation of Si. For convenience, in Fig. 13, the inclusion of Mn in the substrate 10 is represented by [Mn], the inclusion of Mn, Fe, and F in the interface layer 21 is represented by [Mn,Fe,F], and the inclusion of Fe in the initial layer 22 is represented by [Fe].

[0124] Other configurations and manufacturing methods of the semiconductor device 1E can be the same as those described above for the semiconductor device 1A. In the semiconductor device 1E, an interface layer 21 containing Mn, Fe, and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The Mn and Fe in the interface layer 21 are contained at a higher concentration than the Si that adheres to the surface 10a of the substrate 10 and segregates at the interface between the surface 10a and the semiconductor layer 20. Therefore, the Si that segregates at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 is sufficiently compensated for by the Mn and Fe in the interface layer 21, and a decrease in the breakdown voltage of the semiconductor device 1E and signal propagation to the interface can be suppressed. However, from the viewpoint of suppressing current collapse, the total concentration of Mn and Fe in the interface layer 21 should be less than 5×10 18 cm -3 It is preferable to set it as follows:

[0125] The interface layer 21 of the semiconductor device 1E contains F in addition to Mn and Fe. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10. This reduces the amount of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, and allows the amounts of Mn and Fe contained to be higher than the Si segregating at the interface to be suppressed. This eliminates the need to add excessive amounts of Mn and Fe to the semiconductor layer 20 and its interface with the surface 10a of the substrate 10. A relatively low concentration of Mn and Fe can suppress deterioration of current collapse and the resulting decrease in output power of the semiconductor device 1E. In the semiconductor device 1E, the relatively low concentrations of Mn and Fe can compensate for Si at the interface.

[0126] By providing an interface layer 21 containing Mn, Fe, and F at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, a semiconductor device 1E is realized in which characteristic degradation caused by Si at the interface is effectively suppressed.

[0127] 9, the semiconductor device 1E may have a region in which the concentration of the Si compensation element (e.g., Fe) increases in the direction from the interface layer 21 toward the electron transit layer 23 in the entire or part of the region of the initial layer 22 in the semiconductor layer 20 near the interface layer 21. Providing such a region effectively prevents carriers or signals from the electron transit layer 23 from propagating to the interface between the surface 10a of the substrate 10 and the semiconductor layer 20.

[0128] In the semiconductor device 1E, the provision of the interface layer 21 containing Mn, Fe, and F suppresses the effects of Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. There is no need to provide a thick, high-resistance buffer layer to suppress the effects of Si segregating at the interface. In the semiconductor device 1E, the provision of the interface layer 21 suppresses the effects of Si segregating at the interface even if the total thickness of the semiconductor layer 20 is, for example, 5 μm or less, and the time required to form the semiconductor layer 20 is prevented from increasing, thereby improving mass productivity.

[0129] In the example shown here, the substrate 10 of the semiconductor device 1E contains Mn as a Si compensation element, the initial layer 22 contains Fe as a Si compensation element, and the interface layer 21 contains Mn and Fe as Si compensation elements. Alternatively, the substrate 10 may further contain other elements such as Fe and C in addition to Mn as a Si compensation element. The initial layer 22 may further contain other elements such as C and Mn in addition to Fe as a Si compensation element. The interface layer 21 may further contain other elements such as C in addition to Mn and Fe as a Si compensation element. However, in the semiconductor device 1E, the substrate 10 contains the highest integrated concentration of Mn as a Si compensation element, the initial layer 22 contains the highest integrated concentration of Fe as a Si compensation element, and the interface layer 21 contains the highest integrated concentrations of Mn and Fe as a Si compensation element. Even with this configuration, the Si segregated at the interface between the substrate 10 and the semiconductor layer 20 can be compensated for by the Si compensation element mainly composed of Mn contained in the substrate 10, the Si compensation element mainly composed of Fe contained in the initial layer 22, and the Si compensation element mainly composed of Mn and Fe contained in the interface layer 21. Furthermore, the amount of Si segregated at the interface can be reduced by the F contained in the interface layer 21, and the amount of Si compensation element added can be suppressed. This makes it possible to compensate for the Si segregated at the interface with a relatively low concentration of Si compensation element. Furthermore, even with this configuration, it is possible to compensate for the Si segregated at the interface with the concentration of the Si compensation element in the interface layer 21, as in the example of FIG. 8, by adjusting the concentration of the Si compensation element in the interface layer 21 to the concentration N of Si at the interface. Si Above and 5 x 10 18 cm -3 9, a region in the vicinity of the interface layer 21 between the surface 10a of the substrate 10 and the semiconductor layer 20 can be provided in which the concentration of the Si compensation element increases in the direction from the interface side toward the surface 20a of the semiconductor layer 20.

[0130] According to the above example, a semiconductor device can also be obtained in which the substrate 10, the interface layer 21, and the initial layer 22 contain mainly Mn as a Si compensation element. Furthermore, according to the above example, it is also possible to obtain a semiconductor device having a configuration in which the substrate 10 contains mainly Fe as a Si compensation element, the initial layer 22 contains mainly Mn as a Si compensation element, and the interface layer 21 contains mainly Fe and Mn as Si compensation elements.

[0131] Furthermore, according to the above example, it is also possible to obtain a semiconductor device having a configuration in which the substrate 10 contains mainly Mn as a Si compensation element, the initial layer 22 contains mainly C as a Si compensation element, and the interface layer 21 contains mainly Mn and C as Si compensation elements.

[0132] Furthermore, according to the above example, it is also possible to obtain a semiconductor device having a configuration in which the substrate 10 contains mainly C as a Si compensation element, the initial layer 22 contains mainly Mn as a Si compensation element, and the interface layer 21 contains mainly C and Mn as Si compensation elements.

[0133] In the above explanation, an example has been shown in which nitride semiconductors are used for the substrate 10 and the semiconductor layer 20, but the above-described method of using the substrate 10, interface layer 21, and initial layer 22 can be similarly applied to cases in which other semiconductors or compound semiconductors are used for the substrate 10 and the semiconductor layer 20. In such cases, as in the above, it becomes possible to compensate for Si segregated at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20 provided thereon with a relatively low concentration of Si compensating element without increasing the thickness of the semiconductor layer 20.

[0134] The first to sixth embodiments have been described above. The semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. having the configurations described in the first to sixth embodiments can be applied to various electronic devices. As an example, the following describes cases in which the semiconductor device having the configurations described above is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0135] [Seventh embodiment] Here, an example of application of a semiconductor device having the above-described configuration to a semiconductor package will be described as the seventh embodiment.

[0136] Fig. 14 is a diagram illustrating an example of a semiconductor package according to the seventh embodiment, which diagrammatically shows a plan view of a main part of an example of a semiconductor package according to the seventh embodiment.

[0137] 14 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1A (FIG. 3, etc.) described in the second embodiment, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

[0138] The semiconductor device 1A is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pads 30a, 40a, and 50a are connected to a gate lead 211, a source lead 212, and a drain lead 213 of the lead frame 210, respectively, using wires 230 made of Au, Al, or the like. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that a portion of each of the gate lead 211, the source lead 212, and the drain lead 213 is exposed.

[0139] An external connection electrode connected to the source electrode 40 may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

[0140] For example, the semiconductor device 1A described in the second embodiment is used to obtain a semiconductor package 200 having such a configuration. As described above, in the semiconductor device 1A, the interface layer 21 containing a Si compensation element and F is provided at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. The Si compensation element in the interface layer 21 is contained at a higher concentration than the Si segregated at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. Therefore, the Si segregated at the interface is sufficiently compensated by the Si compensation element in the interface layer 21, thereby suppressing a decrease in breakdown voltage and signal propagation to the interface. In addition to the Si compensation element, the interface layer 21 also contains F. The F in the interface layer 21 terminates dangling bonds on the surface 10a of the substrate 10 and reduces the amount of Si segregated at the interface. Therefore, the amount of Si compensation element contained at a higher concentration than the Si segregated at the interface can be suppressed, and a relatively low concentration of the Si compensation element can suppress deterioration of current collapse and the resulting decrease in output power. In the semiconductor device 1A, the Si at the interface can be compensated for by a relatively low concentration of the Si compensation element. The interface layer 21 realizes a semiconductor device 1A that effectively suppresses characteristic degradation caused by Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20. A high-performance semiconductor package 200 is realized by using such a semiconductor device 1A.

[0141] Although the semiconductor device 1A is used as an example here, it is possible to obtain a semiconductor package in the same manner using other semiconductor devices 1, 1B, 1C, 1D, 1E, etc. [Eighth embodiment] Here, an example of application of a semiconductor device having the above-described configuration to a power factor correction circuit will be described as an eighth embodiment.

[0142] Fig. 15 is a diagram for explaining an example of a power factor correction circuit according to the eighth embodiment, showing an equivalent circuit diagram of an example of the power factor correction circuit according to the eighth embodiment. The power factor correction (PFC) circuit 300 shown in FIG. 15 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0143] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out between both terminals of the capacitor 350.

[0144] For example, the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used as the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., an interface layer 21 containing a Si compensation element and F is provided at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. The Si compensation element in the interface layer 21 is contained at a higher concentration than the Si segregated at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. Therefore, the Si segregated at the interface is sufficiently compensated for by the Si compensation element in the interface layer 21, thereby suppressing a decrease in breakdown voltage and signal propagation to the interface. In addition to the Si compensation element, the interface layer 21 also contains F. The F in the interface layer 21 terminates dangling bonds on the surface 10 a of the substrate 10 and reduces the amount of Si segregated at the interface. Therefore, the amount of Si compensation element contained at a higher concentration than the Si segregated at the interface can be suppressed, and a relatively low concentration of the Si compensation element can suppress deterioration of current collapse and the resulting decrease in output power. In the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., Si at the interface can be compensated for with a relatively low concentration of Si compensating element. The interface layer 21 effectively suppresses the deterioration of characteristics caused by Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, thereby realizing the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. A high-performance PFC circuit 300 is realized by using such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc.

[0145] [Ninth embodiment] Here, an example of application of a semiconductor device having the above-described configuration to a power supply device will be described as a ninth embodiment.

[0146] Fig. 16 is a diagram for explaining an example of a power supply device according to the ninth embodiment, showing an equivalent circuit diagram of an example of the power supply device according to the ninth embodiment. The power supply device 400 shown in FIG. 16 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0147] The primary side circuit 410 includes the PFC circuit 300 as described in the eighth embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of (for example, four in this case): a switch element 441, a switch element 442, a switch element 443, and a switch element 444.

[0148] The secondary side circuit 420 includes a plurality of switch elements, three of which are a switch element 421, a switch element 422, and a switch element 423, as an example. For example, the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441 to 444 of the full bridge inverter circuit 440. For example, the switch elements 421 to 423 of the secondary side circuit 420 of the power supply device 400 are ordinary MIS (Metal Insulator Semiconductor) type FETs using silicon.

[0149] As described above, in the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., an interface layer 21 containing a Si compensation element and F is provided at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. The Si compensation element in the interface layer 21 is contained at a higher concentration than the Si segregated at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. Therefore, the Si segregated at the interface is sufficiently compensated for by the Si compensation element in the interface layer 21, thereby suppressing a decrease in breakdown voltage and signal propagation to the interface. In addition to the Si compensation element, the interface layer 21 also contains F. The F in the interface layer 21 terminates dangling bonds on the surface 10 a of the substrate 10 and reduces the amount of Si segregated at the interface. Therefore, the amount of Si compensation element contained at a higher concentration than the Si segregated at the interface can be suppressed, and a relatively low concentration of the Si compensation element can suppress deterioration of current collapse and the resulting decrease in output power. In the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., Si at the interface can be compensated for with a relatively low concentration of Si compensating element. The interface layer 21 effectively suppresses the deterioration of characteristics caused by Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, thereby realizing the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. A high-performance power supply device 400 is realized by using such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc.

[0150] [Tenth embodiment] Here, an example of application of a semiconductor device having the above-described configuration to an amplifier will be described as a tenth embodiment.

[0151] Fig. 17 is a diagram for explaining an example of an amplifier according to the tenth embodiment, showing an equivalent circuit diagram of an example of the amplifier according to the tenth embodiment. The amplifier 500 shown in FIG. 17 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0152] The digital predistortion circuit 510 compensates for nonlinear distortion in the input signal. The mixer 520 mixes the input signal SI, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal resulting from mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0153] The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. As described above, in the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., an interface layer 21 containing a Si compensation element and F is provided at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. The Si compensation element in the interface layer 21 is contained at a higher concentration than the Si segregated at the interface between the surface 10 a of the substrate 10 and the semiconductor layer 20. Therefore, the Si segregated at the interface is sufficiently compensated for by the Si compensation element in the interface layer 21, thereby suppressing a decrease in breakdown voltage and signal propagation to the interface. In addition to the Si compensation element, the interface layer 21 also contains F. The F in the interface layer 21 terminates dangling bonds on the surface 10 a of the substrate 10 and reduces the amount of Si segregated at the interface. Therefore, the amount of Si compensation element contained at a higher concentration than the Si segregated at the interface can be suppressed, and a relatively low concentration of the Si compensation element can suppress deterioration of current collapse and the resulting decrease in output power. In the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., Si at the interface can be compensated for with a relatively low concentration of Si compensating element. The interface layer 21 effectively suppresses the deterioration of characteristics caused by Si segregating at the interface between the surface 10a of the substrate 10 and the semiconductor layer 20, thereby realizing the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. A high-performance amplifier 500 is realized by using such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc.

[0154] Various electronic devices to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the seventh to tenth embodiments) can be mounted in various electronic devices or electronic devices, such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing equipment, transmitters, receivers, and radar devices.

[0155] The following additional notes are provided regarding the above-described embodiment. (Appendix 1) A substrate, a semiconductor layer provided on a first surface of the substrate; Including, the semiconductor layer has an interface layer containing a silicon compensating element and fluorine at an interface with the first surface of the substrate; The semiconductor device is characterized in that the concentration of the silicon in the interface layer is lower than the concentration of the element in the interface layer.

[0156] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the fluorine terminates dangling bonds on the first surface of the substrate. (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the element contains at least one of iron, carbon, and manganese.

[0157] (Note 4) The concentration of the element in the interface layer is 5×10 18 cm -3 4. The semiconductor device according to any one of claims 1 to 3, wherein: (Appendix 5) A semiconductor device described in any one of Appendices 1 to 4, characterized in that the semiconductor layer has a region on the interface layer side containing the element, and the concentration of the element increases in a direction from the interface layer toward a second surface of the semiconductor layer opposite the interface layer side.

[0158] (Supplementary Note 6) The semiconductor layer is an initial layer provided on the interface layer side; an electron transit layer provided on the side of the initial layer opposite to the interface layer; an electron supply layer provided on the side of the electron transit layer opposite to the initial layer side; Including, 6. The semiconductor device according to any one of claims 1 to 5, wherein the element is contained in the substrate, the interface layer, and the initial layer.

[0159] (Appendix 7) The semiconductor device according to appendix 6, wherein the substrate and the initial layer contain the same type of first element as the element, and the interface layer contains the first element.

[0160] (Appendix 8) The semiconductor device described in Appendix 6, characterized in that, as the elements, the substrate and the initial layer contain a second element and a third element that are different from each other, respectively, and the interface layer contains the second element and the third element.

[0161] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, wherein the substrate and the semiconductor layer are made of nitride semiconductors. (Supplementary Note 10) A step of forming a semiconductor layer on a first surface of a substrate; forming an interface layer containing a silicon compensating element and fluorine at an interface of the semiconductor layer with the first surface of the substrate; Including, A method for manufacturing a semiconductor device, wherein the concentration of the silicon in the interface layer is lower than the concentration of the element in the interface layer.

[0162] (Supplementary Note 11) Before forming the semiconductor layer, dangling bonds on the first surface of the substrate are terminated with fluorine; 11. A method for manufacturing a semiconductor device according to claim 10, characterized in that the interface layer is formed by adding the element to the first surface of the substrate terminated with fluorine to form the semiconductor layer.

[0163] (Appendix 12) A method for manufacturing a semiconductor device according to appendix 11, characterized in that the first surface of the substrate before the semiconductor layer is formed is exposed to an environment containing the fluorine, thereby terminating dangling bonds on the first surface with the fluorine.

[0164] (Appendix 13) A substrate; a semiconductor layer provided on a first surface of the substrate; Including, the semiconductor layer has an interface layer containing a silicon compensating element and fluorine at an interface with the first surface of the substrate; An electronic device comprising a semiconductor device in which the concentration of silicon in the interface layer is lower than the concentration of the element in the interface layer. [Explanation of symbols]

[0165] 1, 1A, 1B, 1C, 1D, 1E Semiconductor device 1a 2DEG 10 Substrate 10a,20a,22a,23a,24a,25a side 20 Semiconductor layer 21 Interface layer 22 Initial layer 23 Electron transit layer 24 Electron supply layer 25 cap layer 30 gate electrode 30a, 40a, 50a pads 40 Source electrode 50 drain electrode 60 Passivation Layer 60a opening 70 Environment 200 Semiconductor Packages 210 Lead Frame 210a die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310,421,422,423,441,442,443,444 Switching elements 320 Diode 330 Choke Coil 340,350 capacitors 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 transformer 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520,530 Mixer 540 Power Amplifier AR area

Claims

1. A substrate; a semiconductor layer provided on a first surface of the substrate; Including, the semiconductor layer has an interface layer containing a silicon compensating element and fluorine at an interface with the first surface of the substrate; the concentration of the silicon in the interface layer is lower than the concentration of the element in the interface layer; The semiconductor layer is an initial layer provided on the interface layer on the side opposite to the substrate; an electron transit layer provided on the side of the initial layer opposite to the interface layer; an electron supply layer provided on the side of the electron transit layer opposite to the initial layer side; Including, The semiconductor device is characterized in that the element is contained in the substrate, the interface layer, and the initial layer.

2. The concentration of the element in the interface layer is 5×10 １８ cm －３ 2. The semiconductor device according to claim 1, wherein:

3. 3. The semiconductor device according to claim 1, wherein the semiconductor layer has a region on the interface layer side that contains the element, and the concentration of the element increases in a direction from the interface layer toward a second surface of the semiconductor layer opposite the interface layer side.

4. 4. The semiconductor device according to claim 1, wherein the substrate and the initial layer contain the same first element as the element, and the interface layer contains the first element.

5. 4. The semiconductor device according to claim 1, wherein the substrate and the initial layer contain a second element and a third element, which are different from each other, respectively, and the interface layer contains the second element and the third element.

6. forming a semiconductor layer on a first surface of a substrate; forming an interface layer containing a silicon compensating element and fluorine at an interface of the semiconductor layer with the first surface of the substrate; Including, the concentration of the silicon in the interface layer is lower than the concentration of the element in the interface layer; The semiconductor layer is an initial layer provided on the interface layer on the side opposite to the substrate; an electron transit layer provided on the side of the initial layer opposite to the interface layer; an electron supply layer provided on the side of the electron transit layer opposite to the initial layer side; Including, The method for manufacturing a semiconductor device, wherein the element is contained in the substrate, the interface layer, and the initial layer.

7. terminating dangling bonds on the first surface of the substrate with fluorine before forming the semiconductor layer; 7. The method for manufacturing a semiconductor device according to claim 6, wherein the interface layer is formed by adding the element to the first surface of the substrate terminated with fluorine to form the semiconductor layer.

8. A substrate; a semiconductor layer provided on a first surface of the substrate; Including, the semiconductor layer has an interface layer containing a silicon compensating element and fluorine at an interface with the first surface of the substrate; An electronic device comprising a semiconductor device in which the concentration of silicon in the interface layer is lower than the concentration of the element in the interface layer.

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