Trench-gate trench-field-plate semi-vertical semi-lateral MOSFET

Abstract

To provide a semiconductor device that limits fabrication cost and complexity to desired levels.SOLUTION: A semiconductor device 100 has a vertical drain extended MOS transistor 110 with deep trench structures 104 to define a vertical drift region 108 and at least one vertical drain contact region 106, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions, and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. At least one gate 114, body region 118, and source region 120 are formed above the drift region at a top surface of a substrate 102 of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates generally to semiconductor devices, and more particularly to drain extended transistors in semiconductor devices. [Background technology]

[0002] An extended drain metal-oxide-semiconductor (MOS) transistor can be characterized by the transistor's resistance in the on-state, the lateral area the transistor occupies on the top surface of a substrate containing the transistor, and the breakdown potential between the transistor's drain and source nodes, which limits the transistor's maximum operating potential. It may be desirable to reduce the transistor's area for a given value of on-state resistance and breakdown potential. One approach to reducing the area is to configure the drift region in the extended drain with a vertical orientation so that the drain current in the drift region flows vertically to the top surface of the substrate. Integrating a vertically oriented drift region in a semiconductor device using a planar process while limiting manufacturing cost and complexity to a desired level can be challenging. Summary of the Invention

[0003] In the described example, a semiconductor device having a vertical drain-extended MOS transistor can be formed by forming a deep trench structure to define a vertical drift region of the transistor and at least one vertical drain contact region adjacent to the drift region, separated from the vertical drift region by at least one instance of the deep trench structure. Dopants are implanted into the vertical drain contact region, and the semiconductor device is annealed to cause the implanted dopants to diffuse adjacent the bottom of the deep trench structure. The vertical drain contact region makes electrical contact to the adjacent vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body, and source region are formed above the drift region at or adjacent to the top surface of a substrate of the semiconductor device. The deep trench structures are spaced apart to form a RESURF region for the drift region. [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor.

[0005] [Figure 2] FIG. 10 is a cross-sectional view of another semiconductor device having a vertical drain extended MOS transistor.

[0006] [Figure 3] 1 is a cross-sectional view of a further semiconductor device having a vertical drain extended MOS transistor.

[0007] [Figure 4] FIG. 10 is a cross-sectional view of another semiconductor device having a vertical drain extended MOS transistor.

[0008] [Figure 5] 1 is a cross-sectional view of a further semiconductor device having a vertical drain extended MOS transistor.

[0009] [Figure 6A] 1A-1D are cross-sectional views of a semiconductor device at successive stages of manufacture. [Figure 6B] 1A-1D are cross-sectional views of a semiconductor device at successive stages of manufacture. [Figure 6C] 1A-1D are cross-sectional views of a semiconductor device at successive stages of manufacture. [Figure 6D] 1A-1D are cross-sectional views of a semiconductor device at successive stages of manufacture. [Figure 6E] 1A-1D are cross-sectional views of a semiconductor device at successive stages of manufacture.

[0010] [Figure 7] FIG. 1 is a top view of a semiconductor device having a vertical drain extended MOS transistor.

[0011] [Figure 8] FIG. 1 is a top view of a semiconductor device having a vertical drain extended MOS transistor. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following co-pending patent applications are incorporated herein by reference: [Patent Document 1] U.S. Patent Application No. US14 / 044,915 [Patent Document 2] U.S. Patent Application No. US14 / 044,926

[0013] In at least one example, the semiconductor device can be an integrated circuit including the vertical drain extended MOS transistor and at least one other transistor. In another example, the semiconductor device can be a discrete device in which the vertical drain extended MOS transistor is the only transistor.

[0014] For the purposes of this description, the term "specific resistivity" for a transistor is the product of the area that the transistor occupies on the top surface of the substrate on which it is formed multiplied by the resistance of the transistor when it is fully on.

[0015] For purposes of this description, the term "RESURF" refers to a material that reduces the electric field in nearby semiconductor regions. For example, a RESURF region can be a semiconductor region of the opposite conductivity type to the nearby semiconductor regions. RESURF structures are described in Appel et al., "Thin-Layer High-Voltage Devices," Philips J. Res. 35 1-13, 1980. [Non-Patent Document 1] Appels, et al. “Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980

[0016] The examples described in this disclosure illustrate n-channel devices. Corresponding p-channel devices can be formed by appropriate changes in doping polarity. FIG. 1 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor. A semiconductor device 100 is formed in and on a p-type semiconductor substrate 102. A deep trench structure 104 is disposed in the substrate 102 to define at least one n-type vertical drain contact region 106 and at least one n-type vertically oriented drift region 108 of a vertical drain extended MOS transistor 110. The vertical drain contact region 106 is bounded on at least two opposite sides by the deep trench structure 104. The vertical drain contact region 106 is n-type and, in this example, extends below a bottom 112 of the deep trench structure 104. The vertical drain contact region 106 may extend laterally below the bottom 112 of the deep trench structure 104 to separate the vertically oriented drift region 108 from a p-type bottom region of the substrate 102, as shown in FIG. 1. In other examples, the vertical drain contact region 106 may have a more limited lateral extent. The vertically oriented drift region 108 is n-type and makes electrical connection to the vertical drain contact region 106 near the bottom of the deep trench structure 104. In this example, the electrical connection to the vertical drain contact region 106 is made at the top surface of the substrate 102.

[0017] At least one gate 114 and corresponding gate dielectric layer 116 are disposed over the vertically oriented drift region 108. In this example, the gate 114 is disposed in a trench in the substrate 102, extending between adjacent instances of the deep trench structure 104. At least one p-type body region 118 is disposed in the substrate 102 near the gate 114 and the vertically oriented drift region 108. At least one n-type source region 120 is disposed in the substrate 102 near the gate 114. One or more optional p-type body contact regions 122 may be disposed in the substrate 102 adjacent to the body region 118. In this example, electrical connections to the source region 120 and the body contact region 122 are made at the top surface of the substrate 102. Other gate configurations can be used for the vertical drain extended MOS transistor 110 with the deep trench structure 104, vertical drain contact region 106, and vertically oriented drift region 108 configuration shown in FIG. 1 .

[0018] The deep trench structure 104 may be 1 to 5 microns deep and 0.5 to 1.5 microns wide. For example, a 2.5 micron deep deep trench structure 104 may provide 30 volt operation for the vertical drain extended MOS transistor 110. A 4 micron deep deep trench structure 104 may provide 50 volt operation for the vertical drain extended MOS transistor 110. The deep trench structure 104 may have a dielectric liner 124 and may optionally have a conductive center member 126. Instances of the deep trench structure 104 adjacent to the vertically oriented drift region 108 may be spaced 0.5 to 2 microns apart to provide a RESURF region for the vertically oriented drift region 108. Instances of the deep trench structure 104 adjacent to the vertical drain contact region 106 may be spaced 0.5 to 2.5 microns apart. During operation of the vertical drain extended MOS transistor 110, the conductive center member 126, if present, can be electrically biased to reduce the peak electric field in the vertically oriented drift region 108. For example, the conductive center member 126 can be connected to the source region 120, to the gate 114, or to a bias source having a desired potential.

[0019] Instances of the vertically oriented drift region 108 are disposed near the vertical drain contact region 106. For example, the instances of the vertically oriented drift region 108 can be staggered with the vertical drain contact region 106, as shown in FIG. 1 . The deep trench structure 104 can surround the vertically oriented drift region 108, as shown in FIG. 1 . The vertical drain contact region 106 can be continuous, as shown in FIG. 1 . Staggered configurations of the deep trench structure 104 are described hereinafter. Forming the vertical drain extended MOS transistor 110 so that the deep trench structure 104 provides a RESURF region for the vertically oriented drift region 108 can provide a desired balance between operating voltage and a specific resistivity for the vertical drain extended MOS transistor 110. Forming the vertical drain contact region 106 to isolate the vertically oriented drift region 108 from a bottom region of the substrate 102 can desirably reduce the resistance of the vertical drain extended MOS transistor 110.

[0020] FIG. 2 is a cross-sectional view of another semiconductor device having a vertical drain extended MOS transistor. The semiconductor device 200 is formed in and on a p-type semiconductor substrate 202. As described with reference to FIG. 1, a deep trench structure 204 may be disposed in the substrate 202 to define at least one n-type vertical drain contact region 206 and at least one n-type vertically oriented drift region 208 of a vertical drain extended MOS transistor 210. The vertical drain contact region 206 is bounded on at least two opposite sides by the deep trench structure 204. The vertical drain contact region 206 is n-type and extends below a bottom 212 of the deep trench structure 204 in this example. The vertical drain contact region 206 may extend laterally beyond the bottom 212 of the deep trench structure 204, but does not extend far enough to isolate the vertically oriented drift region 208 from the bottom region of the substrate 202, as shown in FIG. 2. In other examples, the vertical drain contact region 206 may have a more limited vertical and / or lateral extent. The vertically oriented drift region 208 is n-type and makes electrical connection to the vertical drain contact region 206 near the bottom of the deep trench structure 204. In this example, the electrical connection to the vertical drain contact region 206 is made at the top surface of the substrate 202.

[0021] At least one gate 214 and corresponding gate dielectric layer 216 are disposed over the vertically oriented drift region 208. In this example, the gate 214 is disposed in a trench in the substrate 202 and is not adjacent to an adjacent instance of the deep trench structure 204. At least one p-type body region 218 is disposed in the substrate 202 near the gate 214 and the vertically oriented drift region 208. At least one n-type source region 220 is disposed in the substrate near the gate 214. One or more optional p-type body contact regions 222 may be disposed in the substrate 202 adjacent to the body region 218. In this example, electrical connections to the source region 220 and the body contact region 222 are made at the top surface of the substrate 202. Other gate configurations can be used for the vertical drain extended MOS transistor 210 with the deep trench structure 204, vertical drain contact region 206, and vertically oriented drift region 208 configuration shown in FIG. 2 .

[0022] Instances of vertically oriented drift regions 208 are disposed near vertical drain contact regions 206. For example, the instances of vertically oriented drift regions 208 may be staggered with the vertical drain contact regions 206, as shown in FIG. 2. The deep trench structure 204 may surround the vertically oriented drift regions 108, as shown in FIG. 2. The vertical drain contact regions 106 may be continuous, as shown in FIG. 2. Forming the vertical drain extended MOS transistor 210 such that the deep trench structure 204 provides a RESURF region for the vertically oriented drift regions 208 may provide a desired balance between operating voltage and a specific resistivity for the vertical drain extended MOS transistor 210. Forming the vertical drain contact region 206 to extend laterally beyond the bottom 212 of the deep trench structure 204, but not far enough to isolate the vertically oriented drift region 208 from the bottom region of the substrate 202, may enable depletion of the vertically oriented drift region 208 along a greater vertical distance, which may desirably enable operation at higher voltages.

[0023] FIG. 3 is a cross-sectional view of a further semiconductor device having a vertical drain extended MOS transistor. The semiconductor device 300 is formed in and on a p-type semiconductor substrate 302. A deep trench structure 304 may be disposed in the substrate 302 to define at least one n-type vertical drain contact region 306 and at least one n-type vertically oriented drift region 308 of a vertical drain extended MOS transistor 310, as described with reference to FIG. 1. The vertical drain contact region 306 is bounded on at least two opposite sides by the deep trench structure 304. The vertical drain contact region 306 is n-type and may extend below a bottom 312 of the deep trench structure 304, as shown in FIG. 3. In this example, the vertically oriented drift region 308 is laterally offset from the vertical drain contact region 306 by at least two instances of the deep trench structure 304 to provide a horizontal drift component for the extended drain of the vertical drain extended MOS transistor 310. In this example, electrical connection to vertical drain contact region 306 is made at the top surface of substrate 302 .

[0024] At least one gate 314 and corresponding gate dielectric layer 316 are disposed above the vertically oriented drift region 308. In this example, the gate 314 is disposed above the substrate 302 over the p-type body region 318 and the n-type source region 320. One or more optional p-type body contact regions 322 may be disposed in the substrate 302 adjacent to the body region 318. In this example, electrical connections to the source region 320 and the body contact region 322 are made at the top surface of the substrate 302. Other gate configurations may be used for the vertical drain extended MOS transistor 310 with the deep trench structure 304, vertical drain contact region 306, and laterally offset vertically oriented drift region 308 configuration shown in FIG. Forming the vertically oriented drift region 308 laterally offset from the vertical drain contact region 306 may enable lateral depletion of the vertically oriented drift region 308 and may advantageously increase the operating voltage of the vertical drain extended MOS transistor 310 without requiring a deeper instance of the deep trench structure 304.

[0025] FIG. 4 is a cross-sectional view of another semiconductor device having a vertical drain extended MOS transistor. The semiconductor device 400 is formed in and on a p-type semiconductor substrate 402. A deep trench structure 404 is disposed in the substrate 402, as described with reference to FIG. 1, to define at least one vertical drain contact region 406 and at least one vertically oriented drift region 408 of a vertical drain extended MOS transistor 410. The vertical drain contact region 406 is bounded on at least two opposite sides by the deep trench structure 404. The vertical drain contact region 406 is n-type and, in this example, extends proximate to, but does not extend below, the bottom 412 of the deep trench structure 404. The vertically oriented drift region 408 is n-type and makes electrical connection to the vertical drain contact region 406 proximate to the bottom 412 of the deep trench structure 404.

[0026] At least one gate 414 and corresponding gate dielectric layer 416 are disposed above the vertically oriented drift region 408. In this example, the gate 414 is disposed above the substrate 402 over p-type body regions 418 and n-type source regions 420. One or more optional p-type body contact regions 422 may be disposed in the substrate 402 adjacent to the body region 418. In this example, a portion of the vertically oriented drift region 408 directly below the gate 414 is laterally separated from the nearest instance of the deep trench structure 404 by a dielectric material 434, such as a field oxide 434. Such a configuration may add a lateral drift component to the vertical drain extended MOS transistor 410 and may advantageously increase the operating voltage of the vertical drain extended MOS transistor 410. The portion of the vertically oriented drift region 408 directly below the gate 414 may also, in some cases, be laterally separated from the nearest instance of the vertical drain contact region 406 by at least two instances of the deep trench structure 404, as shown in Figure 3. Other configurations of gates may be used in the vertical drain extended MOS transistor 410 with the configuration of the deep trench structure 404, vertical drain contact region 406, and vertically oriented drift region 408 shown in Figure 4. Forming the vertically oriented drift region 408 laterally offset from the vertical drain contact region 406 may enable lateral depletion of the vertically oriented drift region 408 and may advantageously increase the operating voltage of the vertical drain extended MOS transistor 410 without requiring deeper instances or additional instances of the deep trench structure 404.

[0027] FIG. 5 is a cross-sectional view of a further semiconductor device having a vertical drain extended MOS transistor. The semiconductor device 500 is formed in and on a p-type semiconductor substrate 502 as described with reference to FIG. 1. A deep trench structure 504 is disposed in the substrate 502 as described with reference to FIG. 1 to define at least one vertical drain contact region 506 and a vertical portion of at least one vertically oriented drift region 508 of a vertical drain extended MOS transistor 510. The vertical drain contact region 506 is bounded on at least two opposite sides by the deep trench structure 504. The vertical drain contact region 506 is n-type and, in this example, extends adjacent to and possibly below a bottom 512 of the deep trench structure 504. In this example, the vertically oriented drift region 508 extends below the bottom 512 of the deep trench structure 504 and extends laterally to form a continuous n-type region. The vertically oriented drift region 508 is n-type and makes electrical connection to the vertical drain contact region 506. Such a configuration advantageously reduces the on-state resistance of the vertical drain extended MOS transistor 510.

[0028] At least one gate 514 and corresponding gate dielectric layer 516 are disposed above the vertically oriented drift region 508. In this example, the gate 514 is disposed in a dielectric liner 524 of the deep trench structure 504, near a p-type body region 518 and an n-type source region 520. One or more optional p-type body contact regions 522 may be disposed in the substrate 502 adjacent the body region 518. Other gate configurations can be used for the vertical drain extended MOS transistor 510 with the deep trench structure 504, vertical drain contact region 506, and vertically oriented drift region 508 configuration shown in FIG.

[0029] 6A-6E are cross-sectional views of a semiconductor device at successive stages of fabrication. Referring to FIG. 6A, a semiconductor device 600 is formed in and on a p-type semiconductor substrate 602, such as a single crystal silicon wafer. A drift region ion implantation process is performed to implant an n-type dopant, such as phosphorus, into the substrate 602 in an area defined for the vertically oriented drift region to form a drift implanted region 630. For example, the dose of the drift region ion implantation process may be 1×10 cm to 1×10 cm. In at least one version of this embodiment, as shown in FIG. 6A, the drift implanted region 630 may extend across the area defined for the vertical drain contact region. In an alternative version, the drift implanted region 630 may be limited to an area of the substrate defined for the vertically oriented drift region.

[0030] 6B, deep isolation trenches 628 are formed in substrate 602, such as by a process that begins with forming a layer of hard mask material over the top surface of substrate 602. The hard mask may be formed by forming an etch mask by photolithography, followed by removing the hard mask material over the areas defined for deep isolation trenches 628 using a reactive ion etching (RIE) process. After patterning the hard mask, material is removed from substrate 602 in the deep isolation trenches 628 using an anisotropic etch process, such as a Bosch deep RIE process or a sequential deep RIE process.

[0031] 6C, a dielectric liner 624 is formed in the deep isolation trench 628 such that the dielectric liner 624 is adjacent to the substrate 602. For example, the dielectric liner 624 may comprise thermally grown silicon dioxide. The dielectric liner 624 may also comprise one or more layers of a dielectric material, such as silicon dioxide, silicon nitride, and / or silicon oxynitride, formed by a chemical vapor deposition (CVD) process.

[0032] An optional conductive central member 626 may be formed on the dielectric liner 624. For example, the conductive central member 626 may comprise polycrystalline silicon, commonly referred to as polysilicon, formed by pyrolyzing SiH gas in a low-pressure reactor at temperatures between 580°C and 650°C. The polysilicon may be doped during formation to provide the desired electrical conductivity. The deep isolation trenches 628, filled with the dielectric liner 624 and, if present, the conductive central member 626, form the deep trench structure 604. Unwanted dielectric material on the top surface of the substrate 602 from the formation of the dielectric liner 624 and unwanted conductive material on the top surface of the substrate 602 from the formation of the conductive central member 626 may be removed by using processes such as etch-back and / or chemical-mechanical polishing (CMP).

[0033] 6D, a drain contact ion implantation process is performed to implant an n-type dopant, such as phosphorus, into the substrate 602 in areas defined for the vertical drain contact regions to form drain contact implanted regions 632. The dose of the drift region ion implantation process may be at least 10 times higher than the drift region ion implantation dose, for example, 1×10 cm to 3×10 cm. The drain contact ion implantation process may provide dopants to the polysilicon version of the conductive central member 626 to obtain the desired electrical conductivity.

[0034] 6E, a thermal drive operation is performed. This operation heats the substrate 602 to activate and diffuse the implanted dopants in the drift implanted region 630 and the drain contact implanted region 632, thereby forming the vertically oriented drift region 608 and the vertical drain contact region 606, respectively. The conditions of the thermal drive operation depend on the depth of the deep trench structure 604 and the desired lateral extent of the vertical drain contact region 606 at the bottom of the deep trench structure 604. For example, a vertical drain extended MOS transistor with a 2.5 micron deep deep trench structure 604 may have a thermal drive operation that heats the substrate 602 to 1100°C for 3.5-4 hours, or equivalent annealing conditions such as 1125°C for 2 hours or 1050°C for 12 hours.

[0035] 7 and 8 are top views of a semiconductor device having a vertical drain extended MOS transistor. The gates shown in FIGS. 7 and 8 are disposed in trenches as described with reference to FIG. 2, although other gate configurations may be used in these examples. Referring to FIG. 7, a semiconductor device 700 is formed in and on a semiconductor substrate 702 as described with reference to FIG. 6A. A deep trench structure 704 with a closed-loop configuration may be disposed in the substrate 702. Instances of the deep trench structure 704 laterally surround a vertical drain contact region 706. A gate 714 and a gate dielectric layer 716 of a vertical drain extended MOS transistor 710 are disposed between the deep trench structures 704 that laterally surround the vertical drain contact region 706. A vertical drift region 708 is disposed between the deep trench structures 704 that surround the vertical drain contact region 706. The body, source, and body contact regions of vertical drain extended MOS transistor 710 are not shown in FIG. 7 to more clearly show the placement of vertical drift region 708 and vertical drain contact region 706. Instances of deep trench structure 704 laterally surround vertical drain extended MOS transistor 710. Electrical connection to vertical drain contact region 706 is made at the top surface of substrate 702. Surrounding vertical drain contact region 706 with deep trench structure 704 may prevent a breakdown field between the drain contact and body region of vertical drain extended MOS transistor 710 and may advantageously allow vertical drain extended MOS transistor 710 to operate at higher voltages than otherwise possible.

[0036] 8, a semiconductor device 800 is formed in and on a semiconductor substrate 802 as described with reference to FIG. 6A. Deep trench structures 804 with linear configurations may be disposed in the substrate 802. Vertical drain contact regions 806 are disposed between adjacent pairs of the linear deep trench structures 804. Gates 814 and gate dielectric layers 816 are disposed between adjacent pairs of the deep trench structures 804, alternating with the vertical drain contact regions 806. Vertical drift regions 808 are disposed between alternating pairs of the deep trench structures 804 with the gates 814. Body regions 818 are disposed around the linear deep trench structures 804 and extend above the vertical drift regions 808 so as to be adjacent to the gates 814. In this case, the portion of the body region 818 that extends over the vertical drift region 808 and the source and body contact regions of the vertical drain extended MOS transistor 810 are not shown in FIG. 8 to more clearly show the placement of the vertical drift region 808 and the vertical drain contact region 806. Instances of deep trench structures 804 laterally surround the vertical drain extended MOS transistor 810. Electrical connection to the vertical drain contact region 806 is made at the top surface of the substrate 802. Locating the vertical drain contact region 806 between linear deep trench structures 804 may advantageously reduce the area required for the vertical drain extended MOS transistor 810, thereby reducing the manufacturing cost of the semiconductor device 800.

[0037] Variations can be made in the exemplary embodiments described and many other embodiments are possible within the scope of the claims of the invention.

Claims

1. a semiconductor substrate; a perimeter trench formed in a surface of the semiconductor substrate, the perimeter trench having a closed loop configuration and defining a first region; a first trench formed in the first region spaced apart from a sidewall of the periphery trench, the first trench having a closed loop configuration to define a first interior region, the first trench including sidewalls, a bottom, a first dielectric liner formed on the sidewalls and the bottom, and a first conductive member formed on the first dielectric liner; a second trench formed in the first region spaced apart from sidewalls of the periphery trench and sidewalls of the first trench, the second trench having a closed loop configuration to define a second interior region, the second trench including sidewalls, a bottom, a second dielectric liner formed on the sidewalls and the bottom, and a second conductive member formed on the second dielectric liner; a first gate trench formed in the first region between the first trench and the second trench and spaced apart from a sidewall of the periphery trench, a sidewall of the first trench, and a sidewall of the second trench, the first gate trench including a sidewall, a bottom, a first gate dielectric layer formed on the sidewall and the bottom, and a first gate formed on the first gate dielectric layer; a first impurity region of a first conductivity type formed in the first region, the first impurity region extending along sidewalls of the first trench, the second trench, and the first gate trench to a first depth in the first region; a second impurity region of a second conductivity type formed in the first region below the first impurity region; a third impurity region of the first conductivity type formed in the first region below the second impurity region; Including, The first internal region and the second internal region have the first conductivity type and form a contact.

2. 2. The vertical transistor of claim 1, the first conductive member and the second conductive member are electrically connected to the first impurity region.

3. 2. The vertical transistor of claim 1, The vertical transistor, wherein the first trench and the second trench have a depth between 1 μm and 5 μm.

4. 2. The vertical transistor of claim 1, The vertical transistor, wherein the first trench and the second trench have a width between 0.5 μm and 1.5 μm.

5. 2. The vertical transistor of claim 1, A vertical transistor, wherein a sidewall of the first trench facing the first gate trench and a sidewall of the second trench facing the first gate trench have a spacing between 0.5 μm and 2.0 μm.

6. 2. The vertical transistor of claim 1, The vertical transistor, wherein the first and second dielectric liners comprise silicon nitride.

7. 2. The vertical transistor of claim 1, The vertical transistor, wherein the first and second dielectric liners comprise silicon oxynitride.

8. A vertical transistor, a semiconductor substrate; a perimeter trench formed in a surface of the semiconductor substrate, the perimeter trench having a closed loop configuration and defining a first region; a first trench formed in the first region spaced apart from a sidewall of the periphery trench, the first trench having a closed loop configuration to define a first interior region, the first trench including sidewalls, a bottom, a first dielectric liner formed on the sidewalls and the bottom, and a first conductive member formed on the first dielectric liner; a second trench formed in the first region spaced apart from sidewalls of the periphery trench and sidewalls of the first trench, the second trench having a closed loop configuration to define a second interior region, the second trench including sidewalls, a bottom, a second dielectric liner formed on the sidewalls and the bottom, and a second conductive member formed on the second dielectric liner; a first gate trench formed in the first region between the first trench and the second trench and spaced apart from a sidewall of the periphery trench, a sidewall of the first trench, and a sidewall of the second trench, the first gate trench including a sidewall, a bottom, a first gate dielectric layer formed on the sidewall and the bottom, and a first gate formed on the first gate dielectric layer; a first impurity region of a first conductivity type formed in the first region, the first impurity region extending along sidewalls of the first trench, the second trench, and the first gate trench to a first depth in the first region; a second impurity region of a second conductivity type formed in the first region below the first impurity region; a third impurity region of the first conductivity type formed in the first region below the second impurity region; a second gate trench formed in the first region between the periphery trench and the first trench, spaced apart from a sidewall of the periphery trench and a sidewall of the first trench, the second gate trench including a sidewall, a bottom, a second gate dielectric layer formed on the sidewall and the bottom, and a second gate formed on the second gate dielectric layer; Including, the first impurity region extends adjacent a sidewall of the second gate trench to a first depth in the first region;

9. a semiconductor substrate; a perimeter trench formed in a surface of the semiconductor substrate, the perimeter trench having a closed loop configuration and defining a first region; a linear first trench formed in the first region spaced apart from a sidewall of the periphery trench, the first trench including sidewalls, a bottom, a first dielectric liner formed on the sidewalls and the bottom, and a first conductive member formed on the first dielectric liner; a linear second trench formed in the first region and spaced apart from a sidewall of the periphery trench and a sidewall of the first trench, the second trench including sidewalls, a bottom, a second dielectric liner formed on the sidewalls and the bottom, and a second conductive member formed on the second dielectric liner; a first gate trench formed in a second region extending between the first trench and the second trench, spaced apart from sidewalls of the periphery trench, sidewalls of the first trench, and sidewalls of the second trench, the first gate trench including sidewalls, a bottom, a first gate dielectric layer formed on the sidewalls and the bottom, and a first gate formed on the first gate dielectric layer; a first impurity region of a first conductivity type formed in the second region and adjacent to sidewalls of the first trench, the second trench, and the first gate trench, and extending to a first depth in the second region; a second impurity region of a second conductivity type formed below the first impurity region; a third impurity region of the first conductivity type formed below the second impurity region; A vertical transistor comprising:

10. 10. The vertical transistor of claim 9, The vertical transistor further includes a contact of a first conductivity type formed in a third region extending between the perimeter trench and the first trench.

11. 10. A vertical transistor according to claim 9, the first conductive member and the second conductive member are electrically connected to the first impurity region.

12. 10. The vertical transistor of claim 9, The vertical transistor, wherein the first trench and the second trench have a depth between 1 μm and 5 μm.

13. 10. The vertical transistor of claim 9, The vertical transistor, wherein the first trench and the second trench have a width between 0.5 μm and 1.5 μm.

14. 10. The vertical transistor of claim 9, A vertical transistor, wherein a sidewall of the first trench facing the first gate trench and a sidewall of the second trench facing the first gate trench have a spacing between 0.5 μm and 2.0 μm.

15. 10. The vertical transistor of claim 9, The vertical transistor, wherein the first and second dielectric liners comprise silicon nitride.

16. 10. The vertical transistor of claim 9, The vertical transistor, wherein the first and second dielectric liners comprise silicon oxynitride.

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