Stacked structure, manufacturing method thereof, and semiconductor device including the stacked structure

Abstract

This laminate structure (100) comprises a buffer layer (106), a first semiconductor layer (108), and a second semiconductor layer (110). The buffer layer and the first semiconductor layer overlap one another in a vertical direction. The second semiconductor layer is in contact with a side surface of the first semiconductor layer and surrounds at least part of the first semiconductor layer in a plan view perpendicular to the vertical direction. The first semiconductor layer and the second semiconductor layer each contain a group III-V material or a group III nitride material. The crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a stacked structure, a method for manufacturing the same, and a semiconductor device including the stacked structure. [Background technology]

[0002] In recent years, the development of semiconductor devices using III-V group materials or III-nitride materials as semiconductors has been actively pursued. In particular, inorganic materials containing gallium nitride (hereinafter referred to as gallium nitride-based materials) have a larger band gap and higher breakdown field and saturated drift velocity than other semiconductor materials such as silicon and oxide semiconductors. For this reason, the use of gallium nitride-based materials in the active layer may enable the production of semiconductor devices with excellent characteristics, and gallium nitride-based materials have attracted considerable attention (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 155032 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a novel stacked layer structure including a III-V material or a III-nitride material, particularly a gallium nitride-based material, and a method for fabricating the same. Another object of one embodiment of the present invention is to provide a structure-controlled stacked layer structure including a III-V material or a III-nitride material, particularly a gallium nitride-based material, and a method for fabricating the same. Another object of one embodiment of the present invention is to provide a semiconductor device including the stacked layer structure. [Means for solving the problem]

[0005] One embodiment of the present invention is a stacked layer structure. The stacked layer structure includes a buffer layer, a first semiconductor layer, and a second semiconductor layer. The buffer layer and the first semiconductor layer overlap each other in the vertical direction. The second semiconductor layer contacts a side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the vertical direction. Each of the first semiconductor layer and the second semiconductor layer includes a III-V material or a III nitride material. The crystallinity of the first semiconductor layer is higher than that of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

[0006] One embodiment of the present invention is a semiconductor device including a stacked structure. The stacked structure includes a buffer layer, a first semiconductor layer, and a second semiconductor layer. The buffer layer and the first semiconductor layer overlap each other in the vertical direction. The second semiconductor layer contacts a side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the vertical direction. Each of the first semiconductor layer and the second semiconductor layer includes a III-V material or a III nitride material. The crystallinity of the first semiconductor layer is higher than that of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

[0007] One embodiment of the present invention is a method for fabricating a stacked structure. The method includes forming a buffer layer on a substrate, forming a semiconductor layer containing gallium nitride on the buffer layer so as to cover the buffer layer, and etching the semiconductor layer. The semiconductor layer is etched to leave a first portion that overlaps the buffer layer in the vertical direction and a second portion that does not overlap the buffer layer. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is a schematic top view of a laminated structure according to an embodiment of the present invention; [Figure 1B] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 2A] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 2B]1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 3A] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 3B] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 3C] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 4] 1 is a schematic end view of a laminated structure according to an embodiment of the present invention; [Figure 5A] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 5B] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 5C] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 5D] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 6A] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 6B] 1A to 1C are schematic end views illustrating a method for manufacturing a laminated structure according to an embodiment of the present invention. [Figure 7A] 1 is a schematic end view of a semiconductor device according to an embodiment of the present invention; [Figure 7B] 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention; [Figure 8A] 1 is a schematic end view of a semiconductor device according to an embodiment of the present invention; [Figure 8B] 1 is a schematic end view of a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0010] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0011] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0012] In this specification and claims, the expression "a structure exposed from another structure" means a state in which a part of a structure is not covered by another structure, and includes a state in which the part not covered by another structure is covered by yet another structure. The state expressed by this expression also includes a state in which a structure is not in contact with another structure.

[0013] In the embodiment of the present invention, when multiple films are formed simultaneously in the same process, these films have the same layer structure, the same material, and the same composition, and therefore these multiple films are defined as existing in the same layer.

[0014] First Embodiment In this embodiment, the structure of a laminated structure 100, which is one embodiment of the present invention, and a method for manufacturing the same will be described.

[0015] 1.Laminated structure FIG. 1A shows a schematic top view of a stacked structure 100, and FIG. 1B shows a schematic end view taken along the chain line AA′ in FIG. 1A. As shown in these figures, the stacked structure 100 basically includes a buffer layer 106, a first semiconductor layer 108, and a second semiconductor layer 110. The stacked structure 100 can be provided on a substrate 102, and an undercoat 104 may be provided between the stacked structure 100 and the substrate 102 as an optional configuration. As will be described in detail later, the first semiconductor layer 108 and the second semiconductor layer 110 include a III-V material or a III-nitride material. In this example, a gallium nitride-based material is used as an example of a III-V material or a III-nitride material.

[0016] 1-1.Buffer layer The buffer layer 106 has a function of promoting crystallization of the first semiconductor layer formed thereon, and can contain metals such as titanium, aluminum, silver, nickel, copper, strontium, rhodium, palladium, iridium, platinum, and gold, metal nitrides such as titanium nitride, or metal oxides such as zinc oxide. Because these elements or compounds are conductive, the buffer layer 106 can also function as an electrode.

[0017] Preferably, a material having a hexagonal close-packed structure or a structure equivalent thereto, such as titanium or zinc oxide, is used, which is a crystalline structure in which the c-axis is not perpendicular to the a-axis and b-axis. By forming the buffer layer 106 from such a material, the c-axis of the buffer layer 106 is oriented perpendicular or approximately perpendicular to the surface on which the buffer layer 106 is provided (the surface of the substrate 102 in the example shown in FIGS. 1A and 1B). Meanwhile, the gallium nitride-based material contained in the first semiconductor layer 108 is known to have a hexagonal crystal structure such as a wurtzite structure, and to grow crystals in the c-axis direction to minimize its surface energy. Therefore, by forming the buffer layer 106 from a material having a hexagonal close-packed structure or a structure equivalent thereto and forming the first semiconductor layer 108 containing the gallium nitride-based material so as to overlap the buffer layer 106, the first semiconductor layer 108 is influenced by the crystalline structure of the buffer layer 106 and grows crystals in the c-axis direction. As a result, the first semiconductor layer 108 can have a highly crystalline c-axis orientation.

[0018] To more effectively grow the crystal of the first semiconductor layer 108 in the c-axis direction, it is preferable that the surface of the buffer layer 106 be highly flat. Specifically, the arithmetic mean roughness (Ra) of the surface of the buffer layer 106 is preferably smaller than 2.3 nm. Furthermore, the root mean square roughness (Rq) of the surface of the buffer layer 106 is preferably smaller than 2.9 nm. To achieve high surface flatness, the thickness of the buffer layer 106 is preferably 50 nm or less, and the buffer layer 106 is formed to a thickness of, for example, 10 nm or more and 50 nm or less.

[0019] 1-2. First semiconductor layer and second semiconductor layer Both the first semiconductor layer 108 and the second semiconductor layer 110 include a III-V material or a III-nitride material, and gallium nitride materials will be specifically described. Gallium nitride materials include semiconductors containing nitrogen and gallium, such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN). The nitrogen-to-gallium ratio may deviate from the stoichiometric ratio. The first semiconductor layer 108 and the second semiconductor layer 110 may further include other elements. For example, the first semiconductor layer 108 and the second semiconductor layer 110 may include one or more elements such as silicon, germanium, magnesium, zinc, cadmium, beryllium, indium, aluminum, and arsenic. Adding these elements enables valence electron control of the first semiconductor layer 108 and the second semiconductor layer 110, which not only maintains intrinsic (i-type) conductivity but also allows band gap control and imparting p-type or n-type conductivity.

[0020] As shown in FIGS. 1A and 1B , the first semiconductor layer 108 is located on the buffer layer 106 and contacts the upper surface of the buffer layer 106. On the other hand, the second semiconductor layer 110 does not contact the upper surface of the buffer layer 106 and does not overlap the buffer layer 106. That is, the buffer layer 106 is exposed from the second semiconductor layer 110 in the vertical direction. The second semiconductor layer 110 contacts the side surfaces of the buffer layer 106 and surrounds at least a portion or the entire first semiconductor layer 108 in a plane perpendicular to the vertical direction. Therefore, as described above, the first semiconductor layer 108 is significantly influenced by the crystalline structure of the buffer layer 106, and crystal growth occurs preferentially in the c-axis direction during formation. However, the second semiconductor layer 110 is less influenced by the crystalline structure of the buffer layer 106 than the first semiconductor layer 108. Therefore, the crystallinity of the first semiconductor layer 108 is higher than that of the second semiconductor layer 110. For example, in electron beam diffraction analysis, the first semiconductor layer 108 gives a sharper peak (smaller half-width) than the second semiconductor layer 110.

[0021] The thicknesses of the first semiconductor layer 108 and the second semiconductor layer 110 are set appropriately depending on the application of the stacked structure 100. However, as will be described later, the first semiconductor layer 108 and the second semiconductor layer 110 are formed simultaneously. Therefore, the composition and thickness of the first semiconductor layer 108 and the second semiconductor layer 110 can be made the same or substantially the same.

[0022] 1-3. Substrate and undercoat There are no restrictions on the material contained in the substrate 102, and for example, an amorphous glass substrate, a quartz substrate, a sapphire substrate, a silicon substrate, or a substrate containing a polymer such as polyimide, polyamide, or acrylic resin can be used as the substrate 102. Alternatively, a metal substrate such as stainless steel can be used. There are also no restrictions on the crystallinity of the substrate 102, and either a single crystal substrate or an amorphous substrate can be used. The substrate 102 may be flexible.

[0023] The optional undercoat 104 is an electrically insulating film that may contain, for example, silicon-containing inorganic compounds such as silicon nitride and silicon oxide, as well as aluminum oxide. The undercoat 104 may have a single layer structure or may be composed of multiple layers of different compositions. For example, the undercoat 104 may be a laminate of a film containing silicon oxide and a film containing silicon nitride.

[0024] 2. Variations The structure of the stacked structure 100 is not limited to the above-described structure. For example, as shown in FIGS. 2A and 2B, the second semiconductor layer 110 may have a tapered shape. That is, the side surface of the second semiconductor layer 110 that is separated from the first semiconductor layer 108 may be inclined relative to the vertical direction. In this case, the thickness of the second semiconductor layer 110 may decrease (FIG. 2A) or increase (FIG. 2B) as the distance from the first semiconductor layer 108 increases in a plane perpendicular to the vertical direction. Alternatively, as shown in FIGS. 3A and 3C, a part or the entire side surface of the first semiconductor layer 108 may be exposed from the second semiconductor layer 110. Alternatively, as shown in FIGS. 3B and 3C, a part or the entire side surface of the buffer layer 106 may be exposed from the second semiconductor layer 110. The shape of the second semiconductor layer 110 can be controlled by appropriately adjusting the etching conditions.

[0025] Furthermore, in the stacked structure 100, the first semiconductor layer 108 and the second semiconductor layer 110 may each have a single-layer structure, or may be formed of multiple layers as shown in FIG. 4. When multiple layers are stacked, there are no restrictions on the number of layers and the number may be appropriately selected from the range of 2 to 10. In the example shown in FIG. 4, the first semiconductor layer 108 is composed of semiconductor layers 108-1, 108-2, 108-3, and 108-4, and the second semiconductor layer 110 is also composed of semiconductor layers 110-1, 110-2, 110-3, and 110-4. When multiple layers are stacked, the composition of each layer may be appropriately changed so that the conductivity differs between the layers. For example, each of the first semiconductor layer 108 and the second semiconductor layer 110 may be appropriately formed using a semiconductor layer containing p-type gallium nitride, a semiconductor layer containing p-type aluminum gallium nitride, a semiconductor layer containing n-type gallium nitride, and a semiconductor layer containing n-type aluminum gallium nitride. As described above, the first semiconductor layer 108 and the second semiconductor layer 110 are formed simultaneously in the same process. Therefore, the first semiconductor layer 108 and the second semiconductor layer 110 can have the same stacked structure. For example, the first semiconductor layer 108 and the second semiconductor layer 110 can have the same number of stacked layers, configuration, thickness, etc.

[0026] 3.Method for manufacturing laminated structure An example of a method for producing the laminated structure 100 shown in FIGS. 1A and 1B will be described below with reference to FIGS. 5A to 6B.

[0027] First, an undercoat 104 is formed on the substrate 102 (FIG. 5A). The undercoat may be formed by chemical vapor deposition (CVD) or sputtering. Alternatively, when a silicon substrate or a metal substrate is used, an oxide layer formed by oxidizing the surface may be used as the undercoat 104. In this case, a layer containing a silicon-containing inorganic compound may be further laminated on the oxide layer. Note that this step is unnecessary if the undercoat 104 is not provided.

[0028] Subsequently, a buffer layer 106 is formed on the substrate 102 directly or via an undercoat 104 (FIG. 5B). The buffer layer 106 may be formed by sputtering using a target containing the metal contained therein. Alternatively, the buffer layer 106 may be formed by evaporation, CVD, or the like. The buffer layer 106 is patterned by applying known photolithography.

[0029] Next, the first semiconductor layer 108 and the second semiconductor layer 110 are simultaneously formed. Specifically, a sputtering method using a gallium nitride sintered body as a sputtering target is applied to form a semiconductor layer 105 containing a gallium nitride-based material on the upper surface of the substrate 102 (5C). Examples of sputtering methods include bipolar sputtering, magnetron sputtering, dual magnetron sputtering, facing target sputtering, ion beam sputtering, and inductively coupled plasma (ICP) sputtering. When the substrate 102 is an amorphous glass substrate, the semiconductor layer 105 that will become the first semiconductor layer 108 and the second semiconductor layer 110 can be deposited on the buffer layer 106 by sputtering at a temperature of 600°C or less. This allows a semiconductor device including the stacked structure 100, as described below, to be formed on a large amorphous glass substrate at low cost.

[0030] At this time, the semiconductor layer 105 is formed to cover the buffer layer 106. That is, the semiconductor layer 105 is formed so that the entire upper surface of the buffer layer 106 overlaps with the semiconductor layer 105 so that the buffer layer 106 is not exposed from the semiconductor layer 105. As described above, the c-axis of the buffer layer 106 is oriented in a direction perpendicular or approximately perpendicular to the surface on which the buffer layer 106 is provided (here, the surface of the substrate 102 or the undercoat 104). Therefore, the crystalline structure of the buffer layer 106 promotes the crystal growth of the semiconductor layer 105 formed thereon. As a result, in the process of forming the semiconductor layer 105, crystal growth in the c-axis direction is promoted in the portion of the semiconductor layer 105 that overlaps with the buffer layer 106. On the other hand, the portion of the semiconductor layer 105 that does not overlap with the buffer layer 106 is less affected by the crystalline structure of the buffer layer 106, and the degree of crystal growth is smaller than that in the portion that overlaps with the buffer layer 106. Due to the crystal growth promoting function of the buffer layer 106, a first semiconductor layer 108 having high crystallinity and a second semiconductor layer 110 having lower crystallinity than the first semiconductor layer 108 are simultaneously formed (FIG. 5D). Therefore, the first semiconductor layer 108 and the second semiconductor layer 110 exist in the same layer and can have the same composition and structure.

[0031] Thereafter, patterning is performed by etching. Specifically, as shown in FIG. 6A, a resist mask 112 is formed on the first semiconductor layer 108 and the second semiconductor layer 110. The resist mask 112 may be formed by applying a known method. At this time, the shape of the resist mask 112 is determined depending on the characteristics required of the stacked structure 100, but is set so as to cover the first semiconductor layer 108 and a portion of the second semiconductor layer 110. More specifically, the resist mask 112 is provided so that the first semiconductor layer 108 is not exposed from the resist mask 112, the entire upper surface of the first semiconductor layer 108 overlaps with the resist mask 112, and the portion in contact with the second semiconductor layer 110 surrounds the first semiconductor layer 108 in a top view. In other words, the resist mask 112 is provided so as to cover the buffer layer 106, overlap the entire upper surface of the buffer layer 106, and so that the portion in contact with the second semiconductor layer 110 surrounds the buffer layer 106 in a top view.

[0032] Then, the second semiconductor layer 110 is etched through the resist mask 112. The etching may be dry etching or wet etching. For dry etching, chlorine-based dry etching may be used. By etching, the portion not covered by the resist mask 112 is removed. As a result, a portion of the second semiconductor layer 110 that has relatively low crystallinity and does not overlap with the buffer layer 106 remains, and this remaining portion is shaped into a shape that surrounds at least a part or the entire first semiconductor layer 108 in a plane perpendicular to the up-down direction (FIG. 6B). Then, the resist mask 112 is removed, thereby obtaining the stacked structure 100 shown in FIGS. 1A and 1B.

[0033] As described above, the first semiconductor layer 108 has higher crystallinity than the second semiconductor layer 110, and therefore has higher etching resistance than the second semiconductor layer 110. Therefore, when the resist mask 112 is formed so that a part of the first semiconductor layer 108 is exposed and the first semiconductor layer 108 is also etched, harsher etching conditions and a longer etching time are required, and damage such as side etching may occur in the first semiconductor layer 108.

[0034] In contrast, in a method for fabricating a stacked layer structure 100 according to one embodiment of the present invention, etching is performed through a resist mask 112 that covers not only the first semiconductor layer 108 but also the surrounding second semiconductor layer 110, leaving the second semiconductor layer 110 so as to surround at least a portion or all of the first semiconductor layer 108. In other words, only the second semiconductor layer 110 is removed by etching. This allows optimal mild conditions to be selected for etching the second semiconductor layer 110, thereby minimizing damage. As a result, a stacked layer structure 100 containing a gallium nitride-based material with precisely controlled structure and properties can be fabricated.

[0035] Second Embodiment In this embodiment, a semiconductor device including the stacked structure 100 described in the first embodiment will be described. Descriptions of configurations that are the same as or similar to those described in the first embodiment may be omitted.

[0036] There are no particular restrictions on the semiconductor device including the laminated structure 100, and examples include transistors (thin film transistors, power transistors), light-emitting elements including laser elements, photosensors including image sensors, solar cells, various diodes including constant voltage diodes and variable capacitance diodes, and piezoelectric elements.

[0037] As an example, FIG. 7A shows a schematic top view of a transistor 120 including the stacked structure 100, and FIG. 7B shows a schematic end view taken along the dashed line BB′ in FIG. 7A . When the stacked structure 100 is used in a transistor, a portion of the first semiconductor layer 108 of the stacked structure 100 functions as an active layer (channel). As shown in these figures, the transistor 120 includes the stacked structure 100, which is provided directly or via an undercoat 104 on a substrate 102 and includes a buffer layer 106, a first semiconductor layer 108, and a second semiconductor layer 110; a gate insulating film 122 on the stacked structure 100; a gate electrode 124 overlapping the stacked structure 100 via the gate insulating film 122; an interlayer insulating film 126 covering the gate insulating film 122; and source / drain electrodes 128 electrically connected to the first semiconductor layer 108 through openings in the interlayer insulating film 126. Although not shown, the transistor 120 may further include a protective insulating film covering the source / drain electrodes 128 and the interlayer insulating film 126. 7A and 7B is a so-called top-gate transistor. Although not shown, the transistor 120 may be a bottom-gate transistor or a dual-gate transistor having a pair of gate electrodes above and below the stacked structure 100.

[0038] Due to the wide band gap, high breakdown field, and high saturated drift velocity of gallium nitride-based materials, a transistor 120 including the stacked structure 100 is expected to exhibit excellent characteristics, particularly as a power transistor. Furthermore, by applying a method for manufacturing the stacked structure 100, which is one embodiment of the present invention, the structure and characteristics of the stacked structure 100 can be precisely controlled, making it possible to realize a transistor 120 with controlled characteristics. In addition, by forming the stacked structure 100 by sputtering on a substrate 102 containing amorphous glass, a semiconductor device including the stacked structure 100 can be provided at low cost.

[0039] As another example, a schematic end view of an electroluminescent light-emitting element 130 including the stacked structure 100 is shown in FIG. 8A. The light-emitting element 130 includes a lower electrode 132, the stacked structure 100 on the lower electrode 132, and an upper electrode 136 on the stacked structure 100. The light-emitting element 130 may further include an insulating film 134 that covers the edge of the stacked structure 100. In this case, if the buffer layer 106 is conductive, the buffer layer 106 also functions as an electrode together with the lower electrode 132.

[0040] The first semiconductor layer 108 and the second semiconductor layer 110 of the stacked structure 100 have a stacked structure suitable for recombining charges injected from the lower electrode 132 and the upper electrode 136 and converting them into photons. For example, the first semiconductor layer 108 and the second semiconductor layer 110 may be composed of semiconductor layers 108-1 and 110-1 containing a gallium nitride-based material with p-type conductivity, semiconductor layers 108-3 and 110-3 containing a gallium nitride-based material with n-type conductivity, and semiconductor layers 108-2 and 110-2 containing intrinsic gallium nitride or a gallium nitride-based material containing one or more elements selected from indium, aluminum, phosphorus, arsenic, and the like. In this configuration, the semiconductor layers 108-1 and 110-1 function as electron transport layers or hole transport layers, the semiconductor layers 108-3 and 110-3 function as hole transport layers or electron transport layers, and the semiconductor layers 108-2 and 110-2 function as light-emitting layers. Holes are injected from the lower electrode 132 through the semiconductor layers 108-1 and 110-1. Meanwhile, electrons are injected from the upper electrode 136 through the semiconductor layers 108-3 and 110-3. The electrons and holes combine in the semiconductor layers 108-2 and 110-2 to form an excited state, and light is emitted when this returns to the ground state.

[0041] In FIG. 8A , the lower electrode 132 is provided to overlap and contact the second semiconductor layer 110. Therefore, if the lower electrode 132 has the function of promoting crystallization of the layer containing a gallium nitride-based material, it is preferable to provide a wiring 138 on the substrate 102 and form an insulating film 140 thereon, as shown in FIG. 8B . The insulating film 140 may be formed of, for example, polyimide, acrylic resin, epoxy resin, or polysiloxane resin. An opening reaching the wiring 138 is provided in the insulating film 140, and the buffer layer 106 is formed to cover this opening. This allows the second semiconductor layer 110 to be provided on the insulating film 140, which does not have the function of promoting its crystallization, thereby selectively improving the crystallinity of only the first semiconductor layer 108. The wiring 138 may be electrically connected to a semiconductor element, such as a transistor, provided on the substrate 102. This allows the transistor to switch the light-emitting element 130 on and off.

[0042] Organic electroluminescent elements are known as electroluminescent light-emitting elements. Organic electroluminescent elements contain organic compounds in the electron transport layer, hole transport layer, and light-emitting layer, and therefore deteriorate relatively quickly. On the other hand, inorganic compounds such as gallium nitride-based materials deteriorate at a negligible rate compared to organic compounds. Therefore, by utilizing the light-emitting element 130, various highly reliable light-emitting devices and display devices can be obtained. Furthermore, by applying the method for fabricating the stacked structure 100, which is one embodiment of the present invention, the structure and characteristics of the stacked structure 100 can be precisely controlled, making it possible to realize a light-emitting element 130 with controlled characteristics, as well as a light-emitting device and a display device including the same.

[0043] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, a display device in which a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions, based on the display device of each embodiment, is also included in the scope of the present invention as long as it includes the gist of the present invention.

[0044] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0045] 100: stacked structure, 102: substrate, 104: undercoat, 105: semiconductor layer, 106: buffer layer, 108: first semiconductor layer, 108-1: semiconductor layer, 108-2: semiconductor layer, 108-3: semiconductor layer, 108-4: semiconductor layer, 110: second semiconductor layer, 112: resist mask, 120: transistor, 122: gate insulating film, 124: gate electrode, 126: interlayer insulating film, 128: drain electrode, 130: light emitting element, 132: lower electrode, 134: insulating film, 136: upper electrode, 138: wiring, 140: insulating film

Claims

1. a buffer layer and a first semiconductor layer that overlap each other in a vertical direction; a second semiconductor layer that is in contact with a side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the up-down direction; and an insulating film located on the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer and the second semiconductor layer; each of the first semiconductor layer and the second semiconductor layer comprises a Group III-V material or a Group III-nitride material; the crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer; the buffer layer is exposed from the second semiconductor layer in the vertical direction; The insulating film has a pair of through holes exposing the first semiconductor layer.

2. The stacked structure according to claim 1 , wherein the buffer layer and the second semiconductor layer do not overlap in the vertical direction.

3. The stacked structure according to claim 1 , wherein the second semiconductor layer is in contact with a side surface of the buffer layer.

4. The stacked structure according to claim 1 , wherein the second semiconductor layer surrounds the entire first semiconductor layer in the plane.

5. The stacked structure according to claim 1 , wherein a side surface of the second semiconductor layer that is separated from the first semiconductor layer is inclined with respect to the up-down direction.

6. The stacked structure of claim 5 , wherein the thickness of the second semiconductor layer decreases with increasing distance from the first semiconductor layer in the plane.

7. The stacked structure according to claim 5 , wherein the thickness of the second semiconductor layer increases with increasing distance from the first semiconductor layer in the plane.

8. A stacked structure having a buffer layer and a first semiconductor layer overlapping each other in a vertical direction, a second semiconductor layer in contact with a side surface of the first semiconductor layer and surrounding at least a part of the first semiconductor layer in a plane perpendicular to the vertical direction, and an insulating film located on the first semiconductor layer and in contact with the first semiconductor layer; a pair of source / drain electrodes located on the stacked structure and electrically connected to the first semiconductor layer via the insulating film; and a gate electrode on the stacked structure; each of the first semiconductor layer and the second semiconductor layer comprises a Group III-V material or a Group III-nitride material; the crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer; The buffer layer is exposed from the second semiconductor layer in the vertical direction.

9. The semiconductor device according to claim 8 , wherein the buffer layer and the second semiconductor layer do not overlap in the vertical direction.

10. The semiconductor device according to claim 8 , wherein the second semiconductor layer is in contact with a side surface of the buffer layer.

11. The semiconductor device according to claim 8 , wherein said second semiconductor layer surrounds said first semiconductor layer entirely in said plane.

12. The semiconductor device according to claim 8 , wherein a side surface of said second semiconductor layer that is separated from said first semiconductor layer is inclined with respect to the up-down direction.

13. The semiconductor device according to claim 12 , wherein the thickness of said second semiconductor layer decreases as the distance from said first semiconductor layer in said plane increases.

14. The semiconductor device according to claim 12 , wherein the thickness of said second semiconductor layer increases as the distance from said first semiconductor layer in said plane increases.

15. forming a buffer layer on a substrate; forming a semiconductor layer containing gallium nitride on the buffer layer so as to cover the buffer layer; etching the semiconductor layer; The semiconductor layer is etched to leave a first portion that overlaps with the buffer layer in the vertical direction and a second portion that does not overlap with the buffer layer.

16. The manufacturing method according to claim 15 , wherein the semiconductor layer is etched so that the second portion surrounds the first portion in a plane perpendicular to the up-down direction.

17. The manufacturing method according to claim 15 , wherein the semiconductor layer is formed by a sputtering method.

18. The manufacturing method according to claim 15 , wherein the semiconductor layer is etched so that a side surface of the semiconductor layer is inclined from the vertical direction.

Images