Semiconductor Devices

Abstract

To provide a technology capable of securing a desired ESD resistance without breakage of an inner circuit such as a level shifter circuit prior to breakage of an ESD protection circuit.SOLUTION: Provided is a semiconductor device in which an input-output cell, an IO power supply cell, a core power supply cell, and a core logic circuit are arranged on a chip. The core power supply cell includes an ESD protection circuit. The input-output cell includes a level shifter circuit. The level shifter circuit is arranged in the input-output cell. The core logic circuit is arranged outside the input-output cell. The core power supply cell is not arranged on the same row as the input-output cell and is arranged in a third region between a first region where the input-output cell and the IO power supply cell are arranged and a second region where the core logic circuit is arranged.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and is a technique that is effective when applied to a semiconductor device having an ESD (Electro-Static-Discharge) protection circuit. [Background technology]

[0002] As disclosed in Japanese Patent Application Laid-Open No. 2020-161721, there is a semiconductor device in which a signal input to an input / output pad electrode from outside the semiconductor device is transferred to an internal circuit via an input / output cell including an ESD protection element (also called an ESD protection circuit) and an input logic circuit, and a level shift circuit. Also, as disclosed in International Publication No. 2016 / 203648, there is a semiconductor device in which input / output cells and power supply cells are arranged in an IO region provided along the edge of the periphery of a semiconductor chip, and an internal circuit is provided in a central region surrounded by the IO region of the semiconductor chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-161721 [Patent Document 2] International Publication No. 2016 / 203648 Summary of the Invention [Problem to be solved by the invention]

[0004] When a semiconductor device is tested by applying an ESD surge, the level shifter circuit may be destroyed before the ESD protection circuit.

[0005] An object of the present disclosure is to provide a technology capable of ensuring a desired ESD resistance without causing internal circuits such as a level shifter circuit to break down before an ESD protection circuit does.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] According to one embodiment of the present disclosure, there is provided a semiconductor device having input / output cells, IO power supply cells, core power supply cells, and a core logic circuit arranged on a chip, wherein the core power supply cells include an ESD protection circuit. The input / output cells include a level shifter circuit, and the level shifter circuit is arranged within the input / output cells. The core logic circuit is arranged outside the input / output cells. The core power supply cells are not arranged in the same row as the input / output cells, but are arranged in a third region between a first region in which the input / output cells and IO power supply cells are arranged and a second region in which the core logic circuit is arranged. [Effects of the Invention]

[0009] According to the semiconductor device according to the above embodiment, the internal circuits such as the level shifter circuit are not destroyed before the ESD protection circuit is destroyed, and the desired ESD resistance can be ensured. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic block diagram of a semiconductor device according to a comparative example. [Figure 2] FIG. 2 is a schematic layout diagram of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic block diagram of a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a schematic layout diagram of the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic plan view of a semiconductor chip on which the semiconductor device of FIG. 3 is formed. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments and examples will be described with reference to the drawings. However, in the following description, the same components will be assigned the same reference numerals, and repeated description may be omitted. Note that the drawings may be more schematic than the actual embodiment to make the description clearer, but they are merely examples and do not limit the interpretation of the present invention.

[0012] (Embodiment) Before describing embodiments and examples of the present disclosure, in order to facilitate understanding of the present disclosure, a semiconductor device according to a technique (hereinafter referred to as a comparative example) studied by the present inventors will be described with reference to Figures 1 and 2. Figure 1 is a schematic block diagram of the semiconductor device according to the comparative example. Figure 2 is a schematic layout diagram of the semiconductor device of Figure 1.

[0013] The semiconductor device 10S includes input / output cells (IOC) 11, first power supply cells (IO power cells IOPC) 12 (IO power cell 12A, IO power cell 12B), and second power supply cells (core power cells CPC) 13 (core power cell 13A, core power cell 13B) on the periphery of a rectangular semiconductor chip such as monocrystalline silicon. The region where the input / output cells 11 and power supply cells 12 and 13 are arranged is called the IO region. The IO region is provided along the four sides of the chip edge of the semiconductor chip in a plan view. The semiconductor device 10S also includes an internal circuit 14 serving as a core logic circuit (CORE-LOG). The core logic region where the internal circuit 14 is arranged is the central part of the semiconductor chip and is surrounded by the IO region.

[0014] The input / output cell 11 is a formation region of an input / output circuit connected to one input / output pad. The power supply cells 12 and 13 are formation regions of ESD protection circuits (CESD, ESD) that protect the semiconductor device from ESD (Electro-Static-Discharge) and noise, and wiring that supplies power supply potentials (VDDIO, VDD) or ground potentials (VSSIO, VSS) to the inside of the chip. Since it is necessary to uniformly reduce the power supply impedance, the power supply cells 12 and 13 are arranged in a dispersed manner for each of the plurality of input / output cells 11, and are arranged adjacent to and between the input / output cells 11.

[0015] The power supply potentials (VDDIO, VDD) include a first power supply potential VDDIO of the I / O cells 11 and a second power supply potential VDD of the internal circuit 14. Similarly, the ground potentials (VSSIO, VSS) include a first ground potential VSSIO of the I / O cells 11 and a second ground potential VSS of the internal circuit 14. The first power supply potential VDDIO can be a potential greater than the second power supply potential VDD (VDDIO>VDD). The first power supply potential VDDIO, the first ground potential VSSIO, the second power supply potential VDD, and the second ground potential VSS are supplied to the I / O cells 11 via power supply wiring. The second power supply potential VDD and the second ground potential VSS are supplied to the internal circuit 14 via power supply wiring.

[0016] The IO power supply cell 12A includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first power supply potential VDDIO to the power supply wiring. The IO power supply cell 12B includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first ground potential VSSIO to the power supply wiring (also called ground wiring).

[0017] The core power supply cell 13A includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second power supply potential VDD to the power supply wiring. The core power supply cell 13B includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second ground potential VSS to the power supply wiring (also called ground wiring).

[0018] The ESD protection circuit (ESD) is connected between a power supply wiring supplied with a first power supply potential VDDIO and a power supply wiring supplied with a first ground potential VSSIO. The ESD protection circuit (CESD) is connected between a power supply wiring supplied with a second power supply potential VDD and a power supply wiring supplied with a second ground potential VSS.

[0019] The bridge circuit 15 is connected between a power supply wiring supplied with a first ground potential VSSIO and a power supply wiring supplied with a second ground potential VSS, and includes a pair of bidirectional diodes connecting the power supply wiring supplied with the first ground potential VSSIO and the power supply wiring supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring supplied with the first ground potential VSSIO.

[0020] The input / output cell 11 incorporates an input / output circuit connected to an input / output terminal (TIO). The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are respectively arranged on the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13, but may be arranged away from the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13. The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are connected to bonding wires or the like, and are also referred to as input / output pads, power supply pads, and ground pads, respectively.

[0021] The input / output circuit constituting the input / output cell 11 includes diodes D1 and D2 constituting an ESD protection circuit, an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmits an output signal to a signal wiring connected to the input / output terminal TIO, an input / output logic circuit IOL including a CMOS inverter that receives an input signal input from the input / output terminal TIO via the signal wiring, and a level shifter circuit LSC. The input signal input from the input / output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input / output logic circuit IOL, where it is level-converted and supplied to the internal circuit 14. Meanwhile, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, where it is level-converted and supplied to the input / output logic circuit IOL, and then output as an output signal from the output circuit including the P-channel transistor Q1 and the N-channel transistor Q2 to the input / output terminal TIO.

[0022] The P-channel transistor Q1 is connected between the power supply wiring of the first power supply potential VDDIO and the signal wiring from the input / output terminal TIO, and the N-channel transistor Q2 is connected between the signal wiring and the ground wiring of the first ground potential VSSIO. The anode of the diode D1 is connected to the signal wiring from the input / output terminal TIO, and the cathode is connected to the power supply wiring of the first power supply potential VDDIO. The anode of the diode D2 is connected to the ground wiring of the first ground potential VSSIO, and the cathode is connected to the signal wiring from the input / output terminal TIO. The diode D1 flows a surge current from the input / output terminal TIO toward the power supply terminal VDDIO via the signal wiring and the power supply wiring of the first power supply potential VDDIO, and the diode D2 flows a surge current from the ground terminal TVDDIO toward the input / output terminal TIO via the ground wiring of the first ground potential VSSIO and the signal wiring. The output circuit may be a so-called open-drain type that does not have the P-channel transistor Q1. Furthermore, the input / output circuit may not have either the output circuit or the input circuit.

[0023] The power supply cells 12A and 13A have ESD protection circuits (CESD, ESD) corresponding to the power supply terminals (TVDDIO, TVDD), and the power supply cells 12B and 13B have ESD protection circuits (CESD, ESD) corresponding to the ground terminals (TVSSIO, TVSS).

[0024] The first power supply potential VDDIO is, for example, 1.8V (or 3.3V), and the second power supply potential VDD is, for example, 0.8V.

[0025] When the first power supply potential VDDIO is 1.8V and the second power supply potential VDD is 0.8V, 1) The output circuit transistors Q1 and Q2 and the input / output logic circuit IOL are composed only of MOSFETs with a withstand voltage of 1.8V (also called 1.8V-MOS). 2) The internal circuit 14 is composed only of MOSFETs (also called core MOS) that have a withstand voltage of 0.8V. 3) The level shifter circuit LSC is configured by mixing 1.8V-MOS and core MOS. 4) The core power supply cells 13A and 13B protect the core MOS of the internal circuit 14 and the core MOS of the level shifter circuit LSC. 5) The IO power supply cells 12A and 12B protect the transistors Q1 and Q2 of the output circuit and the 1.8V-MOS of the input / output logic circuit IOL.

[0026] 2 shows the layout relationship between IO power supply cells 12A and 12B, two input / output cells 11, and core power supply cells 13A and 13B arranged in the IO region, and the internal circuit 14 arranged in the core logic region. In Fig. 2, MOS transistors T1 and T2 indicate transistors that constitute the ESD protection circuit (CESD), and MOS transistors T3 and T4 indicate transistors that constitute the ESD protection circuit (ESD). As shown in Fig. 2, IO power supply cells 12A and 12B, two input / output cells 11, and core power supply cells 13A and 13B are arranged in this order in the IO region, and the internal circuit 14 is arranged adjacent to the IO region above the IO region.

[0027] In response to an ESD surge between the power supply terminal TVDD and the ground terminal TVSS in Figure 1, an ESD current flows as indicated by the ESD current Iesd. This makes the level shifter circuit LSC, which is relatively smaller than the core logic circuit, which is the internal circuit 14, more susceptible to damage. This is because the resistance of the wiring in the portion indicated by R within the core power supply cells (13A, 13B) deteriorates.

[0028] In the 7nm generation, due to the effects of a decrease in core MOS tolerance and the deterioration of wiring resistance in the core power cells (13A, 13B), the level shifter circuit LSC breaks down before the ESD protection circuit (CESD) in the cell layout method shown in Figure 2. As a result, there was an issue that it was not possible to achieve the ESD tolerance level (Human Body Model (HBM): 2kV) required for automotive products.

[0029] A semiconductor device 10 of the present disclosure is a semiconductor device in which input / output cells 11, IO power supply cells 12 (12A, 12B), core power supply cells 13 (13A, 13B), and a core logic circuit 14 are arranged on a semiconductor chip (101). The core power supply cells 13 (13A, 13B) include an ESD protection circuit (CESD).

[0030] The input / output cell 11 includes a level shifter circuit LSC, and the level shifter circuit LSC is disposed within the input / output cell 11.

[0031] The core logic circuit 14 is arranged outside the input / output cell 11 .

[0032] The core power supply cells 13 (13A, 13B) are It is not arranged in the same row as the input / output cell 11, The input / output cells 11 and the IO power supply cells 12 (12A, 12B) are arranged in a third region (13R) between a first region (IO region IOR) and a second region (central region CER) of the core logic circuit 14.

[0033] In addition, the core power supply cells 13 (13A, 13B) The long side B2 of the external dimensions is formed shorter than the long side B1 of the external dimensions of the IO power cell 12 (12A, 12B) (B2 <B1)、 The short side A2 of the external dimension is equal to or greater than the short side A1 of the external dimension of the IO power cell 12 (12A, 12B) (A2≧A1).

[0034] In addition, the core power supply cells 13 (13A, 13B) It is not placed between the input / output cell 11 and the core logic circuit 14, The power supply cells 12 for IO (12A, 12B) are arranged in the fourth region (13RR) between the core logic circuit 14.

[0035] As a result, the semiconductor device can ensure a desired ESD resistance without causing internal circuits such as the level shifter circuit LSC to break down before the ESD protection circuit (CESD) does.

[0036] In cutting-edge 7nm generation CMOS technology, this technology ensures the desired ESD resistance without damaging vulnerable internal circuits (e.g., level shifter circuits LSC) before the protection circuits do. In particular, it reliably achieves the HBM 2kV required for automotive semiconductor products. [Example]

[0037] Next, a semiconductor device 10 according to an embodiment will be described with reference to FIGS. 3 to 5. FIG. 3 is a schematic block diagram of the semiconductor device according to the embodiment. FIG. 4 is a schematic layout diagram of the semiconductor device of FIG. 3. FIG. 5 is a schematic plan view of a semiconductor chip on which the semiconductor device of FIG. 3 is formed. In FIG. 5, the layout diagram of the area enclosed by the dotted line indicated by V is shown.

[0038] As shown in FIG. 5, a semiconductor device 10 includes input / output cells (IOC) 11, first power supply cells (IOPC) 12 (IO power supply cells 12A and 12B), and second power supply cells (core CPC) 13 (core power supply cells 13A and 13B) on the periphery of a rectangular semiconductor chip 101 made of, for example, monocrystalline silicon. The region in which the input / output cells 11 and power supply cells 12 are arranged is referred to as an IO region IOR. The IO region IOR is provided along four sides 21, 22, 23, and 24 of the chip edge of the semiconductor chip 101 in a plan view. The four sides 21, 22, 23, and 24 include a first side 21, a third side 23 provided opposite the first side 21, a second side 22 provided between the first side 21 and the third side 23, and a fourth side 24 provided opposite the second side 22.

[0039] The semiconductor device 10 also includes an internal circuit 14 serving as a core logic circuit (CORE-LOG). A core logic region (also referred to as a central region or second region) CER in which the internal circuit 14 is arranged is provided in the central portion of the semiconductor chip 101. Second power supply cells (core power supply cells CPC) 13 (core power supply cell 13A, core power supply cell 13B) are arranged in a region (also referred to as a third region) 13R between the core logic region CER and the IO region IOR.

[0040] Fig. 3 shows a schematic block diagram of a semiconductor device 10 according to an embodiment. The semiconductor device 10 of Fig. 3 differs from the semiconductor device 10S of Fig. 1 in that the core power supply cells 13A and 13B are not provided within the array of the input / output cells (IOC) 11 and the first power supply cells (IO power cells IOPC) 12, but are provided on the side of the internal circuit 14. Furthermore, in this example, the core power supply cells 13A and 13B are not provided with a bridge circuit 15.

[0041] 3 are the same as those in Fig. 1, and therefore will not be described again. That is, the description of Fig. 1 can be used and referred to for the description of the circuit configuration, operation, and connection of the input / output cell 11, the IO power supply cell 12A, the IO power supply cell 12B, the core power supply cell 13A, and the core power supply cell 13B.

[0042] 3 and 4, the semiconductor device 10 is provided with an input / output terminal TIO, a first power supply terminal TVDDIO, a second power supply terminal TVDD, a first ground terminal TVSSIO, and a second ground terminal TVSS. A first power supply potential VDDIO is supplied to the first power supply terminal TVDDIO. A second power supply potential VDD is supplied to the second power supply terminal TVDD. A first ground potential VSSIO is supplied to the first ground terminal TVSSIO. A second ground potential VSS is supplied to the second ground terminal TVSS.

[0043] In the IO region IOR, a first power supply wiring 31, a second power supply wiring (also referred to as first ground wiring) 32, a third power supply wiring 33, and a fourth power supply wiring (also referred to as second ground wiring) 34 are provided along a first direction X. A first power supply potential VDDIO is supplied to the first power supply wiring 31 from a first power supply terminal TVDDIO. A first ground potential VSSIO is supplied to the second power supply wiring (first ground wiring) 32 from a first ground terminal TVSSIO. A second power supply potential VDD is supplied to the third power supply wiring 33 from a second power supply terminal TVDD. A second ground potential VSS is supplied to the fourth power supply wiring (second ground wiring) 34 from a second ground terminal TVSS.

[0044] The core logic area CER is provided with a fifth power supply wiring 35 and a sixth power supply wiring 36 provided along a first direction X, and a seventh power supply wiring 37 and an eighth power supply wiring 38 provided along a second direction Y intersecting the first direction X. The fifth power supply wiring 35 is connected to a second power supply terminal TVDD, and the sixth power supply wiring 36 is connected to a second ground terminal TVSS. The fifth power supply wiring 35 and the seventh power supply wiring 37 are electrically connected, and a second power supply potential VDD is supplied from the second power supply terminal TVDD. The sixth power supply wiring 36 and the eighth power supply wiring 38 are electrically connected, and a second ground potential VSS is supplied from the second ground terminal TVSS.

[0045] The seventh power supply wiring 37 and the eighth power supply wiring 38 are also arranged in the region 13R and connected to the third power supply wiring 33 and the fourth power supply wiring 34 provided in the IO region IOR. The core power supply cell 13A and the core power supply cell 13B are connected between the seventh power supply wiring 37 and the eighth power supply wiring 38 arranged in the region 13R.

[0046] A first power supply potential VDDIO, a first ground potential VSSIO, a second power supply potential VDD, and a second ground potential VSS are supplied to the input / output cell 11. A second power supply potential VDD and a second ground potential VSS are supplied to the internal circuit 14.

[0047] The IO power supply cell 12A includes an ESD protection circuit (ESD) having a transistor T1 and a bridge circuit 15, and supplies a first power supply potential VDDIO to the power supply wiring 31. The IO power supply cell 12B includes an ESD protection circuit (ESD) having a transistor T2 and a bridge circuit 15, and supplies a first ground potential VSSIO to the power supply wiring 32.

[0048] The ESD protection circuit (ESD) is connected between a power supply wiring 31 supplied with a first power supply potential VDDIO and a power supply wiring 32 supplied with a first ground potential VSSIO.

[0049] The bridge circuit 15 is connected between the power supply wiring 32 supplied with the first ground potential VSSIO and the power supply wiring 34 supplied with the second ground potential VSS, and includes a pair of bidirectional diodes that connect the power supply wiring 32 supplied with the first ground potential VSSIO to the power supply wiring 34 supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring 34 supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring 34 supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO.

[0050] The core power cell 13A includes an ESD protection circuit (CESD) having a transistor T3, and the core power cell 13B includes an ESD protection circuit (CESD) having a transistor T4. The core power cell 13A and the core power cell 13B protect the internal circuit 14 from ESD and noise. The source-drain paths of the transistors T3 and T4 are connected between the seventh power supply wiring 37 and the eighth power supply wiring 38 arranged in the region 13R.

[0051] The input / output cell 11 incorporates an input / output circuit connected to an input / output terminal (TIO). The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are respectively arranged on the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13, but may be arranged away from the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13. The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are connected to bonding wires or the like, and are also referred to as input / output pads, power supply pads, and ground pads, respectively.

[0052] The input / output circuit constituting the input / output cell 11 includes diodes D1 and D2 constituting an ESD protection circuit, an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmits an output signal to a signal wiring connected to the input / output terminal TIO, an input / output logic circuit IOL including a CMOS inverter that receives an input signal input from the input / output terminal TIO via the signal wiring, and a level shifter circuit LSC. The input signal input from the input / output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input / output logic circuit IOL, where it is level-converted and supplied to the internal circuit 14. Meanwhile, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, where it is level-converted and supplied to the input / output logic circuit IOL, and then output as an output signal from the output circuit including the P-channel transistor Q1 and the N-channel transistor Q2 to the input / output terminal TIO.

[0053] The P-channel transistor Q1 is connected between a power supply wiring 31 of the first power supply potential VDDIO and a signal wiring from the input / output terminal TIO, and the N-channel transistor Q2 is connected between the signal wiring and a ground wiring 32 of the first ground potential VSSIO. The anode of the diode D1 is connected to the signal wiring from the input / output terminal TIO, and the cathode is connected to the power supply wiring 31 of the first power supply potential VDDIO. The anode of the diode D2 is connected to the ground wiring 32 of the first ground potential VSSIO, and the cathode is connected to the signal wiring from the input / output terminal TIO. The diode D1 flows a surge current from the input / output terminal TIO through the signal wiring and the power supply wiring 31 of the first power supply potential VDDIO toward the power supply terminal VDDIO, and the diode D2 flows a surge current from the ground terminal TVDDIO through the ground wiring 32 of the first ground potential VSSIO and the signal wiring toward the input / output terminal TIO. The output circuit may be a so-called open-drain type that does not have the P-channel transistor Q1. Furthermore, the input / output circuit does not necessarily have to include either the output circuit or the input circuit.

[0054] 3, the internal circuit 14, the core power supply cell 13A, and the core power supply cell 13B are connected between the power supply wiring (35, 37, see FIG. 4) to which the second power supply potential VDD is supplied from the power supply terminal TVDD and the ground wiring (36, 38, see FIG. 4) to which the second ground potential VSS is supplied from the ground terminal TVSS. As shown in FIG. 3, the core power supply cell 13A and the core power supply cell 13B are not arranged in the same row as the input / output cell 11, thereby preventing an increase in the wiring resistance within the cell.

[0055] 4, input / output cells 11, IO power supply cells 12A, and IO power supply cells 12B are arranged in an IO region IOR. In this example, the IO power supply cells 12A and 12B are arranged on both sides of the input / output cell 11. The internal circuit 14 is arranged in a core logic region CER. The core power supply cells 13A and 13B are arranged in a region 13R between the core logic region CER and the IO region IOR. The core power supply cells 13A and 13B are also arranged in a region (also referred to as a fourth region) 13RR between the core logic region CER and the IO power supply cells 12A and 12B.

[0056] The power supply terminal TVDD is connected to a power supply wiring 35 of a second power supply potential VDD arranged in the internal circuit 14. The ground terminal TVSS is configured to be connected to a ground wiring 36 of a second ground potential VSS arranged in the internal circuit 14.

[0057] Here, the features of the example of the layout arrangement in FIG. 4 will be described.

[0058] The long side B2 of the outer shape of the core power cell 13 (13A, 13B) can be the side of the core power cell 13 (13A, 13B) along the direction of the source-drain paths (or gate length direction) of the transistors T3, T4 of the core power cell 13 (13A, 13B). The short side A2 of the outer shape of the core power cell 13 (13A, 13B) can be the side of the core power cell 13 (13A, 13B) along the direction (or gate width direction) perpendicular to the direction of the source-drain paths of the transistors T3, T4 of the core power cell 13 (13A, 13B).

[0059] Furthermore, the long side B1 of the outer shape of the IO power cell 12 (12A, 12B) can be the side of the IO power cell 12 (12A, 12B) along the direction of the source-drain paths (or gate length direction) of the transistors T1, T2 of the IO power cell 12 (12A, 12B). The short side A1 of the outer shape of the IO power cell 12 (12A, 12B) can be the side of the IO power cell 12 (12A, 12B) along the direction (or gate width direction) perpendicular to the direction of the source-drain paths of the transistors T1, T2 of the IO power cell 12 (12A, 12B).

[0060] 1) In order to avoid an increase in the wiring resistance within the core power cells 13 (13A, 13B), the core power cells 13 (13A, 13B) are not placed in the same row as the input / output cells 11, but are placed in a region (fourth region) 13RR between the formation region of the IO power cells 12 (12A, 12B) and the formation region of the internal circuit 14.

[0061] 2) The long side B2 of the outer shape of the core power cells 13 (13A, 13B) is smaller than the long side B1 of the IO power cells 12 (12A, 12B) (B2 <B1)。

[0062] 3) The short side A2 of the outer shape of the core power cells (13A, 13B) is equal to or greater than the short side A1 of the IO power cells 12 (12A, 12B) (A2≧A1).

[0063] 4) The core power supply cells 13 (13A, 13B) are not placed between the input / output cells 11 and the internal circuit 14. This improves the degree of freedom in the layout of the signal wiring SL between the level shifter circuit LSC and the internal circuit 14.

[0064] According to the semiconductor device of the embodiment, the internal circuit (e.g., the level shifter circuit LSC) that is vulnerable to electrostatic stress is not destroyed before the ESD protection circuit (CESD) is destroyed, and the desired ESD resistance can be ensured. In particular, the HBM 2kV required for in-vehicle semiconductor products can be reliably achieved.

[0065] The disclosure made by the present inventor has been specifically described above based on embodiments and examples, but it goes without saying that the present disclosure is not limited to the above embodiments and examples and can be modified in various ways. [Explanation of symbols]

[0066] 10: Semiconductor device 11: Input / output cell 12, 12A, 12B: IO power cells 13, 13A, 13B: Core power cells 14: Internal circuit IOR:IO area (first area) CER: Core logic area (central area, second area) 13R: Third area 13RR: 4th area ESD,CESD:ESD protection circuit

Claims

1. A semiconductor device in which input / output cells, IO power supply cells, core power supply cells, and a core logic circuit are arranged on a chip, the core power cell includes an ESD protection circuit; the input / output cell includes a level shifter circuit, the level shifter circuit being disposed within the input / output cell; the core logic circuit is arranged outside the input / output cell; The core power supply cell includes: are not arranged in the same row as the input / output cells, the third region is disposed between a first region in which the input / output cells and the IO power supply cells are disposed and a second region in which the core logic circuit is disposed; The core power supply cell includes: not disposed between the input / output cell and the core logic circuit, and disposing the power supply cells in a fourth region between the IO power supply cells and the core logic circuit. Semiconductor device.

2. 2. The semiconductor device of claim 1, The core power supply cell includes: The long side of the external dimension of the power supply cell for I / O is shorter than the long side of the external dimension of the power supply cell for I / O, The short side of the external dimension of the semiconductor device is equal to or greater than the short side of the external dimension of the IO power supply cell.

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