Trench-type power devices with improved reliability and continuity

Abstract

The power semiconductor device includes a semiconductor layer structure including a drift region 220 of a first conductivity type and a well region 270 of a second conductivity type, a plurality of gate trenches 280 extending into the drift region and including respective gate insulating layers 282 and gate electrodes 284 therein, respective shield patterns 240 of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction promoting regions 250 of the first conductivity type in respective portions of the drift region. The drift region includes a first concentration of dopants of the first conductivity type and each conduction promoting region includes a second concentration of dopants of the first conductivity type that is higher than the first concentration. Related devices and methods of manufacture are also discussed.

Description

[Technical Field]

[0001] This application claims priority from U.S. Patent Application No. 17 / 092,923, filed November 9, 2020, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices. [Background technology]

[0003] Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art, including, for example, power metal-insulator-semiconductor field-effect transistors ("MISFETs," including metal-oxide-semiconductor FETs ("MOSFETs")), bipolar junction transistors ("BJTs"), insulated-gate bipolar transistors ("IGBTs"), junction-barrier Schottky diodes, gate-turn-off transistors ("GTOs"), metal-oxide-semiconductor-controlled thyristors, and various other devices. These power semiconductor devices are typically fabricated from wide-bandgap semiconductor materials, such as, for example, silicon carbide ("SiC") or gallium nitride ("GaN")-based semiconductor materials. As used herein, wide bandgap semiconductor material refers to a semiconductor material having a bandgap greater than about 1.40 eV, for example, greater than about 2 eV.

[0004] A conventional power semiconductor device typically includes a semiconductor substrate having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer structure having the first conductivity type (e.g., n-type) is formed. A portion of this epitaxial layer structure (which may comprise one or more separate layers) serves as the drift layer or drift region of the power semiconductor device. The device typically includes an "active region" that includes one or more "unit cell" structures having junctions, such as p-n junctions. The active region may be formed on and / or within the drift region. The active region acts as a primary junction for blocking voltage in the reverse bias direction and conducting current in the forward bias direction. The power semiconductor device may also have an edge termination in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, with each power semiconductor device typically having its own edge termination. After the substrate is fully processed, the resulting structure can be diced to separate the individual edge-terminated power semiconductor devices.

[0005] Power semiconductor devices may have a unit cell configuration, which includes many individual "unit cell" structures where the active area of each power semiconductor device is electrically connected in parallel to function as a single power semiconductor device. In high-power applications, such power semiconductor devices may include thousands or tens of thousands of unit cells packaged on a single chip or "die." A die or chip may include a small block of semiconductor material or other substrate upon which electronic circuit elements are fabricated.

[0006] A power semiconductor device can have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain terminal, gate terminal, and source terminal for a power MOSFET device) are on the same major surface (e.g., the top surface or the bottom surface) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. As used herein, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers, e.g., a semiconductor substrate and / or a semiconductor epitaxial layer.

[0007] Vertical power semiconductor devices, including MOSFET transistors, can have a standard gate electrode design, in which the transistor's gate electrode is formed on top of a semiconductor layer structure, or alternatively, they may have the gate electrode recessed in a trench within the semiconductor layer structure. MOSFETs with a recessed gate electrode are commonly referred to as gated-trench MOSFETs. In a standard gate electrode design, the channel region of each unit cell transistor is located horizontally beneath the gate electrode. In contrast, in a gated-trench MOSFET design, the channel is located vertically. Gated-trench MOSFETs can offer improved performance but generally require a more complex manufacturing process.

[0008] Power semiconductor devices are designed to block (in forward or reverse blocking conditions) or pass (in forward operating conditions) large voltages and / or currents. For example, in blocking conditions, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. When the applied voltage approaches or exceeds the voltage level at which the device is designed to block, a non-negligible level of current (called leakage current) may begin to flow through the power semiconductor device. The blocking capability of a device may be a function of, among other things, the doping and thickness of the drift region. Leakage current may also arise for other reasons, such as failure of the edge termination and / or primary junction of the device. When the voltage applied to a device is increased to a critical level above the breakdown voltage, the increasing electric field may cause an uncontrolled and undesirable, ever-increasing generation of charge carriers within the semiconductor device, thereby causing a condition known as avalanche breakdown.

[0009] Additionally, the relatively thin gate insulating layer (e.g., gate oxide layer) that separates the gate electrode from the semiconductor layer structure can degrade when the gate insulating layer is exposed to high electric field levels during either on-state (conduction) or off-state (blocking) operation. This degradation of the gate insulating layer can ultimately lead to breakdown of the gate insulating layer, at which point the gate electrode may short to the semiconductor layer structure, potentially destroying the device. Summary of the Invention [Means for solving the problem]

[0010] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches extending into the drift region, respective shield patterns of the second conductivity type in respective portions of the drift region adjacent to the gate trenches, and respective conduction promotion regions of the first conductivity type in respective portions of the drift region. Each conduction promotion region extends into the well region adjacent to its respective shield pattern. The drift region includes a first concentration of dopants of the first conductivity type, and each conduction promotion region includes a second concentration of dopants of the first conductivity type that is higher than the first concentration.

[0011] In some embodiments, the gate trenches may be spaced apart from one another along a first direction, and the respective conduction promotion regions may be spaced apart from respective corners of the gate trenches along the first direction.

[0012] In some embodiments, each portion of the drift region between the gate trenches may include a concentration gradient of a dopant of the first conductivity type that varies between a first concentration and a second concentration along a first direction.

[0013] In some embodiments, the drift region may include a first concentration of dopant proximate each corner of the gate trench, and the second concentration may be about two or more times greater than the first concentration.

[0014] In some embodiments, in response to a voltage applied to the power semiconductor device, each portion of the drift region between the gate trenches may include an electric field distribution having a peak distal to each corner of the gate trench in a first direction.

[0015] In some embodiments, the peak of the electric field distribution may be about 10 times greater than the intensity of the electric field distribution proximate each corner of the gate trench.

[0016] In some embodiments, each conduction-facilitating region may be between gate trenches and may extend beyond the lower boundary of each shield pattern into the drift region.

[0017] In some embodiments, each conductivity promoting region may be offset from each shield pattern toward the gate trench.

[0018] In some embodiments, each conductivity promoting region may extend along both sides and the lower boundary of each shielding pattern.

[0019] In some embodiments, each conduction promotion region may extend along an axis that is not orthogonal to the surface of the drift region.

[0020] In some embodiments, the semiconductor layer structure may further include a current spreading layer including a third concentration of a dopant of the first conductivity type that is greater than the first and / or second concentration, and each portion of the drift region comprising each conduction facilitating region may be between the well region and the current spreading layer.

[0021] In some embodiments, the semiconductor layer structure may include a wide bandgap semiconductor, the drift region may be an epitaxial layer of a first conductivity type, and each conduction promoting region may be an implanted region of the first conductivity type.

[0022] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type, and a plurality of gate trenches extending into the drift region, the gate trenches being spaced apart from one another in a first direction, and respective portions of the drift region adjacent the gate trenches including a dopant of the first conductivity type at a concentration that varies along the first direction.

[0023] In some embodiments, the drift region may include respective conduction-facilitating regions of a first conductivity type spaced from respective corners of the gate trench along the first direction, and the concentration of dopant of the first conductivity type may include a first concentration proximate each corner of the gate trench and a second concentration in each conduction-facilitating region, the second concentration being greater than the first concentration.

[0024] In some embodiments, the concentration of dopants of the first conductivity type further comprises a concentration gradient of dopants of the first conductivity type between the first concentration and the second concentration along the first direction.

[0025] In some embodiments, the second concentration may be about two times or more greater than the first concentration.

[0026] In some embodiments, respective shield patterns of the second conductivity type may be provided in respective portions of the drift region between and / or below the gate trenches, and the respective conduction facilitating regions may be between the gate trenches and may extend beyond a lower boundary of the respective shield patterns into the drift region, the respective conduction facilitating regions may be offset from the respective shield patterns toward the gate trenches, and / or the respective conduction facilitating regions may extend along at least one of one side or a lower boundary of the respective shield patterns.

[0027] In some embodiments, in response to a voltage applied to the power semiconductor device, each portion of the drift region between the gate trenches may include an electric field distribution having a peak distal to each corner of the gate trench in a first direction.

[0028] In some embodiments, the peak of the electric field distribution may be about two times greater than the intensity of the electric field distribution proximate each corner of the gate trench.

[0029] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type, and a plurality of gate trenches extending into the drift region, wherein, in response to a voltage applied to the power semiconductor device, respective portions of the drift region between the gate trenches include an electric field distribution having peaks distal to respective corners of the gate trenches.

[0030] In some embodiments, the gate trenches may be spaced apart from one another in a first direction, and the electric field distribution in each portion of the drift region between the gate trenches may be asymmetric along the first direction.

[0031] In some embodiments, the peak of the electric field distribution may be about 10 times greater than the intensity of the electric field distribution proximate each corner of the gate trench.

[0032] In some embodiments, each portion of the drift region between the gate trenches includes a dopant of the first conductivity type at a concentration that varies along the first direction.

[0033] In some embodiments, each conduction-facilitating region of the first conductivity type may be spaced apart from a respective corner of the gate trench along the first direction, and a concentration of dopant of the first conductivity type may include a first concentration proximate each corner of the gate trench and a second concentration in each conduction-facilitating region, the second concentration being greater than the first concentration.

[0034] In some embodiments, the concentration of the dopant of the first conductivity type may further include a concentration gradient of the dopant of the first conductivity type between the first concentration and the second concentration along the first direction.

[0035] In some embodiments, the second concentration may be about 10 times or more greater than the first concentration.

[0036] In some embodiments, each conduction facilitating region may include a peak in the electric field distribution.

[0037] According to some embodiments, a method for fabricating a power semiconductor device includes forming a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type, forming respective conduction promoting regions of the first conductivity type in respective portions of the drift region, forming respective shield patterns of the second conductivity type in respective portions of the drift region, and forming a plurality of gate trenches in respective portions of the drift region extending into the drift region, each conduction promoting region extending into the well region adjacent a respective shield pattern, the drift region including a first concentration of dopant of the first conductivity type, and each conduction promoting region including a second concentration of dopant of the first conductivity type that is higher than the first concentration.

[0038] In some embodiments, the gate trenches may be spaced apart from one another along a first direction, and the respective conduction promotion regions may be spaced apart from respective corners of the gate trenches along the first direction.

[0039] In some embodiments, each portion of the drift region between the gate trenches may include a concentration gradient of a dopant of the first conductivity type that varies between a first concentration and a second concentration along a first direction.

[0040] In some embodiments, the semiconductor layer structure may include a wide bandgap semiconductor, the drift region may include an epitaxial layer of a first conductivity type, and each conduction promoting region may include an implanted region of the first conductivity type.

[0041] In some embodiments, the drift region may include a first concentration of dopant proximate each corner of the gate trench, and the second concentration may be about 10 times or more greater than the first concentration.

[0042] In some embodiments, each conduction-facilitating region may be between gate trenches and may extend beyond the lower boundary of each shield pattern into the drift region.

[0043] In some embodiments, each conduction facilitating region may be offset from the respective shield pattern toward the gate trench and / or each conduction facilitating region may extend along at least one of a side or lower boundary of the respective shield pattern.

[0044] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following figures and detailed description, and all such additional embodiments, in addition to any and all combinations of the above embodiments, are intended to be included herein, be within the scope of the present invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0045] [Figure 1A] 1 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device including a shield region blocking one side of the gate trench. [Figure 1B] 1 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device including alternating shield regions and gate trench regions. [Figure 2] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including a shielding region and aligned conduction promotion regions between the gate trenches according to some embodiments of the present invention. [Figure 3A] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 3B] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 3C] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 3D] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 3E] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 3F] 3A to 3C are schematic cross-sectional views illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 2. [Figure 4A] FIG. 3 is a graphical example of various p-type and n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. 2. [Figure 4B] FIG. 3 is a graphical example of various p-type and n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. 2. [Figure 4C] FIG. 3 is a graphical example of various p-type and n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. 2. [Figure 4D] FIG. 3 is a graphical example of various p-type and n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. 2. [Figure 5] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including a shielding region and an offset conduction promotion region between the gate trenches according to some embodiments of the present invention. [Figure 6A] 6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 6B] 6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 6C] 6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 6D] 6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 6E] 6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 6F]6 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 5. [Figure 7A] FIG. 6 is a graphical example of various n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. [Figure 7B] FIG. 6 is a graphical example of various n-type dopant concentrations in the JFET region of the gate trench power semiconductor device of FIG. [Figure 8] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including a shielding region and a sloped conduction-facilitating region between the gate trenches according to some embodiments of the present invention. [Figure 9A] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 9B] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 9C] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 9D] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 9E] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 9F] 9 is a schematic cross-sectional view illustrating an example of a process for fabricating the gate trench power semiconductor device of FIG. 8. [Figure 10A] FIG. 9 is a graphical example of the variation of dopant concentration in the JFET region of the gate trench power semiconductor device of FIG. 8. [Figure 10B] FIG. 9 is a graphical example of the variation of dopant concentration in the JFET region of the gate trench power semiconductor device of FIG. 8. [Figure 11A]1 is a graphical example of an electric field distribution in a gate trench power semiconductor device including a drift layer with reduced dopant concentration according to some embodiments of the present invention. [Figure 11B] 1 is a graphical example of an electric field distribution in a gate trench power semiconductor device including a drift layer with reduced dopant concentration according to some embodiments of the present invention. [Figure 12] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including a bottom shield region and an offset conduction promotion region between the gate trenches according to some embodiments of the present invention. [Figure 13A] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 13B] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 13C] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 13D] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 13E] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 13F] 1A-1C are schematic cross-sectional views illustrating an example process for fabricating a gate trench power semiconductor device including a bottom shield region. [Figure 14] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including alternating shielding regions and aligned conduction promoting regions between the gate trenches according to some embodiments of the present invention. [Figure 15] 1 is a schematic cross-sectional view illustrating an example of a gate trench power semiconductor device including a shielding region and an offset conduction facilitating region between gate trenches with a heavily doped current spreading layer or region according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0046] Some embodiments of the present invention are directed to improvements in power semiconductor devices (e.g., MOSFETs and other gate-controlled power devices). Many power semiconductor devices include so-called deep or "buried" shield semiconductor regions, also called shield patterns, of a different conductivity type than the layer of semiconductor material beneath the device's well region and / or gate electrode. For example, in devices having a gate electrode and gate insulating layer formed within a trench in the semiconductor layer structure, high electric fields can degrade the gate insulating layer over time, ultimately leading to device failure. Deep shield patterns can be provided beneath gate trenches to reduce electric field levels in the gate insulating layer, especially at the corners of the gate trenches where the electric field levels may be more concentrated. The deep shield patterns include a heavily doped semiconductor layer having the same conductivity type as the channel region.

[0047] Various approaches can be used to form trench vertical power semiconductor devices. Figures 1A and 1B show two examples of different approaches. While examples are described and illustrated herein with reference to regions of particular conductivity types (i.e., n-type and p-type), it is understood that the conductivity types of the regions in any of the illustrated examples may be reversed (i.e., p-type and n-type) according to embodiments of the present invention.

[0048] 1A and 1B are schematic cross-sectional views illustrating example trench vertical power devices (illustrated as power MOSFETs 100a and 100b) that include deeply buried P-type shield regions 140a and 140b. As shown in FIGS. 1A and 1B, the power MOSFETs 100a and 100b are each heavily doped (N + ) n-type substrate 110, for example a silicon carbide substrate. -An n-type drift layer or region 120 is provided on the substrate 110, for example, by epitaxial growth. In some embodiments, a portion of the n-type drift region 120 may include an n-type current spreading layer (“CSL”) having a higher dopant concentration than the upper portion of the drift region 120 (shown as layer 1530 in the example of FIG. 15 ). A moderately doped p-type layer is formed on the drift region 120 (for example, by epitaxial growth or implantation) to act as a p-type well region (or “P-well”) 170 for the devices 100 a, 100 b. The substrate 110, the drift region 120 (including the current spreading layer), and the moderately doped p-type layer defining the P-well 170, along with various regions / patterns formed therein, are included in the semiconductor layer structure 106 of the MOSFETs 100 a, 100 b.

[0049] 1A and 1B, trenches 180 are formed in the semiconductor layer structure 106 with a "striped" gate trench layout, where the trenches 180 extend continuously parallel to one another in the longitudinal direction and are spaced apart transversely to the longitudinal direction (e.g., perpendicular to the longitudinal direction). The trenches 180 (in which gate electrodes 184 are formed) extend through the moderately doped p-type layer 170 to define respective P-wells. For example, heavily doped (P + ) P-type shield patterns 140a, 140b are formed in the drift region 120. The deep shield patterns 140a, 140b may be electrically connected to the P-well 170. A gate insulating layer 182 is formed on the bottom and sidewalls of each trench 180 (FIG. 1A) or every other trench 180 (FIG. 1B, where source contacts 190b are formed in the intervening trenches 180).

[0050] A gate electrode 184 (or "gate") is formed on each gate insulating layer 182, filling the respective gate trench 180. A vertical transistor channel region (with conduction indicated by the dashed arrow) is defined adjacent the gate insulating layer 182 within the P well 170. A heavily doped n + A source region 160 is formed on top of the P-well 170, for example, by ion implantation. Source contacts 190a, 190b are formed on the heavily doped n-type source region 160 and on the deep shield patterns 140a, 140b. In some embodiments, the source contacts 190a, 190b may be ohmic metal. A drain contact 192 is formed on the underside of the substrate 110. A gate contact (not shown) may be formed on each gate electrode 184.

[0051] 1A and 1B, the deeply buried p-type semiconductor regions or shield patterns 140a, 140b are configured to prevent degradation of the trench MOSFETs 100a, 100b in high electric fields, but can also limit the active conductive area of the devices 100a, 100b. In particular, in the example devices 100a, 100b, the shield patterns 140a, 140b at the bottom and one side 178 (FIG. 1A) or both sides 178 (FIG. 1B) of the gate trench 180 are configured to provide voltage and / or current blocking by connection to respective source contacts 190a, 190b that are connected to ground. A shield connection pattern (not shown) can be connected to the source contacts 190 on the devices 100a, 100b to allow the deep shield patterns 140 to be electrically grounded.

[0052] 1A, the shield pattern 140a is offset toward the source contact 190 on one side of the trench 180 and extends to the lower corner regions of the gate trench 180. Because the gate insulating layer 182 may be particularly susceptible to breakdown in the corner regions, the shield pattern 140a may help protect the gate insulating layer 182 in the lower corner regions of the gate trench 180 from high electric fields during reverse blocking operation.

[0053] Embodiments of the present invention are directed to power semiconductor devices including layout and design configurations that further improve reliability by moving peak electric field distribution away from one or more regions of the device that are more susceptible to dielectric breakdown, such as portions of the gate insulation layer at the corners of the gate trenches. In some embodiments, this can be achieved by forming an upper portion of the drift region (also referred to herein as a "JFET region") below and / or adjacent to the gate electrode with a doping profile that varies along the direction in which adjacent gate electrodes are separated from one another. For example, in a trench-type vertical power semiconductor device, the JFET region can include an upper portion of the drift region between adjacent gate trenches and below the well region.

[0054] When trench vertical power devices are fabricated with silicon carbide or other wide-bandgap semiconductor materials, creating regions with varying doping characteristics can pose challenges. Methods for doping semiconductor materials with n-type and / or p-type dopants include (1) doping the semiconductor material during its growth, (2) diffusing dopants into the semiconductor material, and (3) selectively implanting dopants into the semiconductor material using ion implantation. When silicon carbide is doped during epitaxial growth, the dopants tend to accumulate nonuniformly, resulting in dopant concentrations that may vary (e.g., by ±15%), potentially adversely affecting device operation and / or reliability. Furthermore, doping by diffusion may be undesirable for silicon carbide, gallium nitride, and various wide-bandgap semiconductor devices because n-type and p-type dopants tend not to diffuse well (or at all) in these materials, even at high temperatures.

[0055] In some embodiments, high-energy ion implantation and / or other methods can be used to vary the respective dopant concentrations (e.g., with a non-uniform or asymmetric distribution) in the upper portions of the drift regions between the gate trenches along the lateral direction (referred to herein with reference to the x-direction) in which the gate trenches are spaced apart. The dopant concentrations or concentration gradients described herein can vary in a stepped or continuous (e.g., linear or exponential) manner laterally or along the lateral direction. Depending on the applied voltage, the variation in dopant concentration in the x-direction can result in an asymmetric electric field distribution between adjacent gate trenches. For example, during reverse blocking operation, the peak electric field distribution can be shifted away from the lower corners of the gate trenches. Accordingly, power MOSFETs and other gate-controlled devices according to embodiments of the present invention can exhibit improved reliability.

[0056] In some embodiments, the upper portion of the drift layer (including the JFET region) may be relatively lightly doped during epitaxial growth to reduce the doping concentration. For example, in an n-channel device, the JFET region is doped n-type. The portion of the JFET region adjacent to the gate trench can have a reduced n-type doping concentration, for example, by more lightly n-doping the upper portion of the semiconductor layer structure during epitaxial growth. The reduced n-type dopant concentration in the JFET region can protect the gate insulating layer at the lower corners of the gate trench from breakdown. However, by reducing the dopant concentration, the more lightly doped JFET region may exhibit increased resistance during on-state operation. To compensate for the increased resistance, a portion of the JFET may be formed with an increased dopant concentration of the same conductivity type as the drift layer (referred to herein as a conduction-promoting region). In some embodiments, conduction-promoting regions having a higher dopant concentration can be selectively formed in portions of the drift region between the gate trenches that are laterally spaced from the gate trench corners, for example, using high-energy ion implantation. Thus, (i) the electric field strength adjacent the gate trench corners can be reduced, and (ii) the peak electric field strength can be substantially maintained or improved, but shifted away from the gate trench corners. Thereby, improved reliability of power MOSFETs and other gate-controlled devices according to embodiments of the present invention can be achieved while maintaining or improving device performance.

[0057] FIG. 2 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device (illustratively shown as a power MOSFET 200) including a shield region 240 and an aligned conduction-facilitating region 250 between gate trenches 280 in accordance with some embodiments of the present invention. As shown in FIG. 2, the power MOSFET 200 includes an active region and a termination region (not shown) surrounding the active region. The active region of the power MOSFET 200 includes multiple unit cells 208 electrically connected in parallel. Illustrative unit cells 208 are shown as dashed rectangles. The power MOSFET 200 may include more than the approximately two unit cells 208 shown in FIG. 2. It may also be understood that multiple power MOSFETs 200 may be grown on a single wafer.

[0058] The power MOSFET 200 is a heavily doped (N + ) n-type wide bandgap semiconductor substrate 210. Substrate 210 may comprise, for example, a single crystal silicon carbide semiconductor substrate. Substrate 210 may be doped with n-type impurities (e.g., N + The impurities may include, for example, nitrogen or phosphorus. The dopant concentration of the substrate 210 may be, for example, about 1×10 18 atoms / cm 3 ~1×10 21 atoms / cm 3 Although other doping concentrations can be used, substrate 210 can be of any suitable thickness (eg, in some embodiments, between 100 microns and 500 microns thick).

[0059] Lightly doped (N - ) An n-type drift layer or region 220 (e.g., a silicon carbide drift region) is provided on the substrate 210. The dopant concentration of the drift region 220 is, for example, about 1×10 14 atoms / cm 3 ~Approx. 1×10 16 atoms / cm 3 , e.g., about 5 x 10 14 atoms / cm 3 ~Approx. 5×1015 atoms / cm 3 , or approximately 7 × 10 14 atoms / cm 3 ~Approx. 1×10 15 atoms / cm 3 Although other doping concentrations can be used, drift region 220 can be formed by epitaxial growth on substrate 210. Drift region 220 can be a relatively thick region having a vertical height above substrate 210 of, for example, about 3 microns to about 100 microns. In some embodiments, drift region 220 can include a more heavily doped current spreading layer (e.g., (N + ) n-type current spreading layer). A moderately doped p-type layer is formed (e.g., by epitaxial growth or implantation) on drift region 220 to act as a p-type well region or P-well 270 for device 200. In some embodiments, p-type well region 270 may have a depth (relative to the top surface of drift layer 220) of less than about 1 micrometer (μm), e.g., about 0.8 μm or less. Heavily doped N + A layer is formed on top of the moderately doped p-type layer, for example by ion implantation, to act as a source region 260 for device 200. In some embodiments, source region 260 may have a depth (relative to the top surface of drift layer 220) of less than about 0.5 μm, for example, about 0.3 μm or less. A channel region length may be defined between a lower boundary of source region 260 and a lower boundary of P-well 270. In some embodiments, the channel length may be about 1 μm or less, for example, about 0.5 μm.

[0060] The substrate 210, drift region 220 (including the current spreading layer), and moderately doped p-type layer or P-well 270, together with various regions / patterns formed therein, define a semiconductor layer structure 206 of the power MOSFET. The semiconductor layer structure 206 may include one or more wide-bandgap semiconductor materials. A plurality of gate trenches 280 extend longitudinally parallel to one another within the semiconductor layer structure 206. The gate trenches 280 are spaced apart along a transverse (e.g., perpendicular) direction (e.g., a lateral or x-direction) with portions of the drift layer or JFET region 220 sandwiched therebetween. A gate insulating layer 282 is disposed on the bottom and sidewalls of each gate trench 280, and a gate electrode or gate 284 is disposed on the gate insulating layer 282 and fills each gate trench 280. A source contact 290 is formed on the source region 260 and may be an ohmic metal in some embodiments. A drain contact 292 is formed on the underside of the substrate 210. A gate contact (not shown) may be formed on each gate electrode 284.

[0061] 2, shield pattern 240 extends beyond gate trench 280 (and in the example of FIG. 2, below the bottom and corners of gate trench 280) into drift layer 220. In some embodiments, shield pattern 240 may extend more than about 1 μm into drift layer 220, such as about 1.5 μm or more. Shield pattern 240 is of the opposite conductivity type to drift region 220. In particular, in device 200, a heavily doped (P + ) A p-type shield pattern 240 is formed in the drift region 220 by, for example, ion implantation. For example, the shield pattern 240 has a thickness of about 1×10 15 atoms / cm 3 ~1×10 19 atoms / cm 3 Concentration of, for example, 1 x 10 17 atoms / cm 3The shield pattern 240 below each gate trench 280 may be electrically connected by, for example, a shield connection pattern (not shown).

[0062] The shield pattern 240 is configured to prevent degradation of the trench MOSFET 200 under high electric fields. For example, because corner regions of the gate insulating layer 282 are prone to dielectric breakdown, the shield pattern 240 can help protect the corner regions of the gate insulating layer 282 from high electric fields, such as during reverse blocking operation. In the example of FIG. 2 , the shield pattern 240 extends along one sidewall and below one corner of each gate trench 280. That is, the shield pattern 240 is offset relative to the gate trench 280 toward the source contact 290 and extends to the lower corner region of the gate trench 280. However, more generally, the shield patterns described herein may extend between and / or below the gate trenches, e.g., along at least one sidewall and / or bottom of each gate trench. The absence of shield pattern 240 on the sidewalls 278 of gate trench 280 allows for a (here n-type) channel region and conduction (indicated by the dashed arrow in FIG. 2) along one sidewall 278.

[0063] As mentioned above, in an embodiment of the present invention, the dopant concentration in drift region 220 is, for example, about 1×10 14 atoms / cm 3 ~Approx. 1×10 16 atoms / cm 3 , e.g., about 5 × 10 14 atoms / cm 3 ~Approx. 5×10 15 atoms / cm 3 , or approximately 7 × 10 14 atoms / cm 3 ~Approx. 1×10 15 atoms / cm 3, which reduces the electric field strength at the corners of the gate trenches 280 and therefore reduces the likelihood of breakdown of the gate insulating layer 282, but at the expense of increased resistance. To compensate for this, conduction promotion regions 250 are formed in the portions of the drift region 220 between the gate trenches 280 (i.e., the JFET region). The conduction promotion regions 250 are of the same conductivity type as the drift region 220 and are laterally separated or spaced apart from the gate trenches 280 and / or their corners. In particular, in the example device 200 of FIG. 2, n-type conduction promotion regions 250 are formed in the portions of the drift region 220 between the gate trenches 280, for example, by ion implantation. For example, the conduction promotion regions 250 may be formed with a conductivity of about 1×10 15 atoms / cm 3 ~1×10 17 atoms / cm 3 More than, for example, about 2 × 10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 , e.g., about 5 x 10 16 atoms / cm 3 The conduction promotion region 250 may be formed by implanting an n-type dopant (such as nitrogen (N)) at a concentration of 0.1 to 1.5 μm. The conduction promotion region 250 may extend along at least one side and / or along the bottom / lower boundary of the shield pattern 240. The conduction promotion region 250 may extend through the well 270 and / or beyond the bottom / lower boundary of the shield pattern 240 into the drift region 220.

[0064] Thus, the dopant concentration in conduction facilitating region 250 may be of the same conductivity type as the dopant concentration in drift region 220, but may be greater or higher than the dopant concentration in drift region 220 (particularly higher than the dopant concentration in portions of the drift region along the corners of gate trench 280 or gate insulating layer 282). In some embodiments, the dopant concentration in conduction facilitating region 250 may be about 2 times or more greater than the dopant concentration in drift region 220, e.g., about 3 times or more, about 5 times or more, about 10 times or more, or about 20 times or more. Thus, the dopant concentration (in this example, n-type) of the portions of drift layer 220 between gate trenches 280 may vary along the direction in which gate trenches 280 are spaced apart (e.g., the x-direction in FIG. 2 ) (e.g., with a non-uniform dopant distribution or concentration gradient between a first concentration near the corners of gate trenches 280 and a second, higher concentration in region 250), which may shift the peak electric field distribution under an applied voltage away from the corners of gate trenches 280, for example, during reverse blocking operation. That is, the dopant concentration of the JFET portion of drift region 220 may vary in a stepped or continuous (e.g., linear or exponential) manner along the x-direction within drift layer 220. For example, the dopant concentration may be constant, may be substantially uniform or may vary symmetrically in the portion of drift region 220 between gate trenches 280, or may include a gradient or step increase at the interface or boundary between drift region 220 and conduction promotion region 250, as shown, for example, by the various non-uniform dopant distributions in Figures 4D, 7B, and 10B.

[0065] That is, the peak electric field during reverse blocking operation may be shifted away from the center or central portion of the JFET region toward the shield pattern 240 due to the presence of the more heavily doped n-type conduction-promoting region 250 along the periphery of the p-shield pattern 240. Therefore, the lower corners of the gate trench 280 (exposed by the shield pattern 240) experience lower electric field values during reverse blocking operation. The more heavily doped n-type portion 250 of the JFET region provides a lower resistance current path (shown by the bold and dashed arrows in FIG. 2 ) during on-state operation, thereby helping to compensate for the increased resistance in the remainder of the JFET region due to the more lightly doped epitaxial layer 220. The dopant concentration of the conduction-promoting region 250 may be lower than the dopant concentration of the substrate 210 and / or any current spreading layer (e.g., layer 1530 in FIG. 15 ) between the top of the drift region 220 and the substrate 210. In some embodiments, the relative dopant concentrations of drift layer 220 and conduction facilitating region 250 can be selected or set to provide a blocking voltage of about 300V, up to about 15 kV.

[0066] 3A-3F are schematic cross-sectional views illustrating example processes for fabricating the gate trench power semiconductor device 200 of FIG. 2 with aligned shielding patterns 240 and conduction promotion regions 250 according to some embodiments of the present invention. As shown in FIG. 3A, ion implantation is used to more heavily dope portions 250 of the drift region 220 to define the conduction promotion regions 250 in the portions of the drift region 220 between the gate trenches 280 (to be formed in a later step). For example, a lightly doped (N -After forming n-type drift layer or region 220 and moderately doped p-type well region 270 (e.g., by epitaxial growth or implantation), a first mask 301 (e.g., an oxide mask) may be formed to expose the surface of drift region 220. A first ion implantation process may be performed to implant the surface exposed by first mask 301 with dopants of the same conductivity type as drift region 220 to define conduction-promoting region 250 that extends through P-well 270 and into drift region 220. As mentioned above, in some embodiments, a dopant concentration of about 1×10 15 atoms / cm 3 ~1×10 17 atoms / cm 3 , e.g. 5×10 16 atoms / cm 3 Conduction promoting region 250 is formed by implanting an n-type dopant (such as nitrogen) at a concentration of N - Lightly doped N with a higher dopant concentration than the drift layer 220 - A conduction promotion region 250 may be defined. The energy of the first implantation process may be controlled to bring the lower boundary of the conduction promotion region 250 to a desired depth (relative to the surface of the drift region 220).

[0067] 3B, a second ion implantation process can be performed to define shield pattern 240 that extends through P-well 270 and into drift layer 220. For example, after forming conductivity promoting region 250 and using the same mask 301, a second ion implantation process can be performed to implant a dopant of the opposite conductivity type to drift region 220 into the surface exposed by mask 301 to define shield pattern 240 that extends through P-well 270 and into drift region 220. As described above, shield pattern 240 can have a dopant concentration of approximately 1×10 15 atoms / cm 3 ~1×10 19 atoms / cm 3 , e.g. 1×10 17 atoms / cm 3 Above, cm 3 , a p-type dopant (such as aluminum) is implanted at a concentration of+ 3A-3F , the shield pattern 240 is aligned with conduction-facilitating regions 250 that extend along both sides of the shield pattern and under both corners of the shield pattern.

[0068] 3A and 3B are shown as being formed after conduction promotion region 250, it is understood that the order of these steps may be reversed. That is, in some embodiments, shield pattern 240 may be formed before conduction promotion region 250. Similarly, in some embodiments, conduction promotion region 250 and / or shield pattern 240 may be formed before forming P-well 270 in drift region 220. More generally, elements / layers / regions may be formed in an order different from that shown as an example in the fabrication steps described herein.

[0069] As shown in FIG. 3C, the first mask 301 may be removed, and a second mask 302 may be formed to cover or protect the shield pattern 240 and the conductivity-promoting region 250 and expose the surface of the adjacent P-well 270, and a third ion implantation process may be performed to implant heavily doped N ions into the top of the P-well 270. + 2. Define source region 260. In some embodiments, a more heavily doped P + The region (not shown) is N + The N well 270 is formed on top of the P well 270 adjacent to the source region 260. + The source region 260, the shield pattern 240, and the conductivity promotion region 250 may be protected. In some embodiments, implant activation and / or other further processes may be performed to repair or restore damage caused by the implant process.

[0070] 3D , a further masking step may be performed to define gate trenches 280 in the semiconductor layer structure 206. The gate trenches 280 extend through the P-well 270 and into the drift layer 220. The gate trenches 280 may be formed in a “striped” gate trench layout, in which the trenches 280 extend parallel to one another (continuously or partially) in the longitudinal direction and are spaced apart in a direction transverse to (e.g., perpendicular to) the longitudinal direction. For example, an etching process may be performed to etch the surfaces of the semiconductor layer structure 206 exposed by the respective trench-shaped openings in the gate mask (not shown) to define the gate trenches 280. The etching process may be an anisotropic etch that removes portions of the p-well layer 270 and / or the drift region 220 to form the gate trenches 280. The etching process may be controlled so that the depth or bottom of trench 280 is limited upward and does not extend beyond shield pattern 240 and / or conductivity promoting region 250 .

[0071] 3D, a gate insulating layer 282 may be formed on the bottom and sidewalls of each gate trench 280, and a gate electrode 284 may be formed on the gate insulating layer 282 to fill each gate trench 280. As shown in FIG. 3E, an intermetal dielectric (IMD) layer 286 may be formed on the gate 284, and a source contact 290 (not shown) may be formed on the source region 260. In some embodiments, the source contact 290 may be an ohmic metal. In FIG. 3F, an overlay process may be performed to form a layer 303 on the surface of the semiconductor layer structure 206. A drain contact 292 (not shown) may be formed on the underside of the substrate 210.

[0072] 4A and 4B are graphical example diagrams of the respective concentrations of p-type dopants (illustratively shown relative to Al dopants) and n-type dopants (illustratively shown relative to N dopants) in the JFET region of the gated trench power semiconductor device of FIG. 2 along both the depth (y) and lateral (x) directions. FIGS. 4C and 4D show the dopant concentrations along line a-a′ (i.e., the depth or y direction) and line b-b′ (i.e., the lateral or x direction), respectively. As shown in FIGS. 4A and 4C, the Al dopant distribution extends into drift region 220 to a depth of approximately 2 μm and peaks at a depth of approximately 1.2 μm, which may correspond to the peak dopant concentration of shield pattern 240. As shown in FIGS. 4B and 4C, the N dopant distribution extends into drift layer 220 to a depth of greater than about 2 μm, peaking at a depth of about 1.7 μm, which may correspond to the peak dopant concentration in conduction promotion region 250.

[0073] As shown in FIGS. 4A and 4D , the Al dopant distribution varies laterally within the drift region 220 across a width of approximately 2 μm between the gates 284, peaking at a distance of approximately 0.85 μm. FIGS. 4B and 4D show that the N dopant distribution also varies laterally within the drift region 220, with a similar peak across a similar width as the Al dopant distribution. That is, in this example, the N dopant distribution in the conduction promotion region 250 generally closely matches the Al dopant distribution in the shield pattern 240 laterally between the gates 284. The peak N dopant concentration in the conduction promotion region 250 may be approximately two times or more, e.g., approximately three times or more, approximately five times or more, approximately ten times or more, or approximately twenty times or more higher than the N dopant concentration in the drift region 220 adjacent the corner of the gate insulating layer 282, thereby shifting the peak of the electric field distribution under an applied voltage away from the corner of the gate insulating layer 282. Although N and Al are described herein as n-type and p-type dopants, respectively, it is understood that embodiments are not limited to these particular dopants and other n-type dopants (e.g., phosphorus (P)) and p-type dopants (e.g., boron (B)) can be used.

[0074] 5 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device (illustratively shown as power MOSFET 500) including shielding regions 240 and offset conduction-facilitating regions 550 between gate trenches 280 according to some embodiments of the present invention. Some elements of power MOSFET 500 may be similar to elements of power MOSFET 200 of FIG. 2, and therefore, for the sake of brevity, a detailed description of such similar elements may be omitted.

[0075] 5, power MOSFET 500 includes a plurality of unit cells 508 electrically connected in parallel. While example unit cells 508 are shown as dashed rectangles, it is understood that power MOSFET 500 may include more than the approximately two unit cells 508 shown in FIG.

[0076] Similar to the power MOSFET 200 of FIG. 2, the power MOSFET 500 is a heavily doped (N + ) n-type wide bandgap semiconductor substrate 210, lightly doped (N - ) n-type drift layer or region 220, a moderately doped p-type well region or P-well 270, and a heavily doped N +The gate trench 280 includes a source region 260. A plurality of gate trenches 280 (each including a gate insulating layer 282 on its bottom and sidewalls and including a gate electrode 284 therein) extend parallel to one another in the longitudinal direction within the semiconductor layer structure 206 and are spaced apart along a direction (e.g., the x-direction) that intersects (e.g., is perpendicular to) the longitudinal direction, with a portion of the drift layer or JFET region 220 therebetween. A shield pattern 240 of a conductivity type opposite to that of the drift region 220 extends along one sidewall of each gate trench 280 and below one corner of each gate trench 280 into the semiconductor layer structure 206, and may serve to protect the gate insulating layer 282 at the corner of the gate trench 280 from high electric fields, such as during reverse blocking operation. The absence of the shield pattern 240 on the other sidewall 278 of the gate trench 280 allows a (here n-type) channel region and conduction (indicated by the dashed arrow in FIG. 5) along one sidewall 278.

[0077] As described above, drift region 220 is relatively lightly doped to protect gate insulating layer 282 at the corners of gate trenches 280 or to reduce the likelihood of breakdown of gate insulating layer 282. To compensate for the reduced dopant concentration (and therefore increased resistance) of drift region 220, conduction promotion regions 550 of the same conductivity type as drift region 220 but having a higher dopant concentration than drift region 220 are formed in the portions of drift region 220 between gate trenches 280 (i.e., in the JFET region). In the example device 500 of FIG. 5 , n-type conduction promotion regions 550 are formed, for example, by ion implantation, in the portions of drift region 220 between gate trenches 280, but are offset from p-type shield pattern 240 in the laterally or x-direction (e.g., toward gate trench 280). The more heavily doped n-type portions 550 of the JFET region provide a lower resistance current path (shown by the bold and dashed arrows in FIG. 5). Thus, the (n-type in this example) dopant concentration in the portions of drift region 220 between gate trenches 280 can vary (e.g., with a non-uniform dopant distribution or concentration gradient) along the direction in which gate trenches 280 are spaced apart (e.g., the x-direction in FIG. 5), which can shift the peak electric field distribution under an applied voltage away from the corners of gate trenches 280, for example, during reverse blocking operation.

[0078] Thus, the dopant concentration in the JFET region of drift region 220 may vary in a stepped or continuous manner (e.g., linearly or exponentially) along the x-direction within drift layer 220. For example, in this case, the concentration in drift region 220 may be constant, substantially uniform, or vary symmetrically, with a gradient or step increase at the interface or boundary between drift region 220 and conduction promotion region 550, as shown, for example, in FIG. 7B . Conduction promotion region 550 may extend along at least one side and / or bottom / lower boundary of shield pattern 240 and be laterally spaced from gate trench 280. Conduction promotion region 550 may extend through well 270 and / or beyond the bottom / lower boundary of shield pattern 240 into drift region 220. Otherwise, conduction promotion region 550 may be similar to conduction promotion region 250 of FIG. 2 .

[0079] 6A-6F are schematic cross-sectional views illustrating example processes for fabricating the gate trench power semiconductor device of FIG. 5 with offset shield pattern 240 and conduction promotion region 550 according to some embodiments of the present invention. As shown in FIG. 6A, ion implantation is used to more heavily dope portions 550 of drift region 220 to define conduction promotion region 550 in the portion of drift region 220 between gate trenches 280 (to be formed in a subsequent process). For example, a lightly doped (N - After forming n-type drift layer or region 220 (e.g., by epitaxial growth on substrate 210) and forming a moderately doped p-type well region 270 (e.g., by epitaxial growth or implantation), a first mask 601 (e.g., an oxide mask) may be formed to expose the surface of drift region 220. A first ion implantation process may be performed to implant dopants of the same conductivity type as drift region 220 into the surface exposed by first mask 601 to define conduction promotion region 550 that extends through P-well 270 and into drift region 220. The energy of the first implantation process may be controlled to provide a lower boundary of conduction promotion region 550 at a desired depth (relative to the surface of drift region 220).

[0080] In FIG. 6B , a second ion implantation process can be performed to define shield pattern 240 that extends through P-well 270 and into drift region 220. For example, after forming conductivity promotion region 550, first mask 601 can be removed, and second mask 602 can be formed with openings offset from the openings in first mask 601, and a second ion implantation process can be performed to implant a dopant of the opposite conductivity type to drift region 220 into the surface exposed by second mask 602 to define shield pattern 240. Thus, shield pattern 240 is offset from conductivity promotion region 550, which extends along one side of shield pattern 240 and under one corner of shield pattern 240 in the example of FIGS. 6A-6F . In some embodiments, the order of the masking and implantation steps in FIGS. 6A and 6B can be reversed so that shield pattern 240 can be formed before conductivity promotion region 550.

[0081] As shown in FIG. 6C, the second mask 602 can be removed, a third mask 603 may be formed to cover or protect the shield pattern 240 and the conductivity-promoting region 550 and expose the surface of the P-well 270 adjacent thereto, and a third ion implantation process is performed to implant heavily doped N ions into the upper portion of the P-well 270. + Defines the source region 260. In some embodiments, more heavily doped P + Regions (not shown) are then filled with N, for example by ion implantation using a further masking step (not shown). + It may be formed on top of a P-well 270 adjacent to the source region 260. An implant activation process and / or other additional processes may be performed to recover or repair damage caused by the implant process.

[0082] Referring now to FIG. 6D , further steps are performed to define gate trenches 280 in the semiconductor layer structure 206 that extend through the P well 270 into the drift region 220, and to form a gate insulating layer 282 on the bottom and sidewalls of each gate trench 280;

[0083] In a manner similar to that described above in connection with Figure 3D, a gate electrode 284 may be formed on the gate insulating layer 282 to fill each gate trench 280. As shown in Figure 6E, an intermetal dielectric (IMD) layer 286 may be formed on the gate 284, and a source contact 290 (not shown) may be formed on the source region 260. In some embodiments, the source contact 290 may be an ohmic metal. In Figure 6F, an overlay process may be performed to form a layer 606 on the surface of the semiconductor layer structure 206, and a drain contact 292 (not shown) may be formed on the underside of the substrate 210.

[0084] 7A and 7B are graphical example diagrams of the variation of dopant concentration in the JFET region of the gate trench power semiconductor device of FIG. 5 along the lateral direction (x-direction). As shown in FIGS. 7A and 7B, the n-type dopant distribution in the portion of the drift region between the gate trenches (i.e., the JFET region) varies with lateral position along the separation direction of adjacent gate trenches. The n-type dopant concentration in the conduction promotion region 550 (e.g., 2×10 16 atoms / cm 3 ) is the n-type dopant concentration (e.g., 6×10 15 atoms / cm 3 ), which can shift the peak of the electric field distribution under applied voltage away from the corner of the gate insulating layer 282. In the example of FIGS. 7A and 7B, the dopant distribution of the conduction-facilitating region 550 is offset laterally between the gate / gate trench from the dopant distribution of the shield pattern 240 (not shown).

[0085] 8 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device (illustratively shown as power MOSFET 800) including shield region 240 and sloped or angled conduction-facilitating region 850 between gate trenches 280, according to some embodiments of the present invention. Because some elements of power MOSFET 800 may be similar to elements of power MOSFET 200 of FIG. 2, detailed descriptions of such similar elements may be omitted for the sake of brevity.

[0086] 8, power MOSFET 800 includes a plurality of unit cells 808 electrically connected in parallel. While example unit cells 808 are shown as dashed rectangles, it is understood that power MOSFET 800 may include more than the approximately two unit cells 808 shown in FIG.

[0087] Similar to the power MOSFET 200 of FIG. 2, the power MOSFET 800 is a heavily doped (N + ) n-type wide bandgap semiconductor substrate 210, lightly doped (N - ) n-type drift layer or region 220, a moderately doped p-type well region or P-well 270, and a heavily doped N +The gate trench 280 includes a source region 260. A plurality of gate trenches 280 (each including a gate insulating layer 282 on its bottom and sidewalls and including a gate electrode 284 therein) extend parallel to one another in the longitudinal direction within the semiconductor layer structure 206 and are spaced apart along a direction (e.g., the x-direction) intersecting (e.g., perpendicular to) the longitudinal direction, with a portion of the drift layer or JFET region 220 therebetween. A shield pattern 240 of a conductivity type opposite to that of the drift region 220 extends along one sidewall of each gate trench 280 and below one corner of each gate trench 280 into the semiconductor layer structure 206, and may serve to protect the gate insulating layer 282 at the corner of the gate trench 280 from high electric fields, such as during reverse blocking operation. The absence of the shield pattern 240 on the other sidewall 278 of the gate trench 280 allows a (here n-type) channel region and conduction (indicated by the dashed arrow in FIG. 8) along one sidewall 278.

[0088] As described above, drift region 220 is relatively lightly doped to prevent or reduce the likelihood of breakdown of gate insulating layer 282 at the corners of gate trenches 280. To compensate for the reduced dopant concentration (and therefore increased resistance) of drift region 220, conduction promotion regions 850 of the same conductivity type as drift region 220 but with a higher dopant concentration than drift region 220 are formed in the portions of drift region 220 between gate trenches 280 (i.e., in the JFET region). In the example device 800 of FIG. 5 , n-type conduction promotion regions 850 are formed in the portions of drift region 220 between gate trenches 280, but with an orientation that is tilted or inclined with respect to p-type shield pattern 240. That is, an axis 890 along which the dopant distribution of conduction promotion region 850 extends is not perpendicular to the surface of drift region 220. In the example of FIG. 8, the dopant distribution of the conductivity promoting region 850 extends non-uniformly along at least one side and lower boundary of the shield pattern 240 .

[0089] Similar to conduction promotion regions 250 and 500, the more heavily doped n-type portion 850 of the JFET region provides a lower resistance current path (shown by the bold and dashed arrows in FIG. 8 ). Thus, the (n-type in this example) dopant concentration in the portion of drift region 220 between gate trenches 280 can vary (e.g., with a non-uniform dopant distribution or concentration gradient) along the direction in which gate trenches 280 are spaced apart (e.g., the x-direction in FIG. 8 ), which can shift the peak electric field distribution under an applied voltage away from the corners of gate trenches 280, for example, during reverse blocking operation.

[0090] Thus, the dopant concentration in the JFET region of drift region 220 may vary in a stepped or continuous manner (e.g., linearly or exponentially) along the x-direction within drift layer 220. For example, the concentration in drift region 220 may be substantially uniform or vary symmetrically, with a gradient or step increase at the interface or boundary between drift region 220 and conduction promotion region 850, as shown, for example, in FIG. 10B . Conduction promotion region 850 may extend along at least one side and / or bottom / lower boundary of shield pattern 240 and may be laterally spaced from and tilted or slanted relative to the direction of gate trench 280. Conduction promotion region 850 may extend through well 270 and / or beyond the bottom / lower boundary of shield pattern 240 into drift region 220. Otherwise, conduction promotion region 850 may be similar to conduction promotion region 250 of FIG. 2 .

[0091] 9A-9F are schematic cross-sectional views illustrating example steps for fabricating the gate trench power semiconductor device of FIG. 8 with a sloped conduction-promoting region 850 according to some embodiments of the present invention. As shown in FIG. 8A, a sloped ion implantation process is used to more heavily dope a portion 850 of the drift region 220 of the semiconductor layer structure 206, defining the conduction-promoting region 850 in the portion of the drift region 220 between the gate trenches 280 (to be formed in a subsequent step). For example, a first mask 901 (e.g., an oxide mask) can be formed to expose the surface of the drift region 220, and a first ion implantation process can be performed to implant a dopant of the same conductivity type as the drift region 220 into the surface exposed by the first mask 901 to define the conduction-promoting region 850 extending through the P-well 270 and into the drift region 220. The first ion implantation process can be performed at a non-orthogonal angle to the surface of the drift region 220. In some embodiments, the angle of the first ion implantation process may be between about 3° and about 30°, e.g., about 5°, about 10°, or about 15°, relative to the normal to the surface of drift region 220. The energy of the first implantation process may be controlled to bring the lower boundary of conduction promotion region 850 to a desired depth (relative to the surface of drift region 220) along a non-orthogonal angle.

[0092] In FIG. 9B , a second ion implantation process can be performed to define shield pattern 240, which extends through P-well 270 and into drift region 220. For example, using the same mask 901, a second ion implantation process can be performed to implant dopants of the opposite conductivity type to drift region 220 into the surface exposed by mask 901 to define shield pattern 240. Conduction promotion region 850 extends along one side of shield pattern 240 and under one corner of shield pattern 240 in the examples of FIGS. 9A-9F , but is tilted or angled relative to the direction of shield pattern 240. That is, the dopant distribution in conduction promotion region 850 is asymmetric or non-uniform along both sides and the lower boundary of shield pattern 240. In some embodiments, the order of the implantation steps in FIGS. 9A and 9B can be reversed so that shield pattern 240 can be formed before conduction promotion region 850.

[0093] As shown in FIG. 9C, the first mask 901 can be removed, a second mask 902 can be formed to cover or protect the shield pattern 240 and the conductivity-promoting region 850 and expose the surface of the P-well 270 adjacent thereto, and a third ion implantation process can be performed to implant heavily doped N ions into the top of the P-well 270. + Defines the source region 260. In some embodiments, more heavily doped P + Regions (not shown) are then filled with N, for example by ion implantation using a further masking step (not shown). + It may be formed on top of a P-well 270 adjacent to the source region 260. An implant activation process and / or other additional processes may be performed to recover or repair damage caused by the implant process.

[0094] Referring now to FIG. 9D , further steps can be performed to define gate trenches 280 in the semiconductor layer structure 206 that extend through the P-well 270 into the drift layer 220, form a gate insulating layer 282 on the bottom and sidewalls of each gate trench 280, and form a gate electrode 284 on the gate insulating layer 282 to fill each gate trench 280 in a manner similar to the steps described above in connection with FIG. 3D . As shown in FIG. 9E , an intermetal dielectric (IMD) layer 286 can be formed on the gate 284, and a source contact 290 (not shown) can be formed on the source region 260. In some embodiments, the source contact 290 can be an ohmic metal. In FIG. 9F , an overlay process can be performed to form a layer 903 on the surface of the semiconductor layer structure 206, and a drain contact 292 (not shown) can be formed on the underside of the substrate 210.

[0095] 10A and 10B are graphical example diagrams of varying dopant concentrations along the lateral direction (x-direction) in the JFET region of the gate trench power semiconductor device of FIG. 8. As shown in FIGS. 10A and 10B, the n-type dopant distribution (illustrated as N dopant) in the portion of the drift region between the gate trenches 280 (i.e., the JFET region) varies with lateral position along the separation direction of adjacent gate trenches 280 / gates 284. In particular, the N dopant distribution varies laterally in the drift region 220 between the gates 284, with a minimum dopant concentration at a lateral distance of approximately 0.75 μm (which may correspond to the dopant concentration in the drift region 220) and a peak dopant concentration at a lateral distance of approximately 1.7 μm (which may correspond to the peak dopant concentration in the conduction promotion region 850). As shown in FIG. 10B, the dopant concentration (n-type in this example) of the conduction-facilitating region 850 may be about two times or more, for example, about five times or more, or about ten times or more, or about twenty times or more higher than the dopant concentration of the portion of the drift region 220 adjacent the corner of the gate insulating layer 282, thereby shifting the peak of the electric field distribution under an applied voltage away from the corner of the gate insulating layer 282.

[0096] 11A and 11B are graphical illustrations of electric field distributions in a gate trench power semiconductor device including a drift layer with a reduced dopant concentration, according to some embodiments of the present invention. As shown in FIGS. 11A and 11B, the electric field distribution along the bottom of the gate trench 280 (i.e., in the lateral or x-direction in which the gate trenches 280 are separated from one another) is generally concentrated at the corners of the gate trench 280 exposed by the shield pattern 240. However, FIG. 11B shows that the electric field strength decreases as the dopant concentration of the drift layer or region 220 is reduced, with the dopant concentration of the drift layer 220 selected or configured to reduce the electric field strength (both at the corners and throughout the gate trench 280) by about 10 times or more. By reducing the dopant concentration of the drift layer 220 according to embodiments of the present invention, the peak electric field strength at the corners of the gate trench 280, where the gate insulating layer may be susceptible to breakdown, may be reduced. In combination with a conduction promotion region as described herein, the peak of the electric field distribution can also be shifted away from the corners of the gate trench 282 (i.e., laterally or in the x-direction), in which case the electric field strength is generally comparable to the electric field strength experienced at the corners of the gate trench 282. In some embodiments, the strength of the electric field distribution in the conduction promotion region can be about 10 times or more greater than the strength of the electric field distribution at each corner of the gate trench 282. In some embodiments, the strength of the electric field distribution in the conduction promotion region can be less than about 5 MV / cm, e.g., less than about 3 MV / cm, or less than about 2 MV / cm.

[0097] 12 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device (illustratively shown as power MOSFET 1200) including a bottom shield region 1240 and an offset conduction-facilitating region 550 between gate trench 280 according to some embodiments of the present invention. Some elements of power MOSFET 1200 may be similar to elements of power MOSFET 500 of FIG. 5, and therefore detailed descriptions of such similar elements may be omitted for the sake of brevity.

[0098] 12, power MOSFET 1200 includes a plurality of unit cells 1208 electrically connected in parallel. While example unit cells 1208 are shown as dashed rectangles, it is understood that power MOSFET 1200 may include more than the approximately two unit cells 1208 shown in FIG.

[0099] Similar to the power MOSFET 500 of FIG. 5, the power MOSFET 1200 is a heavily doped (N + ) n-type wide bandgap semiconductor substrate 210, lightly doped (N - ) n-type drift layer or region 220, a moderately doped p-type well region or P-well 270, and a heavily doped N + The gate trench 280 includes a source region 260. A plurality of gate trenches 280 (each including a gate insulating layer 282 on its bottom and sidewalls and including a gate electrode 284 therein) extend parallel to one another in the longitudinal direction within the semiconductor layer structure 206 and are spaced apart along a direction (e.g., the x-direction) intersecting (e.g., perpendicular to) the longitudinal direction, with a portion of the drift layer or JFET region 220 therebetween. A shield pattern 240 of a conductivity type opposite to that of the drift region 220 extends along one sidewall of each gate trench 280 and below one corner of each gate trench 280 into the semiconductor layer structure 206, and may serve to protect the gate insulating layer 282 at the corner of the gate trench 280 from high electric fields, such as during reverse blocking operation. The absence of the shield pattern 240 on the other sidewall 278 of the gate trench 280 allows for a (here n-type) channel region and conduction (indicated by the dashed arrow in FIG. 12) along one sidewall 278.

[0100] As described above, drift region 220 is relatively lightly doped to prevent or reduce the likelihood of breakdown of gate insulating layer 282 at the corners of gate trenches 280. To compensate for the reduced dopant concentration (and therefore increased resistance) of drift region 220, conduction promotion regions 550 of the same conductivity type as drift region 220 but having a higher dopant concentration than drift region 220 are formed in the portions of drift region 220 between gate trenches 280 (i.e., in the JFET region). In the example device 1200 of FIG. 12 , n-type conduction promotion regions 550 are formed, for example, by ion implantation, in the portions of drift region 220 between gate trenches 280, but are offset from p-type shield pattern 1240. Conduction promotion regions 550 can extend into drift region 220 through well 270 and / or beyond the bottom / lower boundary of shield pattern 1240. The more heavily doped n-type portions 550 of the JFET region provide a lower resistance current path (shown by the bold and dashed arrows in FIG. 8). Thus, the (n-type in this example) dopant concentration in the portions of the drift region 220 between the gate trenches 280 can vary (e.g., with a non-uniform dopant distribution or concentration gradient) along the direction in which the gate trenches 280 are spaced from one another (e.g., in the x-direction in FIG. 12), thereby shifting the peak electric field distribution under an applied voltage away from the corners of the gate trenches 280.

[0101] 12, the shield pattern 1240 of the power MOSFET 1200 is formed below the bottom surface of the gate trench 280, but is absent from the sidewalls of either side of the gate trench 280. The shield pattern 1240 may otherwise be similar to the shield pattern 240 described herein. More generally, the power semiconductor devices described herein may include shield patterns 240, 1240 between and / or below the gate trenches 280 (e.g., along at least one sidewall and / or along the bottom surface of the gate trench) in various portions of the drift layer 220 between adjacent gate trenches 280.

[0102] 13A-13F are schematic cross-sectional views illustrating example steps for fabricating a gate trench power semiconductor device including a bottom shield region 1240 with aligned conduction promotion regions 250 according to some embodiments of the present invention. As shown in FIG. 13, an ion implantation process is used to more heavily dope portions 250 of the drift region 220 of the semiconductor layer structure 206 to define the conduction promotion regions 250 in the portions of the drift region 220 between the gate trenches 280 (to be formed in subsequent steps). For example, a first mask 1301 (e.g., an oxide mask) can be formed to expose surfaces of the drift region 220 or the P-well 270, and a first ion implantation process can be performed to implant a dopant of the same conductivity type as the drift region 220 into the surfaces exposed by the first mask 1301 to define the conduction promotion regions 250 extending through the P-well 270 and into the drift region 220. The energy of the first implantation process can be controlled to bring the lower boundary of the conduction promotion region 250 to a desired depth (relative to the surface of the drift region 220).

[0103] 13B, a second ion implantation process can be performed to define shield pattern 1240, which extends through P-well 270 and into drift region 220. For example, using the same mask 1301, a second ion implantation process can be performed to implant a dopant of the opposite conductivity type to drift region 220 into the surface exposed by mask 1301 to define shield pattern 1240. Thus, shield pattern 1240 is aligned with conductivity promotion regions 250, which extend along both sides of shield pattern 1240 and under both corners of shield pattern 1240 in the example of FIGS. 13A-13F. In some embodiments, the order of the implantation steps in FIGS. 13A and 13B can be reversed so that shield pattern 1240 can be formed before conductivity promotion regions 250.

[0104] 13C, the first mask 1301 can be removed, and a second mask 1302 can be formed to cover or protect the shield pattern 1240 and the conductivity-promoting region 250 and expose the adjacent surface of the P-well 270. A third ion implantation process can be performed to implant heavily doped N ions into the top of the P-well 270. + Defines the source region 260. In some embodiments, more heavily doped P + Regions (not shown) are then filled with N, for example by ion implantation using a further masking step (not shown). + It may be formed on top of a P-well 270 adjacent to the source region 260. An implant activation process and / or other additional processes may be performed to recover or repair damage caused by the implant process.

[0105] 13D , further steps may be performed to define gate trenches 280 in the semiconductor layer structure 206 that extend through the P-well 270 into the drift layer 220, form a gate insulating layer 282 on the bottom and sidewalls of each gate trench 280, and form a gate electrode 284 on the gate insulating layer 282 to fill each gate trench 280. The gate trenches 280 may be fabricated in a manner similar to that described above with reference to FIG. 3D , but may also be fabricated using a gate mask (not shown) that exposes the shield pattern 1240. The gate mask may, in some embodiments, expose at least a portion of the conduction promotion region 250. The etching process may be controlled so that the depth or bottom of the trench 280 is limited above the shield pattern 1240 and / or the conduction promotion region 250 and does not extend beyond the shield pattern 1240 and / or the conduction promotion region 250. Thus, the conduction promotion region 250 can extend along the sidewalls of the gate trench 280 (and along the lateral and lower boundaries of the shield pattern 1240), while the shield pattern 1240 extends along the bottom and corners of the gate trench 280. That is, the conduction promotion region 250 can increase conduction to compensate for the reduced dopant concentration in the drift region 220, while the shield pattern 1240 can protect the gate insulating layer 282 at the corners of the gate trench 280 from dielectric breakdown.

[0106] As shown in Figure 13E, an intermetal dielectric (IMD) layer 286 can be formed on gate 284, and a source contact (not shown) can be formed on source region 260. In some embodiments, the source contact can be an ohmic metal. In Figure 13F, an overlay process can be performed to form layer 1303 on the surface of semiconductor layer structure 206, and a drain contact (not shown) can be formed on the underside of substrate 210.

[0107] FIG. 14 is a schematic cross-sectional view illustrating an example gate trench power semiconductor device (illustratively shown as a power MOSFET 1400) including alternating shield regions 1440 and aligned conduction-facilitating regions 1450 between gate trenches 280 according to some embodiments of the present invention. Some elements of the power MOSFET 1400 may be similar to elements of the power MOSFET 200 of FIG. 2 , and therefore detailed descriptions of such similar elements may be omitted for the sake of brevity. The power MOSFET 1400 includes multiple unit cells 1408 electrically connected in parallel. While the example unit cells 1408 are shown as dashed rectangles, it is understood that the power MOSFET 1400 may include more unit cells 1408 than are shown in FIG. 14 .

[0108] Similar to the power MOSFET 200 of FIG. 2, the power MOSFET 1400 is a heavily doped (N + ) n-type wide bandgap semiconductor substrate 210, lightly doped (N - ) n-type drift layer or region 220, a moderately doped p-type well region or P-well 270, and a heavily doped N +14 includes a source region 260. A plurality of gate trenches 280 (each including a gate insulating layer 282 on its bottom and sidewalls and a gate electrode 284 therein) extend parallel to one another in the longitudinal direction within the semiconductor layer structure 206 and are spaced apart along a direction (e.g., the x-direction) that intersects (e.g., is perpendicular to) the longitudinal direction, with a portion of the drift layer or JFET region 220 therebetween. A shield pattern 1440 of a conductivity type opposite to that of the drift region 220 extends into the semiconductor layer structure 206 in the portion of the drift region 220 between adjacent gate trenches 280. In the device 1400 of FIG. 14 , the sidewalls on both sides of the gate trench 280 are free of the shield pattern 1440, allowing for a (here, n-type) channel region and conduction (indicated by dashed arrows in FIG. 14 ) along both sidewalls 278 of the gate trench. The shield patterns 1440 are configured to provide voltage and / or current blocking by connection to respective source contacts 1490, which are connected by shield connection patterns 1491 on top of the device 1400, allowing the deep shield patterns 1440 to be electrically grounded.

[0109] As described above, drift region 220 is relatively lightly doped to prevent or reduce the likelihood of breakdown of gate insulating layer 282 at the corners of gate trenches 280. To compensate for the reduced dopant concentration (and therefore increased resistance) of drift region 220, conduction promotion regions 1450 of the same conductivity type as drift region 220 but with a higher dopant concentration than drift region 220 are formed in the portions of drift region 220 between gate trenches 280 (i.e., in the JFET region). In the example device 1400 of FIG. 14 , n-type conduction promotion regions 1450 are formed, for example, by ion implantation, in the portions of drift region 220 between gate trenches 280 and aligned with p-type shield pattern 1440. For example, as shown in the steps of FIGS. 3A and 3B , respective ion implantation processes using the same implant mask can be used to form shield pattern 1440 aligned with conduction promotion regions 1450. The more heavily doped n-type portion 1450 of the JFET region provides a lower resistance current path (indicated by the bold dashed arrow in FIG. 14).

[0110] Thus, the dopant concentration (in this example, n-type) of the portion of drift region 220 between gate trenches 280 can vary (e.g., with a non-uniform dopant distribution or concentration gradient) along the direction in which gate trenches 280 are spaced from one another (e.g., in the x-direction in FIG. 14 ), which can shift the peak electric field distribution under an applied voltage away from the corners of gate trenches 280. Conduction promotion region 1450 can extend along at least one side and / or bottom / lower boundary of shield pattern 1440. Conduction promotion region 1450 can extend through well 270 and / or beyond the bottom / lower boundary of shield pattern 1440 into drift region 220.

[0111] 15 is a schematic cross-sectional view of an illustrative gate trench power semiconductor device (illustratively shown as a power MOSFET 1500) including a heavily doped current spreading layer 1530 (relative to the drift region 220) according to an embodiment of the present disclosure. As shown in FIG. 15, device 1500 is similar to device 500 of FIG. 5, except that drift region 220 does not include a heavily doped current spreading layer 1530 (e.g., (N + ) n-type current spreading layer). Current spreading layer 1530 and conduction facilitating region 550 each have a higher concentration of dopant than drift region 220, e.g., about 1×10 15 atoms / cm 3 ~1×10 17 atoms / cm 3 More than, for example, about 2 × 10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 , or approximately 5 × 10 15 ~5×10 16 atoms / cm 3 In some embodiments, current spreading layer 1530 may have a higher concentration of dopant (n-type in this example) than conduction facilitating region 550. For example, conduction facilitating region 550 may have a dopant concentration that is about 2 times or more, e.g., about 5 times or more, or about 10 times or more, or about 20 times or more, higher than drift region 220, and current spreading layer 1530 may have a higher dopant concentration than conduction facilitating region 550. The elements and layers of device 1500, including shield region 240 and offset conduction facilitating region 550, may otherwise be identical to device 200 of FIG. 5 and, therefore, will not be described further for the sake of brevity. It is also understood that the current spreading layer 1530 shown in FIG. 15 can similarly be incorporated between the top of the drift region 220 and the substrate 210 of any device (e.g., 200, 500, 800, 1200, 1400) or various embodiments described herein.

[0112] More generally, it is understood that features of different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Furthermore, while the present invention has been described above primarily with respect to power MOSFET implementations, it will be understood that the techniques described herein are equally applicable to other similar power semiconductor devices that require high-voltage blocking and / or include areas or regions susceptible to breakdown in reverse blocking. Accordingly, embodiments of the present invention are not limited to MOSFETs; the techniques disclosed herein can be used with IGBTs or any other suitable gate trench devices. For example, features of any MOSFET embodiment described herein can be incorporated into IGBT embodiments fabricated on SiC or other semiconductor materials, such as Si. Accordingly, while various features of the inventive concepts are described herein with respect to specific embodiments, it will be understood that these features can be added to and / or substituted for features of other embodiments to provide many additional embodiments. Accordingly, the present invention should be understood to encompass these different combinations.

[0113] Therefore, some embodiments of the present invention may include a drift layer or region with a reduced dopant concentration to protect the oxide layer at the corners of the trench, thereby reducing the likelihood of gate oxide breakdown and improving reliability. Additionally or alternatively, some embodiments of the present invention may include a conduction-promoting region with an increased dopant concentration in the portion of the drift layer between the gate and trench, thereby improving conduction, for example, to offset the increased resistance of the drift layer with a reduced dopant concentration.

[0114] In the above description, each illustrative embodiment is described in terms of regions of a particular conductivity type. It is understood that devices of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Thus, it is understood that the present invention covers both n-channel and p-channel devices for each of the different device structures (e.g., MOSFETs, IGBTs, etc.).

[0115] The present invention has been discussed above primarily with respect to silicon carbide-based power semiconductor devices. However, silicon carbide is used herein as an example, and it is understood that the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the above-described examples. More generally, while described with reference to silicon carbide devices, embodiments of the present invention are not limited thereto and may have applicability to devices formed using other wide bandgap semiconductor materials, such as gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor material.

[0116]

[0033] Embodiments of the present invention have been described above with reference to the accompanying drawings, which illustrate embodiments of the invention. It is understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the above-described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0117] Terms such as first, second, etc. are used throughout this specification to describe various elements, but it is understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0118] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that as used herein, the terms "comprises," "comprising," "including," and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0119] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it is understood that it can be directly on or extending directly onto the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0120] Relative terms such as "lower" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0121] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Embodiments of the present invention are also described in terms of manufacturing processes. It is understood that the steps shown in the manufacturing processes do not have to be performed in the order shown.

[0122] Some embodiments of the present invention are described in relation to semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration of the semiconductor layer and / or region. Thus, an n-type material has a majority equilibrium concentration of negatively charged electrons, and a p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" to indicate a relatively greater ("+") or lesser ("-") concentration of majority carriers compared to another layer or region (n + , n - , p + , p - , n ++ , n -- , p ++ , p -- However, such notation does not imply the presence of any particular concentration of majority or minority carriers in a layer or region.

[0123] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the appended claims.

Claims

1. A power semiconductor device, a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type; a plurality of gate trenches extending into the drift region; a respective shield pattern of the second conductivity type in a respective portion of the drift region adjacent to the gate trench; a respective conduction promotion region of the first conductivity type in each portion of the drift region, the respective conduction promotion region extending into the well region adjacent the respective shield pattern; Equipped with the drift region includes a first concentration of dopants of the first conductivity type, and each of the conduction promoting regions includes a second concentration of dopants of the first conductivity type that is higher than the first concentration; a power semiconductor device, wherein, in response to a voltage applied to the power semiconductor device, the respective portions of the drift region between the gate trenches include an electric field distribution having peaks distal to respective corners of the gate trenches in a first direction.

2. 2. The power semiconductor device of claim 1 , wherein the gate trenches are spaced apart from one another along the first direction, and wherein the respective conduction promotion regions are spaced apart from the respective corners of the gate trenches along the first direction.

3. 3. The power semiconductor device of claim 2, wherein the respective portions of the drift region between the gate trenches include the dopant of the first conductivity type at a concentration gradient that varies between the first concentration and the second concentration along the first direction.

4. 4. The power semiconductor device of claim 2, wherein the drift region includes the first concentration of the dopant proximate the respective corners of the gate trench, and the second concentration is at least two times greater than the first concentration.

5. 2. The power semiconductor device of claim 1, wherein the peak of the electric field distribution is at least ten times greater than the intensity of the electric field distribution proximate the respective corners of the gate trench.

6. 4. The power semiconductor device of claim 1, wherein the respective conduction facilitating regions are between the gate trenches and extend beyond a lower boundary of the respective shield pattern into the drift region.

7. 7. The power semiconductor device of claim 6, wherein the respective conduction facilitating regions are offset from the respective shielding patterns toward the gate trench.

8. The power semiconductor device of claim 6 , wherein the respective conduction facilitating regions extend along both sides and a lower boundary of the respective shielding pattern.

9. The power semiconductor device of claim 6 , wherein each of the conduction facilitation regions extends along an axis that is non-orthogonal to a surface of the drift region.

10. The semiconductor layer structure comprises: a current spreading layer including the dopant of the first conductivity type at a third concentration higher than the first and / or second concentration; the respective portions of the drift region including the respective conduction promoting regions are between the well region and the current spreading layer. A power semiconductor device according to any one of claims 1 to 9.

11. 11. The power semiconductor device of claim 1, wherein the semiconductor layer structure comprises a wide bandgap semiconductor, the drift region comprises an epitaxial layer of the first conductivity type, and each of the conduction promoting regions comprises an implanted region of the first conductivity type.

12. A power semiconductor device, a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type; a plurality of gate trenches extending into the drift region; Equipped with a power semiconductor device, wherein, in response to a voltage applied to the power semiconductor device, each portion of the drift region between the gate trenches includes an electric field distribution having a peak distal to each corner of the gate trench.

13. 13. The power semiconductor device of claim 12, wherein the gate trenches are spaced apart from one another in a first direction, and the electric field distribution in the respective portions of the drift region between the gate trenches is asymmetric along the first direction.

14. 14. The power semiconductor device of claim 13, wherein the peak of the electric field distribution is at least ten times greater than the intensity of the electric field distribution proximate the respective corners of the gate trench.

15. 14. The power semiconductor device of claim 13, wherein the respective portions of the drift region between the gate trenches include a dopant of the first conductivity type at a concentration that varies along the first direction, the peak of the concentration of the dopant being spaced apart in the first direction from the respective corner of the gate trench.

16. each of the first conductivity type conduction-promoting regions spaced apart from each of the corners of the gate trench along the first direction; 16. The power semiconductor device of claim 15, wherein the concentration of the dopant of the first conductivity type comprises a first concentration proximate the respective corners of the gate trench and a second concentration in the respective conduction-facilitating region, the second concentration being greater than the first concentration.

17. 17. The power semiconductor device of claim 16, wherein the concentration of the dopant of the first conductivity type further comprises a concentration gradient of the dopant of the first conductivity type between the first concentration and the second concentration along the first direction.

18. 17. The power semiconductor device of claim 16, wherein the second concentration is at least ten times greater than the first concentration.

19. 17. The power semiconductor device of claim 16, wherein each of the conduction facilitating regions comprises the peak of the electric field distribution.

20. 1. A method of manufacturing a power semiconductor device, comprising: forming a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type; forming a respective conduction promoting region of the first conductivity type in a first portion of each of the drift regions; forming a respective shield pattern of the second conductivity type in a second portion of each of the drift regions; forming a plurality of gate trenches extending into the drift region; Including, each of the conduction promoting regions extends into the well region adjacent to the respective shielding pattern, the drift region includes a first concentration of a dopant of the first conductivity type, and each of the conduction promoting regions includes a second concentration of the dopant of the first conductivity type that is greater than the first concentration; responsive to a voltage applied to the power semiconductor device, the respective portions of the drift region between the gate trenches include an electric field distribution having a peak distal to a respective corner of the gate trench in a first direction.

21. 21. The method of claim 20, wherein the gate trenches are spaced apart from one another along the first direction, and wherein the respective conduction-facilitating regions are spaced apart from the respective corners of the gate trenches along the first direction.

22. 22. The method of claim 21 , wherein the respective portions of the drift region between the gate trenches include the dopant of the first conductivity type at a concentration gradient that varies between the first concentration and the second concentration along the first direction.

23. 23. The method of claim 22, wherein the semiconductor layer structure comprises a wide bandgap semiconductor, the drift region comprises an epitaxial layer of the first conductivity type, and each of the conduction promoting regions comprises an implanted region of the first conductivity type.

24. 24. The method of claim 23, wherein the drift region includes the first concentration of the dopant proximate the respective corners of the gate trench, and the second concentration is at least ten times greater than the first concentration.

25. 25. The method of claim 20, wherein the respective conduction-facilitating regions are between the gate trenches and extend beyond a lower boundary of the respective shield pattern into the drift region.

26. 26. The method of claim 25, wherein the respective conduction facilitating regions are offset from the respective shielding patterns toward the gate trench and / or the respective conduction facilitating regions extend along at least one of a side or lower boundary of the respective shielding patterns.

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